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17467f23 TT |
1 | /* |
2 | * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
f0fba2ad LG |
6 | * Copyright 2007-2010 Freescale Semiconductor, Inc. |
7 | * | |
8 | * This file is licensed under the terms of the GNU General Public License | |
9 | * version 2. This program is licensed "as is" without any warranty of any | |
10 | * kind, whether express or implied. | |
de623ece MP |
11 | * |
12 | * | |
13 | * Some notes why imx-pcm-fiq is used instead of DMA on some boards: | |
14 | * | |
15 | * The i.MX SSI core has some nasty limitations in AC97 mode. While most | |
16 | * sane processor vendors have a FIFO per AC97 slot, the i.MX has only | |
17 | * one FIFO which combines all valid receive slots. We cannot even select | |
18 | * which slots we want to receive. The WM9712 with which this driver | |
19 | * was developed with always sends GPIO status data in slot 12 which | |
20 | * we receive in our (PCM-) data stream. The only chance we have is to | |
21 | * manually skip this data in the FIQ handler. With sampling rates different | |
22 | * from 48000Hz not every frame has valid receive data, so the ratio | |
23 | * between pcm data and GPIO status data changes. Our FIQ handler is not | |
24 | * able to handle this, hence this driver only works with 48000Hz sampling | |
25 | * rate. | |
26 | * Reading and writing AC97 registers is another challenge. The core | |
27 | * provides us status bits when the read register is updated with *another* | |
28 | * value. When we read the same register two times (and the register still | |
29 | * contains the same value) these status bits are not set. We work | |
30 | * around this by not polling these bits but only wait a fixed delay. | |
17467f23 TT |
31 | */ |
32 | ||
33 | #include <linux/init.h> | |
dfa1a107 | 34 | #include <linux/io.h> |
17467f23 TT |
35 | #include <linux/module.h> |
36 | #include <linux/interrupt.h> | |
95cd98f9 | 37 | #include <linux/clk.h> |
17467f23 TT |
38 | #include <linux/device.h> |
39 | #include <linux/delay.h> | |
5a0e3ad6 | 40 | #include <linux/slab.h> |
aafa85e7 | 41 | #include <linux/spinlock.h> |
9c72a04c | 42 | #include <linux/of.h> |
dfa1a107 SG |
43 | #include <linux/of_address.h> |
44 | #include <linux/of_irq.h> | |
f0fba2ad | 45 | #include <linux/of_platform.h> |
17467f23 | 46 | |
17467f23 TT |
47 | #include <sound/core.h> |
48 | #include <sound/pcm.h> | |
49 | #include <sound/pcm_params.h> | |
50 | #include <sound/initval.h> | |
51 | #include <sound/soc.h> | |
a8909c9b | 52 | #include <sound/dmaengine_pcm.h> |
17467f23 | 53 | |
17467f23 | 54 | #include "fsl_ssi.h" |
09ce1111 | 55 | #include "imx-pcm.h" |
17467f23 | 56 | |
17467f23 TT |
57 | /** |
58 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
59 | * | |
17467f23 TT |
60 | * The SSI has a limitation in that the samples must be in the same byte |
61 | * order as the host CPU. This is because when multiple bytes are written | |
62 | * to the STX register, the bytes and bits must be written in the same | |
63 | * order. The STX is a shift register, so all the bits need to be aligned | |
64 | * (bit-endianness must match byte-endianness). Processors typically write | |
65 | * the bits within a byte in the same order that the bytes of a word are | |
66 | * written in. So if the host CPU is big-endian, then only big-endian | |
67 | * samples will be written to STX properly. | |
68 | */ | |
69 | #ifdef __BIG_ENDIAN | |
70 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
71 | SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
72 | SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE) | |
73 | #else | |
74 | #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
75 | SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
76 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE) | |
77 | #endif | |
78 | ||
9368acc4 MP |
79 | #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \ |
80 | CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \ | |
81 | CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN) | |
82 | #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \ | |
83 | CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \ | |
84 | CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN) | |
c1953bfe MP |
85 | |
86 | enum fsl_ssi_type { | |
87 | FSL_SSI_MCP8610, | |
88 | FSL_SSI_MX21, | |
0888efd1 | 89 | FSL_SSI_MX35, |
c1953bfe MP |
90 | FSL_SSI_MX51, |
91 | }; | |
92 | ||
4e6ec0d9 MP |
93 | struct fsl_ssi_reg_val { |
94 | u32 sier; | |
95 | u32 srcr; | |
96 | u32 stcr; | |
97 | u32 scr; | |
98 | }; | |
99 | ||
100 | struct fsl_ssi_rxtx_reg_val { | |
101 | struct fsl_ssi_reg_val rx; | |
102 | struct fsl_ssi_reg_val tx; | |
103 | }; | |
05cf2379 | 104 | |
05cf2379 ZW |
105 | static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) |
106 | { | |
107 | switch (reg) { | |
108 | case CCSR_SSI_SACCEN: | |
109 | case CCSR_SSI_SACCDIS: | |
110 | return false; | |
111 | default: | |
112 | return true; | |
113 | } | |
114 | } | |
115 | ||
116 | static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) | |
117 | { | |
118 | switch (reg) { | |
119 | case CCSR_SSI_STX0: | |
120 | case CCSR_SSI_STX1: | |
121 | case CCSR_SSI_SRX0: | |
122 | case CCSR_SSI_SRX1: | |
123 | case CCSR_SSI_SISR: | |
124 | case CCSR_SSI_SFCSR: | |
3f1c241f | 125 | case CCSR_SSI_SACNT: |
05cf2379 ZW |
126 | case CCSR_SSI_SACADD: |
127 | case CCSR_SSI_SACDAT: | |
128 | case CCSR_SSI_SATAG: | |
129 | case CCSR_SSI_SACCST: | |
3cc6185b | 130 | case CCSR_SSI_SOR: |
05cf2379 ZW |
131 | return true; |
132 | default: | |
133 | return false; | |
134 | } | |
135 | } | |
136 | ||
f51e3d53 MS |
137 | static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) |
138 | { | |
139 | switch (reg) { | |
140 | case CCSR_SSI_SRX0: | |
141 | case CCSR_SSI_SRX1: | |
142 | case CCSR_SSI_SISR: | |
143 | case CCSR_SSI_SACADD: | |
144 | case CCSR_SSI_SACDAT: | |
145 | case CCSR_SSI_SATAG: | |
146 | return true; | |
147 | default: | |
148 | return false; | |
149 | } | |
150 | } | |
151 | ||
05cf2379 ZW |
152 | static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) |
153 | { | |
154 | switch (reg) { | |
155 | case CCSR_SSI_SRX0: | |
156 | case CCSR_SSI_SRX1: | |
157 | case CCSR_SSI_SACCST: | |
158 | return false; | |
159 | default: | |
160 | return true; | |
161 | } | |
162 | } | |
163 | ||
43248122 MP |
164 | static const struct regmap_config fsl_ssi_regconfig = { |
165 | .max_register = CCSR_SSI_SACCDIS, | |
166 | .reg_bits = 32, | |
167 | .val_bits = 32, | |
168 | .reg_stride = 4, | |
169 | .val_format_endian = REGMAP_ENDIAN_NATIVE, | |
f26b3b2a | 170 | .num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1, |
05cf2379 ZW |
171 | .readable_reg = fsl_ssi_readable_reg, |
172 | .volatile_reg = fsl_ssi_volatile_reg, | |
f51e3d53 | 173 | .precious_reg = fsl_ssi_precious_reg, |
05cf2379 | 174 | .writeable_reg = fsl_ssi_writeable_reg, |
bfcf928d | 175 | .cache_type = REGCACHE_FLAT, |
43248122 | 176 | }; |
d5a908b2 | 177 | |
fcdbadef SH |
178 | struct fsl_ssi_soc_data { |
179 | bool imx; | |
6139b1b1 | 180 | bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */ |
fcdbadef SH |
181 | bool offline_config; |
182 | u32 sisr_write_mask; | |
183 | }; | |
184 | ||
17467f23 TT |
185 | /** |
186 | * fsl_ssi_private: per-SSI private data | |
187 | * | |
43248122 | 188 | * @reg: Pointer to the regmap registers |
17467f23 | 189 | * @irq: IRQ of this SSI |
737a6b41 MP |
190 | * @cpu_dai_drv: CPU DAI driver for this device |
191 | * | |
192 | * @dai_fmt: DAI configuration this device is currently used with | |
193 | * @i2s_mode: i2s and network mode configuration of the device. Is used to | |
194 | * switch between normal and i2s/network mode | |
195 | * mode depending on the number of channels | |
196 | * @use_dma: DMA is used or FIQ with stream filter | |
197 | * @use_dual_fifo: DMA with support for both FIFOs used | |
198 | * @fifo_deph: Depth of the SSI FIFOs | |
199 | * @rxtx_reg_val: Specific register settings for receive/transmit configuration | |
200 | * | |
201 | * @clk: SSI clock | |
202 | * @baudclk: SSI baud clock for master mode | |
203 | * @baudclk_streams: Active streams that are using baudclk | |
204 | * @bitclk_freq: bitclock frequency set by .set_dai_sysclk | |
205 | * | |
206 | * @dma_params_tx: DMA transmit parameters | |
207 | * @dma_params_rx: DMA receive parameters | |
208 | * @ssi_phys: physical address of the SSI registers | |
209 | * | |
210 | * @fiq_params: FIQ stream filtering parameters | |
211 | * | |
212 | * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card | |
213 | * | |
214 | * @dbg_stats: Debugging statistics | |
215 | * | |
dcfcf2c2 | 216 | * @soc: SoC specific data |
17467f23 TT |
217 | */ |
218 | struct fsl_ssi_private { | |
43248122 | 219 | struct regmap *regs; |
9e446ad5 | 220 | int irq; |
f0fba2ad | 221 | struct snd_soc_dai_driver cpu_dai_drv; |
17467f23 | 222 | |
737a6b41 MP |
223 | unsigned int dai_fmt; |
224 | u8 i2s_mode; | |
de623ece | 225 | bool use_dma; |
0da9e55e | 226 | bool use_dual_fifo; |
f4a43cab | 227 | bool has_ipg_clk_name; |
737a6b41 MP |
228 | unsigned int fifo_depth; |
229 | struct fsl_ssi_rxtx_reg_val rxtx_reg_val; | |
230 | ||
95cd98f9 | 231 | struct clk *clk; |
737a6b41 | 232 | struct clk *baudclk; |
d429d8e3 | 233 | unsigned int baudclk_streams; |
8dd51e23 | 234 | unsigned int bitclk_freq; |
737a6b41 | 235 | |
3f1c241f | 236 | /* regcache for volatile regs */ |
05cf2379 | 237 | u32 regcache_sfcsr; |
3f1c241f | 238 | u32 regcache_sacnt; |
05cf2379 | 239 | |
737a6b41 | 240 | /* DMA params */ |
a8909c9b LPC |
241 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
242 | struct snd_dmaengine_dai_dma_data dma_params_rx; | |
737a6b41 MP |
243 | dma_addr_t ssi_phys; |
244 | ||
245 | /* params for non-dma FIQ stream filtered mode */ | |
de623ece | 246 | struct imx_pcm_fiq_params fiq_params; |
737a6b41 MP |
247 | |
248 | /* Used when using fsl-ssi as sound-card. This is only used by ppc and | |
249 | * should be replaced with simple-sound-card. */ | |
250 | struct platform_device *pdev; | |
09ce1111 | 251 | |
f138e621 | 252 | struct fsl_ssi_dbg dbg_stats; |
17467f23 | 253 | |
fcdbadef | 254 | const struct fsl_ssi_soc_data *soc; |
0096b693 | 255 | struct device *dev; |
c1953bfe | 256 | }; |
171d683d MP |
257 | |
258 | /* | |
259 | * imx51 and later SoCs have a slightly different IP that allows the | |
260 | * SSI configuration while the SSI unit is running. | |
261 | * | |
262 | * More important, it is necessary on those SoCs to configure the | |
263 | * sperate TX/RX DMA bits just before starting the stream | |
264 | * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi | |
265 | * sends any DMA requests to the SDMA unit, otherwise it is not defined | |
266 | * how the SDMA unit handles the DMA request. | |
267 | * | |
268 | * SDMA units are present on devices starting at imx35 but the imx35 | |
269 | * reference manual states that the DMA bits should not be changed | |
270 | * while the SSI unit is running (SSIEN). So we support the necessary | |
271 | * online configuration of fsl-ssi starting at imx51. | |
272 | */ | |
171d683d | 273 | |
fcdbadef SH |
274 | static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { |
275 | .imx = false, | |
276 | .offline_config = true, | |
277 | .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | | |
278 | CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | | |
279 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, | |
280 | }; | |
281 | ||
282 | static struct fsl_ssi_soc_data fsl_ssi_imx21 = { | |
283 | .imx = true, | |
6139b1b1 | 284 | .imx21regs = true, |
fcdbadef SH |
285 | .offline_config = true, |
286 | .sisr_write_mask = 0, | |
287 | }; | |
288 | ||
289 | static struct fsl_ssi_soc_data fsl_ssi_imx35 = { | |
290 | .imx = true, | |
291 | .offline_config = true, | |
292 | .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC | | |
293 | CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | | |
294 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, | |
295 | }; | |
296 | ||
297 | static struct fsl_ssi_soc_data fsl_ssi_imx51 = { | |
298 | .imx = true, | |
299 | .offline_config = false, | |
300 | .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 | | |
301 | CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1, | |
302 | }; | |
303 | ||
304 | static const struct of_device_id fsl_ssi_ids[] = { | |
305 | { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, | |
306 | { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, | |
307 | { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, | |
308 | { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, | |
309 | {} | |
310 | }; | |
311 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
312 | ||
313 | static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private) | |
314 | { | |
5b64c173 AT |
315 | return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == |
316 | SND_SOC_DAIFMT_AC97; | |
171d683d MP |
317 | } |
318 | ||
8dd51e23 SH |
319 | static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private) |
320 | { | |
321 | return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == | |
322 | SND_SOC_DAIFMT_CBS_CFS; | |
323 | } | |
324 | ||
cf4f7fc3 FF |
325 | static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private) |
326 | { | |
327 | return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == | |
328 | SND_SOC_DAIFMT_CBM_CFS; | |
329 | } | |
17467f23 TT |
330 | /** |
331 | * fsl_ssi_isr: SSI interrupt handler | |
332 | * | |
333 | * Although it's possible to use the interrupt handler to send and receive | |
334 | * data to/from the SSI, we use the DMA instead. Programming is more | |
335 | * complicated, but the performance is much better. | |
336 | * | |
337 | * This interrupt handler is used only to gather statistics. | |
338 | * | |
339 | * @irq: IRQ of the SSI device | |
340 | * @dev_id: pointer to the ssi_private structure for this SSI device | |
341 | */ | |
342 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
343 | { | |
344 | struct fsl_ssi_private *ssi_private = dev_id; | |
43248122 | 345 | struct regmap *regs = ssi_private->regs; |
17467f23 | 346 | __be32 sisr; |
0888efd1 | 347 | __be32 sisr2; |
17467f23 TT |
348 | |
349 | /* We got an interrupt, so read the status register to see what we | |
350 | were interrupted for. We mask it with the Interrupt Enable register | |
351 | so that we only check for events that we're interested in. | |
352 | */ | |
43248122 | 353 | regmap_read(regs, CCSR_SSI_SISR, &sisr); |
17467f23 | 354 | |
fcdbadef | 355 | sisr2 = sisr & ssi_private->soc->sisr_write_mask; |
17467f23 TT |
356 | /* Clear the bits that we set */ |
357 | if (sisr2) | |
43248122 | 358 | regmap_write(regs, CCSR_SSI_SISR, sisr2); |
17467f23 | 359 | |
f138e621 | 360 | fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr); |
9368acc4 | 361 | |
f138e621 | 362 | return IRQ_HANDLED; |
9368acc4 MP |
363 | } |
364 | ||
4e6ec0d9 MP |
365 | /* |
366 | * Enable/Disable all rx/tx config flags at once. | |
367 | */ | |
368 | static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private, | |
369 | bool enable) | |
370 | { | |
43248122 | 371 | struct regmap *regs = ssi_private->regs; |
4e6ec0d9 MP |
372 | struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val; |
373 | ||
374 | if (enable) { | |
43248122 MP |
375 | regmap_update_bits(regs, CCSR_SSI_SIER, |
376 | vals->rx.sier | vals->tx.sier, | |
377 | vals->rx.sier | vals->tx.sier); | |
378 | regmap_update_bits(regs, CCSR_SSI_SRCR, | |
379 | vals->rx.srcr | vals->tx.srcr, | |
380 | vals->rx.srcr | vals->tx.srcr); | |
381 | regmap_update_bits(regs, CCSR_SSI_STCR, | |
382 | vals->rx.stcr | vals->tx.stcr, | |
383 | vals->rx.stcr | vals->tx.stcr); | |
4e6ec0d9 | 384 | } else { |
43248122 MP |
385 | regmap_update_bits(regs, CCSR_SSI_SRCR, |
386 | vals->rx.srcr | vals->tx.srcr, 0); | |
387 | regmap_update_bits(regs, CCSR_SSI_STCR, | |
388 | vals->rx.stcr | vals->tx.stcr, 0); | |
389 | regmap_update_bits(regs, CCSR_SSI_SIER, | |
390 | vals->rx.sier | vals->tx.sier, 0); | |
4e6ec0d9 MP |
391 | } |
392 | } | |
393 | ||
027db2e1 AM |
394 | /* |
395 | * Clear RX or TX FIFO to remove samples from the previous | |
396 | * stream session which may be still present in the FIFO and | |
397 | * may introduce bad samples and/or channel slipping. | |
398 | * | |
399 | * Note: The SOR is not documented in recent IMX datasheet, but | |
400 | * is described in IMX51 reference manual at section 56.3.3.15. | |
401 | */ | |
402 | static void fsl_ssi_fifo_clear(struct fsl_ssi_private *ssi_private, | |
403 | bool is_rx) | |
404 | { | |
405 | if (is_rx) { | |
406 | regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR, | |
407 | CCSR_SSI_SOR_RX_CLR, CCSR_SSI_SOR_RX_CLR); | |
408 | } else { | |
409 | regmap_update_bits(ssi_private->regs, CCSR_SSI_SOR, | |
410 | CCSR_SSI_SOR_TX_CLR, CCSR_SSI_SOR_TX_CLR); | |
411 | } | |
412 | } | |
413 | ||
65c961cc MP |
414 | /* |
415 | * Calculate the bits that have to be disabled for the current stream that is | |
416 | * getting disabled. This keeps the bits enabled that are necessary for the | |
417 | * second stream to work if 'stream_active' is true. | |
418 | * | |
419 | * Detailed calculation: | |
420 | * These are the values that need to be active after disabling. For non-active | |
421 | * second stream, this is 0: | |
422 | * vals_stream * !!stream_active | |
423 | * | |
424 | * The following computes the overall differences between the setup for the | |
425 | * to-disable stream and the active stream, a simple XOR: | |
426 | * vals_disable ^ (vals_stream * !!(stream_active)) | |
427 | * | |
428 | * The full expression adds a mask on all values we care about | |
429 | */ | |
430 | #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \ | |
431 | ((vals_disable) & \ | |
432 | ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active)))) | |
433 | ||
4e6ec0d9 MP |
434 | /* |
435 | * Enable/Disable a ssi configuration. You have to pass either | |
436 | * ssi_private->rxtx_reg_val.rx or tx as vals parameter. | |
437 | */ | |
438 | static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable, | |
439 | struct fsl_ssi_reg_val *vals) | |
440 | { | |
43248122 | 441 | struct regmap *regs = ssi_private->regs; |
4e6ec0d9 | 442 | struct fsl_ssi_reg_val *avals; |
43248122 MP |
443 | int nr_active_streams; |
444 | u32 scr_val; | |
65c961cc MP |
445 | int keep_active; |
446 | ||
43248122 MP |
447 | regmap_read(regs, CCSR_SSI_SCR, &scr_val); |
448 | ||
449 | nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) + | |
450 | !!(scr_val & CCSR_SSI_SCR_RE); | |
451 | ||
65c961cc MP |
452 | if (nr_active_streams - 1 > 0) |
453 | keep_active = 1; | |
454 | else | |
455 | keep_active = 0; | |
4e6ec0d9 MP |
456 | |
457 | /* Find the other direction values rx or tx which we do not want to | |
458 | * modify */ | |
459 | if (&ssi_private->rxtx_reg_val.rx == vals) | |
460 | avals = &ssi_private->rxtx_reg_val.tx; | |
461 | else | |
462 | avals = &ssi_private->rxtx_reg_val.rx; | |
463 | ||
464 | /* If vals should be disabled, start with disabling the unit */ | |
465 | if (!enable) { | |
65c961cc MP |
466 | u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr, |
467 | keep_active); | |
43248122 | 468 | regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0); |
4e6ec0d9 MP |
469 | } |
470 | ||
471 | /* | |
472 | * We are running on a SoC which does not support online SSI | |
473 | * reconfiguration, so we have to enable all necessary flags at once | |
474 | * even if we do not use them later (capture and playback configuration) | |
475 | */ | |
fcdbadef | 476 | if (ssi_private->soc->offline_config) { |
4e6ec0d9 | 477 | if ((enable && !nr_active_streams) || |
65c961cc | 478 | (!enable && !keep_active)) |
4e6ec0d9 MP |
479 | fsl_ssi_rxtx_config(ssi_private, enable); |
480 | ||
481 | goto config_done; | |
482 | } | |
483 | ||
484 | /* | |
485 | * Configure single direction units while the SSI unit is running | |
486 | * (online configuration) | |
487 | */ | |
488 | if (enable) { | |
027db2e1 AM |
489 | fsl_ssi_fifo_clear(ssi_private, vals->scr & CCSR_SSI_SCR_RE); |
490 | ||
43248122 MP |
491 | regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr); |
492 | regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr); | |
d9f2a202 | 493 | regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier); |
4e6ec0d9 MP |
494 | } else { |
495 | u32 sier; | |
496 | u32 srcr; | |
497 | u32 stcr; | |
498 | ||
499 | /* | |
500 | * Disabling the necessary flags for one of rx/tx while the | |
501 | * other stream is active is a little bit more difficult. We | |
502 | * have to disable only those flags that differ between both | |
503 | * streams (rx XOR tx) and that are set in the stream that is | |
504 | * disabled now. Otherwise we could alter flags of the other | |
505 | * stream | |
506 | */ | |
507 | ||
508 | /* These assignments are simply vals without bits set in avals*/ | |
65c961cc MP |
509 | sier = fsl_ssi_disable_val(vals->sier, avals->sier, |
510 | keep_active); | |
511 | srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr, | |
512 | keep_active); | |
513 | stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr, | |
514 | keep_active); | |
4e6ec0d9 | 515 | |
43248122 MP |
516 | regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0); |
517 | regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0); | |
518 | regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0); | |
4e6ec0d9 MP |
519 | } |
520 | ||
521 | config_done: | |
522 | /* Enabling of subunits is done after configuration */ | |
61fcf10a AM |
523 | if (enable) { |
524 | if (ssi_private->use_dma && (vals->scr & CCSR_SSI_SCR_TE)) { | |
525 | /* | |
526 | * Be sure the Tx FIFO is filled when TE is set. | |
527 | * Otherwise, there are some chances to start the | |
528 | * playback with some void samples inserted first, | |
529 | * generating a channel slip. | |
530 | * | |
531 | * First, SSIEN must be set, to let the FIFO be filled. | |
532 | * | |
533 | * Notes: | |
534 | * - Limit this fix to the DMA case until FIQ cases can | |
535 | * be tested. | |
536 | * - Limit the length of the busy loop to not lock the | |
537 | * system too long, even if 1-2 loops are sufficient | |
538 | * in general. | |
539 | */ | |
540 | int i; | |
541 | int max_loop = 100; | |
542 | regmap_update_bits(regs, CCSR_SSI_SCR, | |
543 | CCSR_SSI_SCR_SSIEN, CCSR_SSI_SCR_SSIEN); | |
544 | for (i = 0; i < max_loop; i++) { | |
545 | u32 sfcsr; | |
546 | regmap_read(regs, CCSR_SSI_SFCSR, &sfcsr); | |
547 | if (CCSR_SSI_SFCSR_TFCNT0(sfcsr)) | |
548 | break; | |
549 | } | |
550 | if (i == max_loop) { | |
551 | dev_err(ssi_private->dev, | |
552 | "Timeout waiting TX FIFO filling\n"); | |
553 | } | |
554 | } | |
43248122 | 555 | regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr); |
61fcf10a | 556 | } |
4e6ec0d9 MP |
557 | } |
558 | ||
559 | ||
560 | static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable) | |
561 | { | |
562 | fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx); | |
563 | } | |
564 | ||
565 | static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable) | |
566 | { | |
567 | fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx); | |
568 | } | |
569 | ||
6de83879 MP |
570 | /* |
571 | * Setup rx/tx register values used to enable/disable the streams. These will | |
572 | * be used later in fsl_ssi_config to setup the streams without the need to | |
573 | * check for all different SSI modes. | |
574 | */ | |
575 | static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private) | |
576 | { | |
577 | struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val; | |
578 | ||
579 | reg->rx.sier = CCSR_SSI_SIER_RFF0_EN; | |
580 | reg->rx.srcr = CCSR_SSI_SRCR_RFEN0; | |
581 | reg->rx.scr = 0; | |
582 | reg->tx.sier = CCSR_SSI_SIER_TFE0_EN; | |
583 | reg->tx.stcr = CCSR_SSI_STCR_TFEN0; | |
584 | reg->tx.scr = 0; | |
585 | ||
171d683d | 586 | if (!fsl_ssi_is_ac97(ssi_private)) { |
6de83879 MP |
587 | reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE; |
588 | reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN; | |
589 | reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE; | |
590 | reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN; | |
591 | } | |
592 | ||
593 | if (ssi_private->use_dma) { | |
594 | reg->rx.sier |= CCSR_SSI_SIER_RDMAE; | |
595 | reg->tx.sier |= CCSR_SSI_SIER_TDMAE; | |
596 | } else { | |
597 | reg->rx.sier |= CCSR_SSI_SIER_RIE; | |
598 | reg->tx.sier |= CCSR_SSI_SIER_TIE; | |
599 | } | |
600 | ||
601 | reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS; | |
602 | reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS; | |
603 | } | |
604 | ||
d8764646 MP |
605 | static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private) |
606 | { | |
43248122 | 607 | struct regmap *regs = ssi_private->regs; |
d8764646 MP |
608 | |
609 | /* | |
610 | * Setup the clock control register | |
611 | */ | |
43248122 MP |
612 | regmap_write(regs, CCSR_SSI_STCCR, |
613 | CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); | |
614 | regmap_write(regs, CCSR_SSI_SRCCR, | |
615 | CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13)); | |
d8764646 MP |
616 | |
617 | /* | |
618 | * Enable AC97 mode and startup the SSI | |
619 | */ | |
43248122 MP |
620 | regmap_write(regs, CCSR_SSI_SACNT, |
621 | CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV); | |
6139b1b1 MS |
622 | |
623 | /* no SACC{ST,EN,DIS} regs on imx21-class SSI */ | |
624 | if (!ssi_private->soc->imx21regs) { | |
625 | regmap_write(regs, CCSR_SSI_SACCDIS, 0xff); | |
626 | regmap_write(regs, CCSR_SSI_SACCEN, 0x300); | |
627 | } | |
d8764646 MP |
628 | |
629 | /* | |
630 | * Enable SSI, Transmit and Receive. AC97 has to communicate with the | |
631 | * codec before a stream is started. | |
632 | */ | |
43248122 MP |
633 | regmap_update_bits(regs, CCSR_SSI_SCR, |
634 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE, | |
635 | CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE); | |
d8764646 | 636 | |
43248122 | 637 | regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3)); |
d8764646 MP |
638 | } |
639 | ||
17467f23 TT |
640 | /** |
641 | * fsl_ssi_startup: create a new substream | |
642 | * | |
643 | * This is the first function called when a stream is opened. | |
644 | * | |
645 | * If this is the first stream open, then grab the IRQ and program most of | |
646 | * the SSI registers. | |
647 | */ | |
dee89c4d MB |
648 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
649 | struct snd_soc_dai *dai) | |
17467f23 TT |
650 | { |
651 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
5e538eca TT |
652 | struct fsl_ssi_private *ssi_private = |
653 | snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
f4a43cab SW |
654 | int ret; |
655 | ||
656 | ret = clk_prepare_enable(ssi_private->clk); | |
657 | if (ret) | |
658 | return ret; | |
17467f23 | 659 | |
0da9e55e NC |
660 | /* When using dual fifo mode, it is safer to ensure an even period |
661 | * size. If appearing to an odd number while DMA always starts its | |
662 | * task from fifo0, fifo1 would be neglected at the end of each | |
663 | * period. But SSI would still access fifo1 with an invalid data. | |
664 | */ | |
665 | if (ssi_private->use_dual_fifo) | |
666 | snd_pcm_hw_constraint_step(substream->runtime, 0, | |
667 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); | |
668 | ||
17467f23 TT |
669 | return 0; |
670 | } | |
671 | ||
f4a43cab SW |
672 | /** |
673 | * fsl_ssi_shutdown: shutdown the SSI | |
674 | * | |
675 | */ | |
676 | static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, | |
677 | struct snd_soc_dai *dai) | |
678 | { | |
679 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
680 | struct fsl_ssi_private *ssi_private = | |
681 | snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
682 | ||
683 | clk_disable_unprepare(ssi_private->clk); | |
684 | ||
685 | } | |
686 | ||
ee9daad4 | 687 | /** |
8dd51e23 | 688 | * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock |
ee9daad4 SH |
689 | * |
690 | * Note: This function can be only called when using SSI as DAI master | |
691 | * | |
692 | * Quick instruction for parameters: | |
693 | * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels | |
694 | * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK. | |
695 | */ | |
8dd51e23 SH |
696 | static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, |
697 | struct snd_soc_dai *cpu_dai, | |
698 | struct snd_pcm_hw_params *hw_params) | |
ee9daad4 SH |
699 | { |
700 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
43248122 | 701 | struct regmap *regs = ssi_private->regs; |
ee9daad4 SH |
702 | int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret; |
703 | u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; | |
d8ced479 | 704 | unsigned long clkrate, baudrate, tmprate; |
ee9daad4 | 705 | u64 sub, savesub = 100000; |
8dd51e23 | 706 | unsigned int freq; |
d429d8e3 | 707 | bool baudclk_is_used; |
8dd51e23 SH |
708 | |
709 | /* Prefer the explicitly set bitclock frequency */ | |
710 | if (ssi_private->bitclk_freq) | |
711 | freq = ssi_private->bitclk_freq; | |
712 | else | |
713 | freq = params_channels(hw_params) * 32 * params_rate(hw_params); | |
ee9daad4 SH |
714 | |
715 | /* Don't apply it to any non-baudclk circumstance */ | |
716 | if (IS_ERR(ssi_private->baudclk)) | |
717 | return -EINVAL; | |
718 | ||
e09745f2 AM |
719 | /* |
720 | * Hardware limitation: The bclk rate must be | |
721 | * never greater than 1/5 IPG clock rate | |
722 | */ | |
723 | if (freq * 5 > clk_get_rate(ssi_private->clk)) { | |
724 | dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n"); | |
725 | return -EINVAL; | |
726 | } | |
727 | ||
d429d8e3 MP |
728 | baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream)); |
729 | ||
ee9daad4 SH |
730 | /* It should be already enough to divide clock by setting pm alone */ |
731 | psr = 0; | |
732 | div2 = 0; | |
733 | ||
734 | factor = (div2 + 1) * (7 * psr + 1) * 2; | |
735 | ||
736 | for (i = 0; i < 255; i++) { | |
6c8ca30e | 737 | tmprate = freq * factor * (i + 1); |
d429d8e3 MP |
738 | |
739 | if (baudclk_is_used) | |
740 | clkrate = clk_get_rate(ssi_private->baudclk); | |
741 | else | |
742 | clkrate = clk_round_rate(ssi_private->baudclk, tmprate); | |
ee9daad4 | 743 | |
acf2c60a TT |
744 | clkrate /= factor; |
745 | afreq = clkrate / (i + 1); | |
ee9daad4 SH |
746 | |
747 | if (freq == afreq) | |
748 | sub = 0; | |
749 | else if (freq / afreq == 1) | |
750 | sub = freq - afreq; | |
751 | else if (afreq / freq == 1) | |
752 | sub = afreq - freq; | |
753 | else | |
754 | continue; | |
755 | ||
756 | /* Calculate the fraction */ | |
757 | sub *= 100000; | |
758 | do_div(sub, freq); | |
759 | ||
ebac95a9 | 760 | if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) { |
ee9daad4 SH |
761 | baudrate = tmprate; |
762 | savesub = sub; | |
763 | pm = i; | |
764 | } | |
765 | ||
766 | /* We are lucky */ | |
767 | if (savesub == 0) | |
768 | break; | |
769 | } | |
770 | ||
771 | /* No proper pm found if it is still remaining the initial value */ | |
772 | if (pm == 999) { | |
773 | dev_err(cpu_dai->dev, "failed to handle the required sysclk\n"); | |
774 | return -EINVAL; | |
775 | } | |
776 | ||
777 | stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) | | |
778 | (psr ? CCSR_SSI_SxCCR_PSR : 0); | |
779 | mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | | |
780 | CCSR_SSI_SxCCR_PSR; | |
781 | ||
8dd51e23 | 782 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous) |
43248122 | 783 | regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr); |
ee9daad4 | 784 | else |
43248122 | 785 | regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr); |
ee9daad4 | 786 | |
d429d8e3 | 787 | if (!baudclk_is_used) { |
ee9daad4 SH |
788 | ret = clk_set_rate(ssi_private->baudclk, baudrate); |
789 | if (ret) { | |
ee9daad4 SH |
790 | dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); |
791 | return -EINVAL; | |
792 | } | |
ee9daad4 | 793 | } |
ee9daad4 SH |
794 | |
795 | return 0; | |
796 | } | |
797 | ||
8dd51e23 SH |
798 | static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai, |
799 | int clk_id, unsigned int freq, int dir) | |
800 | { | |
801 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
802 | ||
803 | ssi_private->bitclk_freq = freq; | |
804 | ||
805 | return 0; | |
806 | } | |
807 | ||
17467f23 | 808 | /** |
85ef2375 | 809 | * fsl_ssi_hw_params - program the sample size |
17467f23 TT |
810 | * |
811 | * Most of the SSI registers have been programmed in the startup function, | |
812 | * but the word length must be programmed here. Unfortunately, programming | |
813 | * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can | |
814 | * cause a problem with supporting simultaneous playback and capture. If | |
815 | * the SSI is already playing a stream, then that stream may be temporarily | |
816 | * stopped when you start capture. | |
817 | * | |
818 | * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the | |
819 | * clock master. | |
820 | */ | |
85ef2375 TT |
821 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
822 | struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai) | |
17467f23 | 823 | { |
f0fba2ad | 824 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); |
43248122 | 825 | struct regmap *regs = ssi_private->regs; |
2924a998 | 826 | unsigned int channels = params_channels(hw_params); |
4ca73043 | 827 | unsigned int sample_size = params_width(hw_params); |
5e538eca | 828 | u32 wl = CCSR_SSI_SxCCR_WL(sample_size); |
8dd51e23 | 829 | int ret; |
43248122 MP |
830 | u32 scr_val; |
831 | int enabled; | |
832 | ||
833 | regmap_read(regs, CCSR_SSI_SCR, &scr_val); | |
834 | enabled = scr_val & CCSR_SSI_SCR_SSIEN; | |
17467f23 | 835 | |
5e538eca TT |
836 | /* |
837 | * If we're in synchronous mode, and the SSI is already enabled, | |
838 | * then STCCR is already set properly. | |
839 | */ | |
840 | if (enabled && ssi_private->cpu_dai_drv.symmetric_rates) | |
841 | return 0; | |
17467f23 | 842 | |
8dd51e23 SH |
843 | if (fsl_ssi_is_i2s_master(ssi_private)) { |
844 | ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params); | |
845 | if (ret) | |
846 | return ret; | |
d429d8e3 MP |
847 | |
848 | /* Do not enable the clock if it is already enabled */ | |
849 | if (!(ssi_private->baudclk_streams & BIT(substream->stream))) { | |
850 | ret = clk_prepare_enable(ssi_private->baudclk); | |
851 | if (ret) | |
852 | return ret; | |
853 | ||
854 | ssi_private->baudclk_streams |= BIT(substream->stream); | |
855 | } | |
8dd51e23 SH |
856 | } |
857 | ||
cf4f7fc3 FF |
858 | if (!fsl_ssi_is_ac97(ssi_private)) { |
859 | u8 i2smode; | |
860 | /* | |
861 | * Switch to normal net mode in order to have a frame sync | |
862 | * signal every 32 bits instead of 16 bits | |
863 | */ | |
864 | if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16) | |
865 | i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL | | |
866 | CCSR_SSI_SCR_NET; | |
867 | else | |
868 | i2smode = ssi_private->i2s_mode; | |
869 | ||
870 | regmap_update_bits(regs, CCSR_SSI_SCR, | |
871 | CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK, | |
872 | channels == 1 ? 0 : i2smode); | |
873 | } | |
874 | ||
5e538eca TT |
875 | /* |
876 | * FIXME: The documentation says that SxCCR[WL] should not be | |
877 | * modified while the SSI is enabled. The only time this can | |
878 | * happen is if we're trying to do simultaneous playback and | |
879 | * capture in asynchronous mode. Unfortunately, I have been enable | |
880 | * to get that to work at all on the P1022DS. Therefore, we don't | |
881 | * bother to disable/enable the SSI when setting SxCCR[WL], because | |
882 | * the SSI will stop anyway. Maybe one day, this will get fixed. | |
883 | */ | |
17467f23 | 884 | |
5e538eca TT |
885 | /* In synchronous mode, the SSI uses STCCR for capture */ |
886 | if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) || | |
887 | ssi_private->cpu_dai_drv.symmetric_rates) | |
43248122 MP |
888 | regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK, |
889 | wl); | |
5e538eca | 890 | else |
43248122 MP |
891 | regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK, |
892 | wl); | |
17467f23 TT |
893 | |
894 | return 0; | |
895 | } | |
896 | ||
d429d8e3 MP |
897 | static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, |
898 | struct snd_soc_dai *cpu_dai) | |
899 | { | |
900 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
901 | struct fsl_ssi_private *ssi_private = | |
902 | snd_soc_dai_get_drvdata(rtd->cpu_dai); | |
903 | ||
904 | if (fsl_ssi_is_i2s_master(ssi_private) && | |
905 | ssi_private->baudclk_streams & BIT(substream->stream)) { | |
906 | clk_disable_unprepare(ssi_private->baudclk); | |
907 | ssi_private->baudclk_streams &= ~BIT(substream->stream); | |
908 | } | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
85151461 MT |
913 | static int _fsl_ssi_set_dai_fmt(struct device *dev, |
914 | struct fsl_ssi_private *ssi_private, | |
915 | unsigned int fmt) | |
aafa85e7 | 916 | { |
43248122 | 917 | struct regmap *regs = ssi_private->regs; |
aafa85e7 | 918 | u32 strcr = 0, stcr, srcr, scr, mask; |
2b0db996 MP |
919 | u8 wm; |
920 | ||
171d683d MP |
921 | ssi_private->dai_fmt = fmt; |
922 | ||
d429d8e3 | 923 | if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) { |
85151461 | 924 | dev_err(dev, "baudclk is missing which is necessary for master mode\n"); |
d429d8e3 MP |
925 | return -EINVAL; |
926 | } | |
927 | ||
2b0db996 | 928 | fsl_ssi_setup_reg_vals(ssi_private); |
aafa85e7 | 929 | |
43248122 MP |
930 | regmap_read(regs, CCSR_SSI_SCR, &scr); |
931 | scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); | |
50489479 | 932 | scr |= CCSR_SSI_SCR_SYNC_TX_FS; |
aafa85e7 NC |
933 | |
934 | mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR | | |
935 | CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL | | |
936 | CCSR_SSI_STCR_TEFS; | |
43248122 MP |
937 | regmap_read(regs, CCSR_SSI_STCR, &stcr); |
938 | regmap_read(regs, CCSR_SSI_SRCR, &srcr); | |
939 | stcr &= ~mask; | |
940 | srcr &= ~mask; | |
aafa85e7 | 941 | |
07a28dbe | 942 | ssi_private->i2s_mode = CCSR_SSI_SCR_NET; |
aafa85e7 NC |
943 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
944 | case SND_SOC_DAIFMT_I2S: | |
4f14f5c1 AS |
945 | regmap_update_bits(regs, CCSR_SSI_STCCR, |
946 | CCSR_SSI_SxCCR_DC_MASK, | |
947 | CCSR_SSI_SxCCR_DC(2)); | |
948 | regmap_update_bits(regs, CCSR_SSI_SRCCR, | |
949 | CCSR_SSI_SxCCR_DC_MASK, | |
950 | CCSR_SSI_SxCCR_DC(2)); | |
aafa85e7 | 951 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
cf4f7fc3 | 952 | case SND_SOC_DAIFMT_CBM_CFS: |
aafa85e7 | 953 | case SND_SOC_DAIFMT_CBS_CFS: |
07a28dbe | 954 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER; |
aafa85e7 NC |
955 | break; |
956 | case SND_SOC_DAIFMT_CBM_CFM: | |
07a28dbe | 957 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE; |
aafa85e7 NC |
958 | break; |
959 | default: | |
960 | return -EINVAL; | |
961 | } | |
aafa85e7 NC |
962 | |
963 | /* Data on rising edge of bclk, frame low, 1clk before data */ | |
964 | strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP | | |
965 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
966 | break; | |
967 | case SND_SOC_DAIFMT_LEFT_J: | |
968 | /* Data on rising edge of bclk, frame high */ | |
969 | strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP; | |
970 | break; | |
971 | case SND_SOC_DAIFMT_DSP_A: | |
972 | /* Data on rising edge of bclk, frame high, 1clk before data */ | |
973 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
974 | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS; | |
975 | break; | |
976 | case SND_SOC_DAIFMT_DSP_B: | |
977 | /* Data on rising edge of bclk, frame high */ | |
978 | strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP | | |
979 | CCSR_SSI_STCR_TXBIT0; | |
980 | break; | |
2b0db996 | 981 | case SND_SOC_DAIFMT_AC97: |
07a28dbe | 982 | ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL; |
2b0db996 | 983 | break; |
aafa85e7 NC |
984 | default: |
985 | return -EINVAL; | |
986 | } | |
2b0db996 | 987 | scr |= ssi_private->i2s_mode; |
aafa85e7 NC |
988 | |
989 | /* DAI clock inversion */ | |
990 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
991 | case SND_SOC_DAIFMT_NB_NF: | |
992 | /* Nothing to do for both normal cases */ | |
993 | break; | |
994 | case SND_SOC_DAIFMT_IB_NF: | |
995 | /* Invert bit clock */ | |
996 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
997 | break; | |
998 | case SND_SOC_DAIFMT_NB_IF: | |
999 | /* Invert frame clock */ | |
1000 | strcr ^= CCSR_SSI_STCR_TFSI; | |
1001 | break; | |
1002 | case SND_SOC_DAIFMT_IB_IF: | |
1003 | /* Invert both clocks */ | |
1004 | strcr ^= CCSR_SSI_STCR_TSCKP; | |
1005 | strcr ^= CCSR_SSI_STCR_TFSI; | |
1006 | break; | |
1007 | default: | |
1008 | return -EINVAL; | |
1009 | } | |
1010 | ||
1011 | /* DAI clock master masks */ | |
1012 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1013 | case SND_SOC_DAIFMT_CBS_CFS: | |
1014 | strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR; | |
1015 | scr |= CCSR_SSI_SCR_SYS_CLK_EN; | |
1016 | break; | |
1017 | case SND_SOC_DAIFMT_CBM_CFM: | |
1018 | scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; | |
1019 | break; | |
cf4f7fc3 FF |
1020 | case SND_SOC_DAIFMT_CBM_CFS: |
1021 | strcr &= ~CCSR_SSI_STCR_TXDIR; | |
1022 | strcr |= CCSR_SSI_STCR_TFDIR; | |
1023 | scr &= ~CCSR_SSI_SCR_SYS_CLK_EN; | |
1024 | break; | |
aafa85e7 | 1025 | default: |
dce0332c MS |
1026 | if (!fsl_ssi_is_ac97(ssi_private)) |
1027 | return -EINVAL; | |
aafa85e7 NC |
1028 | } |
1029 | ||
1030 | stcr |= strcr; | |
1031 | srcr |= strcr; | |
1032 | ||
dce0332c MS |
1033 | if (ssi_private->cpu_dai_drv.symmetric_rates |
1034 | || fsl_ssi_is_ac97(ssi_private)) { | |
1035 | /* Need to clear RXDIR when using SYNC or AC97 mode */ | |
aafa85e7 NC |
1036 | srcr &= ~CCSR_SSI_SRCR_RXDIR; |
1037 | scr |= CCSR_SSI_SCR_SYN; | |
1038 | } | |
1039 | ||
43248122 MP |
1040 | regmap_write(regs, CCSR_SSI_STCR, stcr); |
1041 | regmap_write(regs, CCSR_SSI_SRCR, srcr); | |
1042 | regmap_write(regs, CCSR_SSI_SCR, scr); | |
aafa85e7 | 1043 | |
2b0db996 MP |
1044 | /* |
1045 | * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't | |
1046 | * use FIFO 1. We program the transmit water to signal a DMA transfer | |
1047 | * if there are only two (or fewer) elements left in the FIFO. Two | |
1048 | * elements equals one frame (left channel, right channel). This value, | |
1049 | * however, depends on the depth of the transmit buffer. | |
1050 | * | |
1051 | * We set the watermark on the same level as the DMA burstsize. For | |
1052 | * fiq it is probably better to use the biggest possible watermark | |
1053 | * size. | |
1054 | */ | |
1055 | if (ssi_private->use_dma) | |
1056 | wm = ssi_private->fifo_depth - 2; | |
1057 | else | |
1058 | wm = ssi_private->fifo_depth; | |
1059 | ||
43248122 MP |
1060 | regmap_write(regs, CCSR_SSI_SFCSR, |
1061 | CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) | | |
1062 | CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm)); | |
2b0db996 MP |
1063 | |
1064 | if (ssi_private->use_dual_fifo) { | |
43248122 | 1065 | regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1, |
2b0db996 | 1066 | CCSR_SSI_SRCR_RFEN1); |
43248122 | 1067 | regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1, |
2b0db996 | 1068 | CCSR_SSI_STCR_TFEN1); |
43248122 | 1069 | regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN, |
2b0db996 MP |
1070 | CCSR_SSI_SCR_TCH_EN); |
1071 | } | |
1072 | ||
5b64c173 | 1073 | if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97) |
2b0db996 MP |
1074 | fsl_ssi_setup_ac97(ssi_private); |
1075 | ||
aafa85e7 | 1076 | return 0; |
85e59af2 MP |
1077 | |
1078 | } | |
1079 | ||
1080 | /** | |
1081 | * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format. | |
1082 | */ | |
1083 | static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
1084 | { | |
1085 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
1086 | ||
85151461 | 1087 | return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt); |
aafa85e7 NC |
1088 | } |
1089 | ||
aafa85e7 NC |
1090 | /** |
1091 | * fsl_ssi_set_dai_tdm_slot - set TDM slot number | |
1092 | * | |
1093 | * Note: This function can be only called when using SSI as DAI master | |
1094 | */ | |
1095 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, | |
1096 | u32 rx_mask, int slots, int slot_width) | |
1097 | { | |
1098 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai); | |
43248122 | 1099 | struct regmap *regs = ssi_private->regs; |
aafa85e7 NC |
1100 | u32 val; |
1101 | ||
1102 | /* The slot number should be >= 2 if using Network mode or I2S mode */ | |
43248122 MP |
1103 | regmap_read(regs, CCSR_SSI_SCR, &val); |
1104 | val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET; | |
aafa85e7 NC |
1105 | if (val && slots < 2) { |
1106 | dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n"); | |
1107 | return -EINVAL; | |
1108 | } | |
1109 | ||
43248122 | 1110 | regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK, |
aafa85e7 | 1111 | CCSR_SSI_SxCCR_DC(slots)); |
43248122 | 1112 | regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK, |
aafa85e7 NC |
1113 | CCSR_SSI_SxCCR_DC(slots)); |
1114 | ||
1115 | /* The register SxMSKs needs SSI to provide essential clock due to | |
1116 | * hardware design. So we here temporarily enable SSI to set them. | |
1117 | */ | |
43248122 MP |
1118 | regmap_read(regs, CCSR_SSI_SCR, &val); |
1119 | val &= CCSR_SSI_SCR_SSIEN; | |
1120 | regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, | |
1121 | CCSR_SSI_SCR_SSIEN); | |
aafa85e7 | 1122 | |
d0077aaf LPC |
1123 | regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask); |
1124 | regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask); | |
aafa85e7 | 1125 | |
43248122 | 1126 | regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val); |
aafa85e7 NC |
1127 | |
1128 | return 0; | |
1129 | } | |
1130 | ||
17467f23 TT |
1131 | /** |
1132 | * fsl_ssi_trigger: start and stop the DMA transfer. | |
1133 | * | |
1134 | * This function is called by ALSA to start, stop, pause, and resume the DMA | |
1135 | * transfer of data. | |
1136 | * | |
1137 | * The DMA channel is in external master start and pause mode, which | |
1138 | * means the SSI completely controls the flow of data. | |
1139 | */ | |
dee89c4d MB |
1140 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
1141 | struct snd_soc_dai *dai) | |
17467f23 TT |
1142 | { |
1143 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 1144 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
43248122 | 1145 | struct regmap *regs = ssi_private->regs; |
9b443e3d | 1146 | |
17467f23 TT |
1147 | switch (cmd) { |
1148 | case SNDRV_PCM_TRIGGER_START: | |
b20e53a8 | 1149 | case SNDRV_PCM_TRIGGER_RESUME: |
17467f23 | 1150 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
a4d11fe5 | 1151 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
6de83879 | 1152 | fsl_ssi_tx_config(ssi_private, true); |
a4d11fe5 | 1153 | else |
6de83879 | 1154 | fsl_ssi_rx_config(ssi_private, true); |
17467f23 TT |
1155 | break; |
1156 | ||
1157 | case SNDRV_PCM_TRIGGER_STOP: | |
b20e53a8 | 1158 | case SNDRV_PCM_TRIGGER_SUSPEND: |
17467f23 TT |
1159 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
1160 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
6de83879 | 1161 | fsl_ssi_tx_config(ssi_private, false); |
17467f23 | 1162 | else |
6de83879 | 1163 | fsl_ssi_rx_config(ssi_private, false); |
17467f23 TT |
1164 | break; |
1165 | ||
1166 | default: | |
1167 | return -EINVAL; | |
1168 | } | |
1169 | ||
171d683d | 1170 | if (fsl_ssi_is_ac97(ssi_private)) { |
a5a7ee7c | 1171 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
43248122 | 1172 | regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR); |
a5a7ee7c | 1173 | else |
43248122 | 1174 | regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR); |
a5a7ee7c | 1175 | } |
9b443e3d | 1176 | |
17467f23 TT |
1177 | return 0; |
1178 | } | |
1179 | ||
fc8ba7f9 LPC |
1180 | static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) |
1181 | { | |
1182 | struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai); | |
1183 | ||
fcdbadef | 1184 | if (ssi_private->soc->imx && ssi_private->use_dma) { |
fc8ba7f9 LPC |
1185 | dai->playback_dma_data = &ssi_private->dma_params_tx; |
1186 | dai->capture_dma_data = &ssi_private->dma_params_rx; | |
1187 | } | |
1188 | ||
1189 | return 0; | |
1190 | } | |
1191 | ||
85e7652d | 1192 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
6335d055 | 1193 | .startup = fsl_ssi_startup, |
f4a43cab | 1194 | .shutdown = fsl_ssi_shutdown, |
6335d055 | 1195 | .hw_params = fsl_ssi_hw_params, |
d429d8e3 | 1196 | .hw_free = fsl_ssi_hw_free, |
aafa85e7 NC |
1197 | .set_fmt = fsl_ssi_set_dai_fmt, |
1198 | .set_sysclk = fsl_ssi_set_dai_sysclk, | |
1199 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, | |
6335d055 | 1200 | .trigger = fsl_ssi_trigger, |
6335d055 EM |
1201 | }; |
1202 | ||
f0fba2ad LG |
1203 | /* Template for the CPU dai driver structure */ |
1204 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { | |
fc8ba7f9 | 1205 | .probe = fsl_ssi_dai_probe, |
17467f23 | 1206 | .playback = { |
e3655004 | 1207 | .stream_name = "CPU-Playback", |
2924a998 | 1208 | .channels_min = 1, |
48a260ee | 1209 | .channels_max = 32, |
58055677 | 1210 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
17467f23 TT |
1211 | .formats = FSLSSI_I2S_FORMATS, |
1212 | }, | |
1213 | .capture = { | |
e3655004 | 1214 | .stream_name = "CPU-Capture", |
2924a998 | 1215 | .channels_min = 1, |
48a260ee | 1216 | .channels_max = 32, |
58055677 | 1217 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
17467f23 TT |
1218 | .formats = FSLSSI_I2S_FORMATS, |
1219 | }, | |
6335d055 | 1220 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
1221 | }; |
1222 | ||
3580aa10 KM |
1223 | static const struct snd_soc_component_driver fsl_ssi_component = { |
1224 | .name = "fsl-ssi", | |
1225 | }; | |
1226 | ||
cd7f0295 | 1227 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { |
bc263214 | 1228 | .bus_control = true, |
793e3e9e | 1229 | .probe = fsl_ssi_dai_probe, |
cd7f0295 MP |
1230 | .playback = { |
1231 | .stream_name = "AC97 Playback", | |
1232 | .channels_min = 2, | |
1233 | .channels_max = 2, | |
1234 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1235 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
1236 | }, | |
1237 | .capture = { | |
1238 | .stream_name = "AC97 Capture", | |
1239 | .channels_min = 2, | |
1240 | .channels_max = 2, | |
1241 | .rates = SNDRV_PCM_RATE_48000, | |
1242 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
1243 | }, | |
a5a7ee7c | 1244 | .ops = &fsl_ssi_dai_ops, |
cd7f0295 MP |
1245 | }; |
1246 | ||
1247 | ||
1248 | static struct fsl_ssi_private *fsl_ac97_data; | |
1249 | ||
a851a2bb | 1250 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
cd7f0295 MP |
1251 | unsigned short val) |
1252 | { | |
43248122 | 1253 | struct regmap *regs = fsl_ac97_data->regs; |
cd7f0295 MP |
1254 | unsigned int lreg; |
1255 | unsigned int lval; | |
8277df3c | 1256 | int ret; |
cd7f0295 MP |
1257 | |
1258 | if (reg > 0x7f) | |
1259 | return; | |
1260 | ||
8277df3c MS |
1261 | ret = clk_prepare_enable(fsl_ac97_data->clk); |
1262 | if (ret) { | |
1263 | pr_err("ac97 write clk_prepare_enable failed: %d\n", | |
1264 | ret); | |
1265 | return; | |
1266 | } | |
cd7f0295 MP |
1267 | |
1268 | lreg = reg << 12; | |
43248122 | 1269 | regmap_write(regs, CCSR_SSI_SACADD, lreg); |
cd7f0295 MP |
1270 | |
1271 | lval = val << 4; | |
43248122 | 1272 | regmap_write(regs, CCSR_SSI_SACDAT, lval); |
cd7f0295 | 1273 | |
43248122 | 1274 | regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, |
cd7f0295 MP |
1275 | CCSR_SSI_SACNT_WR); |
1276 | udelay(100); | |
8277df3c MS |
1277 | |
1278 | clk_disable_unprepare(fsl_ac97_data->clk); | |
cd7f0295 MP |
1279 | } |
1280 | ||
a851a2bb | 1281 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
cd7f0295 MP |
1282 | unsigned short reg) |
1283 | { | |
43248122 | 1284 | struct regmap *regs = fsl_ac97_data->regs; |
cd7f0295 MP |
1285 | |
1286 | unsigned short val = -1; | |
43248122 | 1287 | u32 reg_val; |
cd7f0295 | 1288 | unsigned int lreg; |
8277df3c MS |
1289 | int ret; |
1290 | ||
1291 | ret = clk_prepare_enable(fsl_ac97_data->clk); | |
1292 | if (ret) { | |
1293 | pr_err("ac97 read clk_prepare_enable failed: %d\n", | |
1294 | ret); | |
1295 | return -1; | |
1296 | } | |
cd7f0295 MP |
1297 | |
1298 | lreg = (reg & 0x7f) << 12; | |
43248122 MP |
1299 | regmap_write(regs, CCSR_SSI_SACADD, lreg); |
1300 | regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, | |
cd7f0295 MP |
1301 | CCSR_SSI_SACNT_RD); |
1302 | ||
1303 | udelay(100); | |
1304 | ||
43248122 MP |
1305 | regmap_read(regs, CCSR_SSI_SACDAT, ®_val); |
1306 | val = (reg_val >> 4) & 0xffff; | |
cd7f0295 | 1307 | |
8277df3c MS |
1308 | clk_disable_unprepare(fsl_ac97_data->clk); |
1309 | ||
cd7f0295 MP |
1310 | return val; |
1311 | } | |
1312 | ||
1313 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { | |
1314 | .read = fsl_ssi_ac97_read, | |
1315 | .write = fsl_ssi_ac97_write, | |
1316 | }; | |
1317 | ||
17467f23 | 1318 | /** |
f0fba2ad | 1319 | * Make every character in a string lower-case |
17467f23 | 1320 | */ |
f0fba2ad LG |
1321 | static void make_lowercase(char *s) |
1322 | { | |
1323 | char *p = s; | |
1324 | char c; | |
1325 | ||
1326 | while ((c = *p)) { | |
1327 | if ((c >= 'A') && (c <= 'Z')) | |
1328 | *p = c + ('a' - 'A'); | |
1329 | p++; | |
1330 | } | |
1331 | } | |
1332 | ||
49da09e2 | 1333 | static int fsl_ssi_imx_probe(struct platform_device *pdev, |
4d9b7926 | 1334 | struct fsl_ssi_private *ssi_private, void __iomem *iomem) |
49da09e2 MP |
1335 | { |
1336 | struct device_node *np = pdev->dev.of_node; | |
ed0f1604 | 1337 | u32 dmas[4]; |
49da09e2 MP |
1338 | int ret; |
1339 | ||
f4a43cab SW |
1340 | if (ssi_private->has_ipg_clk_name) |
1341 | ssi_private->clk = devm_clk_get(&pdev->dev, "ipg"); | |
1342 | else | |
1343 | ssi_private->clk = devm_clk_get(&pdev->dev, NULL); | |
49da09e2 MP |
1344 | if (IS_ERR(ssi_private->clk)) { |
1345 | ret = PTR_ERR(ssi_private->clk); | |
1346 | dev_err(&pdev->dev, "could not get clock: %d\n", ret); | |
1347 | return ret; | |
1348 | } | |
1349 | ||
f4a43cab SW |
1350 | if (!ssi_private->has_ipg_clk_name) { |
1351 | ret = clk_prepare_enable(ssi_private->clk); | |
1352 | if (ret) { | |
1353 | dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret); | |
1354 | return ret; | |
1355 | } | |
49da09e2 MP |
1356 | } |
1357 | ||
dcfcf2c2 | 1358 | /* For those SLAVE implementations, we ignore non-baudclk cases |
49da09e2 MP |
1359 | * and, instead, abandon MASTER mode that needs baud clock. |
1360 | */ | |
1361 | ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud"); | |
1362 | if (IS_ERR(ssi_private->baudclk)) | |
1363 | dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", | |
1364 | PTR_ERR(ssi_private->baudclk)); | |
49da09e2 MP |
1365 | |
1366 | /* | |
1367 | * We have burstsize be "fifo_depth - 2" to match the SSI | |
1368 | * watermark setting in fsl_ssi_startup(). | |
1369 | */ | |
1370 | ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2; | |
1371 | ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2; | |
43248122 MP |
1372 | ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0; |
1373 | ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0; | |
49da09e2 | 1374 | |
90aff15b | 1375 | ret = of_property_read_u32_array(np, "dmas", dmas, 4); |
ed0f1604 | 1376 | if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) { |
49da09e2 MP |
1377 | ssi_private->use_dual_fifo = true; |
1378 | /* When using dual fifo mode, we need to keep watermark | |
1379 | * as even numbers due to dma script limitation. | |
1380 | */ | |
1381 | ssi_private->dma_params_tx.maxburst &= ~0x1; | |
1382 | ssi_private->dma_params_rx.maxburst &= ~0x1; | |
1383 | } | |
1384 | ||
4d9b7926 MP |
1385 | if (!ssi_private->use_dma) { |
1386 | ||
1387 | /* | |
1388 | * Some boards use an incompatible codec. To get it | |
1389 | * working, we are using imx-fiq-pcm-audio, that | |
1390 | * can handle those codecs. DMA is not possible in this | |
1391 | * situation. | |
1392 | */ | |
1393 | ||
1394 | ssi_private->fiq_params.irq = ssi_private->irq; | |
1395 | ssi_private->fiq_params.base = iomem; | |
1396 | ssi_private->fiq_params.dma_params_rx = | |
1397 | &ssi_private->dma_params_rx; | |
1398 | ssi_private->fiq_params.dma_params_tx = | |
1399 | &ssi_private->dma_params_tx; | |
1400 | ||
1401 | ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params); | |
1402 | if (ret) | |
1403 | goto error_pcm; | |
1404 | } else { | |
0d69e0dd | 1405 | ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE); |
4d9b7926 MP |
1406 | if (ret) |
1407 | goto error_pcm; | |
1408 | } | |
1409 | ||
49da09e2 | 1410 | return 0; |
4d9b7926 MP |
1411 | |
1412 | error_pcm: | |
4d9b7926 | 1413 | |
f4a43cab SW |
1414 | if (!ssi_private->has_ipg_clk_name) |
1415 | clk_disable_unprepare(ssi_private->clk); | |
4d9b7926 | 1416 | return ret; |
49da09e2 MP |
1417 | } |
1418 | ||
1419 | static void fsl_ssi_imx_clean(struct platform_device *pdev, | |
1420 | struct fsl_ssi_private *ssi_private) | |
1421 | { | |
4d9b7926 MP |
1422 | if (!ssi_private->use_dma) |
1423 | imx_pcm_fiq_exit(pdev); | |
f4a43cab SW |
1424 | if (!ssi_private->has_ipg_clk_name) |
1425 | clk_disable_unprepare(ssi_private->clk); | |
49da09e2 MP |
1426 | } |
1427 | ||
a0a3d518 | 1428 | static int fsl_ssi_probe(struct platform_device *pdev) |
17467f23 | 1429 | { |
17467f23 TT |
1430 | struct fsl_ssi_private *ssi_private; |
1431 | int ret = 0; | |
38fec727 | 1432 | struct device_node *np = pdev->dev.of_node; |
c1953bfe | 1433 | const struct of_device_id *of_id; |
f0fba2ad | 1434 | const char *p, *sprop; |
8e9d8690 | 1435 | const uint32_t *iprop; |
ca264189 | 1436 | struct resource *res; |
43248122 | 1437 | void __iomem *iomem; |
f0fba2ad | 1438 | char name[64]; |
6139b1b1 | 1439 | struct regmap_config regconfig = fsl_ssi_regconfig; |
17467f23 | 1440 | |
c1953bfe | 1441 | of_id = of_match_device(fsl_ssi_ids, &pdev->dev); |
fcdbadef | 1442 | if (!of_id || !of_id->data) |
c1953bfe | 1443 | return -EINVAL; |
c1953bfe | 1444 | |
2a1d102d MP |
1445 | ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private), |
1446 | GFP_KERNEL); | |
17467f23 | 1447 | if (!ssi_private) { |
38fec727 | 1448 | dev_err(&pdev->dev, "could not allocate DAI object\n"); |
f0fba2ad | 1449 | return -ENOMEM; |
17467f23 | 1450 | } |
17467f23 | 1451 | |
fcdbadef | 1452 | ssi_private->soc = of_id->data; |
0096b693 | 1453 | ssi_private->dev = &pdev->dev; |
fcdbadef | 1454 | |
85e59af2 MP |
1455 | sprop = of_get_property(np, "fsl,mode", NULL); |
1456 | if (sprop) { | |
1457 | if (!strcmp(sprop, "ac97-slave")) | |
1458 | ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97; | |
85e59af2 MP |
1459 | } |
1460 | ||
de623ece MP |
1461 | ssi_private->use_dma = !of_property_read_bool(np, |
1462 | "fsl,fiq-stream-filter"); | |
1463 | ||
85e59af2 | 1464 | if (fsl_ssi_is_ac97(ssi_private)) { |
cd7f0295 MP |
1465 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai, |
1466 | sizeof(fsl_ssi_ac97_dai)); | |
1467 | ||
1468 | fsl_ac97_data = ssi_private; | |
cd7f0295 | 1469 | |
04143d61 MS |
1470 | ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); |
1471 | if (ret) { | |
1472 | dev_err(&pdev->dev, "could not set AC'97 ops\n"); | |
1473 | return ret; | |
1474 | } | |
cd7f0295 MP |
1475 | } else { |
1476 | /* Initialize this copy of the CPU DAI driver structure */ | |
1477 | memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template, | |
1478 | sizeof(fsl_ssi_dai_template)); | |
1479 | } | |
2a1d102d | 1480 | ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev); |
f0fba2ad | 1481 | |
ca264189 FE |
1482 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1483 | iomem = devm_ioremap_resource(&pdev->dev, res); | |
1484 | if (IS_ERR(iomem)) | |
1485 | return PTR_ERR(iomem); | |
1486 | ssi_private->ssi_phys = res->start; | |
43248122 | 1487 | |
6139b1b1 MS |
1488 | if (ssi_private->soc->imx21regs) { |
1489 | /* | |
1490 | * According to datasheet imx21-class SSI | |
1491 | * don't have SACC{ST,EN,DIS} regs. | |
1492 | */ | |
1493 | regconfig.max_register = CCSR_SSI_SRMSK; | |
f26b3b2a MB |
1494 | regconfig.num_reg_defaults_raw = |
1495 | CCSR_SSI_SRMSK / sizeof(uint32_t) + 1; | |
6139b1b1 MS |
1496 | } |
1497 | ||
f4a43cab SW |
1498 | ret = of_property_match_string(np, "clock-names", "ipg"); |
1499 | if (ret < 0) { | |
1500 | ssi_private->has_ipg_clk_name = false; | |
1501 | ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem, | |
6139b1b1 | 1502 | ®config); |
f4a43cab SW |
1503 | } else { |
1504 | ssi_private->has_ipg_clk_name = true; | |
1505 | ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev, | |
6139b1b1 | 1506 | "ipg", iomem, ®config); |
f4a43cab | 1507 | } |
43248122 MP |
1508 | if (IS_ERR(ssi_private->regs)) { |
1509 | dev_err(&pdev->dev, "Failed to init register map\n"); | |
1510 | return PTR_ERR(ssi_private->regs); | |
1511 | } | |
1fab6caf | 1512 | |
2ffa5310 | 1513 | ssi_private->irq = platform_get_irq(pdev, 0); |
28ecc0b6 | 1514 | if (ssi_private->irq < 0) { |
0c123250 | 1515 | dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); |
64aa5f58 | 1516 | return ssi_private->irq; |
1fab6caf TT |
1517 | } |
1518 | ||
f0fba2ad | 1519 | /* Are the RX and the TX clocks locked? */ |
07a9483a | 1520 | if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { |
06cb3736 MS |
1521 | if (!fsl_ssi_is_ac97(ssi_private)) |
1522 | ssi_private->cpu_dai_drv.symmetric_rates = 1; | |
1523 | ||
07a9483a NC |
1524 | ssi_private->cpu_dai_drv.symmetric_channels = 1; |
1525 | ssi_private->cpu_dai_drv.symmetric_samplebits = 1; | |
1526 | } | |
17467f23 | 1527 | |
8e9d8690 TT |
1528 | /* Determine the FIFO depth. */ |
1529 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); | |
1530 | if (iprop) | |
147dfe90 | 1531 | ssi_private->fifo_depth = be32_to_cpup(iprop); |
8e9d8690 TT |
1532 | else |
1533 | /* Older 8610 DTs didn't have the fifo-depth property */ | |
1534 | ssi_private->fifo_depth = 8; | |
1535 | ||
4d9b7926 MP |
1536 | dev_set_drvdata(&pdev->dev, ssi_private); |
1537 | ||
fcdbadef | 1538 | if (ssi_private->soc->imx) { |
43248122 | 1539 | ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem); |
49da09e2 | 1540 | if (ret) |
2ffa5310 | 1541 | return ret; |
0888efd1 MP |
1542 | } |
1543 | ||
299e7e97 FE |
1544 | ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component, |
1545 | &ssi_private->cpu_dai_drv, 1); | |
4d9b7926 MP |
1546 | if (ret) { |
1547 | dev_err(&pdev->dev, "failed to register DAI: %d\n", ret); | |
1548 | goto error_asoc_register; | |
1549 | } | |
1550 | ||
0888efd1 | 1551 | if (ssi_private->use_dma) { |
f0377086 | 1552 | ret = devm_request_irq(&pdev->dev, ssi_private->irq, |
171d683d | 1553 | fsl_ssi_isr, 0, dev_name(&pdev->dev), |
f0377086 MG |
1554 | ssi_private); |
1555 | if (ret < 0) { | |
1556 | dev_err(&pdev->dev, "could not claim irq %u\n", | |
1557 | ssi_private->irq); | |
299e7e97 | 1558 | goto error_asoc_register; |
f0377086 | 1559 | } |
09ce1111 SG |
1560 | } |
1561 | ||
f138e621 | 1562 | ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev); |
9368acc4 | 1563 | if (ret) |
299e7e97 | 1564 | goto error_asoc_register; |
09ce1111 SG |
1565 | |
1566 | /* | |
1567 | * If codec-handle property is missing from SSI node, we assume | |
1568 | * that the machine driver uses new binding which does not require | |
1569 | * SSI driver to trigger machine driver's probe. | |
1570 | */ | |
171d683d | 1571 | if (!of_get_property(np, "codec-handle", NULL)) |
09ce1111 | 1572 | goto done; |
09ce1111 | 1573 | |
f0fba2ad | 1574 | /* Trigger the machine driver's probe function. The platform driver |
2b81ec69 | 1575 | * name of the machine driver is taken from /compatible property of the |
f0fba2ad LG |
1576 | * device tree. We also pass the address of the CPU DAI driver |
1577 | * structure. | |
1578 | */ | |
2b81ec69 SG |
1579 | sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL); |
1580 | /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */ | |
f0fba2ad LG |
1581 | p = strrchr(sprop, ','); |
1582 | if (p) | |
1583 | sprop = p + 1; | |
1584 | snprintf(name, sizeof(name), "snd-soc-%s", sprop); | |
1585 | make_lowercase(name); | |
1586 | ||
1587 | ssi_private->pdev = | |
38fec727 | 1588 | platform_device_register_data(&pdev->dev, name, 0, NULL, 0); |
f0fba2ad LG |
1589 | if (IS_ERR(ssi_private->pdev)) { |
1590 | ret = PTR_ERR(ssi_private->pdev); | |
38fec727 | 1591 | dev_err(&pdev->dev, "failed to register platform: %d\n", ret); |
4d9b7926 | 1592 | goto error_sound_card; |
3f4b783c | 1593 | } |
17467f23 | 1594 | |
09ce1111 | 1595 | done: |
85e59af2 | 1596 | if (ssi_private->dai_fmt) |
85151461 MT |
1597 | _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private, |
1598 | ssi_private->dai_fmt); | |
85e59af2 | 1599 | |
8ed0c842 MS |
1600 | if (fsl_ssi_is_ac97(ssi_private)) { |
1601 | u32 ssi_idx; | |
1602 | ||
1603 | ret = of_property_read_u32(np, "cell-index", &ssi_idx); | |
1604 | if (ret) { | |
1605 | dev_err(&pdev->dev, "cannot get SSI index property\n"); | |
1606 | goto error_sound_card; | |
1607 | } | |
1608 | ||
1609 | ssi_private->pdev = | |
1610 | platform_device_register_data(NULL, | |
1611 | "ac97-codec", ssi_idx, NULL, 0); | |
1612 | if (IS_ERR(ssi_private->pdev)) { | |
1613 | ret = PTR_ERR(ssi_private->pdev); | |
1614 | dev_err(&pdev->dev, | |
1615 | "failed to register AC97 codec platform: %d\n", | |
1616 | ret); | |
1617 | goto error_sound_card; | |
1618 | } | |
1619 | } | |
1620 | ||
f0fba2ad | 1621 | return 0; |
87a0632b | 1622 | |
4d9b7926 | 1623 | error_sound_card: |
f138e621 | 1624 | fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); |
9368acc4 | 1625 | |
4d9b7926 | 1626 | error_asoc_register: |
fcdbadef | 1627 | if (ssi_private->soc->imx) |
49da09e2 | 1628 | fsl_ssi_imx_clean(pdev, ssi_private); |
1fab6caf | 1629 | |
87a0632b | 1630 | return ret; |
17467f23 | 1631 | } |
17467f23 | 1632 | |
38fec727 | 1633 | static int fsl_ssi_remove(struct platform_device *pdev) |
17467f23 | 1634 | { |
38fec727 | 1635 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev); |
17467f23 | 1636 | |
f138e621 | 1637 | fsl_ssi_debugfs_remove(&ssi_private->dbg_stats); |
9368acc4 | 1638 | |
171d683d | 1639 | if (ssi_private->pdev) |
09ce1111 | 1640 | platform_device_unregister(ssi_private->pdev); |
49da09e2 | 1641 | |
fcdbadef | 1642 | if (ssi_private->soc->imx) |
49da09e2 MP |
1643 | fsl_ssi_imx_clean(pdev, ssi_private); |
1644 | ||
04143d61 MS |
1645 | if (fsl_ssi_is_ac97(ssi_private)) |
1646 | snd_soc_set_ac97_ops(NULL); | |
1647 | ||
f0fba2ad | 1648 | return 0; |
17467f23 | 1649 | } |
f0fba2ad | 1650 | |
05cf2379 ZW |
1651 | #ifdef CONFIG_PM_SLEEP |
1652 | static int fsl_ssi_suspend(struct device *dev) | |
1653 | { | |
1654 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev); | |
1655 | struct regmap *regs = ssi_private->regs; | |
1656 | ||
1657 | regmap_read(regs, CCSR_SSI_SFCSR, | |
1658 | &ssi_private->regcache_sfcsr); | |
3f1c241f MS |
1659 | regmap_read(regs, CCSR_SSI_SACNT, |
1660 | &ssi_private->regcache_sacnt); | |
05cf2379 ZW |
1661 | |
1662 | regcache_cache_only(regs, true); | |
1663 | regcache_mark_dirty(regs); | |
1664 | ||
1665 | return 0; | |
1666 | } | |
1667 | ||
1668 | static int fsl_ssi_resume(struct device *dev) | |
1669 | { | |
1670 | struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev); | |
1671 | struct regmap *regs = ssi_private->regs; | |
1672 | ||
1673 | regcache_cache_only(regs, false); | |
1674 | ||
1675 | regmap_update_bits(regs, CCSR_SSI_SFCSR, | |
1676 | CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK | | |
1677 | CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK, | |
1678 | ssi_private->regcache_sfcsr); | |
3f1c241f MS |
1679 | regmap_write(regs, CCSR_SSI_SACNT, |
1680 | ssi_private->regcache_sacnt); | |
05cf2379 ZW |
1681 | |
1682 | return regcache_sync(regs); | |
1683 | } | |
1684 | #endif /* CONFIG_PM_SLEEP */ | |
1685 | ||
1686 | static const struct dev_pm_ops fsl_ssi_pm = { | |
1687 | SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume) | |
1688 | }; | |
1689 | ||
f07eb223 | 1690 | static struct platform_driver fsl_ssi_driver = { |
f0fba2ad LG |
1691 | .driver = { |
1692 | .name = "fsl-ssi-dai", | |
f0fba2ad | 1693 | .of_match_table = fsl_ssi_ids, |
05cf2379 | 1694 | .pm = &fsl_ssi_pm, |
f0fba2ad LG |
1695 | }, |
1696 | .probe = fsl_ssi_probe, | |
1697 | .remove = fsl_ssi_remove, | |
1698 | }; | |
17467f23 | 1699 | |
ba0a7e02 | 1700 | module_platform_driver(fsl_ssi_driver); |
a454dad1 | 1701 | |
f3142807 | 1702 | MODULE_ALIAS("platform:fsl-ssi-dai"); |
17467f23 TT |
1703 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
1704 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 1705 | MODULE_LICENSE("GPL v2"); |