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1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // | |
3 | // Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver | |
4 | // | |
5 | // Author: Timur Tabi <timur@freescale.com> | |
6 | // | |
7 | // Copyright 2007-2010 Freescale Semiconductor, Inc. | |
8 | // | |
9 | // Some notes why imx-pcm-fiq is used instead of DMA on some boards: | |
10 | // | |
11 | // The i.MX SSI core has some nasty limitations in AC97 mode. While most | |
12 | // sane processor vendors have a FIFO per AC97 slot, the i.MX has only | |
13 | // one FIFO which combines all valid receive slots. We cannot even select | |
14 | // which slots we want to receive. The WM9712 with which this driver | |
15 | // was developed with always sends GPIO status data in slot 12 which | |
16 | // we receive in our (PCM-) data stream. The only chance we have is to | |
17 | // manually skip this data in the FIQ handler. With sampling rates different | |
18 | // from 48000Hz not every frame has valid receive data, so the ratio | |
19 | // between pcm data and GPIO status data changes. Our FIQ handler is not | |
20 | // able to handle this, hence this driver only works with 48000Hz sampling | |
21 | // rate. | |
22 | // Reading and writing AC97 registers is another challenge. The core | |
23 | // provides us status bits when the read register is updated with *another* | |
24 | // value. When we read the same register two times (and the register still | |
25 | // contains the same value) these status bits are not set. We work | |
26 | // around this by not polling these bits but only wait a fixed delay. | |
17467f23 TT |
27 | |
28 | #include <linux/init.h> | |
dfa1a107 | 29 | #include <linux/io.h> |
17467f23 TT |
30 | #include <linux/module.h> |
31 | #include <linux/interrupt.h> | |
95cd98f9 | 32 | #include <linux/clk.h> |
c6682fed | 33 | #include <linux/ctype.h> |
17467f23 TT |
34 | #include <linux/device.h> |
35 | #include <linux/delay.h> | |
b880b805 | 36 | #include <linux/mutex.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
aafa85e7 | 38 | #include <linux/spinlock.h> |
9c72a04c | 39 | #include <linux/of.h> |
dfa1a107 SG |
40 | #include <linux/of_address.h> |
41 | #include <linux/of_irq.h> | |
f0fba2ad | 42 | #include <linux/of_platform.h> |
17467f23 | 43 | |
17467f23 TT |
44 | #include <sound/core.h> |
45 | #include <sound/pcm.h> | |
46 | #include <sound/pcm_params.h> | |
47 | #include <sound/initval.h> | |
48 | #include <sound/soc.h> | |
a8909c9b | 49 | #include <sound/dmaengine_pcm.h> |
17467f23 | 50 | |
17467f23 | 51 | #include "fsl_ssi.h" |
09ce1111 | 52 | #include "imx-pcm.h" |
17467f23 | 53 | |
1476105c NC |
54 | /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */ |
55 | #define RX 0 | |
56 | #define TX 1 | |
57 | ||
17467f23 TT |
58 | /** |
59 | * FSLSSI_I2S_FORMATS: audio formats supported by the SSI | |
60 | * | |
17467f23 TT |
61 | * The SSI has a limitation in that the samples must be in the same byte |
62 | * order as the host CPU. This is because when multiple bytes are written | |
63 | * to the STX register, the bytes and bits must be written in the same | |
64 | * order. The STX is a shift register, so all the bits need to be aligned | |
65 | * (bit-endianness must match byte-endianness). Processors typically write | |
66 | * the bits within a byte in the same order that the bytes of a word are | |
67 | * written in. So if the host CPU is big-endian, then only big-endian | |
68 | * samples will be written to STX properly. | |
69 | */ | |
70 | #ifdef __BIG_ENDIAN | |
af4f7f38 NC |
71 | #define FSLSSI_I2S_FORMATS \ |
72 | (SNDRV_PCM_FMTBIT_S8 | \ | |
73 | SNDRV_PCM_FMTBIT_S16_BE | \ | |
74 | SNDRV_PCM_FMTBIT_S18_3BE | \ | |
75 | SNDRV_PCM_FMTBIT_S20_3BE | \ | |
76 | SNDRV_PCM_FMTBIT_S24_3BE | \ | |
77 | SNDRV_PCM_FMTBIT_S24_BE) | |
17467f23 | 78 | #else |
af4f7f38 NC |
79 | #define FSLSSI_I2S_FORMATS \ |
80 | (SNDRV_PCM_FMTBIT_S8 | \ | |
81 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
82 | SNDRV_PCM_FMTBIT_S18_3LE | \ | |
83 | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
84 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
85 | SNDRV_PCM_FMTBIT_S24_LE) | |
17467f23 TT |
86 | #endif |
87 | ||
b6c93f7f NC |
88 | /* |
89 | * In AC97 mode, TXDIR bit is forced to 0 and TFDIR bit is forced to 1: | |
90 | * - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS | |
91 | * - Also have NB_NF to mark these two clocks will not be inverted | |
92 | */ | |
93 | #define FSLSSI_AC97_DAIFMT \ | |
94 | (SND_SOC_DAIFMT_AC97 | \ | |
95 | SND_SOC_DAIFMT_CBM_CFS | \ | |
96 | SND_SOC_DAIFMT_NB_NF) | |
97 | ||
af4f7f38 NC |
98 | #define FSLSSI_SIER_DBG_RX_FLAGS \ |
99 | (SSI_SIER_RFF0_EN | \ | |
100 | SSI_SIER_RLS_EN | \ | |
101 | SSI_SIER_RFS_EN | \ | |
102 | SSI_SIER_ROE0_EN | \ | |
103 | SSI_SIER_RFRC_EN) | |
104 | #define FSLSSI_SIER_DBG_TX_FLAGS \ | |
105 | (SSI_SIER_TFE0_EN | \ | |
106 | SSI_SIER_TLS_EN | \ | |
107 | SSI_SIER_TFS_EN | \ | |
108 | SSI_SIER_TUE0_EN | \ | |
109 | SSI_SIER_TFRC_EN) | |
c1953bfe MP |
110 | |
111 | enum fsl_ssi_type { | |
112 | FSL_SSI_MCP8610, | |
113 | FSL_SSI_MX21, | |
0888efd1 | 114 | FSL_SSI_MX35, |
c1953bfe MP |
115 | FSL_SSI_MX51, |
116 | }; | |
117 | ||
2474e403 | 118 | struct fsl_ssi_regvals { |
4e6ec0d9 MP |
119 | u32 sier; |
120 | u32 srcr; | |
121 | u32 stcr; | |
122 | u32 scr; | |
123 | }; | |
124 | ||
05cf2379 ZW |
125 | static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg) |
126 | { | |
127 | switch (reg) { | |
a818aa5f NC |
128 | case REG_SSI_SACCEN: |
129 | case REG_SSI_SACCDIS: | |
05cf2379 ZW |
130 | return false; |
131 | default: | |
132 | return true; | |
133 | } | |
134 | } | |
135 | ||
136 | static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg) | |
137 | { | |
138 | switch (reg) { | |
a818aa5f NC |
139 | case REG_SSI_STX0: |
140 | case REG_SSI_STX1: | |
141 | case REG_SSI_SRX0: | |
142 | case REG_SSI_SRX1: | |
143 | case REG_SSI_SISR: | |
144 | case REG_SSI_SFCSR: | |
145 | case REG_SSI_SACNT: | |
146 | case REG_SSI_SACADD: | |
147 | case REG_SSI_SACDAT: | |
148 | case REG_SSI_SATAG: | |
149 | case REG_SSI_SACCST: | |
150 | case REG_SSI_SOR: | |
05cf2379 ZW |
151 | return true; |
152 | default: | |
153 | return false; | |
154 | } | |
155 | } | |
156 | ||
f51e3d53 MS |
157 | static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg) |
158 | { | |
159 | switch (reg) { | |
a818aa5f NC |
160 | case REG_SSI_SRX0: |
161 | case REG_SSI_SRX1: | |
162 | case REG_SSI_SISR: | |
163 | case REG_SSI_SACADD: | |
164 | case REG_SSI_SACDAT: | |
165 | case REG_SSI_SATAG: | |
f51e3d53 MS |
166 | return true; |
167 | default: | |
168 | return false; | |
169 | } | |
170 | } | |
171 | ||
05cf2379 ZW |
172 | static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg) |
173 | { | |
174 | switch (reg) { | |
a818aa5f NC |
175 | case REG_SSI_SRX0: |
176 | case REG_SSI_SRX1: | |
177 | case REG_SSI_SACCST: | |
05cf2379 ZW |
178 | return false; |
179 | default: | |
180 | return true; | |
181 | } | |
182 | } | |
183 | ||
43248122 | 184 | static const struct regmap_config fsl_ssi_regconfig = { |
a818aa5f | 185 | .max_register = REG_SSI_SACCDIS, |
43248122 MP |
186 | .reg_bits = 32, |
187 | .val_bits = 32, | |
188 | .reg_stride = 4, | |
189 | .val_format_endian = REGMAP_ENDIAN_NATIVE, | |
a818aa5f | 190 | .num_reg_defaults_raw = REG_SSI_SACCDIS / sizeof(uint32_t) + 1, |
05cf2379 ZW |
191 | .readable_reg = fsl_ssi_readable_reg, |
192 | .volatile_reg = fsl_ssi_volatile_reg, | |
f51e3d53 | 193 | .precious_reg = fsl_ssi_precious_reg, |
05cf2379 | 194 | .writeable_reg = fsl_ssi_writeable_reg, |
bfcf928d | 195 | .cache_type = REGCACHE_FLAT, |
43248122 | 196 | }; |
d5a908b2 | 197 | |
fcdbadef SH |
198 | struct fsl_ssi_soc_data { |
199 | bool imx; | |
6139b1b1 | 200 | bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */ |
fcdbadef SH |
201 | bool offline_config; |
202 | u32 sisr_write_mask; | |
203 | }; | |
204 | ||
17467f23 | 205 | /** |
f3176834 | 206 | * fsl_ssi: per-SSI private data |
17467f23 | 207 | * |
7a8fceb7 | 208 | * @regs: Pointer to the regmap registers |
17467f23 | 209 | * @irq: IRQ of this SSI |
737a6b41 MP |
210 | * @cpu_dai_drv: CPU DAI driver for this device |
211 | * | |
212 | * @dai_fmt: DAI configuration this device is currently used with | |
e0582731 | 213 | * @streams: Mask of current active streams: BIT(TX) and BIT(RX) |
8bc84a33 | 214 | * @i2s_net: I2S and Network mode configurations of SCR register |
fac8a5a5 | 215 | * (this is the initial settings based on the DAI format) |
badc9595 | 216 | * @synchronous: Use synchronous mode - both of TX and RX use STCK and SFCK |
737a6b41 | 217 | * @use_dma: DMA is used or FIQ with stream filter |
7a8fceb7 NC |
218 | * @use_dual_fifo: DMA with support for dual FIFO mode |
219 | * @has_ipg_clk_name: If "ipg" is in the clock name list of device tree | |
220 | * @fifo_depth: Depth of the SSI FIFOs | |
221 | * @slot_width: Width of each DAI slot | |
222 | * @slots: Number of slots | |
2474e403 | 223 | * @regvals: Specific RX/TX register settings |
737a6b41 | 224 | * |
7a8fceb7 NC |
225 | * @clk: Clock source to access register |
226 | * @baudclk: Clock source to generate bit and frame-sync clocks | |
737a6b41 | 227 | * @baudclk_streams: Active streams that are using baudclk |
737a6b41 | 228 | * |
7a8fceb7 NC |
229 | * @regcache_sfcsr: Cache sfcsr register value during suspend and resume |
230 | * @regcache_sacnt: Cache sacnt register value during suspend and resume | |
231 | * | |
737a6b41 MP |
232 | * @dma_params_tx: DMA transmit parameters |
233 | * @dma_params_rx: DMA receive parameters | |
234 | * @ssi_phys: physical address of the SSI registers | |
235 | * | |
236 | * @fiq_params: FIQ stream filtering parameters | |
237 | * | |
76f38451 NC |
238 | * @card_pdev: Platform_device pointer to register a sound card for PowerPC or |
239 | * to register a CODEC platform device for AC97 | |
240 | * @card_name: Platform_device name to register a sound card for PowerPC or | |
241 | * to register a CODEC platform device for AC97 | |
242 | * @card_idx: The index of SSI to register a sound card for PowerPC or | |
243 | * to register a CODEC platform device for AC97 | |
737a6b41 MP |
244 | * |
245 | * @dbg_stats: Debugging statistics | |
246 | * | |
dcfcf2c2 | 247 | * @soc: SoC specific data |
7a8fceb7 NC |
248 | * @dev: Pointer to &pdev->dev |
249 | * | |
250 | * @fifo_watermark: The FIFO watermark setting. Notifies DMA when there are | |
251 | * @fifo_watermark or fewer words in TX fifo or | |
252 | * @fifo_watermark or more empty words in RX fifo. | |
253 | * @dma_maxburst: Max number of words to transfer in one go. So far, | |
254 | * this is always the same as fifo_watermark. | |
4ee437fb | 255 | * |
7a8fceb7 | 256 | * @ac97_reg_lock: Mutex lock to serialize AC97 register access operations |
17467f23 | 257 | */ |
f3176834 | 258 | struct fsl_ssi { |
43248122 | 259 | struct regmap *regs; |
9e446ad5 | 260 | int irq; |
f0fba2ad | 261 | struct snd_soc_dai_driver cpu_dai_drv; |
17467f23 | 262 | |
737a6b41 | 263 | unsigned int dai_fmt; |
e0582731 | 264 | u8 streams; |
8bc84a33 | 265 | u8 i2s_net; |
badc9595 | 266 | bool synchronous; |
de623ece | 267 | bool use_dma; |
0da9e55e | 268 | bool use_dual_fifo; |
f4a43cab | 269 | bool has_ipg_clk_name; |
737a6b41 | 270 | unsigned int fifo_depth; |
b0a7043d NC |
271 | unsigned int slot_width; |
272 | unsigned int slots; | |
2474e403 | 273 | struct fsl_ssi_regvals regvals[2]; |
737a6b41 | 274 | |
95cd98f9 | 275 | struct clk *clk; |
737a6b41 | 276 | struct clk *baudclk; |
d429d8e3 | 277 | unsigned int baudclk_streams; |
737a6b41 | 278 | |
05cf2379 | 279 | u32 regcache_sfcsr; |
3f1c241f | 280 | u32 regcache_sacnt; |
05cf2379 | 281 | |
a8909c9b LPC |
282 | struct snd_dmaengine_dai_dma_data dma_params_tx; |
283 | struct snd_dmaengine_dai_dma_data dma_params_rx; | |
737a6b41 MP |
284 | dma_addr_t ssi_phys; |
285 | ||
de623ece | 286 | struct imx_pcm_fiq_params fiq_params; |
737a6b41 | 287 | |
76f38451 NC |
288 | struct platform_device *card_pdev; |
289 | char card_name[32]; | |
290 | u32 card_idx; | |
09ce1111 | 291 | |
f138e621 | 292 | struct fsl_ssi_dbg dbg_stats; |
17467f23 | 293 | |
fcdbadef | 294 | const struct fsl_ssi_soc_data *soc; |
0096b693 | 295 | struct device *dev; |
4ee437fb CC |
296 | |
297 | u32 fifo_watermark; | |
298 | u32 dma_maxburst; | |
b880b805 MS |
299 | |
300 | struct mutex ac97_reg_lock; | |
c1953bfe | 301 | }; |
171d683d MP |
302 | |
303 | /* | |
7a8fceb7 | 304 | * SoC specific data |
171d683d | 305 | * |
7a8fceb7 NC |
306 | * Notes: |
307 | * 1) SSI in earlier SoCS has critical bits in control registers that | |
308 | * cannot be changed after SSI starts running -- a software reset | |
309 | * (set SSIEN to 0) is required to change their values. So adding | |
310 | * an offline_config flag for these SoCs. | |
311 | * 2) SDMA is available since imx35. However, imx35 does not support | |
312 | * DMA bits changing when SSI is running, so set offline_config. | |
313 | * 3) imx51 and later versions support register configurations when | |
314 | * SSI is running (SSIEN); For these versions, DMA needs to be | |
315 | * configured before SSI sends DMA request to avoid an undefined | |
316 | * DMA request on the SDMA side. | |
171d683d | 317 | */ |
171d683d | 318 | |
fcdbadef SH |
319 | static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = { |
320 | .imx = false, | |
321 | .offline_config = true, | |
a818aa5f | 322 | .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | |
af4f7f38 NC |
323 | SSI_SISR_ROE0 | SSI_SISR_ROE1 | |
324 | SSI_SISR_TUE0 | SSI_SISR_TUE1, | |
fcdbadef SH |
325 | }; |
326 | ||
327 | static struct fsl_ssi_soc_data fsl_ssi_imx21 = { | |
328 | .imx = true, | |
6139b1b1 | 329 | .imx21regs = true, |
fcdbadef SH |
330 | .offline_config = true, |
331 | .sisr_write_mask = 0, | |
332 | }; | |
333 | ||
334 | static struct fsl_ssi_soc_data fsl_ssi_imx35 = { | |
335 | .imx = true, | |
336 | .offline_config = true, | |
a818aa5f | 337 | .sisr_write_mask = SSI_SISR_RFRC | SSI_SISR_TFRC | |
af4f7f38 NC |
338 | SSI_SISR_ROE0 | SSI_SISR_ROE1 | |
339 | SSI_SISR_TUE0 | SSI_SISR_TUE1, | |
fcdbadef SH |
340 | }; |
341 | ||
342 | static struct fsl_ssi_soc_data fsl_ssi_imx51 = { | |
343 | .imx = true, | |
344 | .offline_config = false, | |
a818aa5f | 345 | .sisr_write_mask = SSI_SISR_ROE0 | SSI_SISR_ROE1 | |
af4f7f38 | 346 | SSI_SISR_TUE0 | SSI_SISR_TUE1, |
fcdbadef SH |
347 | }; |
348 | ||
349 | static const struct of_device_id fsl_ssi_ids[] = { | |
350 | { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 }, | |
351 | { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 }, | |
352 | { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 }, | |
353 | { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 }, | |
354 | {} | |
355 | }; | |
356 | MODULE_DEVICE_TABLE(of, fsl_ssi_ids); | |
357 | ||
f3176834 | 358 | static bool fsl_ssi_is_ac97(struct fsl_ssi *ssi) |
fcdbadef | 359 | { |
f3176834 | 360 | return (ssi->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == |
5b64c173 | 361 | SND_SOC_DAIFMT_AC97; |
171d683d MP |
362 | } |
363 | ||
f3176834 | 364 | static bool fsl_ssi_is_i2s_master(struct fsl_ssi *ssi) |
8dd51e23 | 365 | { |
f3176834 | 366 | return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == |
8dd51e23 SH |
367 | SND_SOC_DAIFMT_CBS_CFS; |
368 | } | |
369 | ||
f3176834 | 370 | static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi *ssi) |
cf4f7fc3 | 371 | { |
f3176834 | 372 | return (ssi->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) == |
cf4f7fc3 FF |
373 | SND_SOC_DAIFMT_CBM_CFS; |
374 | } | |
7a8fceb7 | 375 | |
17467f23 | 376 | /** |
7a8fceb7 | 377 | * Interrupt handler to gather states |
17467f23 TT |
378 | */ |
379 | static irqreturn_t fsl_ssi_isr(int irq, void *dev_id) | |
380 | { | |
f3176834 NC |
381 | struct fsl_ssi *ssi = dev_id; |
382 | struct regmap *regs = ssi->regs; | |
671f8204 | 383 | u32 sisr, sisr2; |
17467f23 | 384 | |
a818aa5f | 385 | regmap_read(regs, REG_SSI_SISR, &sisr); |
17467f23 | 386 | |
f3176834 | 387 | sisr2 = sisr & ssi->soc->sisr_write_mask; |
17467f23 TT |
388 | /* Clear the bits that we set */ |
389 | if (sisr2) | |
a818aa5f | 390 | regmap_write(regs, REG_SSI_SISR, sisr2); |
17467f23 | 391 | |
f3176834 | 392 | fsl_ssi_dbg_isr(&ssi->dbg_stats, sisr); |
9368acc4 | 393 | |
f138e621 | 394 | return IRQ_HANDLED; |
9368acc4 MP |
395 | } |
396 | ||
7a8fceb7 | 397 | /** |
7d67bcb6 NC |
398 | * Set SCR, SIER, STCR and SRCR registers with cached values in regvals |
399 | * | |
400 | * Notes: | |
401 | * 1) For offline_config SoCs, enable all necessary bits of both streams | |
402 | * when 1st stream starts, even if the opposite stream will not start | |
403 | * 2) It also clears FIFO before setting regvals; SOR is safe to set online | |
4e6ec0d9 | 404 | */ |
7d67bcb6 | 405 | static void fsl_ssi_config_enable(struct fsl_ssi *ssi, bool tx) |
4e6ec0d9 | 406 | { |
2474e403 | 407 | struct fsl_ssi_regvals *vals = ssi->regvals; |
7d67bcb6 NC |
408 | int dir = tx ? TX : RX; |
409 | u32 sier, srcr, stcr; | |
4e6ec0d9 | 410 | |
7d67bcb6 NC |
411 | /* Clear dirty data in the FIFO; It also prevents channel slipping */ |
412 | regmap_update_bits(ssi->regs, REG_SSI_SOR, | |
413 | SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx)); | |
414 | ||
415 | /* | |
416 | * On offline_config SoCs, SxCR and SIER are already configured when | |
417 | * the previous stream started. So skip all SxCR and SIER settings | |
418 | * to prevent online reconfigurations, then jump to set SCR directly | |
419 | */ | |
420 | if (ssi->soc->offline_config && ssi->streams) | |
421 | goto enable_scr; | |
422 | ||
423 | if (ssi->soc->offline_config) { | |
424 | /* | |
425 | * Online reconfiguration not supported, so enable all bits for | |
426 | * both streams at once to avoid necessity of reconfigurations | |
427 | */ | |
428 | srcr = vals[RX].srcr | vals[TX].srcr; | |
429 | stcr = vals[RX].stcr | vals[TX].stcr; | |
430 | sier = vals[RX].sier | vals[TX].sier; | |
4e6ec0d9 | 431 | } else { |
7d67bcb6 NC |
432 | /* Otherwise, only set bits for the current stream */ |
433 | srcr = vals[dir].srcr; | |
434 | stcr = vals[dir].stcr; | |
435 | sier = vals[dir].sier; | |
4e6ec0d9 | 436 | } |
7d67bcb6 NC |
437 | |
438 | /* Configure SRCR, STCR and SIER at once */ | |
439 | regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, srcr); | |
440 | regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, stcr); | |
441 | regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, sier); | |
442 | ||
443 | enable_scr: | |
444 | /* | |
445 | * Start DMA before setting TE to avoid FIFO underrun | |
446 | * which may cause a channel slip or a channel swap | |
447 | * | |
448 | * TODO: FIQ cases might also need this upon testing | |
449 | */ | |
450 | if (ssi->use_dma && tx) { | |
451 | int try = 100; | |
452 | u32 sfcsr; | |
453 | ||
454 | /* Enable SSI first to send TX DMA request */ | |
455 | regmap_update_bits(ssi->regs, REG_SSI_SCR, | |
456 | SSI_SCR_SSIEN, SSI_SCR_SSIEN); | |
457 | ||
458 | /* Busy wait until TX FIFO not empty -- DMA working */ | |
459 | do { | |
460 | regmap_read(ssi->regs, REG_SSI_SFCSR, &sfcsr); | |
461 | if (SSI_SFCSR_TFCNT0(sfcsr)) | |
462 | break; | |
463 | } while (--try); | |
464 | ||
465 | /* FIFO still empty -- something might be wrong */ | |
466 | if (!SSI_SFCSR_TFCNT0(sfcsr)) | |
467 | dev_warn(ssi->dev, "Timeout waiting TX FIFO filling\n"); | |
468 | } | |
469 | /* Enable all remaining bits in SCR */ | |
470 | regmap_update_bits(ssi->regs, REG_SSI_SCR, | |
471 | vals[dir].scr, vals[dir].scr); | |
472 | ||
473 | /* Log the enabled stream to the mask */ | |
474 | ssi->streams |= BIT(dir); | |
4e6ec0d9 MP |
475 | } |
476 | ||
7a8fceb7 | 477 | /** |
06a99454 | 478 | * Exclude bits that are used by the opposite stream |
65c961cc | 479 | * |
06a99454 NC |
480 | * When both streams are active, disabling some bits for the current stream |
481 | * might break the other stream if these bits are used by it. | |
65c961cc | 482 | * |
06a99454 NC |
483 | * @vals : regvals of the current stream |
484 | * @avals: regvals of the opposite stream | |
485 | * @aactive: active state of the opposite stream | |
65c961cc | 486 | * |
06a99454 NC |
487 | * 1) XOR vals and avals to get the differences if the other stream is active; |
488 | * Otherwise, return current vals if the other stream is not active | |
489 | * 2) AND the result of 1) with the current vals | |
65c961cc | 490 | */ |
06a99454 NC |
491 | #define _ssi_xor_shared_bits(vals, avals, aactive) \ |
492 | ((vals) ^ ((avals) * (aactive))) | |
493 | ||
494 | #define ssi_excl_shared_bits(vals, avals, aactive) \ | |
495 | ((vals) & _ssi_xor_shared_bits(vals, avals, aactive)) | |
65c961cc | 496 | |
7a8fceb7 | 497 | /** |
7d67bcb6 NC |
498 | * Unset SCR, SIER, STCR and SRCR registers with cached values in regvals |
499 | * | |
500 | * Notes: | |
501 | * 1) For offline_config SoCs, to avoid online reconfigurations, disable all | |
502 | * bits of both streams at once when the last stream is abort to end | |
503 | * 2) It also clears FIFO after unsetting regvals; SOR is safe to set online | |
4e6ec0d9 | 504 | */ |
7d67bcb6 | 505 | static void fsl_ssi_config_disable(struct fsl_ssi *ssi, bool tx) |
4e6ec0d9 | 506 | { |
7d67bcb6 NC |
507 | struct fsl_ssi_regvals *vals, *avals; |
508 | u32 sier, srcr, stcr, scr; | |
2e132740 NC |
509 | int adir = tx ? RX : TX; |
510 | int dir = tx ? TX : RX; | |
06a99454 | 511 | bool aactive; |
43248122 | 512 | |
06a99454 NC |
513 | /* Check if the opposite stream is active */ |
514 | aactive = ssi->streams & BIT(adir); | |
4e6ec0d9 | 515 | |
7d67bcb6 | 516 | vals = &ssi->regvals[dir]; |
e0582731 | 517 | |
7d67bcb6 NC |
518 | /* Get regvals of the opposite stream to keep opposite stream safe */ |
519 | avals = &ssi->regvals[adir]; | |
4e6ec0d9 MP |
520 | |
521 | /* | |
7d67bcb6 NC |
522 | * To keep the other stream safe, exclude shared bits between |
523 | * both streams, and get safe bits to disable current stream | |
4e6ec0d9 | 524 | */ |
7d67bcb6 | 525 | scr = ssi_excl_shared_bits(vals->scr, avals->scr, aactive); |
4e6ec0d9 | 526 | |
7d67bcb6 NC |
527 | /* Disable safe bits of SCR register for the current stream */ |
528 | regmap_update_bits(ssi->regs, REG_SSI_SCR, scr, 0); | |
4e6ec0d9 | 529 | |
7d67bcb6 NC |
530 | /* Log the disabled stream to the mask */ |
531 | ssi->streams &= ~BIT(dir); | |
027db2e1 | 532 | |
7d67bcb6 NC |
533 | /* |
534 | * On offline_config SoCs, if the other stream is active, skip | |
535 | * SxCR and SIER settings to prevent online reconfigurations | |
536 | */ | |
537 | if (ssi->soc->offline_config && aactive) | |
538 | goto fifo_clear; | |
4e6ec0d9 | 539 | |
7d67bcb6 NC |
540 | if (ssi->soc->offline_config) { |
541 | /* Now there is only current stream active, disable all bits */ | |
542 | srcr = vals->srcr | avals->srcr; | |
543 | stcr = vals->stcr | avals->stcr; | |
544 | sier = vals->sier | avals->sier; | |
545 | } else { | |
4e6ec0d9 | 546 | /* |
7a8fceb7 NC |
547 | * To keep the other stream safe, exclude shared bits between |
548 | * both streams, and get safe bits to disable current stream | |
4e6ec0d9 | 549 | */ |
06a99454 NC |
550 | sier = ssi_excl_shared_bits(vals->sier, avals->sier, aactive); |
551 | srcr = ssi_excl_shared_bits(vals->srcr, avals->srcr, aactive); | |
552 | stcr = ssi_excl_shared_bits(vals->stcr, avals->stcr, aactive); | |
4e6ec0d9 MP |
553 | } |
554 | ||
7d67bcb6 NC |
555 | /* Clear configurations of SRCR, STCR and SIER at once */ |
556 | regmap_update_bits(ssi->regs, REG_SSI_SRCR, srcr, 0); | |
557 | regmap_update_bits(ssi->regs, REG_SSI_STCR, stcr, 0); | |
558 | regmap_update_bits(ssi->regs, REG_SSI_SIER, sier, 0); | |
4e6ec0d9 | 559 | |
7d67bcb6 NC |
560 | fifo_clear: |
561 | /* Clear remaining data in the FIFO */ | |
562 | regmap_update_bits(ssi->regs, REG_SSI_SOR, | |
563 | SSI_SOR_xX_CLR(tx), SSI_SOR_xX_CLR(tx)); | |
4e6ec0d9 MP |
564 | } |
565 | ||
f3176834 | 566 | static void fsl_ssi_tx_ac97_saccst_setup(struct fsl_ssi *ssi) |
01ca4851 | 567 | { |
f3176834 | 568 | struct regmap *regs = ssi->regs; |
01ca4851 MS |
569 | |
570 | /* no SACC{ST,EN,DIS} regs on imx21-class SSI */ | |
f3176834 | 571 | if (!ssi->soc->imx21regs) { |
7a8fceb7 | 572 | /* Disable all channel slots */ |
a818aa5f | 573 | regmap_write(regs, REG_SSI_SACCDIS, 0xff); |
7a8fceb7 | 574 | /* Enable slots 3 & 4 -- PCM Playback Left & Right channels */ |
a818aa5f | 575 | regmap_write(regs, REG_SSI_SACCEN, 0x300); |
01ca4851 MS |
576 | } |
577 | } | |
578 | ||
7a8fceb7 NC |
579 | /** |
580 | * Cache critical bits of SIER, SRCR, STCR and SCR to later set them safely | |
6de83879 | 581 | */ |
2474e403 | 582 | static void fsl_ssi_setup_regvals(struct fsl_ssi *ssi) |
6de83879 | 583 | { |
2474e403 | 584 | struct fsl_ssi_regvals *vals = ssi->regvals; |
6de83879 | 585 | |
501bc1d7 | 586 | vals[RX].sier = SSI_SIER_RFF0_EN | FSLSSI_SIER_DBG_RX_FLAGS; |
2474e403 | 587 | vals[RX].srcr = SSI_SRCR_RFEN0; |
501bc1d7 NC |
588 | vals[RX].scr = SSI_SCR_SSIEN | SSI_SCR_RE; |
589 | vals[TX].sier = SSI_SIER_TFE0_EN | FSLSSI_SIER_DBG_TX_FLAGS; | |
2474e403 | 590 | vals[TX].stcr = SSI_STCR_TFEN0; |
501bc1d7 | 591 | vals[TX].scr = SSI_SCR_SSIEN | SSI_SCR_TE; |
6de83879 | 592 | |
7a8fceb7 | 593 | /* AC97 has already enabled SSIEN, RE and TE, so ignore them */ |
501bc1d7 NC |
594 | if (fsl_ssi_is_ac97(ssi)) |
595 | vals[RX].scr = vals[TX].scr = 0; | |
6de83879 | 596 | |
702d7965 NC |
597 | if (ssi->use_dual_fifo) { |
598 | vals[RX].srcr |= SSI_SRCR_RFEN1; | |
599 | vals[TX].stcr |= SSI_STCR_TFEN1; | |
600 | } | |
601 | ||
f3176834 | 602 | if (ssi->use_dma) { |
2474e403 NC |
603 | vals[RX].sier |= SSI_SIER_RDMAE; |
604 | vals[TX].sier |= SSI_SIER_TDMAE; | |
6de83879 | 605 | } else { |
2474e403 NC |
606 | vals[RX].sier |= SSI_SIER_RIE; |
607 | vals[TX].sier |= SSI_SIER_TIE; | |
6de83879 | 608 | } |
6de83879 MP |
609 | } |
610 | ||
f3176834 | 611 | static void fsl_ssi_setup_ac97(struct fsl_ssi *ssi) |
d8764646 | 612 | { |
f3176834 | 613 | struct regmap *regs = ssi->regs; |
d8764646 | 614 | |
7a8fceb7 | 615 | /* Setup the clock control register */ |
af4f7f38 NC |
616 | regmap_write(regs, REG_SSI_STCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); |
617 | regmap_write(regs, REG_SSI_SRCCR, SSI_SxCCR_WL(17) | SSI_SxCCR_DC(13)); | |
d8764646 | 618 | |
7a8fceb7 | 619 | /* Enable AC97 mode and startup the SSI */ |
af4f7f38 | 620 | regmap_write(regs, REG_SSI_SACNT, SSI_SACNT_AC97EN | SSI_SACNT_FV); |
6139b1b1 | 621 | |
7a8fceb7 | 622 | /* AC97 has to communicate with codec before starting a stream */ |
a818aa5f | 623 | regmap_update_bits(regs, REG_SSI_SCR, |
af4f7f38 NC |
624 | SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE, |
625 | SSI_SCR_SSIEN | SSI_SCR_TE | SSI_SCR_RE); | |
d8764646 | 626 | |
a818aa5f | 627 | regmap_write(regs, REG_SSI_SOR, SSI_SOR_WAIT(3)); |
d8764646 MP |
628 | } |
629 | ||
dee89c4d MB |
630 | static int fsl_ssi_startup(struct snd_pcm_substream *substream, |
631 | struct snd_soc_dai *dai) | |
17467f23 TT |
632 | { |
633 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f3176834 | 634 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
f4a43cab SW |
635 | int ret; |
636 | ||
f3176834 | 637 | ret = clk_prepare_enable(ssi->clk); |
f4a43cab SW |
638 | if (ret) |
639 | return ret; | |
17467f23 | 640 | |
7a8fceb7 NC |
641 | /* |
642 | * When using dual fifo mode, it is safer to ensure an even period | |
0da9e55e NC |
643 | * size. If appearing to an odd number while DMA always starts its |
644 | * task from fifo0, fifo1 would be neglected at the end of each | |
645 | * period. But SSI would still access fifo1 with an invalid data. | |
646 | */ | |
f3176834 | 647 | if (ssi->use_dual_fifo) |
0da9e55e | 648 | snd_pcm_hw_constraint_step(substream->runtime, 0, |
af4f7f38 | 649 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2); |
0da9e55e | 650 | |
17467f23 TT |
651 | return 0; |
652 | } | |
653 | ||
f4a43cab | 654 | static void fsl_ssi_shutdown(struct snd_pcm_substream *substream, |
af4f7f38 | 655 | struct snd_soc_dai *dai) |
f4a43cab SW |
656 | { |
657 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f3176834 | 658 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
f4a43cab | 659 | |
f3176834 | 660 | clk_disable_unprepare(ssi->clk); |
f4a43cab SW |
661 | } |
662 | ||
ee9daad4 | 663 | /** |
7a8fceb7 | 664 | * Configure Digital Audio Interface bit clock |
ee9daad4 SH |
665 | * |
666 | * Note: This function can be only called when using SSI as DAI master | |
667 | * | |
668 | * Quick instruction for parameters: | |
b0a7043d NC |
669 | * freq: Output BCLK frequency = samplerate * slots * slot_width |
670 | * (In 2-channel I2S Master mode, slot_width is fixed 32) | |
ee9daad4 | 671 | */ |
8dd51e23 | 672 | static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, |
0c884bed | 673 | struct snd_soc_dai *dai, |
af4f7f38 | 674 | struct snd_pcm_hw_params *hw_params) |
ee9daad4 | 675 | { |
52eee84e | 676 | bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
0c884bed | 677 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
f3176834 | 678 | struct regmap *regs = ssi->regs; |
ee9daad4 | 679 | u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; |
d8ced479 | 680 | unsigned long clkrate, baudrate, tmprate; |
b0a7043d NC |
681 | unsigned int slots = params_channels(hw_params); |
682 | unsigned int slot_width = 32; | |
ee9daad4 | 683 | u64 sub, savesub = 100000; |
8dd51e23 | 684 | unsigned int freq; |
d429d8e3 | 685 | bool baudclk_is_used; |
badc9595 | 686 | int ret; |
8dd51e23 | 687 | |
b0a7043d | 688 | /* Override slots and slot_width if being specifically set... */ |
f3176834 NC |
689 | if (ssi->slots) |
690 | slots = ssi->slots; | |
b0a7043d | 691 | /* ...but keep 32 bits if slots is 2 -- I2S Master mode */ |
f3176834 NC |
692 | if (ssi->slot_width && slots != 2) |
693 | slot_width = ssi->slot_width; | |
b0a7043d NC |
694 | |
695 | /* Generate bit clock based on the slot number and slot width */ | |
696 | freq = slots * slot_width * params_rate(hw_params); | |
ee9daad4 SH |
697 | |
698 | /* Don't apply it to any non-baudclk circumstance */ | |
f3176834 | 699 | if (IS_ERR(ssi->baudclk)) |
ee9daad4 SH |
700 | return -EINVAL; |
701 | ||
e09745f2 AM |
702 | /* |
703 | * Hardware limitation: The bclk rate must be | |
704 | * never greater than 1/5 IPG clock rate | |
705 | */ | |
f3176834 | 706 | if (freq * 5 > clk_get_rate(ssi->clk)) { |
0c884bed | 707 | dev_err(dai->dev, "bitclk > ipgclk / 5\n"); |
e09745f2 AM |
708 | return -EINVAL; |
709 | } | |
710 | ||
f3176834 | 711 | baudclk_is_used = ssi->baudclk_streams & ~(BIT(substream->stream)); |
d429d8e3 | 712 | |
ee9daad4 SH |
713 | /* It should be already enough to divide clock by setting pm alone */ |
714 | psr = 0; | |
715 | div2 = 0; | |
716 | ||
717 | factor = (div2 + 1) * (7 * psr + 1) * 2; | |
718 | ||
719 | for (i = 0; i < 255; i++) { | |
6c8ca30e | 720 | tmprate = freq * factor * (i + 1); |
d429d8e3 MP |
721 | |
722 | if (baudclk_is_used) | |
f3176834 | 723 | clkrate = clk_get_rate(ssi->baudclk); |
d429d8e3 | 724 | else |
f3176834 | 725 | clkrate = clk_round_rate(ssi->baudclk, tmprate); |
ee9daad4 | 726 | |
acf2c60a TT |
727 | clkrate /= factor; |
728 | afreq = clkrate / (i + 1); | |
ee9daad4 SH |
729 | |
730 | if (freq == afreq) | |
731 | sub = 0; | |
732 | else if (freq / afreq == 1) | |
733 | sub = freq - afreq; | |
734 | else if (afreq / freq == 1) | |
735 | sub = afreq - freq; | |
736 | else | |
737 | continue; | |
738 | ||
739 | /* Calculate the fraction */ | |
740 | sub *= 100000; | |
741 | do_div(sub, freq); | |
742 | ||
ebac95a9 | 743 | if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) { |
ee9daad4 SH |
744 | baudrate = tmprate; |
745 | savesub = sub; | |
746 | pm = i; | |
747 | } | |
748 | ||
749 | /* We are lucky */ | |
750 | if (savesub == 0) | |
751 | break; | |
752 | } | |
753 | ||
754 | /* No proper pm found if it is still remaining the initial value */ | |
755 | if (pm == 999) { | |
0c884bed | 756 | dev_err(dai->dev, "failed to handle the required sysclk\n"); |
ee9daad4 SH |
757 | return -EINVAL; |
758 | } | |
759 | ||
a818aa5f NC |
760 | stccr = SSI_SxCCR_PM(pm + 1) | (div2 ? SSI_SxCCR_DIV2 : 0) | |
761 | (psr ? SSI_SxCCR_PSR : 0); | |
af4f7f38 | 762 | mask = SSI_SxCCR_PM_MASK | SSI_SxCCR_DIV2 | SSI_SxCCR_PSR; |
ee9daad4 | 763 | |
52eee84e | 764 | /* STCCR is used for RX in synchronous mode */ |
badc9595 | 765 | tx2 = tx || ssi->synchronous; |
52eee84e | 766 | regmap_update_bits(regs, REG_SSI_SxCCR(tx2), mask, stccr); |
ee9daad4 | 767 | |
d429d8e3 | 768 | if (!baudclk_is_used) { |
f3176834 | 769 | ret = clk_set_rate(ssi->baudclk, baudrate); |
ee9daad4 | 770 | if (ret) { |
0c884bed | 771 | dev_err(dai->dev, "failed to set baudclk rate\n"); |
ee9daad4 SH |
772 | return -EINVAL; |
773 | } | |
ee9daad4 | 774 | } |
ee9daad4 SH |
775 | |
776 | return 0; | |
777 | } | |
778 | ||
17467f23 | 779 | /** |
7a8fceb7 | 780 | * Configure SSI based on PCM hardware parameters |
17467f23 | 781 | * |
7a8fceb7 NC |
782 | * Notes: |
783 | * 1) SxCCR.WL bits are critical bits that require SSI to be temporarily | |
784 | * disabled on offline_config SoCs. Even for online configurable SoCs | |
785 | * running in synchronous mode (both TX and RX use STCCR), it is not | |
786 | * safe to re-configure them when both two streams start running. | |
787 | * 2) SxCCR.PM, SxCCR.DIV2 and SxCCR.PSR bits will be configured in the | |
788 | * fsl_ssi_set_bclk() if SSI is the DAI clock master. | |
17467f23 | 789 | */ |
85ef2375 | 790 | static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, |
af4f7f38 | 791 | struct snd_pcm_hw_params *hw_params, |
0c884bed | 792 | struct snd_soc_dai *dai) |
17467f23 | 793 | { |
52eee84e | 794 | bool tx2, tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
0c884bed | 795 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
f3176834 | 796 | struct regmap *regs = ssi->regs; |
2924a998 | 797 | unsigned int channels = params_channels(hw_params); |
4ca73043 | 798 | unsigned int sample_size = params_width(hw_params); |
a818aa5f | 799 | u32 wl = SSI_SxCCR_WL(sample_size); |
8dd51e23 | 800 | int ret; |
17467f23 | 801 | |
5e538eca | 802 | /* |
7a8fceb7 NC |
803 | * SSI is properly configured if it is enabled and running in |
804 | * the synchronous mode; Note that AC97 mode is an exception | |
805 | * that should set separate configurations for STCCR and SRCCR | |
806 | * despite running in the synchronous mode. | |
5e538eca | 807 | */ |
9c4f509a | 808 | if (ssi->streams && ssi->synchronous) |
5e538eca | 809 | return 0; |
17467f23 | 810 | |
f3176834 | 811 | if (fsl_ssi_is_i2s_master(ssi)) { |
0c884bed | 812 | ret = fsl_ssi_set_bclk(substream, dai, hw_params); |
8dd51e23 SH |
813 | if (ret) |
814 | return ret; | |
d429d8e3 MP |
815 | |
816 | /* Do not enable the clock if it is already enabled */ | |
f3176834 NC |
817 | if (!(ssi->baudclk_streams & BIT(substream->stream))) { |
818 | ret = clk_prepare_enable(ssi->baudclk); | |
d429d8e3 MP |
819 | if (ret) |
820 | return ret; | |
821 | ||
f3176834 | 822 | ssi->baudclk_streams |= BIT(substream->stream); |
d429d8e3 | 823 | } |
8dd51e23 SH |
824 | } |
825 | ||
f3176834 | 826 | if (!fsl_ssi_is_ac97(ssi)) { |
fac8a5a5 NC |
827 | /* |
828 | * Keep the ssi->i2s_net intact while having a local variable | |
829 | * to override settings for special use cases. Otherwise, the | |
830 | * ssi->i2s_net will lose the settings for regular use cases. | |
831 | */ | |
832 | u8 i2s_net = ssi->i2s_net; | |
833 | ||
7a8fceb7 | 834 | /* Normal + Network mode to send 16-bit data in 32-bit frames */ |
f3176834 | 835 | if (fsl_ssi_is_i2s_cbm_cfs(ssi) && sample_size == 16) |
fac8a5a5 | 836 | i2s_net = SSI_SCR_I2S_MODE_NORMAL | SSI_SCR_NET; |
ebf08ae3 NC |
837 | |
838 | /* Use Normal mode to send mono data at 1st slot of 2 slots */ | |
839 | if (channels == 1) | |
fac8a5a5 | 840 | i2s_net = SSI_SCR_I2S_MODE_NORMAL; |
cf4f7fc3 | 841 | |
a818aa5f | 842 | regmap_update_bits(regs, REG_SSI_SCR, |
fac8a5a5 | 843 | SSI_SCR_I2S_NET_MASK, i2s_net); |
cf4f7fc3 FF |
844 | } |
845 | ||
5e538eca | 846 | /* In synchronous mode, the SSI uses STCCR for capture */ |
badc9595 | 847 | tx2 = tx || ssi->synchronous; |
52eee84e | 848 | regmap_update_bits(regs, REG_SSI_SxCCR(tx2), SSI_SxCCR_WL_MASK, wl); |
17467f23 TT |
849 | |
850 | return 0; | |
851 | } | |
852 | ||
d429d8e3 | 853 | static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, |
0c884bed | 854 | struct snd_soc_dai *dai) |
d429d8e3 MP |
855 | { |
856 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f3176834 | 857 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
d429d8e3 | 858 | |
f3176834 | 859 | if (fsl_ssi_is_i2s_master(ssi) && |
af4f7f38 | 860 | ssi->baudclk_streams & BIT(substream->stream)) { |
f3176834 NC |
861 | clk_disable_unprepare(ssi->baudclk); |
862 | ssi->baudclk_streams &= ~BIT(substream->stream); | |
d429d8e3 MP |
863 | } |
864 | ||
865 | return 0; | |
866 | } | |
867 | ||
26b31f4f | 868 | static int _fsl_ssi_set_dai_fmt(struct fsl_ssi *ssi, unsigned int fmt) |
aafa85e7 | 869 | { |
26b31f4f | 870 | u32 strcr = 0, scr = 0, stcr, srcr, mask; |
2b0db996 | 871 | |
f3176834 | 872 | ssi->dai_fmt = fmt; |
171d683d | 873 | |
7a8fceb7 | 874 | /* Synchronize frame sync clock for TE to avoid data slipping */ |
a818aa5f | 875 | scr |= SSI_SCR_SYNC_TX_FS; |
aafa85e7 | 876 | |
26b31f4f NC |
877 | /* Set to default shifting settings: LSB_ALIGNED */ |
878 | strcr |= SSI_STCR_TXBIT0; | |
aafa85e7 | 879 | |
7a8fceb7 | 880 | /* Use Network mode as default */ |
8bc84a33 | 881 | ssi->i2s_net = SSI_SCR_NET; |
aafa85e7 NC |
882 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
883 | case SND_SOC_DAIFMT_I2S: | |
884 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
885 | case SND_SOC_DAIFMT_CBS_CFS: | |
26b31f4f NC |
886 | if (IS_ERR(ssi->baudclk)) { |
887 | dev_err(ssi->dev, | |
888 | "missing baudclk for master mode\n"); | |
889 | return -EINVAL; | |
890 | } | |
891 | /* fall through */ | |
892 | case SND_SOC_DAIFMT_CBM_CFS: | |
8bc84a33 | 893 | ssi->i2s_net |= SSI_SCR_I2S_MODE_MASTER; |
aafa85e7 NC |
894 | break; |
895 | case SND_SOC_DAIFMT_CBM_CFM: | |
8bc84a33 | 896 | ssi->i2s_net |= SSI_SCR_I2S_MODE_SLAVE; |
aafa85e7 NC |
897 | break; |
898 | default: | |
899 | return -EINVAL; | |
900 | } | |
aafa85e7 | 901 | |
26b31f4f NC |
902 | regmap_update_bits(ssi->regs, REG_SSI_STCCR, |
903 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2)); | |
904 | regmap_update_bits(ssi->regs, REG_SSI_SRCCR, | |
905 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(2)); | |
906 | ||
aafa85e7 | 907 | /* Data on rising edge of bclk, frame low, 1clk before data */ |
26b31f4f | 908 | strcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP | SSI_STCR_TEFS; |
aafa85e7 NC |
909 | break; |
910 | case SND_SOC_DAIFMT_LEFT_J: | |
911 | /* Data on rising edge of bclk, frame high */ | |
26b31f4f | 912 | strcr |= SSI_STCR_TSCKP; |
aafa85e7 NC |
913 | break; |
914 | case SND_SOC_DAIFMT_DSP_A: | |
915 | /* Data on rising edge of bclk, frame high, 1clk before data */ | |
26b31f4f | 916 | strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP | SSI_STCR_TEFS; |
aafa85e7 NC |
917 | break; |
918 | case SND_SOC_DAIFMT_DSP_B: | |
919 | /* Data on rising edge of bclk, frame high */ | |
26b31f4f | 920 | strcr |= SSI_STCR_TFSL | SSI_STCR_TSCKP; |
aafa85e7 | 921 | break; |
2b0db996 | 922 | case SND_SOC_DAIFMT_AC97: |
7a8fceb7 | 923 | /* Data on falling edge of bclk, frame high, 1clk before data */ |
26b31f4f | 924 | strcr |= SSI_STCR_TEFS; |
2b0db996 | 925 | break; |
aafa85e7 NC |
926 | default: |
927 | return -EINVAL; | |
928 | } | |
26b31f4f | 929 | |
8bc84a33 | 930 | scr |= ssi->i2s_net; |
aafa85e7 NC |
931 | |
932 | /* DAI clock inversion */ | |
933 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
934 | case SND_SOC_DAIFMT_NB_NF: | |
935 | /* Nothing to do for both normal cases */ | |
936 | break; | |
937 | case SND_SOC_DAIFMT_IB_NF: | |
938 | /* Invert bit clock */ | |
a818aa5f | 939 | strcr ^= SSI_STCR_TSCKP; |
aafa85e7 NC |
940 | break; |
941 | case SND_SOC_DAIFMT_NB_IF: | |
942 | /* Invert frame clock */ | |
a818aa5f | 943 | strcr ^= SSI_STCR_TFSI; |
aafa85e7 NC |
944 | break; |
945 | case SND_SOC_DAIFMT_IB_IF: | |
946 | /* Invert both clocks */ | |
a818aa5f NC |
947 | strcr ^= SSI_STCR_TSCKP; |
948 | strcr ^= SSI_STCR_TFSI; | |
aafa85e7 NC |
949 | break; |
950 | default: | |
951 | return -EINVAL; | |
952 | } | |
953 | ||
954 | /* DAI clock master masks */ | |
955 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
956 | case SND_SOC_DAIFMT_CBS_CFS: | |
7a8fceb7 | 957 | /* Output bit and frame sync clocks */ |
a818aa5f NC |
958 | strcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR; |
959 | scr |= SSI_SCR_SYS_CLK_EN; | |
aafa85e7 NC |
960 | break; |
961 | case SND_SOC_DAIFMT_CBM_CFM: | |
7a8fceb7 | 962 | /* Input bit or frame sync clocks */ |
aafa85e7 | 963 | break; |
cf4f7fc3 | 964 | case SND_SOC_DAIFMT_CBM_CFS: |
7a8fceb7 | 965 | /* Input bit clock but output frame sync clock */ |
a818aa5f | 966 | strcr |= SSI_STCR_TFDIR; |
cf4f7fc3 | 967 | break; |
aafa85e7 | 968 | default: |
b6c93f7f | 969 | return -EINVAL; |
aafa85e7 NC |
970 | } |
971 | ||
26b31f4f NC |
972 | stcr = strcr; |
973 | srcr = strcr; | |
aafa85e7 | 974 | |
7a8fceb7 | 975 | /* Set SYN mode and clear RXDIR bit when using SYN or AC97 mode */ |
badc9595 | 976 | if (ssi->synchronous || fsl_ssi_is_ac97(ssi)) { |
a818aa5f NC |
977 | srcr &= ~SSI_SRCR_RXDIR; |
978 | scr |= SSI_SCR_SYN; | |
aafa85e7 NC |
979 | } |
980 | ||
26b31f4f NC |
981 | mask = SSI_STCR_TFDIR | SSI_STCR_TXDIR | SSI_STCR_TSCKP | |
982 | SSI_STCR_TFSL | SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0; | |
983 | ||
984 | regmap_update_bits(ssi->regs, REG_SSI_STCR, mask, stcr); | |
985 | regmap_update_bits(ssi->regs, REG_SSI_SRCR, mask, srcr); | |
986 | ||
987 | mask = SSI_SCR_SYNC_TX_FS | SSI_SCR_I2S_MODE_MASK | | |
988 | SSI_SCR_SYS_CLK_EN | SSI_SCR_SYN; | |
989 | regmap_update_bits(ssi->regs, REG_SSI_SCR, mask, scr); | |
aafa85e7 NC |
990 | |
991 | return 0; | |
85e59af2 MP |
992 | } |
993 | ||
994 | /** | |
7a8fceb7 | 995 | * Configure Digital Audio Interface (DAI) Format |
85e59af2 | 996 | */ |
0c884bed | 997 | static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
85e59af2 | 998 | { |
0c884bed | 999 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
85e59af2 | 1000 | |
7a8fceb7 | 1001 | /* AC97 configured DAIFMT earlier in the probe() */ |
f3176834 | 1002 | if (fsl_ssi_is_ac97(ssi)) |
c997a92a MS |
1003 | return 0; |
1004 | ||
26b31f4f | 1005 | return _fsl_ssi_set_dai_fmt(ssi, fmt); |
aafa85e7 NC |
1006 | } |
1007 | ||
aafa85e7 | 1008 | /** |
7a8fceb7 | 1009 | * Set TDM slot number and slot width |
aafa85e7 | 1010 | */ |
0c884bed | 1011 | static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, |
af4f7f38 | 1012 | u32 rx_mask, int slots, int slot_width) |
aafa85e7 | 1013 | { |
0c884bed | 1014 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
f3176834 | 1015 | struct regmap *regs = ssi->regs; |
aafa85e7 NC |
1016 | u32 val; |
1017 | ||
b0a7043d NC |
1018 | /* The word length should be 8, 10, 12, 16, 18, 20, 22 or 24 */ |
1019 | if (slot_width & 1 || slot_width < 8 || slot_width > 24) { | |
0c884bed | 1020 | dev_err(dai->dev, "invalid slot width: %d\n", slot_width); |
b0a7043d NC |
1021 | return -EINVAL; |
1022 | } | |
1023 | ||
aafa85e7 | 1024 | /* The slot number should be >= 2 if using Network mode or I2S mode */ |
09947634 | 1025 | if (ssi->i2s_net && slots < 2) { |
0c884bed | 1026 | dev_err(dai->dev, "slot number should be >= 2 in I2S or NET\n"); |
aafa85e7 NC |
1027 | return -EINVAL; |
1028 | } | |
1029 | ||
af4f7f38 NC |
1030 | regmap_update_bits(regs, REG_SSI_STCCR, |
1031 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); | |
1032 | regmap_update_bits(regs, REG_SSI_SRCCR, | |
1033 | SSI_SxCCR_DC_MASK, SSI_SxCCR_DC(slots)); | |
aafa85e7 | 1034 | |
09947634 | 1035 | /* Save the SCR register value */ |
a818aa5f | 1036 | regmap_read(regs, REG_SSI_SCR, &val); |
7a8fceb7 | 1037 | /* Temporarily enable SSI to allow SxMSKs to be configurable */ |
af4f7f38 | 1038 | regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, SSI_SCR_SSIEN); |
aafa85e7 | 1039 | |
a818aa5f NC |
1040 | regmap_write(regs, REG_SSI_STMSK, ~tx_mask); |
1041 | regmap_write(regs, REG_SSI_SRMSK, ~rx_mask); | |
aafa85e7 | 1042 | |
7a8fceb7 | 1043 | /* Restore the value of SSIEN bit */ |
a818aa5f | 1044 | regmap_update_bits(regs, REG_SSI_SCR, SSI_SCR_SSIEN, val); |
aafa85e7 | 1045 | |
f3176834 NC |
1046 | ssi->slot_width = slot_width; |
1047 | ssi->slots = slots; | |
b0a7043d | 1048 | |
aafa85e7 NC |
1049 | return 0; |
1050 | } | |
1051 | ||
17467f23 | 1052 | /** |
7a8fceb7 | 1053 | * Start or stop SSI and corresponding DMA transaction. |
17467f23 TT |
1054 | * |
1055 | * The DMA channel is in external master start and pause mode, which | |
1056 | * means the SSI completely controls the flow of data. | |
1057 | */ | |
dee89c4d MB |
1058 | static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, |
1059 | struct snd_soc_dai *dai) | |
17467f23 TT |
1060 | { |
1061 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f3176834 | 1062 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(rtd->cpu_dai); |
7d67bcb6 | 1063 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
9b443e3d | 1064 | |
17467f23 TT |
1065 | switch (cmd) { |
1066 | case SNDRV_PCM_TRIGGER_START: | |
b20e53a8 | 1067 | case SNDRV_PCM_TRIGGER_RESUME: |
17467f23 | 1068 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
7d67bcb6 NC |
1069 | /* |
1070 | * SACCST might be modified via AC Link by a CODEC if it sends | |
1071 | * extra bits in their SLOTREQ requests, which'll accidentally | |
1072 | * send valid data to slots other than normal playback slots. | |
1073 | * | |
1074 | * To be safe, configure SACCST right before TX starts. | |
1075 | */ | |
1076 | if (tx && fsl_ssi_is_ac97(ssi)) | |
1077 | fsl_ssi_tx_ac97_saccst_setup(ssi); | |
1078 | fsl_ssi_config_enable(ssi, tx); | |
17467f23 TT |
1079 | break; |
1080 | ||
1081 | case SNDRV_PCM_TRIGGER_STOP: | |
b20e53a8 | 1082 | case SNDRV_PCM_TRIGGER_SUSPEND: |
17467f23 | 1083 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
7d67bcb6 | 1084 | fsl_ssi_config_disable(ssi, tx); |
17467f23 TT |
1085 | break; |
1086 | ||
1087 | default: | |
1088 | return -EINVAL; | |
1089 | } | |
1090 | ||
1091 | return 0; | |
1092 | } | |
1093 | ||
fc8ba7f9 LPC |
1094 | static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) |
1095 | { | |
f3176834 | 1096 | struct fsl_ssi *ssi = snd_soc_dai_get_drvdata(dai); |
fc8ba7f9 | 1097 | |
40f25633 NC |
1098 | if (ssi->soc->imx && ssi->use_dma) |
1099 | snd_soc_dai_init_dma_data(dai, &ssi->dma_params_tx, | |
1100 | &ssi->dma_params_rx); | |
fc8ba7f9 LPC |
1101 | |
1102 | return 0; | |
1103 | } | |
1104 | ||
85e7652d | 1105 | static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { |
af4f7f38 NC |
1106 | .startup = fsl_ssi_startup, |
1107 | .shutdown = fsl_ssi_shutdown, | |
1108 | .hw_params = fsl_ssi_hw_params, | |
1109 | .hw_free = fsl_ssi_hw_free, | |
1110 | .set_fmt = fsl_ssi_set_dai_fmt, | |
1111 | .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, | |
1112 | .trigger = fsl_ssi_trigger, | |
6335d055 EM |
1113 | }; |
1114 | ||
f0fba2ad | 1115 | static struct snd_soc_dai_driver fsl_ssi_dai_template = { |
fc8ba7f9 | 1116 | .probe = fsl_ssi_dai_probe, |
17467f23 | 1117 | .playback = { |
e3655004 | 1118 | .stream_name = "CPU-Playback", |
2924a998 | 1119 | .channels_min = 1, |
48a260ee | 1120 | .channels_max = 32, |
58055677 | 1121 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
17467f23 TT |
1122 | .formats = FSLSSI_I2S_FORMATS, |
1123 | }, | |
1124 | .capture = { | |
e3655004 | 1125 | .stream_name = "CPU-Capture", |
2924a998 | 1126 | .channels_min = 1, |
48a260ee | 1127 | .channels_max = 32, |
58055677 | 1128 | .rates = SNDRV_PCM_RATE_CONTINUOUS, |
17467f23 TT |
1129 | .formats = FSLSSI_I2S_FORMATS, |
1130 | }, | |
6335d055 | 1131 | .ops = &fsl_ssi_dai_ops, |
17467f23 TT |
1132 | }; |
1133 | ||
3580aa10 | 1134 | static const struct snd_soc_component_driver fsl_ssi_component = { |
af4f7f38 | 1135 | .name = "fsl-ssi", |
3580aa10 KM |
1136 | }; |
1137 | ||
cd7f0295 | 1138 | static struct snd_soc_dai_driver fsl_ssi_ac97_dai = { |
bc263214 | 1139 | .bus_control = true, |
76f38451 | 1140 | .symmetric_channels = 1, |
793e3e9e | 1141 | .probe = fsl_ssi_dai_probe, |
cd7f0295 MP |
1142 | .playback = { |
1143 | .stream_name = "AC97 Playback", | |
1144 | .channels_min = 2, | |
1145 | .channels_max = 2, | |
1146 | .rates = SNDRV_PCM_RATE_8000_48000, | |
10582635 | 1147 | .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S20, |
cd7f0295 MP |
1148 | }, |
1149 | .capture = { | |
1150 | .stream_name = "AC97 Capture", | |
1151 | .channels_min = 2, | |
1152 | .channels_max = 2, | |
1153 | .rates = SNDRV_PCM_RATE_48000, | |
10582635 MS |
1154 | /* 16-bit capture is broken (errata ERR003778) */ |
1155 | .formats = SNDRV_PCM_FMTBIT_S20, | |
cd7f0295 | 1156 | }, |
a5a7ee7c | 1157 | .ops = &fsl_ssi_dai_ops, |
cd7f0295 MP |
1158 | }; |
1159 | ||
f3176834 | 1160 | static struct fsl_ssi *fsl_ac97_data; |
cd7f0295 | 1161 | |
a851a2bb | 1162 | static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
af4f7f38 | 1163 | unsigned short val) |
cd7f0295 | 1164 | { |
43248122 | 1165 | struct regmap *regs = fsl_ac97_data->regs; |
cd7f0295 MP |
1166 | unsigned int lreg; |
1167 | unsigned int lval; | |
8277df3c | 1168 | int ret; |
cd7f0295 MP |
1169 | |
1170 | if (reg > 0x7f) | |
1171 | return; | |
1172 | ||
b880b805 MS |
1173 | mutex_lock(&fsl_ac97_data->ac97_reg_lock); |
1174 | ||
8277df3c MS |
1175 | ret = clk_prepare_enable(fsl_ac97_data->clk); |
1176 | if (ret) { | |
1177 | pr_err("ac97 write clk_prepare_enable failed: %d\n", | |
1178 | ret); | |
b880b805 | 1179 | goto ret_unlock; |
8277df3c | 1180 | } |
cd7f0295 MP |
1181 | |
1182 | lreg = reg << 12; | |
a818aa5f | 1183 | regmap_write(regs, REG_SSI_SACADD, lreg); |
cd7f0295 MP |
1184 | |
1185 | lval = val << 4; | |
a818aa5f | 1186 | regmap_write(regs, REG_SSI_SACDAT, lval); |
cd7f0295 | 1187 | |
af4f7f38 NC |
1188 | regmap_update_bits(regs, REG_SSI_SACNT, |
1189 | SSI_SACNT_RDWR_MASK, SSI_SACNT_WR); | |
cd7f0295 | 1190 | udelay(100); |
8277df3c MS |
1191 | |
1192 | clk_disable_unprepare(fsl_ac97_data->clk); | |
b880b805 MS |
1193 | |
1194 | ret_unlock: | |
1195 | mutex_unlock(&fsl_ac97_data->ac97_reg_lock); | |
cd7f0295 MP |
1196 | } |
1197 | ||
a851a2bb | 1198 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
af4f7f38 | 1199 | unsigned short reg) |
cd7f0295 | 1200 | { |
43248122 | 1201 | struct regmap *regs = fsl_ac97_data->regs; |
b880b805 | 1202 | unsigned short val = 0; |
43248122 | 1203 | u32 reg_val; |
cd7f0295 | 1204 | unsigned int lreg; |
8277df3c MS |
1205 | int ret; |
1206 | ||
b880b805 MS |
1207 | mutex_lock(&fsl_ac97_data->ac97_reg_lock); |
1208 | ||
8277df3c MS |
1209 | ret = clk_prepare_enable(fsl_ac97_data->clk); |
1210 | if (ret) { | |
af4f7f38 | 1211 | pr_err("ac97 read clk_prepare_enable failed: %d\n", ret); |
b880b805 | 1212 | goto ret_unlock; |
8277df3c | 1213 | } |
cd7f0295 MP |
1214 | |
1215 | lreg = (reg & 0x7f) << 12; | |
a818aa5f | 1216 | regmap_write(regs, REG_SSI_SACADD, lreg); |
af4f7f38 NC |
1217 | regmap_update_bits(regs, REG_SSI_SACNT, |
1218 | SSI_SACNT_RDWR_MASK, SSI_SACNT_RD); | |
cd7f0295 MP |
1219 | |
1220 | udelay(100); | |
1221 | ||
a818aa5f | 1222 | regmap_read(regs, REG_SSI_SACDAT, ®_val); |
43248122 | 1223 | val = (reg_val >> 4) & 0xffff; |
cd7f0295 | 1224 | |
8277df3c MS |
1225 | clk_disable_unprepare(fsl_ac97_data->clk); |
1226 | ||
b880b805 MS |
1227 | ret_unlock: |
1228 | mutex_unlock(&fsl_ac97_data->ac97_reg_lock); | |
cd7f0295 MP |
1229 | return val; |
1230 | } | |
1231 | ||
1232 | static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = { | |
af4f7f38 NC |
1233 | .read = fsl_ssi_ac97_read, |
1234 | .write = fsl_ssi_ac97_write, | |
cd7f0295 MP |
1235 | }; |
1236 | ||
a1d154ac NC |
1237 | /** |
1238 | * Initialize SSI registers | |
1239 | */ | |
1240 | static int fsl_ssi_hw_init(struct fsl_ssi *ssi) | |
1241 | { | |
1242 | u32 wm = ssi->fifo_watermark; | |
1243 | ||
1244 | /* Initialize regvals */ | |
1245 | fsl_ssi_setup_regvals(ssi); | |
1246 | ||
1247 | /* Set watermarks */ | |
1248 | regmap_write(ssi->regs, REG_SSI_SFCSR, | |
1249 | SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) | | |
1250 | SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm)); | |
1251 | ||
1252 | /* Enable Dual FIFO mode */ | |
1253 | if (ssi->use_dual_fifo) | |
1254 | regmap_update_bits(ssi->regs, REG_SSI_SCR, | |
1255 | SSI_SCR_TCH_EN, SSI_SCR_TCH_EN); | |
1256 | ||
37ac30a4 NC |
1257 | /* AC97 should start earlier to communicate with CODECs */ |
1258 | if (fsl_ssi_is_ac97(ssi)) { | |
26b31f4f | 1259 | _fsl_ssi_set_dai_fmt(ssi, ssi->dai_fmt); |
37ac30a4 NC |
1260 | fsl_ssi_setup_ac97(ssi); |
1261 | } | |
1262 | ||
a1d154ac NC |
1263 | return 0; |
1264 | } | |
1265 | ||
37ac30a4 NC |
1266 | /** |
1267 | * Clear SSI registers | |
1268 | */ | |
1269 | static void fsl_ssi_hw_clean(struct fsl_ssi *ssi) | |
1270 | { | |
1271 | /* Disable registers for AC97 */ | |
1272 | if (fsl_ssi_is_ac97(ssi)) { | |
1273 | /* Disable TE and RE bits first */ | |
1274 | regmap_update_bits(ssi->regs, REG_SSI_SCR, | |
1275 | SSI_SCR_TE | SSI_SCR_RE, 0); | |
1276 | /* Disable AC97 mode */ | |
1277 | regmap_write(ssi->regs, REG_SSI_SACNT, 0); | |
1278 | /* Unset WAIT bits */ | |
1279 | regmap_write(ssi->regs, REG_SSI_SOR, 0); | |
1280 | /* Disable SSI -- software reset */ | |
1281 | regmap_update_bits(ssi->regs, REG_SSI_SCR, SSI_SCR_SSIEN, 0); | |
1282 | } | |
1283 | } | |
17467f23 | 1284 | /** |
f0fba2ad | 1285 | * Make every character in a string lower-case |
17467f23 | 1286 | */ |
f0fba2ad LG |
1287 | static void make_lowercase(char *s) |
1288 | { | |
c6682fed FE |
1289 | if (!s) |
1290 | return; | |
1291 | for (; *s; s++) | |
1292 | *s = tolower(*s); | |
f0fba2ad LG |
1293 | } |
1294 | ||
49da09e2 | 1295 | static int fsl_ssi_imx_probe(struct platform_device *pdev, |
af4f7f38 | 1296 | struct fsl_ssi *ssi, void __iomem *iomem) |
49da09e2 | 1297 | { |
8483c067 | 1298 | struct device *dev = &pdev->dev; |
49da09e2 MP |
1299 | int ret; |
1300 | ||
7a8fceb7 | 1301 | /* Backward compatible for a DT without ipg clock name assigned */ |
f3176834 | 1302 | if (ssi->has_ipg_clk_name) |
8483c067 | 1303 | ssi->clk = devm_clk_get(dev, "ipg"); |
f4a43cab | 1304 | else |
8483c067 | 1305 | ssi->clk = devm_clk_get(dev, NULL); |
f3176834 NC |
1306 | if (IS_ERR(ssi->clk)) { |
1307 | ret = PTR_ERR(ssi->clk); | |
2c225036 | 1308 | dev_err(dev, "failed to get clock: %d\n", ret); |
49da09e2 MP |
1309 | return ret; |
1310 | } | |
1311 | ||
7a8fceb7 | 1312 | /* Enable the clock since regmap will not handle it in this case */ |
f3176834 NC |
1313 | if (!ssi->has_ipg_clk_name) { |
1314 | ret = clk_prepare_enable(ssi->clk); | |
f4a43cab | 1315 | if (ret) { |
8483c067 | 1316 | dev_err(dev, "clk_prepare_enable failed: %d\n", ret); |
f4a43cab SW |
1317 | return ret; |
1318 | } | |
49da09e2 MP |
1319 | } |
1320 | ||
7a8fceb7 | 1321 | /* Do not error out for slave cases that live without a baud clock */ |
8483c067 | 1322 | ssi->baudclk = devm_clk_get(dev, "baud"); |
f3176834 | 1323 | if (IS_ERR(ssi->baudclk)) |
2c225036 | 1324 | dev_dbg(dev, "failed to get baud clock: %ld\n", |
f3176834 | 1325 | PTR_ERR(ssi->baudclk)); |
49da09e2 | 1326 | |
f3176834 NC |
1327 | ssi->dma_params_tx.maxburst = ssi->dma_maxburst; |
1328 | ssi->dma_params_rx.maxburst = ssi->dma_maxburst; | |
a818aa5f NC |
1329 | ssi->dma_params_tx.addr = ssi->ssi_phys + REG_SSI_STX0; |
1330 | ssi->dma_params_rx.addr = ssi->ssi_phys + REG_SSI_SRX0; | |
49da09e2 | 1331 | |
76f38451 NC |
1332 | /* Use even numbers to avoid channel swap due to SDMA script design */ |
1333 | if (ssi->use_dual_fifo) { | |
f3176834 NC |
1334 | ssi->dma_params_tx.maxburst &= ~0x1; |
1335 | ssi->dma_params_rx.maxburst &= ~0x1; | |
49da09e2 MP |
1336 | } |
1337 | ||
f3176834 | 1338 | if (!ssi->use_dma) { |
4d9b7926 | 1339 | /* |
7a8fceb7 NC |
1340 | * Some boards use an incompatible codec. Use imx-fiq-pcm-audio |
1341 | * to get it working, as DMA is not possible in this situation. | |
4d9b7926 | 1342 | */ |
f3176834 NC |
1343 | ssi->fiq_params.irq = ssi->irq; |
1344 | ssi->fiq_params.base = iomem; | |
1345 | ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx; | |
1346 | ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx; | |
4d9b7926 | 1347 | |
f3176834 | 1348 | ret = imx_pcm_fiq_init(pdev, &ssi->fiq_params); |
4d9b7926 MP |
1349 | if (ret) |
1350 | goto error_pcm; | |
1351 | } else { | |
0d69e0dd | 1352 | ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE); |
4d9b7926 MP |
1353 | if (ret) |
1354 | goto error_pcm; | |
1355 | } | |
1356 | ||
49da09e2 | 1357 | return 0; |
4d9b7926 MP |
1358 | |
1359 | error_pcm: | |
f3176834 NC |
1360 | if (!ssi->has_ipg_clk_name) |
1361 | clk_disable_unprepare(ssi->clk); | |
af4f7f38 | 1362 | |
4d9b7926 | 1363 | return ret; |
49da09e2 MP |
1364 | } |
1365 | ||
af4f7f38 | 1366 | static void fsl_ssi_imx_clean(struct platform_device *pdev, struct fsl_ssi *ssi) |
49da09e2 | 1367 | { |
f3176834 | 1368 | if (!ssi->use_dma) |
4d9b7926 | 1369 | imx_pcm_fiq_exit(pdev); |
f3176834 NC |
1370 | if (!ssi->has_ipg_clk_name) |
1371 | clk_disable_unprepare(ssi->clk); | |
49da09e2 MP |
1372 | } |
1373 | ||
76f38451 | 1374 | static int fsl_ssi_probe_from_dt(struct fsl_ssi *ssi) |
17467f23 | 1375 | { |
76f38451 NC |
1376 | struct device *dev = ssi->dev; |
1377 | struct device_node *np = dev->of_node; | |
c1953bfe | 1378 | const struct of_device_id *of_id; |
f0fba2ad | 1379 | const char *p, *sprop; |
da18bcf7 | 1380 | const __be32 *iprop; |
76f38451 NC |
1381 | u32 dmas[4]; |
1382 | int ret; | |
17467f23 | 1383 | |
8483c067 | 1384 | of_id = of_match_device(fsl_ssi_ids, dev); |
fcdbadef | 1385 | if (!of_id || !of_id->data) |
c1953bfe | 1386 | return -EINVAL; |
c1953bfe | 1387 | |
f3176834 | 1388 | ssi->soc = of_id->data; |
76f38451 NC |
1389 | |
1390 | ret = of_property_match_string(np, "clock-names", "ipg"); | |
1391 | /* Get error code if not found */ | |
1392 | ssi->has_ipg_clk_name = ret >= 0; | |
fcdbadef | 1393 | |
7a8fceb7 | 1394 | /* Check if being used in AC97 mode */ |
85e59af2 | 1395 | sprop = of_get_property(np, "fsl,mode", NULL); |
76f38451 NC |
1396 | if (sprop && !strcmp(sprop, "ac97-slave")) { |
1397 | ssi->dai_fmt = FSLSSI_AC97_DAIFMT; | |
1398 | ||
1399 | ret = of_property_read_u32(np, "cell-index", &ssi->card_idx); | |
1400 | if (ret) { | |
1401 | dev_err(dev, "failed to get SSI index property\n"); | |
1402 | return -EINVAL; | |
1403 | } | |
1404 | strcpy(ssi->card_name, "ac97-codec"); | |
1405 | } else if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) { | |
1406 | /* | |
1407 | * In synchronous mode, STCK and STFS ports are used by RX | |
1408 | * as well. So the software should limit the sample rates, | |
1409 | * sample bits and channels to be symmetric. | |
1410 | * | |
1411 | * This is exclusive with FSLSSI_AC97_FORMATS as AC97 runs | |
1412 | * in the SSI synchronous mode however it does not have to | |
1413 | * limit symmetric sample rates and sample bits. | |
1414 | */ | |
1415 | ssi->synchronous = true; | |
85e59af2 MP |
1416 | } |
1417 | ||
7a8fceb7 | 1418 | /* Select DMA or FIQ */ |
f3176834 | 1419 | ssi->use_dma = !of_property_read_bool(np, "fsl,fiq-stream-filter"); |
de623ece | 1420 | |
76f38451 NC |
1421 | /* Fetch FIFO depth; Set to 8 for older DT without this property */ |
1422 | iprop = of_get_property(np, "fsl,fifo-depth", NULL); | |
1423 | if (iprop) | |
1424 | ssi->fifo_depth = be32_to_cpup(iprop); | |
1425 | else | |
1426 | ssi->fifo_depth = 8; | |
1427 | ||
1428 | /* Use dual FIFO mode depending on the support from SDMA script */ | |
1429 | ret = of_property_read_u32_array(np, "dmas", dmas, 4); | |
1430 | if (ssi->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) | |
1431 | ssi->use_dual_fifo = true; | |
1432 | ||
1433 | /* | |
1434 | * Backward compatible for older bindings by manually triggering the | |
1435 | * machine driver's probe(). Use /compatible property, including the | |
1436 | * address of CPU DAI driver structure, as the name of machine driver | |
1437 | * | |
1438 | * If card_name is set by AC97 earlier, bypass here since it uses a | |
1439 | * different name to register the device. | |
1440 | */ | |
1441 | if (!ssi->card_name[0] && of_get_property(np, "codec-handle", NULL)) { | |
1442 | sprop = of_get_property(of_find_node_by_path("/"), | |
1443 | "compatible", NULL); | |
1444 | /* Strip "fsl," in the compatible name if applicable */ | |
1445 | p = strrchr(sprop, ','); | |
1446 | if (p) | |
1447 | sprop = p + 1; | |
1448 | snprintf(ssi->card_name, sizeof(ssi->card_name), | |
1449 | "snd-soc-%s", sprop); | |
1450 | make_lowercase(ssi->card_name); | |
1451 | ssi->card_idx = 0; | |
1452 | } | |
1453 | ||
1454 | return 0; | |
1455 | } | |
1456 | ||
1457 | static int fsl_ssi_probe(struct platform_device *pdev) | |
1458 | { | |
1459 | struct regmap_config regconfig = fsl_ssi_regconfig; | |
1460 | struct device *dev = &pdev->dev; | |
1461 | struct fsl_ssi *ssi; | |
1462 | struct resource *res; | |
1463 | void __iomem *iomem; | |
1464 | int ret = 0; | |
1465 | ||
1466 | ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL); | |
1467 | if (!ssi) | |
1468 | return -ENOMEM; | |
1469 | ||
1470 | ssi->dev = dev; | |
1471 | ||
1472 | /* Probe from DT */ | |
1473 | ret = fsl_ssi_probe_from_dt(ssi); | |
1474 | if (ret) | |
1475 | return ret; | |
1476 | ||
f3176834 NC |
1477 | if (fsl_ssi_is_ac97(ssi)) { |
1478 | memcpy(&ssi->cpu_dai_drv, &fsl_ssi_ac97_dai, | |
af4f7f38 | 1479 | sizeof(fsl_ssi_ac97_dai)); |
f3176834 | 1480 | fsl_ac97_data = ssi; |
cd7f0295 | 1481 | } else { |
f3176834 | 1482 | memcpy(&ssi->cpu_dai_drv, &fsl_ssi_dai_template, |
cd7f0295 MP |
1483 | sizeof(fsl_ssi_dai_template)); |
1484 | } | |
8483c067 | 1485 | ssi->cpu_dai_drv.name = dev_name(dev); |
f0fba2ad | 1486 | |
ca264189 | 1487 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
8483c067 | 1488 | iomem = devm_ioremap_resource(dev, res); |
ca264189 FE |
1489 | if (IS_ERR(iomem)) |
1490 | return PTR_ERR(iomem); | |
f3176834 | 1491 | ssi->ssi_phys = res->start; |
43248122 | 1492 | |
f3176834 | 1493 | if (ssi->soc->imx21regs) { |
7a8fceb7 | 1494 | /* No SACC{ST,EN,DIS} regs in imx21-class SSI */ |
a818aa5f | 1495 | regconfig.max_register = REG_SSI_SRMSK; |
f26b3b2a | 1496 | regconfig.num_reg_defaults_raw = |
a818aa5f | 1497 | REG_SSI_SRMSK / sizeof(uint32_t) + 1; |
6139b1b1 MS |
1498 | } |
1499 | ||
76f38451 | 1500 | if (ssi->has_ipg_clk_name) |
8483c067 NC |
1501 | ssi->regs = devm_regmap_init_mmio_clk(dev, "ipg", iomem, |
1502 | ®config); | |
76f38451 NC |
1503 | else |
1504 | ssi->regs = devm_regmap_init_mmio(dev, iomem, ®config); | |
f3176834 | 1505 | if (IS_ERR(ssi->regs)) { |
2c225036 | 1506 | dev_err(dev, "failed to init register map\n"); |
f3176834 | 1507 | return PTR_ERR(ssi->regs); |
43248122 | 1508 | } |
1fab6caf | 1509 | |
f3176834 NC |
1510 | ssi->irq = platform_get_irq(pdev, 0); |
1511 | if (ssi->irq < 0) { | |
8483c067 | 1512 | dev_err(dev, "no irq for node %s\n", pdev->name); |
f3176834 | 1513 | return ssi->irq; |
1fab6caf TT |
1514 | } |
1515 | ||
76f38451 NC |
1516 | /* Set software limitations for synchronous mode except AC97 */ |
1517 | if (ssi->synchronous && !fsl_ssi_is_ac97(ssi)) { | |
1518 | ssi->cpu_dai_drv.symmetric_rates = 1; | |
f3176834 | 1519 | ssi->cpu_dai_drv.symmetric_channels = 1; |
76f38451 | 1520 | ssi->cpu_dai_drv.symmetric_samplebits = 1; |
07a9483a | 1521 | } |
17467f23 | 1522 | |
4ee437fb | 1523 | /* |
7a8fceb7 | 1524 | * Configure TX and RX DMA watermarks -- when to send a DMA request |
4ee437fb | 1525 | * |
7a8fceb7 NC |
1526 | * Values should be tested to avoid FIFO under/over run. Set maxburst |
1527 | * to fifo_watermark to maxiumize DMA transaction to reduce overhead. | |
4ee437fb | 1528 | */ |
f3176834 | 1529 | switch (ssi->fifo_depth) { |
4ee437fb CC |
1530 | case 15: |
1531 | /* | |
7a8fceb7 NC |
1532 | * Set to 8 as a balanced configuration -- When TX FIFO has 8 |
1533 | * empty slots, send a DMA request to fill these 8 slots. The | |
1534 | * remaining 7 slots should be able to allow DMA to finish the | |
1535 | * transaction before TX FIFO underruns; Same applies to RX. | |
1536 | * | |
1537 | * Tested with cases running at 48kHz @ 16 bits x 16 channels | |
4ee437fb | 1538 | */ |
f3176834 NC |
1539 | ssi->fifo_watermark = 8; |
1540 | ssi->dma_maxburst = 8; | |
4ee437fb CC |
1541 | break; |
1542 | case 8: | |
1543 | default: | |
7a8fceb7 | 1544 | /* Safely use old watermark configurations for older chips */ |
f3176834 NC |
1545 | ssi->fifo_watermark = ssi->fifo_depth - 2; |
1546 | ssi->dma_maxburst = ssi->fifo_depth - 2; | |
4ee437fb CC |
1547 | break; |
1548 | } | |
1549 | ||
8483c067 | 1550 | dev_set_drvdata(dev, ssi); |
4d9b7926 | 1551 | |
f3176834 NC |
1552 | if (ssi->soc->imx) { |
1553 | ret = fsl_ssi_imx_probe(pdev, ssi, iomem); | |
49da09e2 | 1554 | if (ret) |
2ffa5310 | 1555 | return ret; |
0888efd1 MP |
1556 | } |
1557 | ||
f3176834 NC |
1558 | if (fsl_ssi_is_ac97(ssi)) { |
1559 | mutex_init(&ssi->ac97_reg_lock); | |
695b78b5 MS |
1560 | ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev); |
1561 | if (ret) { | |
2c225036 | 1562 | dev_err(dev, "failed to set AC'97 ops\n"); |
695b78b5 MS |
1563 | goto error_ac97_ops; |
1564 | } | |
1565 | } | |
1566 | ||
8483c067 | 1567 | ret = devm_snd_soc_register_component(dev, &fsl_ssi_component, |
f3176834 | 1568 | &ssi->cpu_dai_drv, 1); |
4d9b7926 | 1569 | if (ret) { |
8483c067 | 1570 | dev_err(dev, "failed to register DAI: %d\n", ret); |
4d9b7926 MP |
1571 | goto error_asoc_register; |
1572 | } | |
1573 | ||
f3176834 | 1574 | if (ssi->use_dma) { |
8483c067 NC |
1575 | ret = devm_request_irq(dev, ssi->irq, fsl_ssi_isr, 0, |
1576 | dev_name(dev), ssi); | |
f0377086 | 1577 | if (ret < 0) { |
2c225036 | 1578 | dev_err(dev, "failed to claim irq %u\n", ssi->irq); |
299e7e97 | 1579 | goto error_asoc_register; |
f0377086 | 1580 | } |
09ce1111 SG |
1581 | } |
1582 | ||
8483c067 | 1583 | ret = fsl_ssi_debugfs_create(&ssi->dbg_stats, dev); |
9368acc4 | 1584 | if (ret) |
299e7e97 | 1585 | goto error_asoc_register; |
09ce1111 | 1586 | |
a1d154ac NC |
1587 | /* Initially configures SSI registers */ |
1588 | fsl_ssi_hw_init(ssi); | |
1589 | ||
76f38451 NC |
1590 | /* Register a platform device for older bindings or AC97 */ |
1591 | if (ssi->card_name[0]) { | |
1592 | struct device *parent = dev; | |
1593 | /* | |
1594 | * Do not set SSI dev as the parent of AC97 CODEC device since | |
1595 | * it does not have a DT node. Otherwise ASoC core will assume | |
1596 | * CODEC has the same DT node as the SSI, so it may bypass the | |
1597 | * dai_probe() of SSI and then cause NULL DMA data pointers. | |
1598 | */ | |
1599 | if (fsl_ssi_is_ac97(ssi)) | |
1600 | parent = NULL; | |
1601 | ||
1602 | ssi->card_pdev = platform_device_register_data(parent, | |
1603 | ssi->card_name, ssi->card_idx, NULL, 0); | |
1604 | if (IS_ERR(ssi->card_pdev)) { | |
1605 | ret = PTR_ERR(ssi->card_pdev); | |
1606 | dev_err(dev, "failed to register %s: %d\n", | |
1607 | ssi->card_name, ret); | |
8ed0c842 MS |
1608 | goto error_sound_card; |
1609 | } | |
1610 | } | |
1611 | ||
f0fba2ad | 1612 | return 0; |
87a0632b | 1613 | |
4d9b7926 | 1614 | error_sound_card: |
f3176834 | 1615 | fsl_ssi_debugfs_remove(&ssi->dbg_stats); |
4d9b7926 | 1616 | error_asoc_register: |
f3176834 | 1617 | if (fsl_ssi_is_ac97(ssi)) |
695b78b5 | 1618 | snd_soc_set_ac97_ops(NULL); |
695b78b5 | 1619 | error_ac97_ops: |
f3176834 NC |
1620 | if (fsl_ssi_is_ac97(ssi)) |
1621 | mutex_destroy(&ssi->ac97_reg_lock); | |
b880b805 | 1622 | |
f3176834 NC |
1623 | if (ssi->soc->imx) |
1624 | fsl_ssi_imx_clean(pdev, ssi); | |
1fab6caf | 1625 | |
87a0632b | 1626 | return ret; |
17467f23 | 1627 | } |
17467f23 | 1628 | |
38fec727 | 1629 | static int fsl_ssi_remove(struct platform_device *pdev) |
17467f23 | 1630 | { |
f3176834 | 1631 | struct fsl_ssi *ssi = dev_get_drvdata(&pdev->dev); |
17467f23 | 1632 | |
f3176834 | 1633 | fsl_ssi_debugfs_remove(&ssi->dbg_stats); |
9368acc4 | 1634 | |
76f38451 NC |
1635 | if (ssi->card_pdev) |
1636 | platform_device_unregister(ssi->card_pdev); | |
49da09e2 | 1637 | |
37ac30a4 NC |
1638 | /* Clean up SSI registers */ |
1639 | fsl_ssi_hw_clean(ssi); | |
1640 | ||
f3176834 NC |
1641 | if (ssi->soc->imx) |
1642 | fsl_ssi_imx_clean(pdev, ssi); | |
49da09e2 | 1643 | |
f3176834 | 1644 | if (fsl_ssi_is_ac97(ssi)) { |
04143d61 | 1645 | snd_soc_set_ac97_ops(NULL); |
f3176834 | 1646 | mutex_destroy(&ssi->ac97_reg_lock); |
b880b805 | 1647 | } |
04143d61 | 1648 | |
f0fba2ad | 1649 | return 0; |
17467f23 | 1650 | } |
f0fba2ad | 1651 | |
05cf2379 ZW |
1652 | #ifdef CONFIG_PM_SLEEP |
1653 | static int fsl_ssi_suspend(struct device *dev) | |
1654 | { | |
f3176834 NC |
1655 | struct fsl_ssi *ssi = dev_get_drvdata(dev); |
1656 | struct regmap *regs = ssi->regs; | |
05cf2379 | 1657 | |
a818aa5f NC |
1658 | regmap_read(regs, REG_SSI_SFCSR, &ssi->regcache_sfcsr); |
1659 | regmap_read(regs, REG_SSI_SACNT, &ssi->regcache_sacnt); | |
05cf2379 ZW |
1660 | |
1661 | regcache_cache_only(regs, true); | |
1662 | regcache_mark_dirty(regs); | |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
1667 | static int fsl_ssi_resume(struct device *dev) | |
1668 | { | |
f3176834 NC |
1669 | struct fsl_ssi *ssi = dev_get_drvdata(dev); |
1670 | struct regmap *regs = ssi->regs; | |
05cf2379 ZW |
1671 | |
1672 | regcache_cache_only(regs, false); | |
1673 | ||
a818aa5f | 1674 | regmap_update_bits(regs, REG_SSI_SFCSR, |
af4f7f38 NC |
1675 | SSI_SFCSR_RFWM1_MASK | SSI_SFCSR_TFWM1_MASK | |
1676 | SSI_SFCSR_RFWM0_MASK | SSI_SFCSR_TFWM0_MASK, | |
1677 | ssi->regcache_sfcsr); | |
a818aa5f | 1678 | regmap_write(regs, REG_SSI_SACNT, ssi->regcache_sacnt); |
05cf2379 ZW |
1679 | |
1680 | return regcache_sync(regs); | |
1681 | } | |
1682 | #endif /* CONFIG_PM_SLEEP */ | |
1683 | ||
1684 | static const struct dev_pm_ops fsl_ssi_pm = { | |
1685 | SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume) | |
1686 | }; | |
1687 | ||
f07eb223 | 1688 | static struct platform_driver fsl_ssi_driver = { |
f0fba2ad LG |
1689 | .driver = { |
1690 | .name = "fsl-ssi-dai", | |
f0fba2ad | 1691 | .of_match_table = fsl_ssi_ids, |
05cf2379 | 1692 | .pm = &fsl_ssi_pm, |
f0fba2ad LG |
1693 | }, |
1694 | .probe = fsl_ssi_probe, | |
1695 | .remove = fsl_ssi_remove, | |
1696 | }; | |
17467f23 | 1697 | |
ba0a7e02 | 1698 | module_platform_driver(fsl_ssi_driver); |
a454dad1 | 1699 | |
f3142807 | 1700 | MODULE_ALIAS("platform:fsl-ssi-dai"); |
17467f23 TT |
1701 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); |
1702 | MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver"); | |
f0fba2ad | 1703 | MODULE_LICENSE("GPL v2"); |