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43550821 XL |
1 | /* |
2 | * Copyright 2012-2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef __FSL_SAI_H | |
10 | #define __FSL_SAI_H | |
11 | ||
12 | #include <sound/dmaengine_pcm.h> | |
13 | ||
14 | #define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
15 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
16 | SNDRV_PCM_FMTBIT_S24_LE) | |
17 | ||
18 | /* SAI Transmit/Recieve Control Register */ | |
19 | #define FSL_SAI_TCSR 0x00 | |
20 | #define FSL_SAI_RCSR 0x80 | |
21 | #define FSL_SAI_CSR_TERE BIT(31) | |
22 | #define FSL_SAI_CSR_FWF BIT(17) | |
23 | #define FSL_SAI_CSR_FRIE BIT(8) | |
24 | #define FSL_SAI_CSR_FRDE BIT(0) | |
25 | ||
26 | /* SAI Transmit Data/FIFO/MASK Register */ | |
27 | #define FSL_SAI_TDR 0x20 | |
28 | #define FSL_SAI_TFR 0x40 | |
29 | #define FSL_SAI_TMR 0x60 | |
30 | ||
31 | /* SAI Recieve Data/FIFO/MASK Register */ | |
32 | #define FSL_SAI_RDR 0xa0 | |
33 | #define FSL_SAI_RFR 0xc0 | |
34 | #define FSL_SAI_RMR 0xe0 | |
35 | ||
36 | /* SAI Transmit and Recieve Configuration 1 Register */ | |
37 | #define FSL_SAI_TCR1 0x04 | |
38 | #define FSL_SAI_RCR1 0x84 | |
39 | ||
40 | /* SAI Transmit and Recieve Configuration 2 Register */ | |
41 | #define FSL_SAI_TCR2 0x08 | |
42 | #define FSL_SAI_RCR2 0x88 | |
43 | #define FSL_SAI_CR2_SYNC BIT(30) | |
44 | #define FSL_SAI_CR2_MSEL_MASK (0xff << 26) | |
45 | #define FSL_SAI_CR2_MSEL_BUS 0 | |
46 | #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26) | |
47 | #define FSL_SAI_CR2_MSEL_MCLK2 BIT(27) | |
48 | #define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27)) | |
49 | #define FSL_SAI_CR2_BCP BIT(25) | |
50 | #define FSL_SAI_CR2_BCD_MSTR BIT(24) | |
51 | ||
52 | /* SAI Transmit and Recieve Configuration 3 Register */ | |
53 | #define FSL_SAI_TCR3 0x0c | |
54 | #define FSL_SAI_RCR3 0x8c | |
55 | #define FSL_SAI_CR3_TRCE BIT(16) | |
56 | #define FSL_SAI_CR3_WDFL(x) (x) | |
57 | #define FSL_SAI_CR3_WDFL_MASK 0x1f | |
58 | ||
59 | /* SAI Transmit and Recieve Configuration 4 Register */ | |
60 | #define FSL_SAI_TCR4 0x10 | |
61 | #define FSL_SAI_RCR4 0x90 | |
62 | #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16) | |
63 | #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16) | |
64 | #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8) | |
65 | #define FSL_SAI_CR4_SYWD_MASK (0x1f << 8) | |
66 | #define FSL_SAI_CR4_MF BIT(4) | |
67 | #define FSL_SAI_CR4_FSE BIT(3) | |
68 | #define FSL_SAI_CR4_FSP BIT(1) | |
69 | #define FSL_SAI_CR4_FSD_MSTR BIT(0) | |
70 | ||
71 | /* SAI Transmit and Recieve Configuration 5 Register */ | |
72 | #define FSL_SAI_TCR5 0x14 | |
73 | #define FSL_SAI_RCR5 0x94 | |
74 | #define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24) | |
75 | #define FSL_SAI_CR5_WNW_MASK (0x1f << 24) | |
76 | #define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16) | |
77 | #define FSL_SAI_CR5_W0W_MASK (0x1f << 16) | |
78 | #define FSL_SAI_CR5_FBT(x) ((x) << 8) | |
79 | #define FSL_SAI_CR5_FBT_MASK (0x1f << 8) | |
80 | ||
81 | /* SAI type */ | |
82 | #define FSL_SAI_DMA BIT(0) | |
83 | #define FSL_SAI_USE_AC97 BIT(1) | |
84 | #define FSL_SAI_NET BIT(2) | |
85 | #define FSL_SAI_TRA_SYN BIT(3) | |
86 | #define FSL_SAI_REC_SYN BIT(4) | |
87 | #define FSL_SAI_USE_I2S_SLAVE BIT(5) | |
88 | ||
89 | #define FSL_FMT_TRANSMITTER 0 | |
90 | #define FSL_FMT_RECEIVER 1 | |
91 | ||
92 | /* SAI clock sources */ | |
93 | #define FSL_SAI_CLK_BUS 0 | |
94 | #define FSL_SAI_CLK_MAST1 1 | |
95 | #define FSL_SAI_CLK_MAST2 2 | |
96 | #define FSL_SAI_CLK_MAST3 3 | |
97 | ||
98 | /* SAI data transfer numbers per DMA request */ | |
99 | #define FSL_SAI_MAXBURST_TX 6 | |
100 | #define FSL_SAI_MAXBURST_RX 6 | |
101 | ||
102 | struct fsl_sai { | |
103 | struct clk *clk; | |
104 | ||
105 | void __iomem *base; | |
106 | ||
107 | bool big_endian_regs; | |
108 | bool big_endian_data; | |
109 | ||
110 | struct snd_dmaengine_dai_dma_data dma_params_rx; | |
111 | struct snd_dmaengine_dai_dma_data dma_params_tx; | |
112 | }; | |
113 | ||
114 | #endif /* __FSL_SAI_H */ |