Commit | Line | Data |
---|---|---|
43550821 XL |
1 | /* |
2 | * Freescale ALSA SoC Digital Audio Interface (SAI) driver. | |
3 | * | |
c3ecef21 | 4 | * Copyright 2012-2015 Freescale Semiconductor, Inc. |
43550821 XL |
5 | * |
6 | * This program is free software, you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation, either version 2 of the License, or(at your | |
9 | * option) any later version. | |
10 | * | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of_address.h> | |
78957fc3 | 18 | #include <linux/regmap.h> |
43550821 XL |
19 | #include <linux/slab.h> |
20 | #include <sound/core.h> | |
21 | #include <sound/dmaengine_pcm.h> | |
22 | #include <sound/pcm_params.h> | |
23 | ||
24 | #include "fsl_sai.h" | |
c7540644 | 25 | #include "imx-pcm.h" |
43550821 | 26 | |
e2681a1b NC |
27 | #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ |
28 | FSL_SAI_CSR_FEIE) | |
29 | ||
30 | static irqreturn_t fsl_sai_isr(int irq, void *devid) | |
31 | { | |
32 | struct fsl_sai *sai = (struct fsl_sai *)devid; | |
33 | struct device *dev = &sai->pdev->dev; | |
413312aa NC |
34 | u32 flags, xcsr, mask; |
35 | bool irq_none = true; | |
36 | ||
37 | /* | |
38 | * Both IRQ status bits and IRQ mask bits are in the xCSR but | |
39 | * different shifts. And we here create a mask only for those | |
40 | * IRQs that we activated. | |
41 | */ | |
e2681a1b NC |
42 | mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; |
43 | ||
44 | /* Tx IRQ */ | |
45 | regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr); | |
413312aa NC |
46 | flags = xcsr & mask; |
47 | ||
48 | if (flags) | |
49 | irq_none = false; | |
50 | else | |
51 | goto irq_rx; | |
e2681a1b | 52 | |
413312aa | 53 | if (flags & FSL_SAI_CSR_WSF) |
e2681a1b NC |
54 | dev_dbg(dev, "isr: Start of Tx word detected\n"); |
55 | ||
413312aa | 56 | if (flags & FSL_SAI_CSR_SEF) |
e2681a1b NC |
57 | dev_warn(dev, "isr: Tx Frame sync error detected\n"); |
58 | ||
413312aa | 59 | if (flags & FSL_SAI_CSR_FEF) { |
e2681a1b NC |
60 | dev_warn(dev, "isr: Transmit underrun detected\n"); |
61 | /* FIFO reset for safety */ | |
62 | xcsr |= FSL_SAI_CSR_FR; | |
63 | } | |
64 | ||
413312aa | 65 | if (flags & FSL_SAI_CSR_FWF) |
e2681a1b NC |
66 | dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); |
67 | ||
413312aa | 68 | if (flags & FSL_SAI_CSR_FRF) |
e2681a1b NC |
69 | dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); |
70 | ||
413312aa NC |
71 | flags &= FSL_SAI_CSR_xF_W_MASK; |
72 | xcsr &= ~FSL_SAI_CSR_xF_MASK; | |
73 | ||
74 | if (flags) | |
75 | regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr); | |
e2681a1b | 76 | |
413312aa | 77 | irq_rx: |
e2681a1b NC |
78 | /* Rx IRQ */ |
79 | regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr); | |
413312aa | 80 | flags = xcsr & mask; |
e2681a1b | 81 | |
413312aa NC |
82 | if (flags) |
83 | irq_none = false; | |
84 | else | |
85 | goto out; | |
86 | ||
87 | if (flags & FSL_SAI_CSR_WSF) | |
e2681a1b NC |
88 | dev_dbg(dev, "isr: Start of Rx word detected\n"); |
89 | ||
413312aa | 90 | if (flags & FSL_SAI_CSR_SEF) |
e2681a1b NC |
91 | dev_warn(dev, "isr: Rx Frame sync error detected\n"); |
92 | ||
413312aa | 93 | if (flags & FSL_SAI_CSR_FEF) { |
e2681a1b NC |
94 | dev_warn(dev, "isr: Receive overflow detected\n"); |
95 | /* FIFO reset for safety */ | |
96 | xcsr |= FSL_SAI_CSR_FR; | |
97 | } | |
98 | ||
413312aa | 99 | if (flags & FSL_SAI_CSR_FWF) |
e2681a1b NC |
100 | dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); |
101 | ||
413312aa | 102 | if (flags & FSL_SAI_CSR_FRF) |
e2681a1b NC |
103 | dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); |
104 | ||
413312aa NC |
105 | flags &= FSL_SAI_CSR_xF_W_MASK; |
106 | xcsr &= ~FSL_SAI_CSR_xF_MASK; | |
e2681a1b | 107 | |
413312aa | 108 | if (flags) |
4800f88b | 109 | regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr); |
413312aa NC |
110 | |
111 | out: | |
112 | if (irq_none) | |
113 | return IRQ_NONE; | |
114 | else | |
115 | return IRQ_HANDLED; | |
e2681a1b NC |
116 | } |
117 | ||
43550821 XL |
118 | static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, |
119 | int clk_id, unsigned int freq, int fsl_dir) | |
120 | { | |
43550821 | 121 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b NC |
122 | bool tx = fsl_dir == FSL_FMT_TRANSMITTER; |
123 | u32 val_cr2 = 0; | |
633ff8f8 | 124 | |
43550821 XL |
125 | switch (clk_id) { |
126 | case FSL_SAI_CLK_BUS: | |
43550821 XL |
127 | val_cr2 |= FSL_SAI_CR2_MSEL_BUS; |
128 | break; | |
129 | case FSL_SAI_CLK_MAST1: | |
43550821 XL |
130 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; |
131 | break; | |
132 | case FSL_SAI_CLK_MAST2: | |
43550821 XL |
133 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; |
134 | break; | |
135 | case FSL_SAI_CLK_MAST3: | |
43550821 XL |
136 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; |
137 | break; | |
138 | default: | |
139 | return -EINVAL; | |
140 | } | |
633ff8f8 | 141 | |
2a266f8b NC |
142 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), |
143 | FSL_SAI_CR2_MSEL_MASK, val_cr2); | |
43550821 XL |
144 | |
145 | return 0; | |
146 | } | |
147 | ||
148 | static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
149 | int clk_id, unsigned int freq, int dir) | |
150 | { | |
4e3a99f5 | 151 | int ret; |
43550821 XL |
152 | |
153 | if (dir == SND_SOC_CLOCK_IN) | |
154 | return 0; | |
155 | ||
43550821 XL |
156 | ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, |
157 | FSL_FMT_TRANSMITTER); | |
158 | if (ret) { | |
190af12d | 159 | dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); |
78957fc3 | 160 | return ret; |
43550821 XL |
161 | } |
162 | ||
163 | ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, | |
164 | FSL_FMT_RECEIVER); | |
78957fc3 | 165 | if (ret) |
190af12d | 166 | dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); |
43550821 | 167 | |
1fb2d9d7 | 168 | return ret; |
43550821 XL |
169 | } |
170 | ||
171 | static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, | |
172 | unsigned int fmt, int fsl_dir) | |
173 | { | |
43550821 | 174 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b NC |
175 | bool tx = fsl_dir == FSL_FMT_TRANSMITTER; |
176 | u32 val_cr2 = 0, val_cr4 = 0; | |
43550821 | 177 | |
eadb0019 | 178 | if (!sai->is_lsb_first) |
72aa62be | 179 | val_cr4 |= FSL_SAI_CR4_MF; |
43550821 | 180 | |
13cde090 | 181 | /* DAI mode */ |
43550821 XL |
182 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
183 | case SND_SOC_DAIFMT_I2S: | |
a3f7dcc9 XL |
184 | /* |
185 | * Frame low, 1clk before data, one word length for frame sync, | |
186 | * frame sync starts one serial clock cycle earlier, | |
187 | * that is, together with the last bit of the previous | |
188 | * data word. | |
189 | */ | |
ef33bc32 | 190 | val_cr2 |= FSL_SAI_CR2_BCP; |
13cde090 XL |
191 | val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; |
192 | break; | |
193 | case SND_SOC_DAIFMT_LEFT_J: | |
a3f7dcc9 XL |
194 | /* |
195 | * Frame high, one word length for frame sync, | |
196 | * frame sync asserts with the first bit of the frame. | |
197 | */ | |
ef33bc32 | 198 | val_cr2 |= FSL_SAI_CR2_BCP; |
43550821 | 199 | break; |
a3f7dcc9 XL |
200 | case SND_SOC_DAIFMT_DSP_A: |
201 | /* | |
202 | * Frame high, 1clk before data, one bit for frame sync, | |
203 | * frame sync starts one serial clock cycle earlier, | |
204 | * that is, together with the last bit of the previous | |
205 | * data word. | |
206 | */ | |
ef33bc32 | 207 | val_cr2 |= FSL_SAI_CR2_BCP; |
a3f7dcc9 XL |
208 | val_cr4 |= FSL_SAI_CR4_FSE; |
209 | sai->is_dsp_mode = true; | |
210 | break; | |
211 | case SND_SOC_DAIFMT_DSP_B: | |
212 | /* | |
213 | * Frame high, one bit for frame sync, | |
214 | * frame sync asserts with the first bit of the frame. | |
215 | */ | |
ef33bc32 | 216 | val_cr2 |= FSL_SAI_CR2_BCP; |
a3f7dcc9 XL |
217 | sai->is_dsp_mode = true; |
218 | break; | |
13cde090 XL |
219 | case SND_SOC_DAIFMT_RIGHT_J: |
220 | /* To be done */ | |
43550821 XL |
221 | default: |
222 | return -EINVAL; | |
223 | } | |
224 | ||
13cde090 | 225 | /* DAI clock inversion */ |
43550821 XL |
226 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
227 | case SND_SOC_DAIFMT_IB_IF: | |
13cde090 XL |
228 | /* Invert both clocks */ |
229 | val_cr2 ^= FSL_SAI_CR2_BCP; | |
230 | val_cr4 ^= FSL_SAI_CR4_FSP; | |
43550821 XL |
231 | break; |
232 | case SND_SOC_DAIFMT_IB_NF: | |
13cde090 XL |
233 | /* Invert bit clock */ |
234 | val_cr2 ^= FSL_SAI_CR2_BCP; | |
43550821 XL |
235 | break; |
236 | case SND_SOC_DAIFMT_NB_IF: | |
13cde090 XL |
237 | /* Invert frame clock */ |
238 | val_cr4 ^= FSL_SAI_CR4_FSP; | |
43550821 XL |
239 | break; |
240 | case SND_SOC_DAIFMT_NB_NF: | |
13cde090 | 241 | /* Nothing to do for both normal cases */ |
43550821 XL |
242 | break; |
243 | default: | |
244 | return -EINVAL; | |
245 | } | |
246 | ||
13cde090 | 247 | /* DAI clock master masks */ |
43550821 XL |
248 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
249 | case SND_SOC_DAIFMT_CBS_CFS: | |
250 | val_cr2 |= FSL_SAI_CR2_BCD_MSTR; | |
251 | val_cr4 |= FSL_SAI_CR4_FSD_MSTR; | |
252 | break; | |
253 | case SND_SOC_DAIFMT_CBM_CFM: | |
c3ecef21 | 254 | sai->is_slave_mode = true; |
43550821 | 255 | break; |
13cde090 XL |
256 | case SND_SOC_DAIFMT_CBS_CFM: |
257 | val_cr2 |= FSL_SAI_CR2_BCD_MSTR; | |
13cde090 XL |
258 | break; |
259 | case SND_SOC_DAIFMT_CBM_CFS: | |
13cde090 | 260 | val_cr4 |= FSL_SAI_CR4_FSD_MSTR; |
c3ecef21 | 261 | sai->is_slave_mode = true; |
13cde090 | 262 | break; |
43550821 XL |
263 | default: |
264 | return -EINVAL; | |
265 | } | |
266 | ||
2a266f8b NC |
267 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), |
268 | FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); | |
269 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), | |
270 | FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | | |
271 | FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); | |
43550821 XL |
272 | |
273 | return 0; | |
274 | } | |
275 | ||
276 | static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
277 | { | |
4e3a99f5 | 278 | int ret; |
43550821 | 279 | |
43550821 XL |
280 | ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER); |
281 | if (ret) { | |
190af12d | 282 | dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); |
78957fc3 | 283 | return ret; |
43550821 XL |
284 | } |
285 | ||
286 | ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER); | |
78957fc3 | 287 | if (ret) |
190af12d | 288 | dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); |
43550821 | 289 | |
1fb2d9d7 | 290 | return ret; |
43550821 XL |
291 | } |
292 | ||
c3ecef21 ZW |
293 | static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) |
294 | { | |
295 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); | |
296 | unsigned long clk_rate; | |
297 | u32 savediv = 0, ratio, savesub = freq; | |
298 | u32 id; | |
299 | int ret = 0; | |
300 | ||
301 | /* Don't apply to slave mode */ | |
302 | if (sai->is_slave_mode) | |
303 | return 0; | |
304 | ||
305 | for (id = 0; id < FSL_SAI_MCLK_MAX; id++) { | |
306 | clk_rate = clk_get_rate(sai->mclk_clk[id]); | |
307 | if (!clk_rate) | |
308 | continue; | |
309 | ||
310 | ratio = clk_rate / freq; | |
311 | ||
312 | ret = clk_rate - ratio * freq; | |
313 | ||
314 | /* | |
315 | * Drop the source that can not be | |
316 | * divided into the required rate. | |
317 | */ | |
318 | if (ret != 0 && clk_rate / ret < 1000) | |
319 | continue; | |
320 | ||
321 | dev_dbg(dai->dev, | |
322 | "ratio %d for freq %dHz based on clock %ldHz\n", | |
323 | ratio, freq, clk_rate); | |
324 | ||
325 | if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512) | |
326 | ratio /= 2; | |
327 | else | |
328 | continue; | |
329 | ||
330 | if (ret < savesub) { | |
331 | savediv = ratio; | |
332 | sai->mclk_id[tx] = id; | |
333 | savesub = ret; | |
334 | } | |
335 | ||
336 | if (ret == 0) | |
337 | break; | |
338 | } | |
339 | ||
340 | if (savediv == 0) { | |
341 | dev_err(dai->dev, "failed to derive required %cx rate: %d\n", | |
342 | tx ? 'T' : 'R', freq); | |
343 | return -EINVAL; | |
344 | } | |
345 | ||
346 | if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) { | |
347 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, | |
348 | FSL_SAI_CR2_MSEL_MASK, | |
349 | FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); | |
350 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, | |
351 | FSL_SAI_CR2_DIV_MASK, savediv - 1); | |
352 | } else { | |
353 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, | |
354 | FSL_SAI_CR2_MSEL_MASK, | |
355 | FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); | |
356 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, | |
357 | FSL_SAI_CR2_DIV_MASK, savediv - 1); | |
358 | } | |
359 | ||
360 | dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", | |
361 | sai->mclk_id[tx], savediv, savesub); | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
43550821 XL |
366 | static int fsl_sai_hw_params(struct snd_pcm_substream *substream, |
367 | struct snd_pcm_hw_params *params, | |
368 | struct snd_soc_dai *cpu_dai) | |
369 | { | |
4e3a99f5 | 370 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b | 371 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
43550821 | 372 | unsigned int channels = params_channels(params); |
1d700309 | 373 | u32 word_width = snd_pcm_format_width(params_format(params)); |
2a266f8b | 374 | u32 val_cr4 = 0, val_cr5 = 0; |
c3ecef21 ZW |
375 | int ret; |
376 | ||
377 | if (!sai->is_slave_mode) { | |
378 | ret = fsl_sai_set_bclk(cpu_dai, tx, | |
379 | 2 * word_width * params_rate(params)); | |
380 | if (ret) | |
381 | return ret; | |
382 | ||
383 | /* Do not enable the clock if it is already enabled */ | |
384 | if (!(sai->mclk_streams & BIT(substream->stream))) { | |
385 | ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); | |
386 | if (ret) | |
387 | return ret; | |
388 | ||
389 | sai->mclk_streams |= BIT(substream->stream); | |
390 | } | |
391 | ||
392 | } | |
43550821 | 393 | |
a3f7dcc9 XL |
394 | if (!sai->is_dsp_mode) |
395 | val_cr4 |= FSL_SAI_CR4_SYWD(word_width); | |
396 | ||
43550821 XL |
397 | val_cr5 |= FSL_SAI_CR5_WNW(word_width); |
398 | val_cr5 |= FSL_SAI_CR5_W0W(word_width); | |
399 | ||
eadb0019 | 400 | if (sai->is_lsb_first) |
43550821 | 401 | val_cr5 |= FSL_SAI_CR5_FBT(0); |
72aa62be XL |
402 | else |
403 | val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); | |
43550821 XL |
404 | |
405 | val_cr4 |= FSL_SAI_CR4_FRSZ(channels); | |
43550821 | 406 | |
2a266f8b NC |
407 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), |
408 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
409 | val_cr4); | |
410 | regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx), | |
411 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
412 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
413 | regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1)); | |
43550821 XL |
414 | |
415 | return 0; | |
416 | } | |
417 | ||
c3ecef21 ZW |
418 | static int fsl_sai_hw_free(struct snd_pcm_substream *substream, |
419 | struct snd_soc_dai *cpu_dai) | |
420 | { | |
421 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
422 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
423 | ||
424 | if (!sai->is_slave_mode && | |
425 | sai->mclk_streams & BIT(substream->stream)) { | |
426 | clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); | |
427 | sai->mclk_streams &= ~BIT(substream->stream); | |
428 | } | |
429 | ||
430 | return 0; | |
431 | } | |
432 | ||
433 | ||
43550821 XL |
434 | static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, |
435 | struct snd_soc_dai *cpu_dai) | |
436 | { | |
437 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
e6b39846 | 438 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
c44b56af | 439 | u32 xcsr, count = 100; |
496a39d9 | 440 | |
a3f7dcc9 | 441 | /* |
08fdf65e NC |
442 | * Asynchronous mode: Clear SYNC for both Tx and Rx. |
443 | * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. | |
444 | * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. | |
a3f7dcc9 | 445 | */ |
855675f6 | 446 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, 0); |
78957fc3 | 447 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC, |
08fdf65e | 448 | sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); |
43550821 | 449 | |
a3f7dcc9 XL |
450 | /* |
451 | * It is recommended that the transmitter is the last enabled | |
452 | * and the first disabled. | |
453 | */ | |
43550821 XL |
454 | switch (cmd) { |
455 | case SNDRV_PCM_TRIGGER_START: | |
456 | case SNDRV_PCM_TRIGGER_RESUME: | |
457 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
a3fdc674 NC |
458 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
459 | FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); | |
460 | ||
f4075a8f NC |
461 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, |
462 | FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); | |
463 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, | |
464 | FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); | |
e5d0fa9c | 465 | |
8abba5d6 NC |
466 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
467 | FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); | |
43550821 | 468 | break; |
43550821 XL |
469 | case SNDRV_PCM_TRIGGER_STOP: |
470 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
471 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
e6b39846 NC |
472 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
473 | FSL_SAI_CSR_FRDE, 0); | |
8abba5d6 NC |
474 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
475 | FSL_SAI_CSR_xIE_MASK, 0); | |
e6b39846 | 476 | |
f84526cf | 477 | /* Check if the opposite FRDE is also disabled */ |
f4075a8f NC |
478 | regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr); |
479 | if (!(xcsr & FSL_SAI_CSR_FRDE)) { | |
eff952b7 | 480 | /* Disable both directions and reset their FIFOs */ |
e6b39846 | 481 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, |
c44b56af | 482 | FSL_SAI_CSR_TERE, 0); |
e6b39846 | 483 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, |
c44b56af NC |
484 | FSL_SAI_CSR_TERE, 0); |
485 | ||
486 | /* TERE will remain set till the end of current frame */ | |
487 | do { | |
488 | udelay(10); | |
489 | regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr); | |
490 | } while (--count && xcsr & FSL_SAI_CSR_TERE); | |
491 | ||
492 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, | |
493 | FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); | |
494 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, | |
495 | FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); | |
43550821 | 496 | } |
43550821 XL |
497 | break; |
498 | default: | |
499 | return -EINVAL; | |
500 | } | |
501 | ||
502 | return 0; | |
503 | } | |
504 | ||
505 | static int fsl_sai_startup(struct snd_pcm_substream *substream, | |
506 | struct snd_soc_dai *cpu_dai) | |
507 | { | |
43550821 | 508 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b | 509 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
ca3e35c7 | 510 | struct device *dev = &sai->pdev->dev; |
ca3e35c7 NC |
511 | int ret; |
512 | ||
513 | ret = clk_prepare_enable(sai->bus_clk); | |
514 | if (ret) { | |
515 | dev_err(dev, "failed to enable bus clock: %d\n", ret); | |
516 | return ret; | |
517 | } | |
43550821 | 518 | |
2a266f8b | 519 | regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, |
78957fc3 XL |
520 | FSL_SAI_CR3_TRCE); |
521 | ||
522 | return 0; | |
43550821 XL |
523 | } |
524 | ||
525 | static void fsl_sai_shutdown(struct snd_pcm_substream *substream, | |
526 | struct snd_soc_dai *cpu_dai) | |
527 | { | |
528 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
2a266f8b | 529 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
43550821 | 530 | |
2a266f8b | 531 | regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0); |
ca3e35c7 NC |
532 | |
533 | clk_disable_unprepare(sai->bus_clk); | |
43550821 XL |
534 | } |
535 | ||
536 | static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { | |
537 | .set_sysclk = fsl_sai_set_dai_sysclk, | |
538 | .set_fmt = fsl_sai_set_dai_fmt, | |
539 | .hw_params = fsl_sai_hw_params, | |
c3ecef21 | 540 | .hw_free = fsl_sai_hw_free, |
43550821 XL |
541 | .trigger = fsl_sai_trigger, |
542 | .startup = fsl_sai_startup, | |
543 | .shutdown = fsl_sai_shutdown, | |
544 | }; | |
545 | ||
546 | static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) | |
547 | { | |
548 | struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); | |
e6dc12d7 | 549 | |
376d1a92 NC |
550 | /* Software Reset for both Tx and Rx */ |
551 | regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); | |
552 | regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); | |
553 | /* Clear SR bit to finish the reset */ | |
554 | regmap_write(sai->regmap, FSL_SAI_TCSR, 0); | |
555 | regmap_write(sai->regmap, FSL_SAI_RCSR, 0); | |
556 | ||
78957fc3 XL |
557 | regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK, |
558 | FSL_SAI_MAXBURST_TX * 2); | |
559 | regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK, | |
560 | FSL_SAI_MAXBURST_RX - 1); | |
43550821 | 561 | |
dd9f4060 XL |
562 | snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, |
563 | &sai->dma_params_rx); | |
43550821 XL |
564 | |
565 | snd_soc_dai_set_drvdata(cpu_dai, sai); | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
43550821 XL |
570 | static struct snd_soc_dai_driver fsl_sai_dai = { |
571 | .probe = fsl_sai_dai_probe, | |
43550821 | 572 | .playback = { |
20d5b76f | 573 | .stream_name = "CPU-Playback", |
43550821 XL |
574 | .channels_min = 1, |
575 | .channels_max = 2, | |
576 | .rates = SNDRV_PCM_RATE_8000_96000, | |
577 | .formats = FSL_SAI_FORMATS, | |
578 | }, | |
579 | .capture = { | |
20d5b76f | 580 | .stream_name = "CPU-Capture", |
43550821 XL |
581 | .channels_min = 1, |
582 | .channels_max = 2, | |
583 | .rates = SNDRV_PCM_RATE_8000_96000, | |
584 | .formats = FSL_SAI_FORMATS, | |
585 | }, | |
586 | .ops = &fsl_sai_pcm_dai_ops, | |
587 | }; | |
588 | ||
589 | static const struct snd_soc_component_driver fsl_component = { | |
590 | .name = "fsl-sai", | |
591 | }; | |
592 | ||
78957fc3 XL |
593 | static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) |
594 | { | |
595 | switch (reg) { | |
596 | case FSL_SAI_TCSR: | |
597 | case FSL_SAI_TCR1: | |
598 | case FSL_SAI_TCR2: | |
599 | case FSL_SAI_TCR3: | |
600 | case FSL_SAI_TCR4: | |
601 | case FSL_SAI_TCR5: | |
602 | case FSL_SAI_TFR: | |
603 | case FSL_SAI_TMR: | |
604 | case FSL_SAI_RCSR: | |
605 | case FSL_SAI_RCR1: | |
606 | case FSL_SAI_RCR2: | |
607 | case FSL_SAI_RCR3: | |
608 | case FSL_SAI_RCR4: | |
609 | case FSL_SAI_RCR5: | |
610 | case FSL_SAI_RDR: | |
611 | case FSL_SAI_RFR: | |
612 | case FSL_SAI_RMR: | |
613 | return true; | |
614 | default: | |
615 | return false; | |
616 | } | |
617 | } | |
618 | ||
619 | static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) | |
620 | { | |
621 | switch (reg) { | |
622 | case FSL_SAI_TFR: | |
623 | case FSL_SAI_RFR: | |
624 | case FSL_SAI_TDR: | |
625 | case FSL_SAI_RDR: | |
626 | return true; | |
627 | default: | |
628 | return false; | |
629 | } | |
630 | ||
631 | } | |
632 | ||
633 | static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) | |
634 | { | |
635 | switch (reg) { | |
636 | case FSL_SAI_TCSR: | |
637 | case FSL_SAI_TCR1: | |
638 | case FSL_SAI_TCR2: | |
639 | case FSL_SAI_TCR3: | |
640 | case FSL_SAI_TCR4: | |
641 | case FSL_SAI_TCR5: | |
642 | case FSL_SAI_TDR: | |
643 | case FSL_SAI_TMR: | |
644 | case FSL_SAI_RCSR: | |
645 | case FSL_SAI_RCR1: | |
646 | case FSL_SAI_RCR2: | |
647 | case FSL_SAI_RCR3: | |
648 | case FSL_SAI_RCR4: | |
649 | case FSL_SAI_RCR5: | |
650 | case FSL_SAI_RMR: | |
651 | return true; | |
652 | default: | |
653 | return false; | |
654 | } | |
655 | } | |
656 | ||
014fd22e | 657 | static const struct regmap_config fsl_sai_regmap_config = { |
78957fc3 XL |
658 | .reg_bits = 32, |
659 | .reg_stride = 4, | |
660 | .val_bits = 32, | |
661 | ||
662 | .max_register = FSL_SAI_RMR, | |
663 | .readable_reg = fsl_sai_readable_reg, | |
664 | .volatile_reg = fsl_sai_volatile_reg, | |
665 | .writeable_reg = fsl_sai_writeable_reg, | |
666 | }; | |
667 | ||
43550821 XL |
668 | static int fsl_sai_probe(struct platform_device *pdev) |
669 | { | |
4e3a99f5 | 670 | struct device_node *np = pdev->dev.of_node; |
43550821 XL |
671 | struct fsl_sai *sai; |
672 | struct resource *res; | |
78957fc3 | 673 | void __iomem *base; |
ca3e35c7 NC |
674 | char tmp[8]; |
675 | int irq, ret, i; | |
43550821 XL |
676 | |
677 | sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); | |
678 | if (!sai) | |
679 | return -ENOMEM; | |
680 | ||
e2681a1b NC |
681 | sai->pdev = pdev; |
682 | ||
c7540644 NC |
683 | if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai")) |
684 | sai->sai_on_imx = true; | |
685 | ||
eadb0019 | 686 | sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); |
78957fc3 | 687 | |
43550821 | 688 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
78957fc3 XL |
689 | base = devm_ioremap_resource(&pdev->dev, res); |
690 | if (IS_ERR(base)) | |
691 | return PTR_ERR(base); | |
692 | ||
693 | sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, | |
ca3e35c7 NC |
694 | "bus", base, &fsl_sai_regmap_config); |
695 | ||
696 | /* Compatible with old DTB cases */ | |
697 | if (IS_ERR(sai->regmap)) | |
698 | sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, | |
699 | "sai", base, &fsl_sai_regmap_config); | |
78957fc3 XL |
700 | if (IS_ERR(sai->regmap)) { |
701 | dev_err(&pdev->dev, "regmap init failed\n"); | |
702 | return PTR_ERR(sai->regmap); | |
43550821 XL |
703 | } |
704 | ||
ca3e35c7 NC |
705 | /* No error out for old DTB cases but only mark the clock NULL */ |
706 | sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); | |
707 | if (IS_ERR(sai->bus_clk)) { | |
708 | dev_err(&pdev->dev, "failed to get bus clock: %ld\n", | |
709 | PTR_ERR(sai->bus_clk)); | |
710 | sai->bus_clk = NULL; | |
711 | } | |
712 | ||
c3ecef21 ZW |
713 | sai->mclk_clk[0] = sai->bus_clk; |
714 | for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { | |
715 | sprintf(tmp, "mclk%d", i); | |
ca3e35c7 NC |
716 | sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); |
717 | if (IS_ERR(sai->mclk_clk[i])) { | |
718 | dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n", | |
719 | i + 1, PTR_ERR(sai->mclk_clk[i])); | |
720 | sai->mclk_clk[i] = NULL; | |
721 | } | |
722 | } | |
723 | ||
e2681a1b NC |
724 | irq = platform_get_irq(pdev, 0); |
725 | if (irq < 0) { | |
0954237f | 726 | dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); |
e2681a1b NC |
727 | return irq; |
728 | } | |
729 | ||
730 | ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai); | |
731 | if (ret) { | |
732 | dev_err(&pdev->dev, "failed to claim irq %u\n", irq); | |
733 | return ret; | |
734 | } | |
735 | ||
08fdf65e NC |
736 | /* Sync Tx with Rx as default by following old DT binding */ |
737 | sai->synchronous[RX] = true; | |
738 | sai->synchronous[TX] = false; | |
739 | fsl_sai_dai.symmetric_rates = 1; | |
740 | fsl_sai_dai.symmetric_channels = 1; | |
741 | fsl_sai_dai.symmetric_samplebits = 1; | |
742 | ||
ce7344a4 NC |
743 | if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && |
744 | of_find_property(np, "fsl,sai-asynchronous", NULL)) { | |
745 | /* error out if both synchronous and asynchronous are present */ | |
746 | dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); | |
747 | return -EINVAL; | |
748 | } | |
749 | ||
08fdf65e NC |
750 | if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { |
751 | /* Sync Rx with Tx */ | |
752 | sai->synchronous[RX] = false; | |
753 | sai->synchronous[TX] = true; | |
754 | } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { | |
755 | /* Discard all settings for asynchronous mode */ | |
756 | sai->synchronous[RX] = false; | |
757 | sai->synchronous[TX] = false; | |
758 | fsl_sai_dai.symmetric_rates = 0; | |
759 | fsl_sai_dai.symmetric_channels = 0; | |
760 | fsl_sai_dai.symmetric_samplebits = 0; | |
761 | } | |
762 | ||
43550821 XL |
763 | sai->dma_params_rx.addr = res->start + FSL_SAI_RDR; |
764 | sai->dma_params_tx.addr = res->start + FSL_SAI_TDR; | |
765 | sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; | |
766 | sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; | |
767 | ||
43550821 XL |
768 | platform_set_drvdata(pdev, sai); |
769 | ||
770 | ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, | |
771 | &fsl_sai_dai, 1); | |
772 | if (ret) | |
773 | return ret; | |
774 | ||
c7540644 NC |
775 | if (sai->sai_on_imx) |
776 | return imx_pcm_dma_init(pdev); | |
777 | else | |
778 | return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, | |
779 | SND_DMAENGINE_PCM_FLAG_NO_RESIDUE); | |
43550821 XL |
780 | } |
781 | ||
782 | static const struct of_device_id fsl_sai_ids[] = { | |
783 | { .compatible = "fsl,vf610-sai", }, | |
c7540644 | 784 | { .compatible = "fsl,imx6sx-sai", }, |
43550821 XL |
785 | { /* sentinel */ } |
786 | }; | |
787 | ||
788 | static struct platform_driver fsl_sai_driver = { | |
789 | .probe = fsl_sai_probe, | |
43550821 XL |
790 | .driver = { |
791 | .name = "fsl-sai", | |
43550821 XL |
792 | .of_match_table = fsl_sai_ids, |
793 | }, | |
794 | }; | |
795 | module_platform_driver(fsl_sai_driver); | |
796 | ||
797 | MODULE_DESCRIPTION("Freescale Soc SAI Interface"); | |
798 | MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); | |
799 | MODULE_ALIAS("platform:fsl-sai"); | |
800 | MODULE_LICENSE("GPL"); |