[linux-2.6-block.git] / sound / soc / fsl / fsl_sai.c

/*
 * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
 *
 * Copyright 2012-2013 Freescale Semiconductor, Inc.
 *
 * This program is free software, you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation, either version 2 of the License, or(at your
 * option) any later version.
 *
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm_params.h>

#include "fsl_sai.h"
#include "imx-pcm.h"

#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
		       FSL_SAI_CSR_FEIE)

static irqreturn_t fsl_sai_isr(int irq, void *devid)
{
	struct fsl_sai *sai = (struct fsl_sai *)devid;
	struct device *dev = &sai->pdev->dev;
	u32 flags, xcsr, mask;
	bool irq_none = true;

	/*
	 * Both IRQ status bits and IRQ mask bits are in the xCSR but
	 * different shifts. And we here create a mask only for those
	 * IRQs that we activated.
	 */
	mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;

	/* Tx IRQ */
	regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
	flags = xcsr & mask;

	if (flags)
		irq_none = false;
	else
		goto irq_rx;

	if (flags & FSL_SAI_CSR_WSF)
		dev_dbg(dev, "isr: Start of Tx word detected\n");

	if (flags & FSL_SAI_CSR_SEF)
		dev_warn(dev, "isr: Tx Frame sync error detected\n");

	if (flags & FSL_SAI_CSR_FEF) {
		dev_warn(dev, "isr: Transmit underrun detected\n");
		/* FIFO reset for safety */
		xcsr |= FSL_SAI_CSR_FR;
	}

	if (flags & FSL_SAI_CSR_FWF)
		dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");

	if (flags & FSL_SAI_CSR_FRF)
		dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");

	flags &= FSL_SAI_CSR_xF_W_MASK;
	xcsr &= ~FSL_SAI_CSR_xF_MASK;

	if (flags)
		regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);

irq_rx:
	/* Rx IRQ */
	regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
	flags = xcsr & mask;

	if (flags)
		irq_none = false;
	else
		goto out;

	if (flags & FSL_SAI_CSR_WSF)
		dev_dbg(dev, "isr: Start of Rx word detected\n");

	if (flags & FSL_SAI_CSR_SEF)
		dev_warn(dev, "isr: Rx Frame sync error detected\n");

	if (flags & FSL_SAI_CSR_FEF) {
		dev_warn(dev, "isr: Receive overflow detected\n");
		/* FIFO reset for safety */
		xcsr |= FSL_SAI_CSR_FR;
	}

	if (flags & FSL_SAI_CSR_FWF)
		dev_dbg(dev, "isr: Enabled receive FIFO is full\n");

	if (flags & FSL_SAI_CSR_FRF)
		dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");

	flags &= FSL_SAI_CSR_xF_W_MASK;
	xcsr &= ~FSL_SAI_CSR_xF_MASK;

	if (flags)
		regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);

out:
	if (irq_none)
		return IRQ_NONE;
	else
		return IRQ_HANDLED;
}

static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
		int clk_id, unsigned int freq, int fsl_dir)
{
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
	bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
	u32 val_cr2 = 0;

	switch (clk_id) {
	case FSL_SAI_CLK_BUS:
		val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
		break;
	case FSL_SAI_CLK_MAST1:
		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
		break;
	case FSL_SAI_CLK_MAST2:
		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
		break;
	case FSL_SAI_CLK_MAST3:
		val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
			   FSL_SAI_CR2_MSEL_MASK, val_cr2);

	return 0;
}

static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
		int clk_id, unsigned int freq, int dir)
{
	int ret;

	if (dir == SND_SOC_CLOCK_IN)
		return 0;

	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
					FSL_FMT_TRANSMITTER);
	if (ret) {
		dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
		return ret;
	}

	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
					FSL_FMT_RECEIVER);
	if (ret)
		dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);

	return ret;
}

static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
				unsigned int fmt, int fsl_dir)
{
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
	bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
	u32 val_cr2 = 0, val_cr4 = 0;

	if (!sai->big_endian_data)
		val_cr4 |= FSL_SAI_CR4_MF;

	/* DAI mode */
	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		/*
		 * Frame low, 1clk before data, one word length for frame sync,
		 * frame sync starts one serial clock cycle earlier,
		 * that is, together with the last bit of the previous
		 * data word.
		 */
		val_cr2 |= FSL_SAI_CR2_BCP;
		val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		/*
		 * Frame high, one word length for frame sync,
		 * frame sync asserts with the first bit of the frame.
		 */
		val_cr2 |= FSL_SAI_CR2_BCP;
		break;
	case SND_SOC_DAIFMT_DSP_A:
		/*
		 * Frame high, 1clk before data, one bit for frame sync,
		 * frame sync starts one serial clock cycle earlier,
		 * that is, together with the last bit of the previous
		 * data word.
		 */
		val_cr2 |= FSL_SAI_CR2_BCP;
		val_cr4 |= FSL_SAI_CR4_FSE;
		sai->is_dsp_mode = true;
		break;
	case SND_SOC_DAIFMT_DSP_B:
		/*
		 * Frame high, one bit for frame sync,
		 * frame sync asserts with the first bit of the frame.
		 */
		val_cr2 |= FSL_SAI_CR2_BCP;
		sai->is_dsp_mode = true;
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		/* To be done */
	default:
		return -EINVAL;
	}

	/* DAI clock inversion */
	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
	case SND_SOC_DAIFMT_IB_IF:
		/* Invert both clocks */
		val_cr2 ^= FSL_SAI_CR2_BCP;
		val_cr4 ^= FSL_SAI_CR4_FSP;
		break;
	case SND_SOC_DAIFMT_IB_NF:
		/* Invert bit clock */
		val_cr2 ^= FSL_SAI_CR2_BCP;
		break;
	case SND_SOC_DAIFMT_NB_IF:
		/* Invert frame clock */
		val_cr4 ^= FSL_SAI_CR4_FSP;
		break;
	case SND_SOC_DAIFMT_NB_NF:
		/* Nothing to do for both normal cases */
		break;
	default:
		return -EINVAL;
	}

	/* DAI clock master masks */
	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	case SND_SOC_DAIFMT_CBS_CFS:
		val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
		val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
		break;
	case SND_SOC_DAIFMT_CBM_CFM:
		break;
	case SND_SOC_DAIFMT_CBS_CFM:
		val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
		break;
	case SND_SOC_DAIFMT_CBM_CFS:
		val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
		break;
	default:
		return -EINVAL;
	}

	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
			   FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
			   FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
			   FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);

	return 0;
}

static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
{
	int ret;

	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
	if (ret) {
		dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
		return ret;
	}

	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
	if (ret)
		dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);

	return ret;
}

static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
		struct snd_pcm_hw_params *params,
		struct snd_soc_dai *cpu_dai)
{
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	unsigned int channels = params_channels(params);
	u32 word_width = snd_pcm_format_width(params_format(params));
	u32 val_cr4 = 0, val_cr5 = 0;

	if (!sai->is_dsp_mode)
		val_cr4 |= FSL_SAI_CR4_SYWD(word_width);

	val_cr5 |= FSL_SAI_CR5_WNW(word_width);
	val_cr5 |= FSL_SAI_CR5_W0W(word_width);

	if (sai->big_endian_data)
		val_cr5 |= FSL_SAI_CR5_FBT(0);
	else
		val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);

	val_cr4 |= FSL_SAI_CR4_FRSZ(channels);

	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
			   FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
			   val_cr4);
	regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
			   FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
			   FSL_SAI_CR5_FBT_MASK, val_cr5);
	regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));

	return 0;
}

static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
		struct snd_soc_dai *cpu_dai)
{
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	u32 tcsr, rcsr;

	/*
	 * The transmitter bit clock and frame sync are to be
	 * used by both the transmitter and receiver.
	 */
	regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
			   ~FSL_SAI_CR2_SYNC);
	regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
			   FSL_SAI_CR2_SYNC);

	regmap_read(sai->regmap, FSL_SAI_TCSR, &tcsr);
	regmap_read(sai->regmap, FSL_SAI_RCSR, &rcsr);

	/*
	 * It is recommended that the transmitter is the last enabled
	 * and the first disabled.
	 */
	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (!(tcsr & FSL_SAI_CSR_FRDE || rcsr & FSL_SAI_CSR_FRDE)) {
			regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
					   FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
			regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
					   FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
		}

		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
				   FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
				   FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
		break;
	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
				   FSL_SAI_CSR_FRDE, 0);
		regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
				   FSL_SAI_CSR_xIE_MASK, 0);

		/* Check if the opposite FRDE is also disabled */
		if (!(tx ? rcsr & FSL_SAI_CSR_FRDE : tcsr & FSL_SAI_CSR_FRDE)) {
			regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
					   FSL_SAI_CSR_TERE, 0);
			regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
					   FSL_SAI_CSR_TERE, 0);
		}
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int fsl_sai_startup(struct snd_pcm_substream *substream,
		struct snd_soc_dai *cpu_dai)
{
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
	struct device *dev = &sai->pdev->dev;
	int ret;

	ret = clk_prepare_enable(sai->bus_clk);
	if (ret) {
		dev_err(dev, "failed to enable bus clock: %d\n", ret);
		return ret;
	}

	regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
			   FSL_SAI_CR3_TRCE);

	return 0;
}

static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
		struct snd_soc_dai *cpu_dai)
{
	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;

	regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);

	clk_disable_unprepare(sai->bus_clk);
}

static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
	.set_sysclk	= fsl_sai_set_dai_sysclk,
	.set_fmt	= fsl_sai_set_dai_fmt,
	.hw_params	= fsl_sai_hw_params,
	.trigger	= fsl_sai_trigger,
	.startup	= fsl_sai_startup,
	.shutdown	= fsl_sai_shutdown,
};

static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
{
	struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);

	regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 0xffffffff, 0x0);
	regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 0xffffffff, 0x0);
	regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
			   FSL_SAI_MAXBURST_TX * 2);
	regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
			   FSL_SAI_MAXBURST_RX - 1);

	snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
				&sai->dma_params_rx);

	snd_soc_dai_set_drvdata(cpu_dai, sai);

	return 0;
}

static struct snd_soc_dai_driver fsl_sai_dai = {
	.probe = fsl_sai_dai_probe,
	.playback = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = FSL_SAI_FORMATS,
	},
	.capture = {
		.channels_min = 1,
		.channels_max = 2,
		.rates = SNDRV_PCM_RATE_8000_96000,
		.formats = FSL_SAI_FORMATS,
	},
	.ops = &fsl_sai_pcm_dai_ops,
};

static const struct snd_soc_component_driver fsl_component = {
	.name           = "fsl-sai",
};

static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case FSL_SAI_TCSR:
	case FSL_SAI_TCR1:
	case FSL_SAI_TCR2:
	case FSL_SAI_TCR3:
	case FSL_SAI_TCR4:
	case FSL_SAI_TCR5:
	case FSL_SAI_TFR:
	case FSL_SAI_TMR:
	case FSL_SAI_RCSR:
	case FSL_SAI_RCR1:
	case FSL_SAI_RCR2:
	case FSL_SAI_RCR3:
	case FSL_SAI_RCR4:
	case FSL_SAI_RCR5:
	case FSL_SAI_RDR:
	case FSL_SAI_RFR:
	case FSL_SAI_RMR:
		return true;
	default:
		return false;
	}
}

static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case FSL_SAI_TFR:
	case FSL_SAI_RFR:
	case FSL_SAI_TDR:
	case FSL_SAI_RDR:
		return true;
	default:
		return false;
	}

}

static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
{
	switch (reg) {
	case FSL_SAI_TCSR:
	case FSL_SAI_TCR1:
	case FSL_SAI_TCR2:
	case FSL_SAI_TCR3:
	case FSL_SAI_TCR4:
	case FSL_SAI_TCR5:
	case FSL_SAI_TDR:
	case FSL_SAI_TMR:
	case FSL_SAI_RCSR:
	case FSL_SAI_RCR1:
	case FSL_SAI_RCR2:
	case FSL_SAI_RCR3:
	case FSL_SAI_RCR4:
	case FSL_SAI_RCR5:
	case FSL_SAI_RMR:
		return true;
	default:
		return false;
	}
}

static struct regmap_config fsl_sai_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,

	.max_register = FSL_SAI_RMR,
	.readable_reg = fsl_sai_readable_reg,
	.volatile_reg = fsl_sai_volatile_reg,
	.writeable_reg = fsl_sai_writeable_reg,
};

static int fsl_sai_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct fsl_sai *sai;
	struct resource *res;
	void __iomem *base;
	char tmp[8];
	int irq, ret, i;

	sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
	if (!sai)
		return -ENOMEM;

	sai->pdev = pdev;

	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
		sai->sai_on_imx = true;

	sai->big_endian_regs = of_property_read_bool(np, "big-endian-regs");
	if (sai->big_endian_regs)
		fsl_sai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;

	sai->big_endian_data = of_property_read_bool(np, "big-endian-data");

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
			"bus", base, &fsl_sai_regmap_config);

	/* Compatible with old DTB cases */
	if (IS_ERR(sai->regmap))
		sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
				"sai", base, &fsl_sai_regmap_config);
	if (IS_ERR(sai->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(sai->regmap);
	}

	/* No error out for old DTB cases but only mark the clock NULL */
	sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
	if (IS_ERR(sai->bus_clk)) {
		dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
				PTR_ERR(sai->bus_clk));
		sai->bus_clk = NULL;
	}

	for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
		sprintf(tmp, "mclk%d", i + 1);
		sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
		if (IS_ERR(sai->mclk_clk[i])) {
			dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
					i + 1, PTR_ERR(sai->mclk_clk[i]));
			sai->mclk_clk[i] = NULL;
		}
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
		return irq;
	}

	ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
	if (ret) {
		dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
		return ret;
	}

	sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
	sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
	sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
	sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;

	platform_set_drvdata(pdev, sai);

	ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
			&fsl_sai_dai, 1);
	if (ret)
		return ret;

	if (sai->sai_on_imx)
		return imx_pcm_dma_init(pdev);
	else
		return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
				SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
}

static const struct of_device_id fsl_sai_ids[] = {
	{ .compatible = "fsl,vf610-sai", },
	{ .compatible = "fsl,imx6sx-sai", },
	{ /* sentinel */ }
};

static struct platform_driver fsl_sai_driver = {
	.probe = fsl_sai_probe,
	.driver = {
		.name = "fsl-sai",
		.owner = THIS_MODULE,
		.of_match_table = fsl_sai_ids,
	},
};
module_platform_driver(fsl_sai_driver);

MODULE_DESCRIPTION("Freescale Soc SAI Interface");
MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
MODULE_ALIAS("platform:fsl-sai");
MODULE_LICENSE("GPL");
Commit	Line	Data
43550821 XL	1	/*
	2	* Freescale ALSA SoC Digital Audio Interface (SAI) driver.
	3	*
	4	* Copyright 2012-2013 Freescale Semiconductor, Inc.
	5	*
	6	* This program is free software, you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation, either version 2 of the License, or(at your
	9	* option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/delay.h>
	15	#include <linux/dmaengine.h>
	16	#include <linux/module.h>
	17	#include <linux/of_address.h>
78957fc3	18	#include <linux/regmap.h>
43550821 XL	19	#include <linux/slab.h>
	20	#include <sound/core.h>
	21	#include <sound/dmaengine_pcm.h>
	22	#include <sound/pcm_params.h>
	23
	24	#include "fsl_sai.h"
c7540644	25	#include "imx-pcm.h"
43550821	26
e2681a1b NC	27	#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE \|\
	28	FSL_SAI_CSR_FEIE)
	29
	30	static irqreturn_t fsl_sai_isr(int irq, void *devid)
	31	{
	32	struct fsl_sai sai = (struct fsl_sai )devid;
	33	struct device *dev = &sai->pdev->dev;
413312aa NC	34	u32 flags, xcsr, mask;
	35	bool irq_none = true;
	36
	37	/*
	38	* Both IRQ status bits and IRQ mask bits are in the xCSR but
	39	* different shifts. And we here create a mask only for those
	40	* IRQs that we activated.
	41	*/
e2681a1b NC	42	mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
	43
	44	/* Tx IRQ */
	45	regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
413312aa NC	46	flags = xcsr & mask;
	47
	48	if (flags)
	49	irq_none = false;
	50	else
	51	goto irq_rx;
e2681a1b	52
413312aa	53	if (flags & FSL_SAI_CSR_WSF)
e2681a1b NC	54	dev_dbg(dev, "isr: Start of Tx word detected\n");
e2681a1b NC	55
413312aa	56	if (flags & FSL_SAI_CSR_SEF)
e2681a1b NC	57	dev_warn(dev, "isr: Tx Frame sync error detected\n");
e2681a1b NC	58
413312aa	59	if (flags & FSL_SAI_CSR_FEF) {
e2681a1b NC	60	dev_warn(dev, "isr: Transmit underrun detected\n");
	61	/* FIFO reset for safety */
	62	xcsr \|= FSL_SAI_CSR_FR;
	63	}
	64
413312aa	65	if (flags & FSL_SAI_CSR_FWF)
e2681a1b NC	66	dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
e2681a1b NC	67
413312aa	68	if (flags & FSL_SAI_CSR_FRF)
e2681a1b NC	69	dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
e2681a1b NC	70
413312aa NC	71	flags &= FSL_SAI_CSR_xF_W_MASK;
	72	xcsr &= ~FSL_SAI_CSR_xF_MASK;
	73
	74	if (flags)
	75	regmap_write(sai->regmap, FSL_SAI_TCSR, flags \| xcsr);
e2681a1b	76
413312aa	77	irq_rx:
e2681a1b NC	78	/* Rx IRQ */
e2681a1b NC	79	regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
413312aa	80	flags = xcsr & mask;
e2681a1b	81
413312aa NC	82	if (flags)
	83	irq_none = false;
	84	else
	85	goto out;
	86
	87	if (flags & FSL_SAI_CSR_WSF)
e2681a1b NC	88	dev_dbg(dev, "isr: Start of Rx word detected\n");
e2681a1b NC	89
413312aa	90	if (flags & FSL_SAI_CSR_SEF)
e2681a1b NC	91	dev_warn(dev, "isr: Rx Frame sync error detected\n");
e2681a1b NC	92
413312aa	93	if (flags & FSL_SAI_CSR_FEF) {
e2681a1b NC	94	dev_warn(dev, "isr: Receive overflow detected\n");
	95	/* FIFO reset for safety */
	96	xcsr \|= FSL_SAI_CSR_FR;
	97	}
	98
413312aa	99	if (flags & FSL_SAI_CSR_FWF)
e2681a1b NC	100	dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
e2681a1b NC	101
413312aa	102	if (flags & FSL_SAI_CSR_FRF)
e2681a1b NC	103	dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
e2681a1b NC	104
413312aa NC	105	flags &= FSL_SAI_CSR_xF_W_MASK;
413312aa NC	106	xcsr &= ~FSL_SAI_CSR_xF_MASK;
e2681a1b	107
413312aa NC	108	if (flags)
	109	regmap_write(sai->regmap, FSL_SAI_TCSR, flags \| xcsr);
	110
	111	out:
	112	if (irq_none)
	113	return IRQ_NONE;
	114	else
	115	return IRQ_HANDLED;
e2681a1b NC	116	}
e2681a1b NC	117
43550821 XL	118	static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
	119	int clk_id, unsigned int freq, int fsl_dir)
	120	{
43550821	121	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
2a266f8b NC	122	bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
2a266f8b NC	123	u32 val_cr2 = 0;
633ff8f8	124
43550821 XL	125	switch (clk_id) {
43550821 XL	126	case FSL_SAI_CLK_BUS:
43550821 XL	127	val_cr2 \|= FSL_SAI_CR2_MSEL_BUS;
	128	break;
	129	case FSL_SAI_CLK_MAST1:
43550821 XL	130	val_cr2 \|= FSL_SAI_CR2_MSEL_MCLK1;
	131	break;
	132	case FSL_SAI_CLK_MAST2:
43550821 XL	133	val_cr2 \|= FSL_SAI_CR2_MSEL_MCLK2;
	134	break;
	135	case FSL_SAI_CLK_MAST3:
43550821 XL	136	val_cr2 \|= FSL_SAI_CR2_MSEL_MCLK3;
	137	break;
	138	default:
	139	return -EINVAL;
	140	}
633ff8f8	141
2a266f8b NC	142	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
2a266f8b NC	143	FSL_SAI_CR2_MSEL_MASK, val_cr2);
43550821 XL	144
	145	return 0;
	146	}
	147
	148	static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
	149	int clk_id, unsigned int freq, int dir)
	150	{
4e3a99f5	151	int ret;
43550821 XL	152
	153	if (dir == SND_SOC_CLOCK_IN)
	154	return 0;
	155
43550821 XL	156	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
	157	FSL_FMT_TRANSMITTER);
	158	if (ret) {
190af12d	159	dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
78957fc3	160	return ret;
43550821 XL	161	}
	162
	163	ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
	164	FSL_FMT_RECEIVER);
78957fc3	165	if (ret)
190af12d	166	dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
43550821	167
1fb2d9d7	168	return ret;
43550821 XL	169	}
	170
	171	static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
	172	unsigned int fmt, int fsl_dir)
	173	{
43550821	174	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
2a266f8b NC	175	bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
2a266f8b NC	176	u32 val_cr2 = 0, val_cr4 = 0;
43550821	177
2a266f8b	178	if (!sai->big_endian_data)
72aa62be	179	val_cr4 \|= FSL_SAI_CR4_MF;
43550821	180
13cde090	181	/* DAI mode */
43550821 XL	182	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
43550821 XL	183	case SND_SOC_DAIFMT_I2S:
a3f7dcc9 XL	184	/*
	185	* Frame low, 1clk before data, one word length for frame sync,
	186	* frame sync starts one serial clock cycle earlier,
	187	* that is, together with the last bit of the previous
	188	* data word.
	189	*/
ef33bc32	190	val_cr2 \|= FSL_SAI_CR2_BCP;
13cde090 XL	191	val_cr4 \|= FSL_SAI_CR4_FSE \| FSL_SAI_CR4_FSP;
	192	break;
	193	case SND_SOC_DAIFMT_LEFT_J:
a3f7dcc9 XL	194	/*
	195	* Frame high, one word length for frame sync,
	196	* frame sync asserts with the first bit of the frame.
	197	*/
ef33bc32	198	val_cr2 \|= FSL_SAI_CR2_BCP;
43550821	199	break;
a3f7dcc9 XL	200	case SND_SOC_DAIFMT_DSP_A:
	201	/*
	202	* Frame high, 1clk before data, one bit for frame sync,
	203	* frame sync starts one serial clock cycle earlier,
	204	* that is, together with the last bit of the previous
	205	* data word.
	206	*/
ef33bc32	207	val_cr2 \|= FSL_SAI_CR2_BCP;
a3f7dcc9 XL	208	val_cr4 \|= FSL_SAI_CR4_FSE;
	209	sai->is_dsp_mode = true;
	210	break;
	211	case SND_SOC_DAIFMT_DSP_B:
	212	/*
	213	* Frame high, one bit for frame sync,
	214	* frame sync asserts with the first bit of the frame.
	215	*/
ef33bc32	216	val_cr2 \|= FSL_SAI_CR2_BCP;
a3f7dcc9 XL	217	sai->is_dsp_mode = true;
a3f7dcc9 XL	218	break;
13cde090 XL	219	case SND_SOC_DAIFMT_RIGHT_J:
13cde090 XL	220	/* To be done */
43550821 XL	221	default:
	222	return -EINVAL;
	223	}
	224
13cde090	225	/* DAI clock inversion */
43550821 XL	226	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
43550821 XL	227	case SND_SOC_DAIFMT_IB_IF:
13cde090 XL	228	/* Invert both clocks */
	229	val_cr2 ^= FSL_SAI_CR2_BCP;
	230	val_cr4 ^= FSL_SAI_CR4_FSP;
43550821 XL	231	break;
43550821 XL	232	case SND_SOC_DAIFMT_IB_NF:
13cde090 XL	233	/* Invert bit clock */
13cde090 XL	234	val_cr2 ^= FSL_SAI_CR2_BCP;
43550821 XL	235	break;
43550821 XL	236	case SND_SOC_DAIFMT_NB_IF:
13cde090 XL	237	/* Invert frame clock */
13cde090 XL	238	val_cr4 ^= FSL_SAI_CR4_FSP;
43550821 XL	239	break;
43550821 XL	240	case SND_SOC_DAIFMT_NB_NF:
13cde090	241	/* Nothing to do for both normal cases */
43550821 XL	242	break;
	243	default:
	244	return -EINVAL;
	245	}
	246
13cde090	247	/* DAI clock master masks */
43550821 XL	248	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
	249	case SND_SOC_DAIFMT_CBS_CFS:
	250	val_cr2 \|= FSL_SAI_CR2_BCD_MSTR;
	251	val_cr4 \|= FSL_SAI_CR4_FSD_MSTR;
	252	break;
	253	case SND_SOC_DAIFMT_CBM_CFM:
43550821	254	break;
13cde090 XL	255	case SND_SOC_DAIFMT_CBS_CFM:
13cde090 XL	256	val_cr2 \|= FSL_SAI_CR2_BCD_MSTR;
13cde090 XL	257	break;
13cde090 XL	258	case SND_SOC_DAIFMT_CBM_CFS:
13cde090 XL	259	val_cr4 \|= FSL_SAI_CR4_FSD_MSTR;
13cde090 XL	260	break;
43550821 XL	261	default:
	262	return -EINVAL;
	263	}
	264
2a266f8b NC	265	regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
	266	FSL_SAI_CR2_BCP \| FSL_SAI_CR2_BCD_MSTR, val_cr2);
	267	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
	268	FSL_SAI_CR4_MF \| FSL_SAI_CR4_FSE \|
	269	FSL_SAI_CR4_FSP \| FSL_SAI_CR4_FSD_MSTR, val_cr4);
43550821 XL	270
	271	return 0;
	272	}
	273
	274	static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
	275	{
4e3a99f5	276	int ret;
43550821	277
43550821 XL	278	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
43550821 XL	279	if (ret) {
190af12d	280	dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
78957fc3	281	return ret;
43550821 XL	282	}
	283
	284	ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
78957fc3	285	if (ret)
190af12d	286	dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
43550821	287
1fb2d9d7	288	return ret;
43550821 XL	289	}
	290
	291	static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
	292	struct snd_pcm_hw_params *params,
	293	struct snd_soc_dai *cpu_dai)
	294	{
4e3a99f5	295	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
2a266f8b	296	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
43550821	297	unsigned int channels = params_channels(params);
1d700309	298	u32 word_width = snd_pcm_format_width(params_format(params));
2a266f8b	299	u32 val_cr4 = 0, val_cr5 = 0;
43550821	300
a3f7dcc9 XL	301	if (!sai->is_dsp_mode)
	302	val_cr4 \|= FSL_SAI_CR4_SYWD(word_width);
	303
43550821 XL	304	val_cr5 \|= FSL_SAI_CR5_WNW(word_width);
	305	val_cr5 \|= FSL_SAI_CR5_W0W(word_width);
	306
	307	if (sai->big_endian_data)
43550821	308	val_cr5 \|= FSL_SAI_CR5_FBT(0);
72aa62be XL	309	else
72aa62be XL	310	val_cr5 \|= FSL_SAI_CR5_FBT(word_width - 1);
43550821 XL	311
43550821 XL	312	val_cr4 \|= FSL_SAI_CR4_FRSZ(channels);
43550821	313
2a266f8b NC	314	regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
	315	FSL_SAI_CR4_SYWD_MASK \| FSL_SAI_CR4_FRSZ_MASK,
	316	val_cr4);
	317	regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
	318	FSL_SAI_CR5_WNW_MASK \| FSL_SAI_CR5_W0W_MASK \|
	319	FSL_SAI_CR5_FBT_MASK, val_cr5);
	320	regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
43550821 XL	321
	322	return 0;
	323	}
	324
	325	static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
	326	struct snd_soc_dai *cpu_dai)
	327	{
	328	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
e6b39846	329	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
78957fc3	330	u32 tcsr, rcsr;
496a39d9	331
a3f7dcc9 XL	332	/*
	333	* The transmitter bit clock and frame sync are to be
	334	* used by both the transmitter and receiver.
	335	*/
78957fc3 XL	336	regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
	337	~FSL_SAI_CR2_SYNC);
	338	regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
	339	FSL_SAI_CR2_SYNC);
43550821	340
78957fc3 XL	341	regmap_read(sai->regmap, FSL_SAI_TCSR, &tcsr);
78957fc3 XL	342	regmap_read(sai->regmap, FSL_SAI_RCSR, &rcsr);
43550821	343
a3f7dcc9 XL	344	/*
	345	* It is recommended that the transmitter is the last enabled
	346	* and the first disabled.
	347	*/
43550821 XL	348	switch (cmd) {
	349	case SNDRV_PCM_TRIGGER_START:
	350	case SNDRV_PCM_TRIGGER_RESUME:
	351	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
e6b39846 NC	352	if (!(tcsr & FSL_SAI_CSR_FRDE \|\| rcsr & FSL_SAI_CSR_FRDE)) {
	353	regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
	354	FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
	355	regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
	356	FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
	357	}
e5d0fa9c	358
8abba5d6 NC	359	regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
8abba5d6 NC	360	FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
e6b39846 NC	361	regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
e6b39846 NC	362	FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
43550821	363	break;
43550821 XL	364	case SNDRV_PCM_TRIGGER_STOP:
	365	case SNDRV_PCM_TRIGGER_SUSPEND:
	366	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
e6b39846 NC	367	regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
e6b39846 NC	368	FSL_SAI_CSR_FRDE, 0);
8abba5d6 NC	369	regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
8abba5d6 NC	370	FSL_SAI_CSR_xIE_MASK, 0);
e6b39846	371
f84526cf NC	372	/* Check if the opposite FRDE is also disabled */
f84526cf NC	373	if (!(tx ? rcsr & FSL_SAI_CSR_FRDE : tcsr & FSL_SAI_CSR_FRDE)) {
e6b39846 NC	374	regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
	375	FSL_SAI_CSR_TERE, 0);
	376	regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
	377	FSL_SAI_CSR_TERE, 0);
43550821	378	}
43550821 XL	379	break;
	380	default:
	381	return -EINVAL;
	382	}
	383
	384	return 0;
	385	}
	386
	387	static int fsl_sai_startup(struct snd_pcm_substream *substream,
	388	struct snd_soc_dai *cpu_dai)
	389	{
43550821	390	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
2a266f8b	391	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
ca3e35c7	392	struct device *dev = &sai->pdev->dev;
ca3e35c7 NC	393	int ret;
	394
	395	ret = clk_prepare_enable(sai->bus_clk);
	396	if (ret) {
	397	dev_err(dev, "failed to enable bus clock: %d\n", ret);
	398	return ret;
	399	}
43550821	400
2a266f8b	401	regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
78957fc3 XL	402	FSL_SAI_CR3_TRCE);
	403
	404	return 0;
43550821 XL	405	}
	406
	407	static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
	408	struct snd_soc_dai *cpu_dai)
	409	{
	410	struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
2a266f8b	411	bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
43550821	412
2a266f8b	413	regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
ca3e35c7 NC	414
ca3e35c7 NC	415	clk_disable_unprepare(sai->bus_clk);
43550821 XL	416	}
	417
	418	static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
	419	.set_sysclk = fsl_sai_set_dai_sysclk,
	420	.set_fmt = fsl_sai_set_dai_fmt,
	421	.hw_params = fsl_sai_hw_params,
	422	.trigger = fsl_sai_trigger,
	423	.startup = fsl_sai_startup,
	424	.shutdown = fsl_sai_shutdown,
	425	};
	426
	427	static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
	428	{
	429	struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
e6dc12d7	430
8abba5d6 NC	431	regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 0xffffffff, 0x0);
8abba5d6 NC	432	regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 0xffffffff, 0x0);
78957fc3 XL	433	regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
	434	FSL_SAI_MAXBURST_TX * 2);
	435	regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
	436	FSL_SAI_MAXBURST_RX - 1);
43550821	437
dd9f4060 XL	438	snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
dd9f4060 XL	439	&sai->dma_params_rx);
43550821 XL	440
	441	snd_soc_dai_set_drvdata(cpu_dai, sai);
	442
	443	return 0;
	444	}
	445
43550821 XL	446	static struct snd_soc_dai_driver fsl_sai_dai = {
43550821 XL	447	.probe = fsl_sai_dai_probe,
43550821 XL	448	.playback = {
	449	.channels_min = 1,
	450	.channels_max = 2,
	451	.rates = SNDRV_PCM_RATE_8000_96000,
	452	.formats = FSL_SAI_FORMATS,
	453	},
	454	.capture = {
	455	.channels_min = 1,
	456	.channels_max = 2,
	457	.rates = SNDRV_PCM_RATE_8000_96000,
	458	.formats = FSL_SAI_FORMATS,
	459	},
	460	.ops = &fsl_sai_pcm_dai_ops,
	461	};
	462
	463	static const struct snd_soc_component_driver fsl_component = {
	464	.name = "fsl-sai",
	465	};
	466
78957fc3 XL	467	static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
	468	{
	469	switch (reg) {
	470	case FSL_SAI_TCSR:
	471	case FSL_SAI_TCR1:
	472	case FSL_SAI_TCR2:
	473	case FSL_SAI_TCR3:
	474	case FSL_SAI_TCR4:
	475	case FSL_SAI_TCR5:
	476	case FSL_SAI_TFR:
	477	case FSL_SAI_TMR:
	478	case FSL_SAI_RCSR:
	479	case FSL_SAI_RCR1:
	480	case FSL_SAI_RCR2:
	481	case FSL_SAI_RCR3:
	482	case FSL_SAI_RCR4:
	483	case FSL_SAI_RCR5:
	484	case FSL_SAI_RDR:
	485	case FSL_SAI_RFR:
	486	case FSL_SAI_RMR:
	487	return true;
	488	default:
	489	return false;
	490	}
	491	}
	492
	493	static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
	494	{
	495	switch (reg) {
	496	case FSL_SAI_TFR:
	497	case FSL_SAI_RFR:
	498	case FSL_SAI_TDR:
	499	case FSL_SAI_RDR:
	500	return true;
	501	default:
	502	return false;
	503	}
	504
	505	}
	506
	507	static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
	508	{
	509	switch (reg) {
	510	case FSL_SAI_TCSR:
	511	case FSL_SAI_TCR1:
	512	case FSL_SAI_TCR2:
	513	case FSL_SAI_TCR3:
	514	case FSL_SAI_TCR4:
	515	case FSL_SAI_TCR5:
	516	case FSL_SAI_TDR:
	517	case FSL_SAI_TMR:
	518	case FSL_SAI_RCSR:
	519	case FSL_SAI_RCR1:
	520	case FSL_SAI_RCR2:
	521	case FSL_SAI_RCR3:
	522	case FSL_SAI_RCR4:
	523	case FSL_SAI_RCR5:
	524	case FSL_SAI_RMR:
	525	return true;
	526	default:
	527	return false;
	528	}
	529	}
	530
531	static struct regmap_config fsl_sai_regmap_config = {
532	.reg_bits = 32,
533	.reg_stride = 4,
534	.val_bits = 32,
535
536	.max_register = FSL_SAI_RMR,
537	.readable_reg = fsl_sai_readable_reg,
538	.volatile_reg = fsl_sai_volatile_reg,
539	.writeable_reg = fsl_sai_writeable_reg,
540	};
541
43550821 XL	542	static int fsl_sai_probe(struct platform_device *pdev)
43550821 XL	543	{
4e3a99f5	544	struct device_node *np = pdev->dev.of_node;
43550821 XL	545	struct fsl_sai *sai;
43550821 XL	546	struct resource *res;
78957fc3	547	void __iomem *base;
ca3e35c7 NC	548	char tmp[8];
ca3e35c7 NC	549	int irq, ret, i;
43550821 XL	550
	551	sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
	552	if (!sai)
	553	return -ENOMEM;
	554
e2681a1b NC	555	sai->pdev = pdev;
e2681a1b NC	556
c7540644 NC	557	if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
	558	sai->sai_on_imx = true;
	559
78957fc3 XL	560	sai->big_endian_regs = of_property_read_bool(np, "big-endian-regs");
	561	if (sai->big_endian_regs)
	562	fsl_sai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
	563
	564	sai->big_endian_data = of_property_read_bool(np, "big-endian-data");
	565
43550821	566	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
78957fc3 XL	567	base = devm_ioremap_resource(&pdev->dev, res);
	568	if (IS_ERR(base))
	569	return PTR_ERR(base);
	570
	571	sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
ca3e35c7 NC	572	"bus", base, &fsl_sai_regmap_config);
	573
	574	/* Compatible with old DTB cases */
	575	if (IS_ERR(sai->regmap))
	576	sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
	577	"sai", base, &fsl_sai_regmap_config);
78957fc3 XL	578	if (IS_ERR(sai->regmap)) {
	579	dev_err(&pdev->dev, "regmap init failed\n");
	580	return PTR_ERR(sai->regmap);
43550821 XL	581	}
43550821 XL	582
ca3e35c7 NC	583	/* No error out for old DTB cases but only mark the clock NULL */
	584	sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
	585	if (IS_ERR(sai->bus_clk)) {
	586	dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
	587	PTR_ERR(sai->bus_clk));
	588	sai->bus_clk = NULL;
	589	}
	590
	591	for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
	592	sprintf(tmp, "mclk%d", i + 1);
	593	sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
	594	if (IS_ERR(sai->mclk_clk[i])) {
	595	dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
	596	i + 1, PTR_ERR(sai->mclk_clk[i]));
	597	sai->mclk_clk[i] = NULL;
	598	}
	599	}
	600
e2681a1b NC	601	irq = platform_get_irq(pdev, 0);
	602	if (irq < 0) {
	603	dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
	604	return irq;
	605	}
	606
	607	ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
	608	if (ret) {
	609	dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
	610	return ret;
	611	}
	612
43550821 XL	613	sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
	614	sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
	615	sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
	616	sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
	617
43550821 XL	618	platform_set_drvdata(pdev, sai);
	619
	620	ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
	621	&fsl_sai_dai, 1);
	622	if (ret)
	623	return ret;
	624
c7540644 NC	625	if (sai->sai_on_imx)
	626	return imx_pcm_dma_init(pdev);
	627	else
	628	return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
	629	SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
43550821 XL	630	}
	631
	632	static const struct of_device_id fsl_sai_ids[] = {
	633	{ .compatible = "fsl,vf610-sai", },
c7540644	634	{ .compatible = "fsl,imx6sx-sai", },
43550821 XL	635	{ /* sentinel */ }
	636	};
	637
	638	static struct platform_driver fsl_sai_driver = {
	639	.probe = fsl_sai_probe,
43550821 XL	640	.driver = {
	641	.name = "fsl-sai",
	642	.owner = THIS_MODULE,
	643	.of_match_table = fsl_sai_ids,
	644	},
	645	};
	646	module_platform_driver(fsl_sai_driver);
	647
	648	MODULE_DESCRIPTION("Freescale Soc SAI Interface");
	649	MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
	650	MODULE_ALIAS("platform:fsl-sai");
	651	MODULE_LICENSE("GPL");