Commit | Line | Data |
---|---|---|
43550821 XL |
1 | /* |
2 | * Freescale ALSA SoC Digital Audio Interface (SAI) driver. | |
3 | * | |
c3ecef21 | 4 | * Copyright 2012-2015 Freescale Semiconductor, Inc. |
43550821 XL |
5 | * |
6 | * This program is free software, you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation, either version 2 of the License, or(at your | |
9 | * option) any later version. | |
10 | * | |
11 | */ | |
12 | ||
13 | #include <linux/clk.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/of_address.h> | |
78957fc3 | 18 | #include <linux/regmap.h> |
43550821 XL |
19 | #include <linux/slab.h> |
20 | #include <sound/core.h> | |
21 | #include <sound/dmaengine_pcm.h> | |
22 | #include <sound/pcm_params.h> | |
23 | ||
24 | #include "fsl_sai.h" | |
c7540644 | 25 | #include "imx-pcm.h" |
43550821 | 26 | |
e2681a1b NC |
27 | #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ |
28 | FSL_SAI_CSR_FEIE) | |
29 | ||
444c37ae | 30 | static const unsigned int fsl_sai_rates[] = { |
c5f4823b ZW |
31 | 8000, 11025, 12000, 16000, 22050, |
32 | 24000, 32000, 44100, 48000, 64000, | |
33 | 88200, 96000, 176400, 192000 | |
34 | }; | |
35 | ||
444c37ae | 36 | static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { |
c5f4823b ZW |
37 | .count = ARRAY_SIZE(fsl_sai_rates), |
38 | .list = fsl_sai_rates, | |
39 | }; | |
40 | ||
e2681a1b NC |
41 | static irqreturn_t fsl_sai_isr(int irq, void *devid) |
42 | { | |
43 | struct fsl_sai *sai = (struct fsl_sai *)devid; | |
44 | struct device *dev = &sai->pdev->dev; | |
413312aa NC |
45 | u32 flags, xcsr, mask; |
46 | bool irq_none = true; | |
47 | ||
48 | /* | |
49 | * Both IRQ status bits and IRQ mask bits are in the xCSR but | |
50 | * different shifts. And we here create a mask only for those | |
51 | * IRQs that we activated. | |
52 | */ | |
e2681a1b NC |
53 | mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; |
54 | ||
55 | /* Tx IRQ */ | |
56 | regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr); | |
413312aa NC |
57 | flags = xcsr & mask; |
58 | ||
59 | if (flags) | |
60 | irq_none = false; | |
61 | else | |
62 | goto irq_rx; | |
e2681a1b | 63 | |
413312aa | 64 | if (flags & FSL_SAI_CSR_WSF) |
e2681a1b NC |
65 | dev_dbg(dev, "isr: Start of Tx word detected\n"); |
66 | ||
413312aa | 67 | if (flags & FSL_SAI_CSR_SEF) |
e2681a1b NC |
68 | dev_warn(dev, "isr: Tx Frame sync error detected\n"); |
69 | ||
413312aa | 70 | if (flags & FSL_SAI_CSR_FEF) { |
e2681a1b NC |
71 | dev_warn(dev, "isr: Transmit underrun detected\n"); |
72 | /* FIFO reset for safety */ | |
73 | xcsr |= FSL_SAI_CSR_FR; | |
74 | } | |
75 | ||
413312aa | 76 | if (flags & FSL_SAI_CSR_FWF) |
e2681a1b NC |
77 | dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); |
78 | ||
413312aa | 79 | if (flags & FSL_SAI_CSR_FRF) |
e2681a1b NC |
80 | dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); |
81 | ||
413312aa NC |
82 | flags &= FSL_SAI_CSR_xF_W_MASK; |
83 | xcsr &= ~FSL_SAI_CSR_xF_MASK; | |
84 | ||
85 | if (flags) | |
86 | regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr); | |
e2681a1b | 87 | |
413312aa | 88 | irq_rx: |
e2681a1b NC |
89 | /* Rx IRQ */ |
90 | regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr); | |
413312aa | 91 | flags = xcsr & mask; |
e2681a1b | 92 | |
413312aa NC |
93 | if (flags) |
94 | irq_none = false; | |
95 | else | |
96 | goto out; | |
97 | ||
98 | if (flags & FSL_SAI_CSR_WSF) | |
e2681a1b NC |
99 | dev_dbg(dev, "isr: Start of Rx word detected\n"); |
100 | ||
413312aa | 101 | if (flags & FSL_SAI_CSR_SEF) |
e2681a1b NC |
102 | dev_warn(dev, "isr: Rx Frame sync error detected\n"); |
103 | ||
413312aa | 104 | if (flags & FSL_SAI_CSR_FEF) { |
e2681a1b NC |
105 | dev_warn(dev, "isr: Receive overflow detected\n"); |
106 | /* FIFO reset for safety */ | |
107 | xcsr |= FSL_SAI_CSR_FR; | |
108 | } | |
109 | ||
413312aa | 110 | if (flags & FSL_SAI_CSR_FWF) |
e2681a1b NC |
111 | dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); |
112 | ||
413312aa | 113 | if (flags & FSL_SAI_CSR_FRF) |
e2681a1b NC |
114 | dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); |
115 | ||
413312aa NC |
116 | flags &= FSL_SAI_CSR_xF_W_MASK; |
117 | xcsr &= ~FSL_SAI_CSR_xF_MASK; | |
e2681a1b | 118 | |
413312aa | 119 | if (flags) |
4800f88b | 120 | regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr); |
413312aa NC |
121 | |
122 | out: | |
123 | if (irq_none) | |
124 | return IRQ_NONE; | |
125 | else | |
126 | return IRQ_HANDLED; | |
e2681a1b NC |
127 | } |
128 | ||
43550821 XL |
129 | static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, |
130 | int clk_id, unsigned int freq, int fsl_dir) | |
131 | { | |
43550821 | 132 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b NC |
133 | bool tx = fsl_dir == FSL_FMT_TRANSMITTER; |
134 | u32 val_cr2 = 0; | |
633ff8f8 | 135 | |
43550821 XL |
136 | switch (clk_id) { |
137 | case FSL_SAI_CLK_BUS: | |
43550821 XL |
138 | val_cr2 |= FSL_SAI_CR2_MSEL_BUS; |
139 | break; | |
140 | case FSL_SAI_CLK_MAST1: | |
43550821 XL |
141 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; |
142 | break; | |
143 | case FSL_SAI_CLK_MAST2: | |
43550821 XL |
144 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; |
145 | break; | |
146 | case FSL_SAI_CLK_MAST3: | |
43550821 XL |
147 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; |
148 | break; | |
149 | default: | |
150 | return -EINVAL; | |
151 | } | |
633ff8f8 | 152 | |
2a266f8b NC |
153 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), |
154 | FSL_SAI_CR2_MSEL_MASK, val_cr2); | |
43550821 XL |
155 | |
156 | return 0; | |
157 | } | |
158 | ||
159 | static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
160 | int clk_id, unsigned int freq, int dir) | |
161 | { | |
4e3a99f5 | 162 | int ret; |
43550821 XL |
163 | |
164 | if (dir == SND_SOC_CLOCK_IN) | |
165 | return 0; | |
166 | ||
43550821 XL |
167 | ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, |
168 | FSL_FMT_TRANSMITTER); | |
169 | if (ret) { | |
190af12d | 170 | dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); |
78957fc3 | 171 | return ret; |
43550821 XL |
172 | } |
173 | ||
174 | ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, | |
175 | FSL_FMT_RECEIVER); | |
78957fc3 | 176 | if (ret) |
190af12d | 177 | dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); |
43550821 | 178 | |
1fb2d9d7 | 179 | return ret; |
43550821 XL |
180 | } |
181 | ||
182 | static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, | |
183 | unsigned int fmt, int fsl_dir) | |
184 | { | |
43550821 | 185 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b NC |
186 | bool tx = fsl_dir == FSL_FMT_TRANSMITTER; |
187 | u32 val_cr2 = 0, val_cr4 = 0; | |
43550821 | 188 | |
eadb0019 | 189 | if (!sai->is_lsb_first) |
72aa62be | 190 | val_cr4 |= FSL_SAI_CR4_MF; |
43550821 | 191 | |
13cde090 | 192 | /* DAI mode */ |
43550821 XL |
193 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
194 | case SND_SOC_DAIFMT_I2S: | |
a3f7dcc9 XL |
195 | /* |
196 | * Frame low, 1clk before data, one word length for frame sync, | |
197 | * frame sync starts one serial clock cycle earlier, | |
198 | * that is, together with the last bit of the previous | |
199 | * data word. | |
200 | */ | |
ef33bc32 | 201 | val_cr2 |= FSL_SAI_CR2_BCP; |
13cde090 XL |
202 | val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; |
203 | break; | |
204 | case SND_SOC_DAIFMT_LEFT_J: | |
a3f7dcc9 XL |
205 | /* |
206 | * Frame high, one word length for frame sync, | |
207 | * frame sync asserts with the first bit of the frame. | |
208 | */ | |
ef33bc32 | 209 | val_cr2 |= FSL_SAI_CR2_BCP; |
43550821 | 210 | break; |
a3f7dcc9 XL |
211 | case SND_SOC_DAIFMT_DSP_A: |
212 | /* | |
213 | * Frame high, 1clk before data, one bit for frame sync, | |
214 | * frame sync starts one serial clock cycle earlier, | |
215 | * that is, together with the last bit of the previous | |
216 | * data word. | |
217 | */ | |
ef33bc32 | 218 | val_cr2 |= FSL_SAI_CR2_BCP; |
a3f7dcc9 XL |
219 | val_cr4 |= FSL_SAI_CR4_FSE; |
220 | sai->is_dsp_mode = true; | |
221 | break; | |
222 | case SND_SOC_DAIFMT_DSP_B: | |
223 | /* | |
224 | * Frame high, one bit for frame sync, | |
225 | * frame sync asserts with the first bit of the frame. | |
226 | */ | |
ef33bc32 | 227 | val_cr2 |= FSL_SAI_CR2_BCP; |
a3f7dcc9 XL |
228 | sai->is_dsp_mode = true; |
229 | break; | |
13cde090 XL |
230 | case SND_SOC_DAIFMT_RIGHT_J: |
231 | /* To be done */ | |
43550821 XL |
232 | default: |
233 | return -EINVAL; | |
234 | } | |
235 | ||
13cde090 | 236 | /* DAI clock inversion */ |
43550821 XL |
237 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
238 | case SND_SOC_DAIFMT_IB_IF: | |
13cde090 XL |
239 | /* Invert both clocks */ |
240 | val_cr2 ^= FSL_SAI_CR2_BCP; | |
241 | val_cr4 ^= FSL_SAI_CR4_FSP; | |
43550821 XL |
242 | break; |
243 | case SND_SOC_DAIFMT_IB_NF: | |
13cde090 XL |
244 | /* Invert bit clock */ |
245 | val_cr2 ^= FSL_SAI_CR2_BCP; | |
43550821 XL |
246 | break; |
247 | case SND_SOC_DAIFMT_NB_IF: | |
13cde090 XL |
248 | /* Invert frame clock */ |
249 | val_cr4 ^= FSL_SAI_CR4_FSP; | |
43550821 XL |
250 | break; |
251 | case SND_SOC_DAIFMT_NB_NF: | |
13cde090 | 252 | /* Nothing to do for both normal cases */ |
43550821 XL |
253 | break; |
254 | default: | |
255 | return -EINVAL; | |
256 | } | |
257 | ||
13cde090 | 258 | /* DAI clock master masks */ |
43550821 XL |
259 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
260 | case SND_SOC_DAIFMT_CBS_CFS: | |
261 | val_cr2 |= FSL_SAI_CR2_BCD_MSTR; | |
262 | val_cr4 |= FSL_SAI_CR4_FSD_MSTR; | |
263 | break; | |
264 | case SND_SOC_DAIFMT_CBM_CFM: | |
c3ecef21 | 265 | sai->is_slave_mode = true; |
43550821 | 266 | break; |
13cde090 XL |
267 | case SND_SOC_DAIFMT_CBS_CFM: |
268 | val_cr2 |= FSL_SAI_CR2_BCD_MSTR; | |
13cde090 XL |
269 | break; |
270 | case SND_SOC_DAIFMT_CBM_CFS: | |
13cde090 | 271 | val_cr4 |= FSL_SAI_CR4_FSD_MSTR; |
c3ecef21 | 272 | sai->is_slave_mode = true; |
13cde090 | 273 | break; |
43550821 XL |
274 | default: |
275 | return -EINVAL; | |
276 | } | |
277 | ||
2a266f8b NC |
278 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), |
279 | FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); | |
280 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), | |
281 | FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | | |
282 | FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); | |
43550821 XL |
283 | |
284 | return 0; | |
285 | } | |
286 | ||
287 | static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
288 | { | |
4e3a99f5 | 289 | int ret; |
43550821 | 290 | |
43550821 XL |
291 | ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER); |
292 | if (ret) { | |
190af12d | 293 | dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); |
78957fc3 | 294 | return ret; |
43550821 XL |
295 | } |
296 | ||
297 | ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER); | |
78957fc3 | 298 | if (ret) |
190af12d | 299 | dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); |
43550821 | 300 | |
1fb2d9d7 | 301 | return ret; |
43550821 XL |
302 | } |
303 | ||
c3ecef21 ZW |
304 | static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) |
305 | { | |
306 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); | |
307 | unsigned long clk_rate; | |
308 | u32 savediv = 0, ratio, savesub = freq; | |
309 | u32 id; | |
310 | int ret = 0; | |
311 | ||
312 | /* Don't apply to slave mode */ | |
313 | if (sai->is_slave_mode) | |
314 | return 0; | |
315 | ||
316 | for (id = 0; id < FSL_SAI_MCLK_MAX; id++) { | |
317 | clk_rate = clk_get_rate(sai->mclk_clk[id]); | |
318 | if (!clk_rate) | |
319 | continue; | |
320 | ||
321 | ratio = clk_rate / freq; | |
322 | ||
323 | ret = clk_rate - ratio * freq; | |
324 | ||
325 | /* | |
326 | * Drop the source that can not be | |
327 | * divided into the required rate. | |
328 | */ | |
329 | if (ret != 0 && clk_rate / ret < 1000) | |
330 | continue; | |
331 | ||
332 | dev_dbg(dai->dev, | |
333 | "ratio %d for freq %dHz based on clock %ldHz\n", | |
334 | ratio, freq, clk_rate); | |
335 | ||
336 | if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512) | |
337 | ratio /= 2; | |
338 | else | |
339 | continue; | |
340 | ||
341 | if (ret < savesub) { | |
342 | savediv = ratio; | |
343 | sai->mclk_id[tx] = id; | |
344 | savesub = ret; | |
345 | } | |
346 | ||
347 | if (ret == 0) | |
348 | break; | |
349 | } | |
350 | ||
351 | if (savediv == 0) { | |
352 | dev_err(dai->dev, "failed to derive required %cx rate: %d\n", | |
353 | tx ? 'T' : 'R', freq); | |
354 | return -EINVAL; | |
355 | } | |
356 | ||
9cc58712 ZW |
357 | /* |
358 | * 1) For Asynchronous mode, we must set RCR2 register for capture, and | |
359 | * set TCR2 register for playback. | |
360 | * 2) For Tx sync with Rx clock, we must set RCR2 register for playback | |
361 | * and capture. | |
362 | * 3) For Rx sync with Tx clock, we must set TCR2 register for playback | |
363 | * and capture. | |
364 | * 4) For Tx and Rx are both Synchronous with another SAI, we just | |
365 | * ignore it. | |
366 | */ | |
367 | if ((sai->synchronous[TX] && !sai->synchronous[RX]) || | |
368 | (!tx && !sai->synchronous[RX])) { | |
c3ecef21 ZW |
369 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, |
370 | FSL_SAI_CR2_MSEL_MASK, | |
371 | FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); | |
372 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, | |
373 | FSL_SAI_CR2_DIV_MASK, savediv - 1); | |
9cc58712 ZW |
374 | } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) || |
375 | (tx && !sai->synchronous[TX])) { | |
c3ecef21 ZW |
376 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, |
377 | FSL_SAI_CR2_MSEL_MASK, | |
378 | FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); | |
379 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, | |
380 | FSL_SAI_CR2_DIV_MASK, savediv - 1); | |
381 | } | |
382 | ||
383 | dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", | |
384 | sai->mclk_id[tx], savediv, savesub); | |
385 | ||
386 | return 0; | |
387 | } | |
388 | ||
43550821 XL |
389 | static int fsl_sai_hw_params(struct snd_pcm_substream *substream, |
390 | struct snd_pcm_hw_params *params, | |
391 | struct snd_soc_dai *cpu_dai) | |
392 | { | |
4e3a99f5 | 393 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b | 394 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
43550821 | 395 | unsigned int channels = params_channels(params); |
1d700309 | 396 | u32 word_width = snd_pcm_format_width(params_format(params)); |
2a266f8b | 397 | u32 val_cr4 = 0, val_cr5 = 0; |
c3ecef21 ZW |
398 | int ret; |
399 | ||
400 | if (!sai->is_slave_mode) { | |
401 | ret = fsl_sai_set_bclk(cpu_dai, tx, | |
402 | 2 * word_width * params_rate(params)); | |
403 | if (ret) | |
404 | return ret; | |
405 | ||
406 | /* Do not enable the clock if it is already enabled */ | |
407 | if (!(sai->mclk_streams & BIT(substream->stream))) { | |
408 | ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); | |
409 | if (ret) | |
410 | return ret; | |
411 | ||
412 | sai->mclk_streams |= BIT(substream->stream); | |
413 | } | |
414 | ||
415 | } | |
43550821 | 416 | |
a3f7dcc9 XL |
417 | if (!sai->is_dsp_mode) |
418 | val_cr4 |= FSL_SAI_CR4_SYWD(word_width); | |
419 | ||
43550821 XL |
420 | val_cr5 |= FSL_SAI_CR5_WNW(word_width); |
421 | val_cr5 |= FSL_SAI_CR5_W0W(word_width); | |
422 | ||
eadb0019 | 423 | if (sai->is_lsb_first) |
43550821 | 424 | val_cr5 |= FSL_SAI_CR5_FBT(0); |
72aa62be XL |
425 | else |
426 | val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); | |
43550821 XL |
427 | |
428 | val_cr4 |= FSL_SAI_CR4_FRSZ(channels); | |
43550821 | 429 | |
51659ca0 ZW |
430 | /* |
431 | * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will | |
432 | * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), | |
433 | * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync | |
434 | * error. | |
435 | */ | |
436 | ||
437 | if (!sai->is_slave_mode) { | |
438 | if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { | |
439 | regmap_update_bits(sai->regmap, FSL_SAI_TCR4, | |
440 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
441 | val_cr4); | |
442 | regmap_update_bits(sai->regmap, FSL_SAI_TCR5, | |
443 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
444 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
445 | regmap_write(sai->regmap, FSL_SAI_TMR, | |
446 | ~0UL - ((1 << channels) - 1)); | |
447 | } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { | |
448 | regmap_update_bits(sai->regmap, FSL_SAI_RCR4, | |
449 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
450 | val_cr4); | |
451 | regmap_update_bits(sai->regmap, FSL_SAI_RCR5, | |
452 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
453 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
454 | regmap_write(sai->regmap, FSL_SAI_RMR, | |
455 | ~0UL - ((1 << channels) - 1)); | |
456 | } | |
457 | } | |
458 | ||
2a266f8b NC |
459 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), |
460 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
461 | val_cr4); | |
462 | regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx), | |
463 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
464 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
465 | regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1)); | |
43550821 XL |
466 | |
467 | return 0; | |
468 | } | |
469 | ||
c3ecef21 ZW |
470 | static int fsl_sai_hw_free(struct snd_pcm_substream *substream, |
471 | struct snd_soc_dai *cpu_dai) | |
472 | { | |
473 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
474 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
475 | ||
476 | if (!sai->is_slave_mode && | |
477 | sai->mclk_streams & BIT(substream->stream)) { | |
478 | clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); | |
479 | sai->mclk_streams &= ~BIT(substream->stream); | |
480 | } | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | ||
43550821 XL |
486 | static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, |
487 | struct snd_soc_dai *cpu_dai) | |
488 | { | |
489 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
e6b39846 | 490 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
c44b56af | 491 | u32 xcsr, count = 100; |
496a39d9 | 492 | |
a3f7dcc9 | 493 | /* |
08fdf65e NC |
494 | * Asynchronous mode: Clear SYNC for both Tx and Rx. |
495 | * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. | |
496 | * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. | |
a3f7dcc9 | 497 | */ |
855675f6 | 498 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, 0); |
78957fc3 | 499 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC, |
08fdf65e | 500 | sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); |
43550821 | 501 | |
a3f7dcc9 XL |
502 | /* |
503 | * It is recommended that the transmitter is the last enabled | |
504 | * and the first disabled. | |
505 | */ | |
43550821 XL |
506 | switch (cmd) { |
507 | case SNDRV_PCM_TRIGGER_START: | |
508 | case SNDRV_PCM_TRIGGER_RESUME: | |
509 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
a3fdc674 NC |
510 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
511 | FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); | |
512 | ||
f4075a8f NC |
513 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, |
514 | FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); | |
515 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, | |
516 | FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); | |
e5d0fa9c | 517 | |
8abba5d6 NC |
518 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
519 | FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); | |
43550821 | 520 | break; |
43550821 XL |
521 | case SNDRV_PCM_TRIGGER_STOP: |
522 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
523 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
e6b39846 NC |
524 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
525 | FSL_SAI_CSR_FRDE, 0); | |
8abba5d6 NC |
526 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
527 | FSL_SAI_CSR_xIE_MASK, 0); | |
e6b39846 | 528 | |
f84526cf | 529 | /* Check if the opposite FRDE is also disabled */ |
f4075a8f NC |
530 | regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr); |
531 | if (!(xcsr & FSL_SAI_CSR_FRDE)) { | |
eff952b7 | 532 | /* Disable both directions and reset their FIFOs */ |
e6b39846 | 533 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, |
c44b56af | 534 | FSL_SAI_CSR_TERE, 0); |
e6b39846 | 535 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, |
c44b56af NC |
536 | FSL_SAI_CSR_TERE, 0); |
537 | ||
538 | /* TERE will remain set till the end of current frame */ | |
539 | do { | |
540 | udelay(10); | |
541 | regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr); | |
542 | } while (--count && xcsr & FSL_SAI_CSR_TERE); | |
543 | ||
544 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, | |
545 | FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); | |
546 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, | |
547 | FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); | |
43550821 | 548 | } |
43550821 XL |
549 | break; |
550 | default: | |
551 | return -EINVAL; | |
552 | } | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
557 | static int fsl_sai_startup(struct snd_pcm_substream *substream, | |
558 | struct snd_soc_dai *cpu_dai) | |
559 | { | |
43550821 | 560 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b | 561 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
ca3e35c7 | 562 | struct device *dev = &sai->pdev->dev; |
ca3e35c7 NC |
563 | int ret; |
564 | ||
565 | ret = clk_prepare_enable(sai->bus_clk); | |
566 | if (ret) { | |
567 | dev_err(dev, "failed to enable bus clock: %d\n", ret); | |
568 | return ret; | |
569 | } | |
43550821 | 570 | |
2a266f8b | 571 | regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, |
78957fc3 XL |
572 | FSL_SAI_CR3_TRCE); |
573 | ||
c5f4823b ZW |
574 | ret = snd_pcm_hw_constraint_list(substream->runtime, 0, |
575 | SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); | |
576 | ||
577 | return ret; | |
43550821 XL |
578 | } |
579 | ||
580 | static void fsl_sai_shutdown(struct snd_pcm_substream *substream, | |
581 | struct snd_soc_dai *cpu_dai) | |
582 | { | |
583 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
2a266f8b | 584 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
43550821 | 585 | |
2a266f8b | 586 | regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0); |
ca3e35c7 NC |
587 | |
588 | clk_disable_unprepare(sai->bus_clk); | |
43550821 XL |
589 | } |
590 | ||
591 | static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { | |
592 | .set_sysclk = fsl_sai_set_dai_sysclk, | |
593 | .set_fmt = fsl_sai_set_dai_fmt, | |
594 | .hw_params = fsl_sai_hw_params, | |
c3ecef21 | 595 | .hw_free = fsl_sai_hw_free, |
43550821 XL |
596 | .trigger = fsl_sai_trigger, |
597 | .startup = fsl_sai_startup, | |
598 | .shutdown = fsl_sai_shutdown, | |
599 | }; | |
600 | ||
601 | static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) | |
602 | { | |
603 | struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); | |
e6dc12d7 | 604 | |
376d1a92 NC |
605 | /* Software Reset for both Tx and Rx */ |
606 | regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); | |
607 | regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); | |
608 | /* Clear SR bit to finish the reset */ | |
609 | regmap_write(sai->regmap, FSL_SAI_TCSR, 0); | |
610 | regmap_write(sai->regmap, FSL_SAI_RCSR, 0); | |
611 | ||
78957fc3 XL |
612 | regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK, |
613 | FSL_SAI_MAXBURST_TX * 2); | |
614 | regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK, | |
615 | FSL_SAI_MAXBURST_RX - 1); | |
43550821 | 616 | |
dd9f4060 XL |
617 | snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, |
618 | &sai->dma_params_rx); | |
43550821 XL |
619 | |
620 | snd_soc_dai_set_drvdata(cpu_dai, sai); | |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
43550821 XL |
625 | static struct snd_soc_dai_driver fsl_sai_dai = { |
626 | .probe = fsl_sai_dai_probe, | |
43550821 | 627 | .playback = { |
20d5b76f | 628 | .stream_name = "CPU-Playback", |
43550821 XL |
629 | .channels_min = 1, |
630 | .channels_max = 2, | |
c5f4823b ZW |
631 | .rate_min = 8000, |
632 | .rate_max = 192000, | |
633 | .rates = SNDRV_PCM_RATE_KNOT, | |
43550821 XL |
634 | .formats = FSL_SAI_FORMATS, |
635 | }, | |
636 | .capture = { | |
20d5b76f | 637 | .stream_name = "CPU-Capture", |
43550821 XL |
638 | .channels_min = 1, |
639 | .channels_max = 2, | |
c5f4823b ZW |
640 | .rate_min = 8000, |
641 | .rate_max = 192000, | |
642 | .rates = SNDRV_PCM_RATE_KNOT, | |
43550821 XL |
643 | .formats = FSL_SAI_FORMATS, |
644 | }, | |
645 | .ops = &fsl_sai_pcm_dai_ops, | |
646 | }; | |
647 | ||
648 | static const struct snd_soc_component_driver fsl_component = { | |
649 | .name = "fsl-sai", | |
650 | }; | |
651 | ||
78957fc3 XL |
652 | static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) |
653 | { | |
654 | switch (reg) { | |
655 | case FSL_SAI_TCSR: | |
656 | case FSL_SAI_TCR1: | |
657 | case FSL_SAI_TCR2: | |
658 | case FSL_SAI_TCR3: | |
659 | case FSL_SAI_TCR4: | |
660 | case FSL_SAI_TCR5: | |
661 | case FSL_SAI_TFR: | |
662 | case FSL_SAI_TMR: | |
663 | case FSL_SAI_RCSR: | |
664 | case FSL_SAI_RCR1: | |
665 | case FSL_SAI_RCR2: | |
666 | case FSL_SAI_RCR3: | |
667 | case FSL_SAI_RCR4: | |
668 | case FSL_SAI_RCR5: | |
669 | case FSL_SAI_RDR: | |
670 | case FSL_SAI_RFR: | |
671 | case FSL_SAI_RMR: | |
672 | return true; | |
673 | default: | |
674 | return false; | |
675 | } | |
676 | } | |
677 | ||
678 | static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) | |
679 | { | |
680 | switch (reg) { | |
1fde5e83 ZW |
681 | case FSL_SAI_TCSR: |
682 | case FSL_SAI_RCSR: | |
78957fc3 XL |
683 | case FSL_SAI_TFR: |
684 | case FSL_SAI_RFR: | |
685 | case FSL_SAI_TDR: | |
686 | case FSL_SAI_RDR: | |
687 | return true; | |
688 | default: | |
689 | return false; | |
690 | } | |
691 | ||
692 | } | |
693 | ||
694 | static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) | |
695 | { | |
696 | switch (reg) { | |
697 | case FSL_SAI_TCSR: | |
698 | case FSL_SAI_TCR1: | |
699 | case FSL_SAI_TCR2: | |
700 | case FSL_SAI_TCR3: | |
701 | case FSL_SAI_TCR4: | |
702 | case FSL_SAI_TCR5: | |
703 | case FSL_SAI_TDR: | |
704 | case FSL_SAI_TMR: | |
705 | case FSL_SAI_RCSR: | |
706 | case FSL_SAI_RCR1: | |
707 | case FSL_SAI_RCR2: | |
708 | case FSL_SAI_RCR3: | |
709 | case FSL_SAI_RCR4: | |
710 | case FSL_SAI_RCR5: | |
711 | case FSL_SAI_RMR: | |
712 | return true; | |
713 | default: | |
714 | return false; | |
715 | } | |
716 | } | |
717 | ||
014fd22e | 718 | static const struct regmap_config fsl_sai_regmap_config = { |
78957fc3 XL |
719 | .reg_bits = 32, |
720 | .reg_stride = 4, | |
721 | .val_bits = 32, | |
722 | ||
723 | .max_register = FSL_SAI_RMR, | |
724 | .readable_reg = fsl_sai_readable_reg, | |
725 | .volatile_reg = fsl_sai_volatile_reg, | |
726 | .writeable_reg = fsl_sai_writeable_reg, | |
1fde5e83 | 727 | .cache_type = REGCACHE_FLAT, |
78957fc3 XL |
728 | }; |
729 | ||
43550821 XL |
730 | static int fsl_sai_probe(struct platform_device *pdev) |
731 | { | |
4e3a99f5 | 732 | struct device_node *np = pdev->dev.of_node; |
43550821 XL |
733 | struct fsl_sai *sai; |
734 | struct resource *res; | |
78957fc3 | 735 | void __iomem *base; |
ca3e35c7 NC |
736 | char tmp[8]; |
737 | int irq, ret, i; | |
43550821 XL |
738 | |
739 | sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); | |
740 | if (!sai) | |
741 | return -ENOMEM; | |
742 | ||
e2681a1b NC |
743 | sai->pdev = pdev; |
744 | ||
c7540644 NC |
745 | if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai")) |
746 | sai->sai_on_imx = true; | |
747 | ||
eadb0019 | 748 | sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); |
78957fc3 | 749 | |
43550821 | 750 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
78957fc3 XL |
751 | base = devm_ioremap_resource(&pdev->dev, res); |
752 | if (IS_ERR(base)) | |
753 | return PTR_ERR(base); | |
754 | ||
755 | sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, | |
ca3e35c7 NC |
756 | "bus", base, &fsl_sai_regmap_config); |
757 | ||
758 | /* Compatible with old DTB cases */ | |
759 | if (IS_ERR(sai->regmap)) | |
760 | sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, | |
761 | "sai", base, &fsl_sai_regmap_config); | |
78957fc3 XL |
762 | if (IS_ERR(sai->regmap)) { |
763 | dev_err(&pdev->dev, "regmap init failed\n"); | |
764 | return PTR_ERR(sai->regmap); | |
43550821 XL |
765 | } |
766 | ||
ca3e35c7 NC |
767 | /* No error out for old DTB cases but only mark the clock NULL */ |
768 | sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); | |
769 | if (IS_ERR(sai->bus_clk)) { | |
770 | dev_err(&pdev->dev, "failed to get bus clock: %ld\n", | |
771 | PTR_ERR(sai->bus_clk)); | |
772 | sai->bus_clk = NULL; | |
773 | } | |
774 | ||
c3ecef21 ZW |
775 | sai->mclk_clk[0] = sai->bus_clk; |
776 | for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { | |
777 | sprintf(tmp, "mclk%d", i); | |
ca3e35c7 NC |
778 | sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); |
779 | if (IS_ERR(sai->mclk_clk[i])) { | |
780 | dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n", | |
781 | i + 1, PTR_ERR(sai->mclk_clk[i])); | |
782 | sai->mclk_clk[i] = NULL; | |
783 | } | |
784 | } | |
785 | ||
e2681a1b NC |
786 | irq = platform_get_irq(pdev, 0); |
787 | if (irq < 0) { | |
0954237f | 788 | dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); |
e2681a1b NC |
789 | return irq; |
790 | } | |
791 | ||
792 | ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai); | |
793 | if (ret) { | |
794 | dev_err(&pdev->dev, "failed to claim irq %u\n", irq); | |
795 | return ret; | |
796 | } | |
797 | ||
08fdf65e NC |
798 | /* Sync Tx with Rx as default by following old DT binding */ |
799 | sai->synchronous[RX] = true; | |
800 | sai->synchronous[TX] = false; | |
801 | fsl_sai_dai.symmetric_rates = 1; | |
802 | fsl_sai_dai.symmetric_channels = 1; | |
803 | fsl_sai_dai.symmetric_samplebits = 1; | |
804 | ||
ce7344a4 NC |
805 | if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && |
806 | of_find_property(np, "fsl,sai-asynchronous", NULL)) { | |
807 | /* error out if both synchronous and asynchronous are present */ | |
808 | dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); | |
809 | return -EINVAL; | |
810 | } | |
811 | ||
08fdf65e NC |
812 | if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { |
813 | /* Sync Rx with Tx */ | |
814 | sai->synchronous[RX] = false; | |
815 | sai->synchronous[TX] = true; | |
816 | } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { | |
817 | /* Discard all settings for asynchronous mode */ | |
818 | sai->synchronous[RX] = false; | |
819 | sai->synchronous[TX] = false; | |
820 | fsl_sai_dai.symmetric_rates = 0; | |
821 | fsl_sai_dai.symmetric_channels = 0; | |
822 | fsl_sai_dai.symmetric_samplebits = 0; | |
823 | } | |
824 | ||
43550821 XL |
825 | sai->dma_params_rx.addr = res->start + FSL_SAI_RDR; |
826 | sai->dma_params_tx.addr = res->start + FSL_SAI_TDR; | |
827 | sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; | |
828 | sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; | |
829 | ||
43550821 XL |
830 | platform_set_drvdata(pdev, sai); |
831 | ||
832 | ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, | |
833 | &fsl_sai_dai, 1); | |
834 | if (ret) | |
835 | return ret; | |
836 | ||
c7540644 | 837 | if (sai->sai_on_imx) |
0d69e0dd | 838 | return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE); |
c7540644 | 839 | else |
acde50a7 | 840 | return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); |
43550821 XL |
841 | } |
842 | ||
843 | static const struct of_device_id fsl_sai_ids[] = { | |
844 | { .compatible = "fsl,vf610-sai", }, | |
c7540644 | 845 | { .compatible = "fsl,imx6sx-sai", }, |
43550821 XL |
846 | { /* sentinel */ } |
847 | }; | |
c759241f | 848 | MODULE_DEVICE_TABLE(of, fsl_sai_ids); |
43550821 | 849 | |
739146b6 | 850 | #ifdef CONFIG_PM_SLEEP |
1fde5e83 ZW |
851 | static int fsl_sai_suspend(struct device *dev) |
852 | { | |
853 | struct fsl_sai *sai = dev_get_drvdata(dev); | |
854 | ||
855 | regcache_cache_only(sai->regmap, true); | |
856 | regcache_mark_dirty(sai->regmap); | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
861 | static int fsl_sai_resume(struct device *dev) | |
862 | { | |
863 | struct fsl_sai *sai = dev_get_drvdata(dev); | |
864 | ||
865 | regcache_cache_only(sai->regmap, false); | |
866 | regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); | |
867 | regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); | |
868 | msleep(1); | |
869 | regmap_write(sai->regmap, FSL_SAI_TCSR, 0); | |
870 | regmap_write(sai->regmap, FSL_SAI_RCSR, 0); | |
871 | return regcache_sync(sai->regmap); | |
872 | } | |
873 | #endif /* CONFIG_PM_SLEEP */ | |
874 | ||
875 | static const struct dev_pm_ops fsl_sai_pm_ops = { | |
876 | SET_SYSTEM_SLEEP_PM_OPS(fsl_sai_suspend, fsl_sai_resume) | |
877 | }; | |
878 | ||
43550821 XL |
879 | static struct platform_driver fsl_sai_driver = { |
880 | .probe = fsl_sai_probe, | |
43550821 XL |
881 | .driver = { |
882 | .name = "fsl-sai", | |
1fde5e83 | 883 | .pm = &fsl_sai_pm_ops, |
43550821 XL |
884 | .of_match_table = fsl_sai_ids, |
885 | }, | |
886 | }; | |
887 | module_platform_driver(fsl_sai_driver); | |
888 | ||
889 | MODULE_DESCRIPTION("Freescale Soc SAI Interface"); | |
890 | MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); | |
891 | MODULE_ALIAS("platform:fsl-sai"); | |
892 | MODULE_LICENSE("GPL"); |