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dbbeaad4 FE |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | // | |
3 | // Freescale ALSA SoC Digital Audio Interface (SAI) driver. | |
4 | // | |
5 | // Copyright 2012-2015 Freescale Semiconductor, Inc. | |
43550821 XL |
6 | |
7 | #include <linux/clk.h> | |
8 | #include <linux/delay.h> | |
9 | #include <linux/dmaengine.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/of_address.h> | |
812ad463 | 12 | #include <linux/pm_runtime.h> |
78957fc3 | 13 | #include <linux/regmap.h> |
43550821 | 14 | #include <linux/slab.h> |
512feb4e | 15 | #include <linux/time.h> |
43550821 XL |
16 | #include <sound/core.h> |
17 | #include <sound/dmaengine_pcm.h> | |
18 | #include <sound/pcm_params.h> | |
4d245850 FE |
19 | #include <linux/mfd/syscon.h> |
20 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
43550821 XL |
21 | |
22 | #include "fsl_sai.h" | |
c7540644 | 23 | #include "imx-pcm.h" |
43550821 | 24 | |
e2681a1b NC |
25 | #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ |
26 | FSL_SAI_CSR_FEIE) | |
27 | ||
444c37ae | 28 | static const unsigned int fsl_sai_rates[] = { |
c5f4823b ZW |
29 | 8000, 11025, 12000, 16000, 22050, |
30 | 24000, 32000, 44100, 48000, 64000, | |
31 | 88200, 96000, 176400, 192000 | |
32 | }; | |
33 | ||
444c37ae | 34 | static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = { |
c5f4823b ZW |
35 | .count = ARRAY_SIZE(fsl_sai_rates), |
36 | .list = fsl_sai_rates, | |
37 | }; | |
38 | ||
e2681a1b NC |
39 | static irqreturn_t fsl_sai_isr(int irq, void *devid) |
40 | { | |
41 | struct fsl_sai *sai = (struct fsl_sai *)devid; | |
42 | struct device *dev = &sai->pdev->dev; | |
413312aa NC |
43 | u32 flags, xcsr, mask; |
44 | bool irq_none = true; | |
45 | ||
46 | /* | |
47 | * Both IRQ status bits and IRQ mask bits are in the xCSR but | |
48 | * different shifts. And we here create a mask only for those | |
49 | * IRQs that we activated. | |
50 | */ | |
e2681a1b NC |
51 | mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT; |
52 | ||
53 | /* Tx IRQ */ | |
54 | regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr); | |
413312aa NC |
55 | flags = xcsr & mask; |
56 | ||
57 | if (flags) | |
58 | irq_none = false; | |
59 | else | |
60 | goto irq_rx; | |
e2681a1b | 61 | |
413312aa | 62 | if (flags & FSL_SAI_CSR_WSF) |
e2681a1b NC |
63 | dev_dbg(dev, "isr: Start of Tx word detected\n"); |
64 | ||
413312aa | 65 | if (flags & FSL_SAI_CSR_SEF) |
e412fcb0 | 66 | dev_dbg(dev, "isr: Tx Frame sync error detected\n"); |
e2681a1b | 67 | |
413312aa | 68 | if (flags & FSL_SAI_CSR_FEF) { |
e412fcb0 | 69 | dev_dbg(dev, "isr: Transmit underrun detected\n"); |
e2681a1b NC |
70 | /* FIFO reset for safety */ |
71 | xcsr |= FSL_SAI_CSR_FR; | |
72 | } | |
73 | ||
413312aa | 74 | if (flags & FSL_SAI_CSR_FWF) |
e2681a1b NC |
75 | dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n"); |
76 | ||
413312aa | 77 | if (flags & FSL_SAI_CSR_FRF) |
e2681a1b NC |
78 | dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n"); |
79 | ||
413312aa NC |
80 | flags &= FSL_SAI_CSR_xF_W_MASK; |
81 | xcsr &= ~FSL_SAI_CSR_xF_MASK; | |
82 | ||
83 | if (flags) | |
84 | regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr); | |
e2681a1b | 85 | |
413312aa | 86 | irq_rx: |
e2681a1b NC |
87 | /* Rx IRQ */ |
88 | regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr); | |
413312aa | 89 | flags = xcsr & mask; |
e2681a1b | 90 | |
413312aa NC |
91 | if (flags) |
92 | irq_none = false; | |
93 | else | |
94 | goto out; | |
95 | ||
96 | if (flags & FSL_SAI_CSR_WSF) | |
e2681a1b NC |
97 | dev_dbg(dev, "isr: Start of Rx word detected\n"); |
98 | ||
413312aa | 99 | if (flags & FSL_SAI_CSR_SEF) |
e412fcb0 | 100 | dev_dbg(dev, "isr: Rx Frame sync error detected\n"); |
e2681a1b | 101 | |
413312aa | 102 | if (flags & FSL_SAI_CSR_FEF) { |
e412fcb0 | 103 | dev_dbg(dev, "isr: Receive overflow detected\n"); |
e2681a1b NC |
104 | /* FIFO reset for safety */ |
105 | xcsr |= FSL_SAI_CSR_FR; | |
106 | } | |
107 | ||
413312aa | 108 | if (flags & FSL_SAI_CSR_FWF) |
e2681a1b NC |
109 | dev_dbg(dev, "isr: Enabled receive FIFO is full\n"); |
110 | ||
413312aa | 111 | if (flags & FSL_SAI_CSR_FRF) |
e2681a1b NC |
112 | dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n"); |
113 | ||
413312aa NC |
114 | flags &= FSL_SAI_CSR_xF_W_MASK; |
115 | xcsr &= ~FSL_SAI_CSR_xF_MASK; | |
e2681a1b | 116 | |
413312aa | 117 | if (flags) |
4800f88b | 118 | regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr); |
413312aa NC |
119 | |
120 | out: | |
121 | if (irq_none) | |
122 | return IRQ_NONE; | |
123 | else | |
124 | return IRQ_HANDLED; | |
e2681a1b NC |
125 | } |
126 | ||
c1df2964 ZW |
127 | static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, |
128 | u32 rx_mask, int slots, int slot_width) | |
129 | { | |
130 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
131 | ||
132 | sai->slots = slots; | |
133 | sai->slot_width = slot_width; | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
43550821 XL |
138 | static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, |
139 | int clk_id, unsigned int freq, int fsl_dir) | |
140 | { | |
43550821 | 141 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b NC |
142 | bool tx = fsl_dir == FSL_FMT_TRANSMITTER; |
143 | u32 val_cr2 = 0; | |
633ff8f8 | 144 | |
43550821 XL |
145 | switch (clk_id) { |
146 | case FSL_SAI_CLK_BUS: | |
43550821 XL |
147 | val_cr2 |= FSL_SAI_CR2_MSEL_BUS; |
148 | break; | |
149 | case FSL_SAI_CLK_MAST1: | |
43550821 XL |
150 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; |
151 | break; | |
152 | case FSL_SAI_CLK_MAST2: | |
43550821 XL |
153 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; |
154 | break; | |
155 | case FSL_SAI_CLK_MAST3: | |
43550821 XL |
156 | val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; |
157 | break; | |
158 | default: | |
159 | return -EINVAL; | |
160 | } | |
633ff8f8 | 161 | |
2a266f8b NC |
162 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), |
163 | FSL_SAI_CR2_MSEL_MASK, val_cr2); | |
43550821 XL |
164 | |
165 | return 0; | |
166 | } | |
167 | ||
168 | static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |
169 | int clk_id, unsigned int freq, int dir) | |
170 | { | |
4e3a99f5 | 171 | int ret; |
43550821 XL |
172 | |
173 | if (dir == SND_SOC_CLOCK_IN) | |
174 | return 0; | |
175 | ||
43550821 XL |
176 | ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, |
177 | FSL_FMT_TRANSMITTER); | |
178 | if (ret) { | |
190af12d | 179 | dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); |
78957fc3 | 180 | return ret; |
43550821 XL |
181 | } |
182 | ||
183 | ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, | |
184 | FSL_FMT_RECEIVER); | |
78957fc3 | 185 | if (ret) |
190af12d | 186 | dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret); |
43550821 | 187 | |
1fb2d9d7 | 188 | return ret; |
43550821 XL |
189 | } |
190 | ||
191 | static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, | |
192 | unsigned int fmt, int fsl_dir) | |
193 | { | |
43550821 | 194 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b NC |
195 | bool tx = fsl_dir == FSL_FMT_TRANSMITTER; |
196 | u32 val_cr2 = 0, val_cr4 = 0; | |
43550821 | 197 | |
eadb0019 | 198 | if (!sai->is_lsb_first) |
72aa62be | 199 | val_cr4 |= FSL_SAI_CR4_MF; |
43550821 | 200 | |
13cde090 | 201 | /* DAI mode */ |
43550821 XL |
202 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
203 | case SND_SOC_DAIFMT_I2S: | |
a3f7dcc9 XL |
204 | /* |
205 | * Frame low, 1clk before data, one word length for frame sync, | |
206 | * frame sync starts one serial clock cycle earlier, | |
207 | * that is, together with the last bit of the previous | |
208 | * data word. | |
209 | */ | |
ef33bc32 | 210 | val_cr2 |= FSL_SAI_CR2_BCP; |
13cde090 XL |
211 | val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP; |
212 | break; | |
213 | case SND_SOC_DAIFMT_LEFT_J: | |
a3f7dcc9 XL |
214 | /* |
215 | * Frame high, one word length for frame sync, | |
216 | * frame sync asserts with the first bit of the frame. | |
217 | */ | |
ef33bc32 | 218 | val_cr2 |= FSL_SAI_CR2_BCP; |
43550821 | 219 | break; |
a3f7dcc9 XL |
220 | case SND_SOC_DAIFMT_DSP_A: |
221 | /* | |
222 | * Frame high, 1clk before data, one bit for frame sync, | |
223 | * frame sync starts one serial clock cycle earlier, | |
224 | * that is, together with the last bit of the previous | |
225 | * data word. | |
226 | */ | |
ef33bc32 | 227 | val_cr2 |= FSL_SAI_CR2_BCP; |
a3f7dcc9 XL |
228 | val_cr4 |= FSL_SAI_CR4_FSE; |
229 | sai->is_dsp_mode = true; | |
230 | break; | |
231 | case SND_SOC_DAIFMT_DSP_B: | |
232 | /* | |
233 | * Frame high, one bit for frame sync, | |
234 | * frame sync asserts with the first bit of the frame. | |
235 | */ | |
ef33bc32 | 236 | val_cr2 |= FSL_SAI_CR2_BCP; |
a3f7dcc9 XL |
237 | sai->is_dsp_mode = true; |
238 | break; | |
13cde090 XL |
239 | case SND_SOC_DAIFMT_RIGHT_J: |
240 | /* To be done */ | |
43550821 XL |
241 | default: |
242 | return -EINVAL; | |
243 | } | |
244 | ||
13cde090 | 245 | /* DAI clock inversion */ |
43550821 XL |
246 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
247 | case SND_SOC_DAIFMT_IB_IF: | |
13cde090 XL |
248 | /* Invert both clocks */ |
249 | val_cr2 ^= FSL_SAI_CR2_BCP; | |
250 | val_cr4 ^= FSL_SAI_CR4_FSP; | |
43550821 XL |
251 | break; |
252 | case SND_SOC_DAIFMT_IB_NF: | |
13cde090 XL |
253 | /* Invert bit clock */ |
254 | val_cr2 ^= FSL_SAI_CR2_BCP; | |
43550821 XL |
255 | break; |
256 | case SND_SOC_DAIFMT_NB_IF: | |
13cde090 XL |
257 | /* Invert frame clock */ |
258 | val_cr4 ^= FSL_SAI_CR4_FSP; | |
43550821 XL |
259 | break; |
260 | case SND_SOC_DAIFMT_NB_NF: | |
13cde090 | 261 | /* Nothing to do for both normal cases */ |
43550821 XL |
262 | break; |
263 | default: | |
264 | return -EINVAL; | |
265 | } | |
266 | ||
13cde090 | 267 | /* DAI clock master masks */ |
43550821 XL |
268 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
269 | case SND_SOC_DAIFMT_CBS_CFS: | |
270 | val_cr2 |= FSL_SAI_CR2_BCD_MSTR; | |
271 | val_cr4 |= FSL_SAI_CR4_FSD_MSTR; | |
ddb35114 | 272 | sai->is_slave_mode = false; |
43550821 XL |
273 | break; |
274 | case SND_SOC_DAIFMT_CBM_CFM: | |
c3ecef21 | 275 | sai->is_slave_mode = true; |
43550821 | 276 | break; |
13cde090 XL |
277 | case SND_SOC_DAIFMT_CBS_CFM: |
278 | val_cr2 |= FSL_SAI_CR2_BCD_MSTR; | |
ddb35114 | 279 | sai->is_slave_mode = false; |
13cde090 XL |
280 | break; |
281 | case SND_SOC_DAIFMT_CBM_CFS: | |
13cde090 | 282 | val_cr4 |= FSL_SAI_CR4_FSD_MSTR; |
c3ecef21 | 283 | sai->is_slave_mode = true; |
13cde090 | 284 | break; |
43550821 XL |
285 | default: |
286 | return -EINVAL; | |
287 | } | |
288 | ||
2a266f8b NC |
289 | regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx), |
290 | FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2); | |
291 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), | |
292 | FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE | | |
293 | FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4); | |
43550821 XL |
294 | |
295 | return 0; | |
296 | } | |
297 | ||
298 | static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) | |
299 | { | |
4e3a99f5 | 300 | int ret; |
43550821 | 301 | |
43550821 XL |
302 | ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER); |
303 | if (ret) { | |
190af12d | 304 | dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret); |
78957fc3 | 305 | return ret; |
43550821 XL |
306 | } |
307 | ||
308 | ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER); | |
78957fc3 | 309 | if (ret) |
190af12d | 310 | dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret); |
43550821 | 311 | |
1fb2d9d7 | 312 | return ret; |
43550821 XL |
313 | } |
314 | ||
c3ecef21 ZW |
315 | static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq) |
316 | { | |
317 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai); | |
318 | unsigned long clk_rate; | |
319 | u32 savediv = 0, ratio, savesub = freq; | |
320 | u32 id; | |
321 | int ret = 0; | |
322 | ||
323 | /* Don't apply to slave mode */ | |
324 | if (sai->is_slave_mode) | |
325 | return 0; | |
326 | ||
327 | for (id = 0; id < FSL_SAI_MCLK_MAX; id++) { | |
328 | clk_rate = clk_get_rate(sai->mclk_clk[id]); | |
329 | if (!clk_rate) | |
330 | continue; | |
331 | ||
332 | ratio = clk_rate / freq; | |
333 | ||
334 | ret = clk_rate - ratio * freq; | |
335 | ||
336 | /* | |
337 | * Drop the source that can not be | |
338 | * divided into the required rate. | |
339 | */ | |
340 | if (ret != 0 && clk_rate / ret < 1000) | |
341 | continue; | |
342 | ||
343 | dev_dbg(dai->dev, | |
344 | "ratio %d for freq %dHz based on clock %ldHz\n", | |
345 | ratio, freq, clk_rate); | |
346 | ||
347 | if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512) | |
348 | ratio /= 2; | |
349 | else | |
350 | continue; | |
351 | ||
352 | if (ret < savesub) { | |
353 | savediv = ratio; | |
354 | sai->mclk_id[tx] = id; | |
355 | savesub = ret; | |
356 | } | |
357 | ||
358 | if (ret == 0) | |
359 | break; | |
360 | } | |
361 | ||
362 | if (savediv == 0) { | |
363 | dev_err(dai->dev, "failed to derive required %cx rate: %d\n", | |
364 | tx ? 'T' : 'R', freq); | |
365 | return -EINVAL; | |
366 | } | |
367 | ||
9cc58712 ZW |
368 | /* |
369 | * 1) For Asynchronous mode, we must set RCR2 register for capture, and | |
370 | * set TCR2 register for playback. | |
371 | * 2) For Tx sync with Rx clock, we must set RCR2 register for playback | |
372 | * and capture. | |
373 | * 3) For Rx sync with Tx clock, we must set TCR2 register for playback | |
374 | * and capture. | |
375 | * 4) For Tx and Rx are both Synchronous with another SAI, we just | |
376 | * ignore it. | |
377 | */ | |
378 | if ((sai->synchronous[TX] && !sai->synchronous[RX]) || | |
379 | (!tx && !sai->synchronous[RX])) { | |
c3ecef21 ZW |
380 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, |
381 | FSL_SAI_CR2_MSEL_MASK, | |
382 | FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); | |
383 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, | |
384 | FSL_SAI_CR2_DIV_MASK, savediv - 1); | |
9cc58712 ZW |
385 | } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) || |
386 | (tx && !sai->synchronous[TX])) { | |
c3ecef21 ZW |
387 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, |
388 | FSL_SAI_CR2_MSEL_MASK, | |
389 | FSL_SAI_CR2_MSEL(sai->mclk_id[tx])); | |
390 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, | |
391 | FSL_SAI_CR2_DIV_MASK, savediv - 1); | |
392 | } | |
393 | ||
394 | dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n", | |
395 | sai->mclk_id[tx], savediv, savesub); | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
43550821 XL |
400 | static int fsl_sai_hw_params(struct snd_pcm_substream *substream, |
401 | struct snd_pcm_hw_params *params, | |
402 | struct snd_soc_dai *cpu_dai) | |
403 | { | |
4e3a99f5 | 404 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b | 405 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
43550821 | 406 | unsigned int channels = params_channels(params); |
4ca73043 | 407 | u32 word_width = params_width(params); |
2a266f8b | 408 | u32 val_cr4 = 0, val_cr5 = 0; |
c1df2964 ZW |
409 | u32 slots = (channels == 1) ? 2 : channels; |
410 | u32 slot_width = word_width; | |
c3ecef21 ZW |
411 | int ret; |
412 | ||
c1df2964 ZW |
413 | if (sai->slots) |
414 | slots = sai->slots; | |
415 | ||
416 | if (sai->slot_width) | |
417 | slot_width = sai->slot_width; | |
418 | ||
c3ecef21 ZW |
419 | if (!sai->is_slave_mode) { |
420 | ret = fsl_sai_set_bclk(cpu_dai, tx, | |
c1df2964 | 421 | slots * slot_width * params_rate(params)); |
c3ecef21 ZW |
422 | if (ret) |
423 | return ret; | |
424 | ||
425 | /* Do not enable the clock if it is already enabled */ | |
426 | if (!(sai->mclk_streams & BIT(substream->stream))) { | |
427 | ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]); | |
428 | if (ret) | |
429 | return ret; | |
430 | ||
431 | sai->mclk_streams |= BIT(substream->stream); | |
432 | } | |
c3ecef21 | 433 | } |
43550821 | 434 | |
a3f7dcc9 | 435 | if (!sai->is_dsp_mode) |
c1df2964 | 436 | val_cr4 |= FSL_SAI_CR4_SYWD(slot_width); |
a3f7dcc9 | 437 | |
c1df2964 ZW |
438 | val_cr5 |= FSL_SAI_CR5_WNW(slot_width); |
439 | val_cr5 |= FSL_SAI_CR5_W0W(slot_width); | |
43550821 | 440 | |
eadb0019 | 441 | if (sai->is_lsb_first) |
43550821 | 442 | val_cr5 |= FSL_SAI_CR5_FBT(0); |
72aa62be XL |
443 | else |
444 | val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); | |
43550821 | 445 | |
c1df2964 | 446 | val_cr4 |= FSL_SAI_CR4_FRSZ(slots); |
43550821 | 447 | |
51659ca0 ZW |
448 | /* |
449 | * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will | |
450 | * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), | |
451 | * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync | |
452 | * error. | |
453 | */ | |
454 | ||
455 | if (!sai->is_slave_mode) { | |
456 | if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { | |
457 | regmap_update_bits(sai->regmap, FSL_SAI_TCR4, | |
458 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
459 | val_cr4); | |
460 | regmap_update_bits(sai->regmap, FSL_SAI_TCR5, | |
461 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
462 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
463 | regmap_write(sai->regmap, FSL_SAI_TMR, | |
464 | ~0UL - ((1 << channels) - 1)); | |
465 | } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { | |
466 | regmap_update_bits(sai->regmap, FSL_SAI_RCR4, | |
467 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
468 | val_cr4); | |
469 | regmap_update_bits(sai->regmap, FSL_SAI_RCR5, | |
470 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
471 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
472 | regmap_write(sai->regmap, FSL_SAI_RMR, | |
473 | ~0UL - ((1 << channels) - 1)); | |
474 | } | |
475 | } | |
43550821 | 476 | |
2a266f8b NC |
477 | regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), |
478 | FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, | |
479 | val_cr4); | |
480 | regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx), | |
481 | FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | | |
482 | FSL_SAI_CR5_FBT_MASK, val_cr5); | |
483 | regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1)); | |
43550821 XL |
484 | |
485 | return 0; | |
486 | } | |
487 | ||
c3ecef21 ZW |
488 | static int fsl_sai_hw_free(struct snd_pcm_substream *substream, |
489 | struct snd_soc_dai *cpu_dai) | |
490 | { | |
491 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
492 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; | |
493 | ||
494 | if (!sai->is_slave_mode && | |
495 | sai->mclk_streams & BIT(substream->stream)) { | |
496 | clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]); | |
497 | sai->mclk_streams &= ~BIT(substream->stream); | |
498 | } | |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
503 | ||
43550821 XL |
504 | static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd, |
505 | struct snd_soc_dai *cpu_dai) | |
506 | { | |
507 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
e6b39846 | 508 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
c44b56af | 509 | u32 xcsr, count = 100; |
496a39d9 | 510 | |
a3f7dcc9 | 511 | /* |
08fdf65e NC |
512 | * Asynchronous mode: Clear SYNC for both Tx and Rx. |
513 | * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx. | |
514 | * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx. | |
a3f7dcc9 | 515 | */ |
3cc7780b SA |
516 | regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, |
517 | sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0); | |
78957fc3 | 518 | regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC, |
08fdf65e | 519 | sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0); |
43550821 | 520 | |
a3f7dcc9 XL |
521 | /* |
522 | * It is recommended that the transmitter is the last enabled | |
523 | * and the first disabled. | |
524 | */ | |
43550821 XL |
525 | switch (cmd) { |
526 | case SNDRV_PCM_TRIGGER_START: | |
527 | case SNDRV_PCM_TRIGGER_RESUME: | |
528 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
a3fdc674 NC |
529 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
530 | FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE); | |
531 | ||
f4075a8f NC |
532 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, |
533 | FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); | |
534 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, | |
535 | FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE); | |
e5d0fa9c | 536 | |
8abba5d6 NC |
537 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
538 | FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS); | |
43550821 | 539 | break; |
43550821 XL |
540 | case SNDRV_PCM_TRIGGER_STOP: |
541 | case SNDRV_PCM_TRIGGER_SUSPEND: | |
542 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
e6b39846 NC |
543 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
544 | FSL_SAI_CSR_FRDE, 0); | |
8abba5d6 NC |
545 | regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx), |
546 | FSL_SAI_CSR_xIE_MASK, 0); | |
e6b39846 | 547 | |
f84526cf | 548 | /* Check if the opposite FRDE is also disabled */ |
f4075a8f NC |
549 | regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr); |
550 | if (!(xcsr & FSL_SAI_CSR_FRDE)) { | |
eff952b7 | 551 | /* Disable both directions and reset their FIFOs */ |
e6b39846 | 552 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, |
c44b56af | 553 | FSL_SAI_CSR_TERE, 0); |
e6b39846 | 554 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, |
c44b56af NC |
555 | FSL_SAI_CSR_TERE, 0); |
556 | ||
557 | /* TERE will remain set till the end of current frame */ | |
558 | do { | |
559 | udelay(10); | |
560 | regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr); | |
561 | } while (--count && xcsr & FSL_SAI_CSR_TERE); | |
562 | ||
563 | regmap_update_bits(sai->regmap, FSL_SAI_TCSR, | |
564 | FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); | |
565 | regmap_update_bits(sai->regmap, FSL_SAI_RCSR, | |
566 | FSL_SAI_CSR_FR, FSL_SAI_CSR_FR); | |
3e3f8bd5 ZW |
567 | |
568 | /* | |
569 | * For sai master mode, after several open/close sai, | |
570 | * there will be no frame clock, and can't recover | |
571 | * anymore. Add software reset to fix this issue. | |
572 | * This is a hardware bug, and will be fix in the | |
573 | * next sai version. | |
574 | */ | |
575 | if (!sai->is_slave_mode) { | |
576 | /* Software Reset for both Tx and Rx */ | |
577 | regmap_write(sai->regmap, | |
578 | FSL_SAI_TCSR, FSL_SAI_CSR_SR); | |
579 | regmap_write(sai->regmap, | |
580 | FSL_SAI_RCSR, FSL_SAI_CSR_SR); | |
581 | /* Clear SR bit to finish the reset */ | |
582 | regmap_write(sai->regmap, FSL_SAI_TCSR, 0); | |
583 | regmap_write(sai->regmap, FSL_SAI_RCSR, 0); | |
584 | } | |
43550821 | 585 | } |
43550821 XL |
586 | break; |
587 | default: | |
588 | return -EINVAL; | |
589 | } | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
594 | static int fsl_sai_startup(struct snd_pcm_substream *substream, | |
595 | struct snd_soc_dai *cpu_dai) | |
596 | { | |
43550821 | 597 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); |
2a266f8b | 598 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
ca3e35c7 | 599 | struct device *dev = &sai->pdev->dev; |
ca3e35c7 NC |
600 | int ret; |
601 | ||
602 | ret = clk_prepare_enable(sai->bus_clk); | |
603 | if (ret) { | |
604 | dev_err(dev, "failed to enable bus clock: %d\n", ret); | |
605 | return ret; | |
606 | } | |
43550821 | 607 | |
2a266f8b | 608 | regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, |
78957fc3 XL |
609 | FSL_SAI_CR3_TRCE); |
610 | ||
c5f4823b ZW |
611 | ret = snd_pcm_hw_constraint_list(substream->runtime, 0, |
612 | SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints); | |
613 | ||
614 | return ret; | |
43550821 XL |
615 | } |
616 | ||
617 | static void fsl_sai_shutdown(struct snd_pcm_substream *substream, | |
618 | struct snd_soc_dai *cpu_dai) | |
619 | { | |
620 | struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); | |
2a266f8b | 621 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
43550821 | 622 | |
2a266f8b | 623 | regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0); |
ca3e35c7 NC |
624 | |
625 | clk_disable_unprepare(sai->bus_clk); | |
43550821 XL |
626 | } |
627 | ||
628 | static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = { | |
629 | .set_sysclk = fsl_sai_set_dai_sysclk, | |
630 | .set_fmt = fsl_sai_set_dai_fmt, | |
c1df2964 | 631 | .set_tdm_slot = fsl_sai_set_dai_tdm_slot, |
43550821 | 632 | .hw_params = fsl_sai_hw_params, |
c3ecef21 | 633 | .hw_free = fsl_sai_hw_free, |
43550821 XL |
634 | .trigger = fsl_sai_trigger, |
635 | .startup = fsl_sai_startup, | |
636 | .shutdown = fsl_sai_shutdown, | |
637 | }; | |
638 | ||
639 | static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai) | |
640 | { | |
641 | struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev); | |
e6dc12d7 | 642 | |
376d1a92 NC |
643 | /* Software Reset for both Tx and Rx */ |
644 | regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); | |
645 | regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); | |
646 | /* Clear SR bit to finish the reset */ | |
647 | regmap_write(sai->regmap, FSL_SAI_TCSR, 0); | |
648 | regmap_write(sai->regmap, FSL_SAI_RCSR, 0); | |
649 | ||
78957fc3 XL |
650 | regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK, |
651 | FSL_SAI_MAXBURST_TX * 2); | |
652 | regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK, | |
653 | FSL_SAI_MAXBURST_RX - 1); | |
43550821 | 654 | |
dd9f4060 XL |
655 | snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx, |
656 | &sai->dma_params_rx); | |
43550821 XL |
657 | |
658 | snd_soc_dai_set_drvdata(cpu_dai, sai); | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
43550821 XL |
663 | static struct snd_soc_dai_driver fsl_sai_dai = { |
664 | .probe = fsl_sai_dai_probe, | |
43550821 | 665 | .playback = { |
20d5b76f | 666 | .stream_name = "CPU-Playback", |
43550821 | 667 | .channels_min = 1, |
4957b556 | 668 | .channels_max = 32, |
c5f4823b ZW |
669 | .rate_min = 8000, |
670 | .rate_max = 192000, | |
671 | .rates = SNDRV_PCM_RATE_KNOT, | |
43550821 XL |
672 | .formats = FSL_SAI_FORMATS, |
673 | }, | |
674 | .capture = { | |
20d5b76f | 675 | .stream_name = "CPU-Capture", |
43550821 | 676 | .channels_min = 1, |
4957b556 | 677 | .channels_max = 32, |
c5f4823b ZW |
678 | .rate_min = 8000, |
679 | .rate_max = 192000, | |
680 | .rates = SNDRV_PCM_RATE_KNOT, | |
43550821 XL |
681 | .formats = FSL_SAI_FORMATS, |
682 | }, | |
683 | .ops = &fsl_sai_pcm_dai_ops, | |
684 | }; | |
685 | ||
686 | static const struct snd_soc_component_driver fsl_component = { | |
687 | .name = "fsl-sai", | |
688 | }; | |
689 | ||
3f6f5b0c ZW |
690 | static struct reg_default fsl_sai_reg_defaults[] = { |
691 | {FSL_SAI_TCR1, 0}, | |
692 | {FSL_SAI_TCR2, 0}, | |
693 | {FSL_SAI_TCR3, 0}, | |
694 | {FSL_SAI_TCR4, 0}, | |
695 | {FSL_SAI_TCR5, 0}, | |
696 | {FSL_SAI_TDR, 0}, | |
697 | {FSL_SAI_TMR, 0}, | |
698 | {FSL_SAI_RCR1, 0}, | |
699 | {FSL_SAI_RCR2, 0}, | |
700 | {FSL_SAI_RCR3, 0}, | |
701 | {FSL_SAI_RCR4, 0}, | |
702 | {FSL_SAI_RCR5, 0}, | |
703 | {FSL_SAI_RMR, 0}, | |
704 | }; | |
705 | ||
78957fc3 XL |
706 | static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) |
707 | { | |
708 | switch (reg) { | |
709 | case FSL_SAI_TCSR: | |
710 | case FSL_SAI_TCR1: | |
711 | case FSL_SAI_TCR2: | |
712 | case FSL_SAI_TCR3: | |
713 | case FSL_SAI_TCR4: | |
714 | case FSL_SAI_TCR5: | |
715 | case FSL_SAI_TFR: | |
716 | case FSL_SAI_TMR: | |
717 | case FSL_SAI_RCSR: | |
718 | case FSL_SAI_RCR1: | |
719 | case FSL_SAI_RCR2: | |
720 | case FSL_SAI_RCR3: | |
721 | case FSL_SAI_RCR4: | |
722 | case FSL_SAI_RCR5: | |
723 | case FSL_SAI_RDR: | |
724 | case FSL_SAI_RFR: | |
725 | case FSL_SAI_RMR: | |
726 | return true; | |
727 | default: | |
728 | return false; | |
729 | } | |
730 | } | |
731 | ||
732 | static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg) | |
733 | { | |
734 | switch (reg) { | |
1fde5e83 ZW |
735 | case FSL_SAI_TCSR: |
736 | case FSL_SAI_RCSR: | |
78957fc3 XL |
737 | case FSL_SAI_TFR: |
738 | case FSL_SAI_RFR: | |
78957fc3 XL |
739 | case FSL_SAI_RDR: |
740 | return true; | |
741 | default: | |
742 | return false; | |
743 | } | |
78957fc3 XL |
744 | } |
745 | ||
746 | static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg) | |
747 | { | |
748 | switch (reg) { | |
749 | case FSL_SAI_TCSR: | |
750 | case FSL_SAI_TCR1: | |
751 | case FSL_SAI_TCR2: | |
752 | case FSL_SAI_TCR3: | |
753 | case FSL_SAI_TCR4: | |
754 | case FSL_SAI_TCR5: | |
755 | case FSL_SAI_TDR: | |
756 | case FSL_SAI_TMR: | |
757 | case FSL_SAI_RCSR: | |
758 | case FSL_SAI_RCR1: | |
759 | case FSL_SAI_RCR2: | |
760 | case FSL_SAI_RCR3: | |
761 | case FSL_SAI_RCR4: | |
762 | case FSL_SAI_RCR5: | |
763 | case FSL_SAI_RMR: | |
764 | return true; | |
765 | default: | |
766 | return false; | |
767 | } | |
768 | } | |
769 | ||
014fd22e | 770 | static const struct regmap_config fsl_sai_regmap_config = { |
78957fc3 XL |
771 | .reg_bits = 32, |
772 | .reg_stride = 4, | |
773 | .val_bits = 32, | |
774 | ||
775 | .max_register = FSL_SAI_RMR, | |
3f6f5b0c ZW |
776 | .reg_defaults = fsl_sai_reg_defaults, |
777 | .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults), | |
78957fc3 XL |
778 | .readable_reg = fsl_sai_readable_reg, |
779 | .volatile_reg = fsl_sai_volatile_reg, | |
780 | .writeable_reg = fsl_sai_writeable_reg, | |
1fde5e83 | 781 | .cache_type = REGCACHE_FLAT, |
78957fc3 XL |
782 | }; |
783 | ||
43550821 XL |
784 | static int fsl_sai_probe(struct platform_device *pdev) |
785 | { | |
4e3a99f5 | 786 | struct device_node *np = pdev->dev.of_node; |
43550821 | 787 | struct fsl_sai *sai; |
4d245850 | 788 | struct regmap *gpr; |
43550821 | 789 | struct resource *res; |
78957fc3 | 790 | void __iomem *base; |
ca3e35c7 NC |
791 | char tmp[8]; |
792 | int irq, ret, i; | |
4d245850 | 793 | int index; |
43550821 XL |
794 | |
795 | sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); | |
796 | if (!sai) | |
797 | return -ENOMEM; | |
798 | ||
e2681a1b NC |
799 | sai->pdev = pdev; |
800 | ||
6ea9c7dd FE |
801 | if (of_device_is_compatible(np, "fsl,imx6sx-sai") || |
802 | of_device_is_compatible(np, "fsl,imx6ul-sai")) | |
c7540644 NC |
803 | sai->sai_on_imx = true; |
804 | ||
eadb0019 | 805 | sai->is_lsb_first = of_property_read_bool(np, "lsb-first"); |
78957fc3 | 806 | |
43550821 | 807 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
78957fc3 XL |
808 | base = devm_ioremap_resource(&pdev->dev, res); |
809 | if (IS_ERR(base)) | |
810 | return PTR_ERR(base); | |
811 | ||
812 | sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, | |
ca3e35c7 NC |
813 | "bus", base, &fsl_sai_regmap_config); |
814 | ||
815 | /* Compatible with old DTB cases */ | |
816 | if (IS_ERR(sai->regmap)) | |
817 | sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev, | |
818 | "sai", base, &fsl_sai_regmap_config); | |
78957fc3 XL |
819 | if (IS_ERR(sai->regmap)) { |
820 | dev_err(&pdev->dev, "regmap init failed\n"); | |
821 | return PTR_ERR(sai->regmap); | |
43550821 XL |
822 | } |
823 | ||
ca3e35c7 NC |
824 | /* No error out for old DTB cases but only mark the clock NULL */ |
825 | sai->bus_clk = devm_clk_get(&pdev->dev, "bus"); | |
826 | if (IS_ERR(sai->bus_clk)) { | |
827 | dev_err(&pdev->dev, "failed to get bus clock: %ld\n", | |
828 | PTR_ERR(sai->bus_clk)); | |
829 | sai->bus_clk = NULL; | |
830 | } | |
831 | ||
c3ecef21 ZW |
832 | sai->mclk_clk[0] = sai->bus_clk; |
833 | for (i = 1; i < FSL_SAI_MCLK_MAX; i++) { | |
834 | sprintf(tmp, "mclk%d", i); | |
ca3e35c7 NC |
835 | sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp); |
836 | if (IS_ERR(sai->mclk_clk[i])) { | |
837 | dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n", | |
838 | i + 1, PTR_ERR(sai->mclk_clk[i])); | |
839 | sai->mclk_clk[i] = NULL; | |
840 | } | |
841 | } | |
842 | ||
e2681a1b NC |
843 | irq = platform_get_irq(pdev, 0); |
844 | if (irq < 0) { | |
0954237f | 845 | dev_err(&pdev->dev, "no irq for node %s\n", pdev->name); |
e2681a1b NC |
846 | return irq; |
847 | } | |
848 | ||
849 | ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai); | |
850 | if (ret) { | |
851 | dev_err(&pdev->dev, "failed to claim irq %u\n", irq); | |
852 | return ret; | |
853 | } | |
854 | ||
08fdf65e NC |
855 | /* Sync Tx with Rx as default by following old DT binding */ |
856 | sai->synchronous[RX] = true; | |
857 | sai->synchronous[TX] = false; | |
858 | fsl_sai_dai.symmetric_rates = 1; | |
859 | fsl_sai_dai.symmetric_channels = 1; | |
860 | fsl_sai_dai.symmetric_samplebits = 1; | |
861 | ||
ce7344a4 NC |
862 | if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) && |
863 | of_find_property(np, "fsl,sai-asynchronous", NULL)) { | |
864 | /* error out if both synchronous and asynchronous are present */ | |
865 | dev_err(&pdev->dev, "invalid binding for synchronous mode\n"); | |
866 | return -EINVAL; | |
867 | } | |
868 | ||
08fdf65e NC |
869 | if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) { |
870 | /* Sync Rx with Tx */ | |
871 | sai->synchronous[RX] = false; | |
872 | sai->synchronous[TX] = true; | |
873 | } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) { | |
874 | /* Discard all settings for asynchronous mode */ | |
875 | sai->synchronous[RX] = false; | |
876 | sai->synchronous[TX] = false; | |
877 | fsl_sai_dai.symmetric_rates = 0; | |
878 | fsl_sai_dai.symmetric_channels = 0; | |
879 | fsl_sai_dai.symmetric_samplebits = 0; | |
880 | } | |
881 | ||
4d245850 | 882 | if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) && |
6ea9c7dd | 883 | of_device_is_compatible(np, "fsl,imx6ul-sai")) { |
4d245850 FE |
884 | gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr"); |
885 | if (IS_ERR(gpr)) { | |
886 | dev_err(&pdev->dev, "cannot find iomuxc registers\n"); | |
887 | return PTR_ERR(gpr); | |
888 | } | |
889 | ||
890 | index = of_alias_get_id(np, "sai"); | |
891 | if (index < 0) | |
892 | return index; | |
893 | ||
894 | regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index), | |
895 | MCLK_DIR(index)); | |
896 | } | |
897 | ||
43550821 XL |
898 | sai->dma_params_rx.addr = res->start + FSL_SAI_RDR; |
899 | sai->dma_params_tx.addr = res->start + FSL_SAI_TDR; | |
900 | sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX; | |
901 | sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX; | |
902 | ||
43550821 XL |
903 | platform_set_drvdata(pdev, sai); |
904 | ||
812ad463 DB |
905 | pm_runtime_enable(&pdev->dev); |
906 | ||
43550821 XL |
907 | ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component, |
908 | &fsl_sai_dai, 1); | |
909 | if (ret) | |
910 | return ret; | |
911 | ||
c7540644 | 912 | if (sai->sai_on_imx) |
0d69e0dd | 913 | return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE); |
c7540644 | 914 | else |
acde50a7 | 915 | return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); |
43550821 XL |
916 | } |
917 | ||
812ad463 DB |
918 | static int fsl_sai_remove(struct platform_device *pdev) |
919 | { | |
920 | pm_runtime_disable(&pdev->dev); | |
b46ea8f4 NC |
921 | |
922 | return 0; | |
812ad463 DB |
923 | } |
924 | ||
43550821 XL |
925 | static const struct of_device_id fsl_sai_ids[] = { |
926 | { .compatible = "fsl,vf610-sai", }, | |
c7540644 | 927 | { .compatible = "fsl,imx6sx-sai", }, |
1593af62 | 928 | { .compatible = "fsl,imx6ul-sai", }, |
43550821 XL |
929 | { /* sentinel */ } |
930 | }; | |
c759241f | 931 | MODULE_DEVICE_TABLE(of, fsl_sai_ids); |
43550821 | 932 | |
812ad463 DB |
933 | #ifdef CONFIG_PM |
934 | static int fsl_sai_runtime_suspend(struct device *dev) | |
1fde5e83 ZW |
935 | { |
936 | struct fsl_sai *sai = dev_get_drvdata(dev); | |
937 | ||
938 | regcache_cache_only(sai->regmap, true); | |
939 | regcache_mark_dirty(sai->regmap); | |
940 | ||
941 | return 0; | |
942 | } | |
943 | ||
812ad463 | 944 | static int fsl_sai_runtime_resume(struct device *dev) |
1fde5e83 ZW |
945 | { |
946 | struct fsl_sai *sai = dev_get_drvdata(dev); | |
947 | ||
948 | regcache_cache_only(sai->regmap, false); | |
949 | regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR); | |
950 | regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR); | |
512feb4e | 951 | usleep_range(1000, 2000); |
1fde5e83 ZW |
952 | regmap_write(sai->regmap, FSL_SAI_TCSR, 0); |
953 | regmap_write(sai->regmap, FSL_SAI_RCSR, 0); | |
954 | return regcache_sync(sai->regmap); | |
955 | } | |
812ad463 | 956 | #endif /* CONFIG_PM */ |
1fde5e83 ZW |
957 | |
958 | static const struct dev_pm_ops fsl_sai_pm_ops = { | |
812ad463 DB |
959 | SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend, |
960 | fsl_sai_runtime_resume, NULL) | |
961 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, | |
962 | pm_runtime_force_resume) | |
1fde5e83 ZW |
963 | }; |
964 | ||
43550821 XL |
965 | static struct platform_driver fsl_sai_driver = { |
966 | .probe = fsl_sai_probe, | |
812ad463 | 967 | .remove = fsl_sai_remove, |
43550821 XL |
968 | .driver = { |
969 | .name = "fsl-sai", | |
1fde5e83 | 970 | .pm = &fsl_sai_pm_ops, |
43550821 XL |
971 | .of_match_table = fsl_sai_ids, |
972 | }, | |
973 | }; | |
974 | module_platform_driver(fsl_sai_driver); | |
975 | ||
976 | MODULE_DESCRIPTION("Freescale Soc SAI Interface"); | |
977 | MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>"); | |
978 | MODULE_ALIAS("platform:fsl-sai"); | |
979 | MODULE_LICENSE("GPL"); |