[linux-2.6-block.git] / sound / soc / fsl / fsl_asrc.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * fsl_asrc.h - Freescale ASRC ALSA SoC header file
 *
 * Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * Author: Nicolin Chen <nicoleotsuka@gmail.com>
 */

#ifndef _FSL_ASRC_H
#define _FSL_ASRC_H

#define IN	0
#define OUT	1

#define ASRC_DMA_BUFFER_NUM		2
#define ASRC_INPUTFIFO_THRESHOLD	32
#define ASRC_OUTPUTFIFO_THRESHOLD	32
#define ASRC_FIFO_THRESHOLD_MIN		0
#define ASRC_FIFO_THRESHOLD_MAX		63
#define ASRC_DMA_BUFFER_SIZE		(1024 * 48 * 4)
#define ASRC_MAX_BUFFER_SIZE		(1024 * 48)
#define ASRC_OUTPUT_LAST_SAMPLE		8

#define IDEAL_RATIO_RATE		1000000

#define REG_ASRCTR			0x00
#define REG_ASRIER			0x04
#define REG_ASRCNCR			0x0C
#define REG_ASRCFG			0x10
#define REG_ASRCSR			0x14

#define REG_ASRCDR1			0x18
#define REG_ASRCDR2			0x1C
#define REG_ASRCDR(i)			((i < 2) ? REG_ASRCDR1 : REG_ASRCDR2)

#define REG_ASRSTR			0x20
#define REG_ASRRA			0x24
#define REG_ASRRB			0x28
#define REG_ASRRC			0x2C
#define REG_ASRPM1			0x40
#define REG_ASRPM2			0x44
#define REG_ASRPM3			0x48
#define REG_ASRPM4			0x4C
#define REG_ASRPM5			0x50
#define REG_ASRTFR1			0x54
#define REG_ASRCCR			0x5C

#define REG_ASRDIA			0x60
#define REG_ASRDOA			0x64
#define REG_ASRDIB			0x68
#define REG_ASRDOB			0x6C
#define REG_ASRDIC			0x70
#define REG_ASRDOC			0x74
#define REG_ASRDI(i)			(REG_ASRDIA + (i << 3))
#define REG_ASRDO(i)			(REG_ASRDOA + (i << 3))
#define REG_ASRDx(x, i)			((x) == IN ? REG_ASRDI(i) : REG_ASRDO(i))

#define REG_ASRIDRHA			0x80
#define REG_ASRIDRLA			0x84
#define REG_ASRIDRHB			0x88
#define REG_ASRIDRLB			0x8C
#define REG_ASRIDRHC			0x90
#define REG_ASRIDRLC			0x94
#define REG_ASRIDRH(i)			(REG_ASRIDRHA + (i << 3))
#define REG_ASRIDRL(i)			(REG_ASRIDRLA + (i << 3))

#define REG_ASR76K			0x98
#define REG_ASR56K			0x9C

#define REG_ASRMCRA			0xA0
#define REG_ASRFSTA			0xA4
#define REG_ASRMCRB			0xA8
#define REG_ASRFSTB			0xAC
#define REG_ASRMCRC			0xB0
#define REG_ASRFSTC			0xB4
#define REG_ASRMCR(i)			(REG_ASRMCRA + (i << 3))
#define REG_ASRFST(i)			(REG_ASRFSTA + (i << 3))

#define REG_ASRMCR1A			0xC0
#define REG_ASRMCR1B			0xC4
#define REG_ASRMCR1C			0xC8
#define REG_ASRMCR1(i)			(REG_ASRMCR1A + (i << 2))


/* REG0 0x00 REG_ASRCTR */
#define ASRCTR_ATSi_SHIFT(i)		(20 + i)
#define ASRCTR_ATSi_MASK(i)		(1 << ASRCTR_ATSi_SHIFT(i))
#define ASRCTR_ATS(i)			(1 << ASRCTR_ATSi_SHIFT(i))
#define ASRCTR_USRi_SHIFT(i)		(14 + (i << 1))
#define ASRCTR_USRi_MASK(i)		(1 << ASRCTR_USRi_SHIFT(i))
#define ASRCTR_USR(i)			(1 << ASRCTR_USRi_SHIFT(i))
#define ASRCTR_IDRi_SHIFT(i)		(13 + (i << 1))
#define ASRCTR_IDRi_MASK(i)		(1 << ASRCTR_IDRi_SHIFT(i))
#define ASRCTR_IDR(i)			(1 << ASRCTR_IDRi_SHIFT(i))
#define ASRCTR_SRST_SHIFT		4
#define ASRCTR_SRST_MASK		(1 << ASRCTR_SRST_SHIFT)
#define ASRCTR_SRST			(1 << ASRCTR_SRST_SHIFT)
#define ASRCTR_ASRCEi_SHIFT(i)		(1 + i)
#define ASRCTR_ASRCEi_MASK(i)		(1 << ASRCTR_ASRCEi_SHIFT(i))
#define ASRCTR_ASRCE(i)			(1 << ASRCTR_ASRCEi_SHIFT(i))
#define ASRCTR_ASRCEi_ALL_MASK		(0x7 << ASRCTR_ASRCEi_SHIFT(0))
#define ASRCTR_ASRCEN_SHIFT		0
#define ASRCTR_ASRCEN_MASK		(1 << ASRCTR_ASRCEN_SHIFT)
#define ASRCTR_ASRCEN			(1 << ASRCTR_ASRCEN_SHIFT)

/* REG1 0x04 REG_ASRIER */
#define ASRIER_AFPWE_SHIFT		7
#define ASRIER_AFPWE_MASK		(1 << ASRIER_AFPWE_SHIFT)
#define ASRIER_AFPWE			(1 << ASRIER_AFPWE_SHIFT)
#define ASRIER_AOLIE_SHIFT		6
#define ASRIER_AOLIE_MASK		(1 << ASRIER_AOLIE_SHIFT)
#define ASRIER_AOLIE			(1 << ASRIER_AOLIE_SHIFT)
#define ASRIER_ADOEi_SHIFT(i)		(3 + i)
#define ASRIER_ADOEi_MASK(i)		(1 << ASRIER_ADOEi_SHIFT(i))
#define ASRIER_ADOE(i)			(1 << ASRIER_ADOEi_SHIFT(i))
#define ASRIER_ADIEi_SHIFT(i)		(0 + i)
#define ASRIER_ADIEi_MASK(i)		(1 << ASRIER_ADIEi_SHIFT(i))
#define ASRIER_ADIE(i)			(1 << ASRIER_ADIEi_SHIFT(i))

/* REG2 0x0C REG_ASRCNCR */
#define ASRCNCR_ANCi_SHIFT(i, b)	(b * i)
#define ASRCNCR_ANCi_MASK(i, b)		(((1 << b) - 1) << ASRCNCR_ANCi_SHIFT(i, b))
#define ASRCNCR_ANCi(i, v, b)		((v << ASRCNCR_ANCi_SHIFT(i, b)) & ASRCNCR_ANCi_MASK(i, b))

/* REG3 0x10 REG_ASRCFG */
#define ASRCFG_INIRQi_SHIFT(i)		(21 + i)
#define ASRCFG_INIRQi_MASK(i)		(1 << ASRCFG_INIRQi_SHIFT(i))
#define ASRCFG_INIRQi			(1 << ASRCFG_INIRQi_SHIFT(i))
#define ASRCFG_NDPRi_SHIFT(i)		(18 + i)
#define ASRCFG_NDPRi_MASK(i)		(1 << ASRCFG_NDPRi_SHIFT(i))
#define ASRCFG_NDPRi_ALL_SHIFT		18
#define ASRCFG_NDPRi_ALL_MASK		(7 << ASRCFG_NDPRi_ALL_SHIFT)
#define ASRCFG_NDPRi			(1 << ASRCFG_NDPRi_SHIFT(i))
#define ASRCFG_POSTMODi_SHIFT(i)	(8 + (i << 2))
#define ASRCFG_POSTMODi_WIDTH		2
#define ASRCFG_POSTMODi_MASK(i)		(((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
#define ASRCFG_POSTMODi_ALL_MASK	(ASRCFG_POSTMODi_MASK(0) | ASRCFG_POSTMODi_MASK(1) | ASRCFG_POSTMODi_MASK(2))
#define ASRCFG_POSTMOD(i, v)		((v) << ASRCFG_POSTMODi_SHIFT(i))
#define ASRCFG_POSTMODi_UP(i)		(0 << ASRCFG_POSTMODi_SHIFT(i))
#define ASRCFG_POSTMODi_DCON(i)		(1 << ASRCFG_POSTMODi_SHIFT(i))
#define ASRCFG_POSTMODi_DOWN(i)		(2 << ASRCFG_POSTMODi_SHIFT(i))
#define ASRCFG_PREMODi_SHIFT(i)		(6 + (i << 2))
#define ASRCFG_PREMODi_WIDTH		2
#define ASRCFG_PREMODi_MASK(i)		(((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
#define ASRCFG_PREMODi_ALL_MASK		(ASRCFG_PREMODi_MASK(0) | ASRCFG_PREMODi_MASK(1) | ASRCFG_PREMODi_MASK(2))
#define ASRCFG_PREMOD(i, v)		((v) << ASRCFG_PREMODi_SHIFT(i))
#define ASRCFG_PREMODi_UP(i)		(0 << ASRCFG_PREMODi_SHIFT(i))
#define ASRCFG_PREMODi_DCON(i)		(1 << ASRCFG_PREMODi_SHIFT(i))
#define ASRCFG_PREMODi_DOWN(i)		(2 << ASRCFG_PREMODi_SHIFT(i))
#define ASRCFG_PREMODi_BYPASS(i)	(3 << ASRCFG_PREMODi_SHIFT(i))

/* REG4 0x14 REG_ASRCSR */
#define ASRCSR_AxCSi_WIDTH		4
#define ASRCSR_AxCSi_MASK		((1 << ASRCSR_AxCSi_WIDTH) - 1)
#define ASRCSR_AOCSi_SHIFT(i)		(12 + (i << 2))
#define ASRCSR_AOCSi_MASK(i)		(((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AOCSi_SHIFT(i))
#define ASRCSR_AOCS(i, v)		((v) << ASRCSR_AOCSi_SHIFT(i))
#define ASRCSR_AICSi_SHIFT(i)		(i << 2)
#define ASRCSR_AICSi_MASK(i)		(((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AICSi_SHIFT(i))
#define ASRCSR_AICS(i, v)		((v) << ASRCSR_AICSi_SHIFT(i))

/* REG5&6 0x18 & 0x1C REG_ASRCDR1 & ASRCDR2 */
#define ASRCDRi_AxCPi_WIDTH		3
#define ASRCDRi_AICPi_SHIFT(i)		(0 + (i % 2) * 6)
#define ASRCDRi_AICPi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICPi_SHIFT(i))
#define ASRCDRi_AICP(i, v)		((v) << ASRCDRi_AICPi_SHIFT(i))
#define ASRCDRi_AICDi_SHIFT(i)		(3 + (i % 2) * 6)
#define ASRCDRi_AICDi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICDi_SHIFT(i))
#define ASRCDRi_AICD(i, v)		((v) << ASRCDRi_AICDi_SHIFT(i))
#define ASRCDRi_AOCPi_SHIFT(i)		((i < 2) ? 12 + i * 6 : 6)
#define ASRCDRi_AOCPi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCPi_SHIFT(i))
#define ASRCDRi_AOCP(i, v)		((v) << ASRCDRi_AOCPi_SHIFT(i))
#define ASRCDRi_AOCDi_SHIFT(i)		((i < 2) ? 15 + i * 6 : 9)
#define ASRCDRi_AOCDi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCDi_SHIFT(i))
#define ASRCDRi_AOCD(i, v)		((v) << ASRCDRi_AOCDi_SHIFT(i))

/* REG7 0x20 REG_ASRSTR */
#define ASRSTR_DSLCNT_SHIFT		21
#define ASRSTR_DSLCNT_MASK		(1 << ASRSTR_DSLCNT_SHIFT)
#define ASRSTR_DSLCNT			(1 << ASRSTR_DSLCNT_SHIFT)
#define ASRSTR_ATQOL_SHIFT		20
#define ASRSTR_ATQOL_MASK		(1 << ASRSTR_ATQOL_SHIFT)
#define ASRSTR_ATQOL			(1 << ASRSTR_ATQOL_SHIFT)
#define ASRSTR_AOOLi_SHIFT(i)		(17 + i)
#define ASRSTR_AOOLi_MASK(i)		(1 << ASRSTR_AOOLi_SHIFT(i))
#define ASRSTR_AOOL(i)			(1 << ASRSTR_AOOLi_SHIFT(i))
#define ASRSTR_AIOLi_SHIFT(i)		(14 + i)
#define ASRSTR_AIOLi_MASK(i)		(1 << ASRSTR_AIOLi_SHIFT(i))
#define ASRSTR_AIOL(i)			(1 << ASRSTR_AIOLi_SHIFT(i))
#define ASRSTR_AODOi_SHIFT(i)		(11 + i)
#define ASRSTR_AODOi_MASK(i)		(1 << ASRSTR_AODOi_SHIFT(i))
#define ASRSTR_AODO(i)			(1 << ASRSTR_AODOi_SHIFT(i))
#define ASRSTR_AIDUi_SHIFT(i)		(8 + i)
#define ASRSTR_AIDUi_MASK(i)		(1 << ASRSTR_AIDUi_SHIFT(i))
#define ASRSTR_AIDU(i)			(1 << ASRSTR_AIDUi_SHIFT(i))
#define ASRSTR_FPWT_SHIFT		7
#define ASRSTR_FPWT_MASK		(1 << ASRSTR_FPWT_SHIFT)
#define ASRSTR_FPWT			(1 << ASRSTR_FPWT_SHIFT)
#define ASRSTR_AOLE_SHIFT		6
#define ASRSTR_AOLE_MASK		(1 << ASRSTR_AOLE_SHIFT)
#define ASRSTR_AOLE			(1 << ASRSTR_AOLE_SHIFT)
#define ASRSTR_AODEi_SHIFT(i)		(3 + i)
#define ASRSTR_AODFi_MASK(i)		(1 << ASRSTR_AODEi_SHIFT(i))
#define ASRSTR_AODF(i)			(1 << ASRSTR_AODEi_SHIFT(i))
#define ASRSTR_AIDEi_SHIFT(i)		(0 + i)
#define ASRSTR_AIDEi_MASK(i)		(1 << ASRSTR_AIDEi_SHIFT(i))
#define ASRSTR_AIDE(i)			(1 << ASRSTR_AIDEi_SHIFT(i))

/* REG10 0x54 REG_ASRTFR1 */
#define ASRTFR1_TF_BASE_WIDTH		7
#define ASRTFR1_TF_BASE_SHIFT		6
#define ASRTFR1_TF_BASE_MASK		(((1 << ASRTFR1_TF_BASE_WIDTH) - 1) << ASRTFR1_TF_BASE_SHIFT)
#define ASRTFR1_TF_BASE(i)		((i) << ASRTFR1_TF_BASE_SHIFT)

/*
 * REG22 0xA0 REG_ASRMCRA
 * REG24 0xA8 REG_ASRMCRB
 * REG26 0xB0 REG_ASRMCRC
 */
#define ASRMCRi_ZEROBUFi_SHIFT		23
#define ASRMCRi_ZEROBUFi_MASK		(1 << ASRMCRi_ZEROBUFi_SHIFT)
#define ASRMCRi_ZEROBUFi		(1 << ASRMCRi_ZEROBUFi_SHIFT)
#define ASRMCRi_EXTTHRSHi_SHIFT		22
#define ASRMCRi_EXTTHRSHi_MASK		(1 << ASRMCRi_EXTTHRSHi_SHIFT)
#define ASRMCRi_EXTTHRSHi		(1 << ASRMCRi_EXTTHRSHi_SHIFT)
#define ASRMCRi_BUFSTALLi_SHIFT		21
#define ASRMCRi_BUFSTALLi_MASK		(1 << ASRMCRi_BUFSTALLi_SHIFT)
#define ASRMCRi_BUFSTALLi		(1 << ASRMCRi_BUFSTALLi_SHIFT)
#define ASRMCRi_BYPASSPOLYi_SHIFT	20
#define ASRMCRi_BYPASSPOLYi_MASK	(1 << ASRMCRi_BYPASSPOLYi_SHIFT)
#define ASRMCRi_BYPASSPOLYi		(1 << ASRMCRi_BYPASSPOLYi_SHIFT)
#define ASRMCRi_OUTFIFO_THRESHOLD_WIDTH	6
#define ASRMCRi_OUTFIFO_THRESHOLD_SHIFT	12
#define ASRMCRi_OUTFIFO_THRESHOLD_MASK	(((1 << ASRMCRi_OUTFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT)
#define ASRMCRi_OUTFIFO_THRESHOLD(v)	(((v) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRi_OUTFIFO_THRESHOLD_MASK)
#define ASRMCRi_RSYNIFi_SHIFT		11
#define ASRMCRi_RSYNIFi_MASK		(1 << ASRMCRi_RSYNIFi_SHIFT)
#define ASRMCRi_RSYNIFi			(1 << ASRMCRi_RSYNIFi_SHIFT)
#define ASRMCRi_RSYNOFi_SHIFT		10
#define ASRMCRi_RSYNOFi_MASK		(1 << ASRMCRi_RSYNOFi_SHIFT)
#define ASRMCRi_RSYNOFi			(1 << ASRMCRi_RSYNOFi_SHIFT)
#define ASRMCRi_INFIFO_THRESHOLD_WIDTH	6
#define ASRMCRi_INFIFO_THRESHOLD_SHIFT	0
#define ASRMCRi_INFIFO_THRESHOLD_MASK	(((1 << ASRMCRi_INFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_INFIFO_THRESHOLD_SHIFT)
#define ASRMCRi_INFIFO_THRESHOLD(v)	(((v) << ASRMCRi_INFIFO_THRESHOLD_SHIFT) & ASRMCRi_INFIFO_THRESHOLD_MASK)

/*
 * REG23 0xA4 REG_ASRFSTA
 * REG25 0xAC REG_ASRFSTB
 * REG27 0xB4 REG_ASRFSTC
 */
#define ASRFSTi_OAFi_SHIFT		23
#define ASRFSTi_OAFi_MASK		(1 << ASRFSTi_OAFi_SHIFT)
#define ASRFSTi_OAFi			(1 << ASRFSTi_OAFi_SHIFT)
#define ASRFSTi_OUTPUT_FIFO_WIDTH	7
#define ASRFSTi_OUTPUT_FIFO_SHIFT	12
#define ASRFSTi_OUTPUT_FIFO_MASK	(((1 << ASRFSTi_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTi_OUTPUT_FIFO_SHIFT)
#define ASRFSTi_IAEi_SHIFT		11
#define ASRFSTi_IAEi_MASK		(1 << ASRFSTi_IAEi_SHIFT)
#define ASRFSTi_IAEi			(1 << ASRFSTi_IAEi_SHIFT)
#define ASRFSTi_INPUT_FIFO_WIDTH	7
#define ASRFSTi_INPUT_FIFO_SHIFT	0
#define ASRFSTi_INPUT_FIFO_MASK		((1 << ASRFSTi_INPUT_FIFO_WIDTH) - 1)

/* REG28 0xC0 & 0xC4 & 0xC8 REG_ASRMCR1i */
#define ASRMCR1i_IWD_WIDTH		3
#define ASRMCR1i_IWD_SHIFT		9
#define ASRMCR1i_IWD_MASK		(((1 << ASRMCR1i_IWD_WIDTH) - 1) << ASRMCR1i_IWD_SHIFT)
#define ASRMCR1i_IWD(v)			((v) << ASRMCR1i_IWD_SHIFT)
#define ASRMCR1i_IMSB_SHIFT		8
#define ASRMCR1i_IMSB_MASK		(1 << ASRMCR1i_IMSB_SHIFT)
#define ASRMCR1i_IMSB_MSB		(1 << ASRMCR1i_IMSB_SHIFT)
#define ASRMCR1i_IMSB_LSB		(0 << ASRMCR1i_IMSB_SHIFT)
#define ASRMCR1i_OMSB_SHIFT		2
#define ASRMCR1i_OMSB_MASK		(1 << ASRMCR1i_OMSB_SHIFT)
#define ASRMCR1i_OMSB_MSB		(1 << ASRMCR1i_OMSB_SHIFT)
#define ASRMCR1i_OMSB_LSB		(0 << ASRMCR1i_OMSB_SHIFT)
#define ASRMCR1i_OSGN_SHIFT		1
#define ASRMCR1i_OSGN_MASK		(1 << ASRMCR1i_OSGN_SHIFT)
#define ASRMCR1i_OSGN			(1 << ASRMCR1i_OSGN_SHIFT)
#define ASRMCR1i_OW16_SHIFT		0
#define ASRMCR1i_OW16_MASK		(1 << ASRMCR1i_OW16_SHIFT)
#define ASRMCR1i_OW16(v)		((v) << ASRMCR1i_OW16_SHIFT)


enum asrc_pair_index {
	ASRC_INVALID_PAIR = -1,
	ASRC_PAIR_A = 0,
	ASRC_PAIR_B = 1,
	ASRC_PAIR_C = 2,
};

#define ASRC_PAIR_MAX_NUM	(ASRC_PAIR_C + 1)

enum asrc_inclk {
	INCLK_NONE = 0x03,
	INCLK_ESAI_RX = 0x00,
	INCLK_SSI1_RX = 0x01,
	INCLK_SSI2_RX = 0x02,
	INCLK_SSI3_RX = 0x07,
	INCLK_SPDIF_RX = 0x04,
	INCLK_MLB_CLK = 0x05,
	INCLK_PAD = 0x06,
	INCLK_ESAI_TX = 0x08,
	INCLK_SSI1_TX = 0x09,
	INCLK_SSI2_TX = 0x0a,
	INCLK_SSI3_TX = 0x0b,
	INCLK_SPDIF_TX = 0x0c,
	INCLK_ASRCK1_CLK = 0x0f,
};

enum asrc_outclk {
	OUTCLK_NONE = 0x03,
	OUTCLK_ESAI_TX = 0x00,
	OUTCLK_SSI1_TX = 0x01,
	OUTCLK_SSI2_TX = 0x02,
	OUTCLK_SSI3_TX = 0x07,
	OUTCLK_SPDIF_TX = 0x04,
	OUTCLK_MLB_CLK = 0x05,
	OUTCLK_PAD = 0x06,
	OUTCLK_ESAI_RX = 0x08,
	OUTCLK_SSI1_RX = 0x09,
	OUTCLK_SSI2_RX = 0x0a,
	OUTCLK_SSI3_RX = 0x0b,
	OUTCLK_SPDIF_RX = 0x0c,
	OUTCLK_ASRCK1_CLK = 0x0f,
};

#define ASRC_CLK_MAX_NUM	16

enum asrc_word_width {
	ASRC_WIDTH_24_BIT = 0,
	ASRC_WIDTH_16_BIT = 1,
	ASRC_WIDTH_8_BIT = 2,
};

struct asrc_config {
	enum asrc_pair_index pair;
	unsigned int channel_num;
	unsigned int buffer_num;
	unsigned int dma_buffer_size;
	unsigned int input_sample_rate;
	unsigned int output_sample_rate;
	enum asrc_word_width input_word_width;
	enum asrc_word_width output_word_width;
	enum asrc_inclk inclk;
	enum asrc_outclk outclk;
};

struct asrc_req {
	unsigned int chn_num;
	enum asrc_pair_index index;
};

struct asrc_querybuf {
	unsigned int buffer_index;
	unsigned int input_length;
	unsigned int output_length;
	unsigned long input_offset;
	unsigned long output_offset;
};

struct asrc_convert_buffer {
	void *input_buffer_vaddr;
	void *output_buffer_vaddr;
	unsigned int input_buffer_length;
	unsigned int output_buffer_length;
};

struct asrc_status_flags {
	enum asrc_pair_index index;
	unsigned int overload_error;
};

enum asrc_error_status {
	ASRC_TASK_Q_OVERLOAD		= 0x01,
	ASRC_OUTPUT_TASK_OVERLOAD	= 0x02,
	ASRC_INPUT_TASK_OVERLOAD	= 0x04,
	ASRC_OUTPUT_BUFFER_OVERFLOW	= 0x08,
	ASRC_INPUT_BUFFER_UNDERRUN	= 0x10,
};

struct dma_block {
	dma_addr_t dma_paddr;
	void *dma_vaddr;
	unsigned int length;
};

/**
 * fsl_asrc_pair: ASRC Pair private data
 *
 * @asrc_priv: pointer to its parent module
 * @config: configuration profile
 * @error: error record
 * @index: pair index (ASRC_PAIR_A, ASRC_PAIR_B, ASRC_PAIR_C)
 * @channels: occupied channel number
 * @desc: input and output dma descriptors
 * @dma_chan: inputer and output DMA channels
 * @dma_data: private dma data
 * @pos: hardware pointer position
 * @private: pair private area
 */
struct fsl_asrc_pair {
	struct fsl_asrc *asrc_priv;
	struct asrc_config *config;
	unsigned int error;

	enum asrc_pair_index index;
	unsigned int channels;

	struct dma_async_tx_descriptor *desc[2];
	struct dma_chan *dma_chan[2];
	struct imx_dma_data dma_data;
	unsigned int pos;

	void *private;
};

/**
 * fsl_asrc_pair: ASRC private data
 *
 * @dma_params_rx: DMA parameters for receive channel
 * @dma_params_tx: DMA parameters for transmit channel
 * @pdev: platform device pointer
 * @regmap: regmap handler
 * @paddr: physical address to the base address of registers
 * @mem_clk: clock source to access register
 * @ipg_clk: clock source to drive peripheral
 * @spba_clk: SPBA clock (optional, depending on SoC design)
 * @asrck_clk: clock sources to driver ASRC internal logic
 * @lock: spin lock for resource protection
 * @pair: pair pointers
 * @channel_bits: width of ASRCNCR register for each pair
 * @channel_avail: non-occupied channel numbers
 * @asrc_rate: default sample rate for ASoC Back-Ends
 * @asrc_width: default sample width for ASoC Back-Ends
 * @regcache_cfg: store register value of REG_ASRCFG
 */
struct fsl_asrc {
	struct snd_dmaengine_dai_dma_data dma_params_rx;
	struct snd_dmaengine_dai_dma_data dma_params_tx;
	struct platform_device *pdev;
	struct regmap *regmap;
	unsigned long paddr;
	struct clk *mem_clk;
	struct clk *ipg_clk;
	struct clk *spba_clk;
	struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
	spinlock_t lock;

	struct fsl_asrc_pair *pair[ASRC_PAIR_MAX_NUM];
	unsigned int channel_bits;
	unsigned int channel_avail;

	int asrc_rate;
	int asrc_width;

	u32 regcache_cfg;
};

#define DRV_NAME "fsl-asrc-dai"
extern struct snd_soc_component_driver fsl_asrc_component;
struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir);
#endif /* _FSL_ASRC_H */
Commit	Line	Data
2ba28053	1	/* SPDX-License-Identifier: GPL-2.0 */
3117bb31 NC	2	/*
	3	* fsl_asrc.h - Freescale ASRC ALSA SoC header file
	4	*
	5	* Copyright (C) 2014 Freescale Semiconductor, Inc.
	6	*
	7	* Author: Nicolin Chen <nicoleotsuka@gmail.com>
3117bb31 NC	8	*/
	9
	10	#ifndef _FSL_ASRC_H
	11	#define _FSL_ASRC_H
	12
	13	#define IN 0
	14	#define OUT 1
	15
	16	#define ASRC_DMA_BUFFER_NUM 2
	17	#define ASRC_INPUTFIFO_THRESHOLD 32
	18	#define ASRC_OUTPUTFIFO_THRESHOLD 32
	19	#define ASRC_FIFO_THRESHOLD_MIN 0
	20	#define ASRC_FIFO_THRESHOLD_MAX 63
	21	#define ASRC_DMA_BUFFER_SIZE (1024 * 48 * 4)
	22	#define ASRC_MAX_BUFFER_SIZE (1024 * 48)
	23	#define ASRC_OUTPUT_LAST_SAMPLE 8
	24
	25	#define IDEAL_RATIO_RATE 1000000
	26
	27	#define REG_ASRCTR 0x00
	28	#define REG_ASRIER 0x04
	29	#define REG_ASRCNCR 0x0C
	30	#define REG_ASRCFG 0x10
	31	#define REG_ASRCSR 0x14
	32
	33	#define REG_ASRCDR1 0x18
	34	#define REG_ASRCDR2 0x1C
	35	#define REG_ASRCDR(i) ((i < 2) ? REG_ASRCDR1 : REG_ASRCDR2)
	36
	37	#define REG_ASRSTR 0x20
	38	#define REG_ASRRA 0x24
	39	#define REG_ASRRB 0x28
	40	#define REG_ASRRC 0x2C
	41	#define REG_ASRPM1 0x40
	42	#define REG_ASRPM2 0x44
	43	#define REG_ASRPM3 0x48
	44	#define REG_ASRPM4 0x4C
	45	#define REG_ASRPM5 0x50
	46	#define REG_ASRTFR1 0x54
	47	#define REG_ASRCCR 0x5C
	48
	49	#define REG_ASRDIA 0x60
	50	#define REG_ASRDOA 0x64
	51	#define REG_ASRDIB 0x68
	52	#define REG_ASRDOB 0x6C
	53	#define REG_ASRDIC 0x70
	54	#define REG_ASRDOC 0x74
	55	#define REG_ASRDI(i) (REG_ASRDIA + (i << 3))
	56	#define REG_ASRDO(i) (REG_ASRDOA + (i << 3))
d1b726a9	57	#define REG_ASRDx(x, i) ((x) == IN ? REG_ASRDI(i) : REG_ASRDO(i))
3117bb31 NC	58
	59	#define REG_ASRIDRHA 0x80
	60	#define REG_ASRIDRLA 0x84
	61	#define REG_ASRIDRHB 0x88
	62	#define REG_ASRIDRLB 0x8C
	63	#define REG_ASRIDRHC 0x90
	64	#define REG_ASRIDRLC 0x94
	65	#define REG_ASRIDRH(i) (REG_ASRIDRHA + (i << 3))
	66	#define REG_ASRIDRL(i) (REG_ASRIDRLA + (i << 3))
	67
	68	#define REG_ASR76K 0x98
	69	#define REG_ASR56K 0x9C
	70
	71	#define REG_ASRMCRA 0xA0
	72	#define REG_ASRFSTA 0xA4
	73	#define REG_ASRMCRB 0xA8
	74	#define REG_ASRFSTB 0xAC
	75	#define REG_ASRMCRC 0xB0
	76	#define REG_ASRFSTC 0xB4
	77	#define REG_ASRMCR(i) (REG_ASRMCRA + (i << 3))
	78	#define REG_ASRFST(i) (REG_ASRFSTA + (i << 3))
	79
	80	#define REG_ASRMCR1A 0xC0
	81	#define REG_ASRMCR1B 0xC4
	82	#define REG_ASRMCR1C 0xC8
	83	#define REG_ASRMCR1(i) (REG_ASRMCR1A + (i << 2))
	84
	85
	86	/* REG0 0x00 REG_ASRCTR */
	87	#define ASRCTR_ATSi_SHIFT(i) (20 + i)
	88	#define ASRCTR_ATSi_MASK(i) (1 << ASRCTR_ATSi_SHIFT(i))
	89	#define ASRCTR_ATS(i) (1 << ASRCTR_ATSi_SHIFT(i))
	90	#define ASRCTR_USRi_SHIFT(i) (14 + (i << 1))
	91	#define ASRCTR_USRi_MASK(i) (1 << ASRCTR_USRi_SHIFT(i))
	92	#define ASRCTR_USR(i) (1 << ASRCTR_USRi_SHIFT(i))
	93	#define ASRCTR_IDRi_SHIFT(i) (13 + (i << 1))
	94	#define ASRCTR_IDRi_MASK(i) (1 << ASRCTR_IDRi_SHIFT(i))
	95	#define ASRCTR_IDR(i) (1 << ASRCTR_IDRi_SHIFT(i))
	96	#define ASRCTR_SRST_SHIFT 4
	97	#define ASRCTR_SRST_MASK (1 << ASRCTR_SRST_SHIFT)
	98	#define ASRCTR_SRST (1 << ASRCTR_SRST_SHIFT)
	99	#define ASRCTR_ASRCEi_SHIFT(i) (1 + i)
	100	#define ASRCTR_ASRCEi_MASK(i) (1 << ASRCTR_ASRCEi_SHIFT(i))
	101	#define ASRCTR_ASRCE(i) (1 << ASRCTR_ASRCEi_SHIFT(i))
	102	#define ASRCTR_ASRCEi_ALL_MASK (0x7 << ASRCTR_ASRCEi_SHIFT(0))
	103	#define ASRCTR_ASRCEN_SHIFT 0
	104	#define ASRCTR_ASRCEN_MASK (1 << ASRCTR_ASRCEN_SHIFT)
	105	#define ASRCTR_ASRCEN (1 << ASRCTR_ASRCEN_SHIFT)
	106
	107	/* REG1 0x04 REG_ASRIER */
	108	#define ASRIER_AFPWE_SHIFT 7
	109	#define ASRIER_AFPWE_MASK (1 << ASRIER_AFPWE_SHIFT)
	110	#define ASRIER_AFPWE (1 << ASRIER_AFPWE_SHIFT)
	111	#define ASRIER_AOLIE_SHIFT 6
	112	#define ASRIER_AOLIE_MASK (1 << ASRIER_AOLIE_SHIFT)
	113	#define ASRIER_AOLIE (1 << ASRIER_AOLIE_SHIFT)
	114	#define ASRIER_ADOEi_SHIFT(i) (3 + i)
	115	#define ASRIER_ADOEi_MASK(i) (1 << ASRIER_ADOEi_SHIFT(i))
	116	#define ASRIER_ADOE(i) (1 << ASRIER_ADOEi_SHIFT(i))
	117	#define ASRIER_ADIEi_SHIFT(i) (0 + i)
	118	#define ASRIER_ADIEi_MASK(i) (1 << ASRIER_ADIEi_SHIFT(i))
	119	#define ASRIER_ADIE(i) (1 << ASRIER_ADIEi_SHIFT(i))
	120
	121	/* REG2 0x0C REG_ASRCNCR */
122	#define ASRCNCR_ANCi_SHIFT(i, b) (b * i)
123	#define ASRCNCR_ANCi_MASK(i, b) (((1 << b) - 1) << ASRCNCR_ANCi_SHIFT(i, b))
124	#define ASRCNCR_ANCi(i, v, b) ((v << ASRCNCR_ANCi_SHIFT(i, b)) & ASRCNCR_ANCi_MASK(i, b))
125
126	/* REG3 0x10 REG_ASRCFG */
127	#define ASRCFG_INIRQi_SHIFT(i) (21 + i)
128	#define ASRCFG_INIRQi_MASK(i) (1 << ASRCFG_INIRQi_SHIFT(i))
129	#define ASRCFG_INIRQi (1 << ASRCFG_INIRQi_SHIFT(i))
130	#define ASRCFG_NDPRi_SHIFT(i) (18 + i)
131	#define ASRCFG_NDPRi_MASK(i) (1 << ASRCFG_NDPRi_SHIFT(i))
d44c6114 ZW	132	#define ASRCFG_NDPRi_ALL_SHIFT 18
d44c6114 ZW	133	#define ASRCFG_NDPRi_ALL_MASK (7 << ASRCFG_NDPRi_ALL_SHIFT)
3117bb31 NC	134	#define ASRCFG_NDPRi (1 << ASRCFG_NDPRi_SHIFT(i))
	135	#define ASRCFG_POSTMODi_SHIFT(i) (8 + (i << 2))
	136	#define ASRCFG_POSTMODi_WIDTH 2
	137	#define ASRCFG_POSTMODi_MASK(i) (((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
d44c6114	138	#define ASRCFG_POSTMODi_ALL_MASK (ASRCFG_POSTMODi_MASK(0) \| ASRCFG_POSTMODi_MASK(1) \| ASRCFG_POSTMODi_MASK(2))
3117bb31 NC	139	#define ASRCFG_POSTMOD(i, v) ((v) << ASRCFG_POSTMODi_SHIFT(i))
	140	#define ASRCFG_POSTMODi_UP(i) (0 << ASRCFG_POSTMODi_SHIFT(i))
	141	#define ASRCFG_POSTMODi_DCON(i) (1 << ASRCFG_POSTMODi_SHIFT(i))
	142	#define ASRCFG_POSTMODi_DOWN(i) (2 << ASRCFG_POSTMODi_SHIFT(i))
	143	#define ASRCFG_PREMODi_SHIFT(i) (6 + (i << 2))
	144	#define ASRCFG_PREMODi_WIDTH 2
	145	#define ASRCFG_PREMODi_MASK(i) (((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
d44c6114	146	#define ASRCFG_PREMODi_ALL_MASK (ASRCFG_PREMODi_MASK(0) \| ASRCFG_PREMODi_MASK(1) \| ASRCFG_PREMODi_MASK(2))
3117bb31 NC	147	#define ASRCFG_PREMOD(i, v) ((v) << ASRCFG_PREMODi_SHIFT(i))
	148	#define ASRCFG_PREMODi_UP(i) (0 << ASRCFG_PREMODi_SHIFT(i))
	149	#define ASRCFG_PREMODi_DCON(i) (1 << ASRCFG_PREMODi_SHIFT(i))
	150	#define ASRCFG_PREMODi_DOWN(i) (2 << ASRCFG_PREMODi_SHIFT(i))
	151	#define ASRCFG_PREMODi_BYPASS(i) (3 << ASRCFG_PREMODi_SHIFT(i))
	152
	153	/* REG4 0x14 REG_ASRCSR */
	154	#define ASRCSR_AxCSi_WIDTH 4
	155	#define ASRCSR_AxCSi_MASK ((1 << ASRCSR_AxCSi_WIDTH) - 1)
	156	#define ASRCSR_AOCSi_SHIFT(i) (12 + (i << 2))
	157	#define ASRCSR_AOCSi_MASK(i) (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AOCSi_SHIFT(i))
	158	#define ASRCSR_AOCS(i, v) ((v) << ASRCSR_AOCSi_SHIFT(i))
	159	#define ASRCSR_AICSi_SHIFT(i) (i << 2)
	160	#define ASRCSR_AICSi_MASK(i) (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AICSi_SHIFT(i))
	161	#define ASRCSR_AICS(i, v) ((v) << ASRCSR_AICSi_SHIFT(i))
	162
	163	/* REG5&6 0x18 & 0x1C REG_ASRCDR1 & ASRCDR2 */
	164	#define ASRCDRi_AxCPi_WIDTH 3
	165	#define ASRCDRi_AICPi_SHIFT(i) (0 + (i % 2) * 6)
	166	#define ASRCDRi_AICPi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICPi_SHIFT(i))
	167	#define ASRCDRi_AICP(i, v) ((v) << ASRCDRi_AICPi_SHIFT(i))
	168	#define ASRCDRi_AICDi_SHIFT(i) (3 + (i % 2) * 6)
	169	#define ASRCDRi_AICDi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICDi_SHIFT(i))
	170	#define ASRCDRi_AICD(i, v) ((v) << ASRCDRi_AICDi_SHIFT(i))
	171	#define ASRCDRi_AOCPi_SHIFT(i) ((i < 2) ? 12 + i * 6 : 6)
	172	#define ASRCDRi_AOCPi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCPi_SHIFT(i))
	173	#define ASRCDRi_AOCP(i, v) ((v) << ASRCDRi_AOCPi_SHIFT(i))
	174	#define ASRCDRi_AOCDi_SHIFT(i) ((i < 2) ? 15 + i * 6 : 9)
	175	#define ASRCDRi_AOCDi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCDi_SHIFT(i))
	176	#define ASRCDRi_AOCD(i, v) ((v) << ASRCDRi_AOCDi_SHIFT(i))
	177
	178	/* REG7 0x20 REG_ASRSTR */
	179	#define ASRSTR_DSLCNT_SHIFT 21
	180	#define ASRSTR_DSLCNT_MASK (1 << ASRSTR_DSLCNT_SHIFT)
	181	#define ASRSTR_DSLCNT (1 << ASRSTR_DSLCNT_SHIFT)
	182	#define ASRSTR_ATQOL_SHIFT 20
	183	#define ASRSTR_ATQOL_MASK (1 << ASRSTR_ATQOL_SHIFT)
	184	#define ASRSTR_ATQOL (1 << ASRSTR_ATQOL_SHIFT)
	185	#define ASRSTR_AOOLi_SHIFT(i) (17 + i)
	186	#define ASRSTR_AOOLi_MASK(i) (1 << ASRSTR_AOOLi_SHIFT(i))
	187	#define ASRSTR_AOOL(i) (1 << ASRSTR_AOOLi_SHIFT(i))
	188	#define ASRSTR_AIOLi_SHIFT(i) (14 + i)
	189	#define ASRSTR_AIOLi_MASK(i) (1 << ASRSTR_AIOLi_SHIFT(i))
	190	#define ASRSTR_AIOL(i) (1 << ASRSTR_AIOLi_SHIFT(i))
	191	#define ASRSTR_AODOi_SHIFT(i) (11 + i)
	192	#define ASRSTR_AODOi_MASK(i) (1 << ASRSTR_AODOi_SHIFT(i))
	193	#define ASRSTR_AODO(i) (1 << ASRSTR_AODOi_SHIFT(i))
	194	#define ASRSTR_AIDUi_SHIFT(i) (8 + i)
	195	#define ASRSTR_AIDUi_MASK(i) (1 << ASRSTR_AIDUi_SHIFT(i))
	196	#define ASRSTR_AIDU(i) (1 << ASRSTR_AIDUi_SHIFT(i))
	197	#define ASRSTR_FPWT_SHIFT 7
	198	#define ASRSTR_FPWT_MASK (1 << ASRSTR_FPWT_SHIFT)
	199	#define ASRSTR_FPWT (1 << ASRSTR_FPWT_SHIFT)
	200	#define ASRSTR_AOLE_SHIFT 6
	201	#define ASRSTR_AOLE_MASK (1 << ASRSTR_AOLE_SHIFT)
	202	#define ASRSTR_AOLE (1 << ASRSTR_AOLE_SHIFT)
	203	#define ASRSTR_AODEi_SHIFT(i) (3 + i)
	204	#define ASRSTR_AODFi_MASK(i) (1 << ASRSTR_AODEi_SHIFT(i))
	205	#define ASRSTR_AODF(i) (1 << ASRSTR_AODEi_SHIFT(i))
	206	#define ASRSTR_AIDEi_SHIFT(i) (0 + i)
	207	#define ASRSTR_AIDEi_MASK(i) (1 << ASRSTR_AIDEi_SHIFT(i))
	208	#define ASRSTR_AIDE(i) (1 << ASRSTR_AIDEi_SHIFT(i))
	209
	210	/* REG10 0x54 REG_ASRTFR1 */
211	#define ASRTFR1_TF_BASE_WIDTH 7
212	#define ASRTFR1_TF_BASE_SHIFT 6
213	#define ASRTFR1_TF_BASE_MASK (((1 << ASRTFR1_TF_BASE_WIDTH) - 1) << ASRTFR1_TF_BASE_SHIFT)
214	#define ASRTFR1_TF_BASE(i) ((i) << ASRTFR1_TF_BASE_SHIFT)
215
216	/*
217	* REG22 0xA0 REG_ASRMCRA
218	* REG24 0xA8 REG_ASRMCRB
219	* REG26 0xB0 REG_ASRMCRC
220	*/
221	#define ASRMCRi_ZEROBUFi_SHIFT 23
222	#define ASRMCRi_ZEROBUFi_MASK (1 << ASRMCRi_ZEROBUFi_SHIFT)
223	#define ASRMCRi_ZEROBUFi (1 << ASRMCRi_ZEROBUFi_SHIFT)
224	#define ASRMCRi_EXTTHRSHi_SHIFT 22
225	#define ASRMCRi_EXTTHRSHi_MASK (1 << ASRMCRi_EXTTHRSHi_SHIFT)
226	#define ASRMCRi_EXTTHRSHi (1 << ASRMCRi_EXTTHRSHi_SHIFT)
227	#define ASRMCRi_BUFSTALLi_SHIFT 21
228	#define ASRMCRi_BUFSTALLi_MASK (1 << ASRMCRi_BUFSTALLi_SHIFT)
229	#define ASRMCRi_BUFSTALLi (1 << ASRMCRi_BUFSTALLi_SHIFT)
230	#define ASRMCRi_BYPASSPOLYi_SHIFT 20
231	#define ASRMCRi_BYPASSPOLYi_MASK (1 << ASRMCRi_BYPASSPOLYi_SHIFT)
232	#define ASRMCRi_BYPASSPOLYi (1 << ASRMCRi_BYPASSPOLYi_SHIFT)
233	#define ASRMCRi_OUTFIFO_THRESHOLD_WIDTH 6
234	#define ASRMCRi_OUTFIFO_THRESHOLD_SHIFT 12
235	#define ASRMCRi_OUTFIFO_THRESHOLD_MASK (((1 << ASRMCRi_OUTFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT)
236	#define ASRMCRi_OUTFIFO_THRESHOLD(v) (((v) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRi_OUTFIFO_THRESHOLD_MASK)
237	#define ASRMCRi_RSYNIFi_SHIFT 11
238	#define ASRMCRi_RSYNIFi_MASK (1 << ASRMCRi_RSYNIFi_SHIFT)
239	#define ASRMCRi_RSYNIFi (1 << ASRMCRi_RSYNIFi_SHIFT)
240	#define ASRMCRi_RSYNOFi_SHIFT 10
241	#define ASRMCRi_RSYNOFi_MASK (1 << ASRMCRi_RSYNOFi_SHIFT)
242	#define ASRMCRi_RSYNOFi (1 << ASRMCRi_RSYNOFi_SHIFT)
243	#define ASRMCRi_INFIFO_THRESHOLD_WIDTH 6
244	#define ASRMCRi_INFIFO_THRESHOLD_SHIFT 0
245	#define ASRMCRi_INFIFO_THRESHOLD_MASK (((1 << ASRMCRi_INFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_INFIFO_THRESHOLD_SHIFT)
246	#define ASRMCRi_INFIFO_THRESHOLD(v) (((v) << ASRMCRi_INFIFO_THRESHOLD_SHIFT) & ASRMCRi_INFIFO_THRESHOLD_MASK)
247
248	/*
249	* REG23 0xA4 REG_ASRFSTA
250	* REG25 0xAC REG_ASRFSTB
251	* REG27 0xB4 REG_ASRFSTC
252	*/
253	#define ASRFSTi_OAFi_SHIFT 23
254	#define ASRFSTi_OAFi_MASK (1 << ASRFSTi_OAFi_SHIFT)
255	#define ASRFSTi_OAFi (1 << ASRFSTi_OAFi_SHIFT)
256	#define ASRFSTi_OUTPUT_FIFO_WIDTH 7
257	#define ASRFSTi_OUTPUT_FIFO_SHIFT 12
258	#define ASRFSTi_OUTPUT_FIFO_MASK (((1 << ASRFSTi_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTi_OUTPUT_FIFO_SHIFT)
259	#define ASRFSTi_IAEi_SHIFT 11
b89b6925 NC	260	#define ASRFSTi_IAEi_MASK (1 << ASRFSTi_IAEi_SHIFT)
b89b6925 NC	261	#define ASRFSTi_IAEi (1 << ASRFSTi_IAEi_SHIFT)
3117bb31 NC	262	#define ASRFSTi_INPUT_FIFO_WIDTH 7
	263	#define ASRFSTi_INPUT_FIFO_SHIFT 0
	264	#define ASRFSTi_INPUT_FIFO_MASK ((1 << ASRFSTi_INPUT_FIFO_WIDTH) - 1)
	265
	266	/* REG28 0xC0 & 0xC4 & 0xC8 REG_ASRMCR1i */
	267	#define ASRMCR1i_IWD_WIDTH 3
	268	#define ASRMCR1i_IWD_SHIFT 9
	269	#define ASRMCR1i_IWD_MASK (((1 << ASRMCR1i_IWD_WIDTH) - 1) << ASRMCR1i_IWD_SHIFT)
	270	#define ASRMCR1i_IWD(v) ((v) << ASRMCR1i_IWD_SHIFT)
	271	#define ASRMCR1i_IMSB_SHIFT 8
	272	#define ASRMCR1i_IMSB_MASK (1 << ASRMCR1i_IMSB_SHIFT)
	273	#define ASRMCR1i_IMSB_MSB (1 << ASRMCR1i_IMSB_SHIFT)
	274	#define ASRMCR1i_IMSB_LSB (0 << ASRMCR1i_IMSB_SHIFT)
	275	#define ASRMCR1i_OMSB_SHIFT 2
	276	#define ASRMCR1i_OMSB_MASK (1 << ASRMCR1i_OMSB_SHIFT)
	277	#define ASRMCR1i_OMSB_MSB (1 << ASRMCR1i_OMSB_SHIFT)
	278	#define ASRMCR1i_OMSB_LSB (0 << ASRMCR1i_OMSB_SHIFT)
	279	#define ASRMCR1i_OSGN_SHIFT 1
	280	#define ASRMCR1i_OSGN_MASK (1 << ASRMCR1i_OSGN_SHIFT)
	281	#define ASRMCR1i_OSGN (1 << ASRMCR1i_OSGN_SHIFT)
	282	#define ASRMCR1i_OW16_SHIFT 0
	283	#define ASRMCR1i_OW16_MASK (1 << ASRMCR1i_OW16_SHIFT)
	284	#define ASRMCR1i_OW16(v) ((v) << ASRMCR1i_OW16_SHIFT)
	285
	286
	287	enum asrc_pair_index {
	288	ASRC_INVALID_PAIR = -1,
	289	ASRC_PAIR_A = 0,
	290	ASRC_PAIR_B = 1,
	291	ASRC_PAIR_C = 2,
	292	};
	293
	294	#define ASRC_PAIR_MAX_NUM (ASRC_PAIR_C + 1)
	295
	296	enum asrc_inclk {
	297	INCLK_NONE = 0x03,
	298	INCLK_ESAI_RX = 0x00,
	299	INCLK_SSI1_RX = 0x01,
	300	INCLK_SSI2_RX = 0x02,
	301	INCLK_SSI3_RX = 0x07,
	302	INCLK_SPDIF_RX = 0x04,
	303	INCLK_MLB_CLK = 0x05,
	304	INCLK_PAD = 0x06,
	305	INCLK_ESAI_TX = 0x08,
	306	INCLK_SSI1_TX = 0x09,
	307	INCLK_SSI2_TX = 0x0a,
	308	INCLK_SSI3_TX = 0x0b,
	309	INCLK_SPDIF_TX = 0x0c,
	310	INCLK_ASRCK1_CLK = 0x0f,
	311	};
	312
	313	enum asrc_outclk {
	314	OUTCLK_NONE = 0x03,
	315	OUTCLK_ESAI_TX = 0x00,
	316	OUTCLK_SSI1_TX = 0x01,
	317	OUTCLK_SSI2_TX = 0x02,
	318	OUTCLK_SSI3_TX = 0x07,
	319	OUTCLK_SPDIF_TX = 0x04,
	320	OUTCLK_MLB_CLK = 0x05,
	321	OUTCLK_PAD = 0x06,
	322	OUTCLK_ESAI_RX = 0x08,
	323	OUTCLK_SSI1_RX = 0x09,
	324	OUTCLK_SSI2_RX = 0x0a,
	325	OUTCLK_SSI3_RX = 0x0b,
326	OUTCLK_SPDIF_RX = 0x0c,
327	OUTCLK_ASRCK1_CLK = 0x0f,
328	};
329
330	#define ASRC_CLK_MAX_NUM 16
331
332	enum asrc_word_width {
333	ASRC_WIDTH_24_BIT = 0,
334	ASRC_WIDTH_16_BIT = 1,
335	ASRC_WIDTH_8_BIT = 2,
336	};
337
338	struct asrc_config {
339	enum asrc_pair_index pair;
340	unsigned int channel_num;
341	unsigned int buffer_num;
342	unsigned int dma_buffer_size;
343	unsigned int input_sample_rate;
344	unsigned int output_sample_rate;
345	enum asrc_word_width input_word_width;
346	enum asrc_word_width output_word_width;
347	enum asrc_inclk inclk;
348	enum asrc_outclk outclk;
349	};
350
351	struct asrc_req {
352	unsigned int chn_num;
353	enum asrc_pair_index index;
354	};
355
356	struct asrc_querybuf {
357	unsigned int buffer_index;
358	unsigned int input_length;
359	unsigned int output_length;
360	unsigned long input_offset;
361	unsigned long output_offset;
362	};
363
364	struct asrc_convert_buffer {
365	void *input_buffer_vaddr;
366	void *output_buffer_vaddr;
367	unsigned int input_buffer_length;
368	unsigned int output_buffer_length;
369	};
370
371	struct asrc_status_flags {
372	enum asrc_pair_index index;
373	unsigned int overload_error;
374	};
375
376	enum asrc_error_status {
377	ASRC_TASK_Q_OVERLOAD = 0x01,
378	ASRC_OUTPUT_TASK_OVERLOAD = 0x02,
379	ASRC_INPUT_TASK_OVERLOAD = 0x04,
380	ASRC_OUTPUT_BUFFER_OVERFLOW = 0x08,
381	ASRC_INPUT_BUFFER_UNDERRUN = 0x10,
382	};
383
384	struct dma_block {
385	dma_addr_t dma_paddr;
386	void *dma_vaddr;
387	unsigned int length;
388	};
389
390	/**
391	* fsl_asrc_pair: ASRC Pair private data
392	*
393	* @asrc_priv: pointer to its parent module
394	* @config: configuration profile
395	* @error: error record
396	* @index: pair index (ASRC_PAIR_A, ASRC_PAIR_B, ASRC_PAIR_C)
397	* @channels: occupied channel number
398	* @desc: input and output dma descriptors
399	* @dma_chan: inputer and output DMA channels
400	* @dma_data: private dma data
401	* @pos: hardware pointer position
402	* @private: pair private area
403	*/
404	struct fsl_asrc_pair {
405	struct fsl_asrc *asrc_priv;
406	struct asrc_config *config;
407	unsigned int error;
408
409	enum asrc_pair_index index;
410	unsigned int channels;
411
412	struct dma_async_tx_descriptor *desc[2];
413	struct dma_chan *dma_chan[2];
414	struct imx_dma_data dma_data;
415	unsigned int pos;
416
417	void *private;
418	};
419
420	/**
421	* fsl_asrc_pair: ASRC private data
422	*
423	* @dma_params_rx: DMA parameters for receive channel
424	* @dma_params_tx: DMA parameters for transmit channel
425	* @pdev: platform device pointer
426	* @regmap: regmap handler
427	* @paddr: physical address to the base address of registers
428	* @mem_clk: clock source to access register
429	* @ipg_clk: clock source to drive peripheral
13b8a97a	430	* @spba_clk: SPBA clock (optional, depending on SoC design)
3117bb31 NC	431	* @asrck_clk: clock sources to driver ASRC internal logic
	432	* @lock: spin lock for resource protection
	433	* @pair: pair pointers
	434	* @channel_bits: width of ASRCNCR register for each pair
	435	* @channel_avail: non-occupied channel numbers
	436	* @asrc_rate: default sample rate for ASoC Back-Ends
	437	* @asrc_width: default sample width for ASoC Back-Ends
d44c6114	438	* @regcache_cfg: store register value of REG_ASRCFG
3117bb31 NC	439	*/
	440	struct fsl_asrc {
	441	struct snd_dmaengine_dai_dma_data dma_params_rx;
	442	struct snd_dmaengine_dai_dma_data dma_params_tx;
	443	struct platform_device *pdev;
	444	struct regmap *regmap;
	445	unsigned long paddr;
	446	struct clk *mem_clk;
	447	struct clk *ipg_clk;
13b8a97a	448	struct clk *spba_clk;
3117bb31 NC	449	struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
	450	spinlock_t lock;
	451
	452	struct fsl_asrc_pair *pair[ASRC_PAIR_MAX_NUM];
	453	unsigned int channel_bits;
	454	unsigned int channel_avail;
	455
	456	int asrc_rate;
	457	int asrc_width;
d44c6114 ZW	458
d44c6114 ZW	459	u32 regcache_cfg;
3117bb31 NC	460	};
3117bb31 NC	461
7f110661 KM	462	#define DRV_NAME "fsl-asrc-dai"
7f110661 KM	463	extern struct snd_soc_component_driver fsl_asrc_component;
3117bb31 NC	464	struct dma_chan fsl_asrc_get_dma_channel(struct fsl_asrc_pair pair, bool dir);
3117bb31 NC	465	#endif /* _FSL_ASRC_H */