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Merge branch 'asoc-4.19' into asoc-4.20 for rt5682 deps.
[linux-2.6-block.git] / sound / soc / fsl / fsl_asrc.c
CommitLineData
2ba28053
FE		 1// SPDX-License-Identifier: GPL-2.0
2//
3// Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
4//
5// Copyright (C) 2014 Freescale Semiconductor, Inc.
6//
7// Author: Nicolin Chen <nicoleotsuka@gmail.com>
3117bb31
NC		 8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dma-mapping.h>
12#include <linux/module.h>
13#include <linux/of_platform.h>
14#include <linux/platform_data/dma-imx.h>
15#include <linux/pm_runtime.h>
16#include <sound/dmaengine_pcm.h>
17#include <sound/pcm_params.h>
18
19#include "fsl_asrc.h"
20
21#define IDEAL_RATIO_DECIMAL_DEPTH 26
22
23#define pair_err(fmt, ...) \
24 dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
25
26#define pair_dbg(fmt, ...) \
27 dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
28
29/* Sample rates are aligned with that defined in pcm.h file */
fff6e03c
ZW		 30static const u8 process_option[][12][2] = {
31 /* 8kHz 11.025kHz 16kHz 22.05kHz 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */
32 {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */
33 {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */
34 {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */
35 {{1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */
36 {{1, 2}, {1, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */
37 {{1, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */
38 {{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */
39 {{2, 2}, {2, 2}, {2, 1}, {2, 1}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */
40 {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */
41 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */
42 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */
43 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */
44 {{2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */
3117bb31
NC		 45};
46
47/* Corresponding to process_option */
48static int supported_input_rate[] = {
49 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200,
50 96000, 176400, 192000,
51};
52
53static int supported_asrc_rate[] = {
fff6e03c 54 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000,
3117bb31
NC		 55};
56
57/**
58 * The following tables map the relationship between asrc_inclk/asrc_outclk in
59 * fsl_asrc.h and the registers of ASRCSR
60 */
61static unsigned char input_clk_map_imx35[] = {
62 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
63};
64
65static unsigned char output_clk_map_imx35[] = {
66 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
67};
68
69/* i.MX53 uses the same map for input and output */
70static unsigned char input_clk_map_imx53[] = {
71/* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
72 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
73};
74
75static unsigned char output_clk_map_imx53[] = {
76/* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
77 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
78};
79
80static unsigned char *clk_map[2];
81
82/**
83 * Request ASRC pair
84 *
85 * It assigns pair by the order of A->C->B because allocation of pair B,
86 * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
87 * while pair A and pair C are comparatively independent.
88 */
89static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
90{
91 enum asrc_pair_index index = ASRC_INVALID_PAIR;
92 struct fsl_asrc *asrc_priv = pair->asrc_priv;
93 struct device *dev = &asrc_priv->pdev->dev;
94 unsigned long lock_flags;
95 int i, ret = 0;
96
97 spin_lock_irqsave(&asrc_priv->lock, lock_flags);
98
99 for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
100 if (asrc_priv->pair[i] != NULL)
101 continue;
102
103 index = i;
104
105 if (i != ASRC_PAIR_B)
106 break;
107 }
108
109 if (index == ASRC_INVALID_PAIR) {
110 dev_err(dev, "all pairs are busy now\n");
111 ret = -EBUSY;
112 } else if (asrc_priv->channel_avail < channels) {
113 dev_err(dev, "can't afford required channels: %d\n", channels);
114 ret = -EINVAL;
115 } else {
116 asrc_priv->channel_avail -= channels;
117 asrc_priv->pair[index] = pair;
118 pair->channels = channels;
119 pair->index = index;
120 }
121
122 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
123
124 return ret;
125}
126
127/**
128 * Release ASRC pair
129 *
130 * It clears the resource from asrc_priv and releases the occupied channels.
131 */
132static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
133{
134 struct fsl_asrc *asrc_priv = pair->asrc_priv;
135 enum asrc_pair_index index = pair->index;
136 unsigned long lock_flags;
137
138 /* Make sure the pair is disabled */
139 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
140 ASRCTR_ASRCEi_MASK(index), 0);
141
142 spin_lock_irqsave(&asrc_priv->lock, lock_flags);
143
144 asrc_priv->channel_avail += pair->channels;
145 asrc_priv->pair[index] = NULL;
146 pair->error = 0;
147
148 spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
149}
150
151/**
152 * Configure input and output thresholds
153 */
154static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
155{
156 struct fsl_asrc *asrc_priv = pair->asrc_priv;
157 enum asrc_pair_index index = pair->index;
158
159 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
160 ASRMCRi_EXTTHRSHi_MASK |
161 ASRMCRi_INFIFO_THRESHOLD_MASK |
162 ASRMCRi_OUTFIFO_THRESHOLD_MASK,
163 ASRMCRi_EXTTHRSHi |
164 ASRMCRi_INFIFO_THRESHOLD(in) |
165 ASRMCRi_OUTFIFO_THRESHOLD(out));
166}
167
168/**
169 * Calculate the total divisor between asrck clock rate and sample rate
170 *
171 * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
172 */
173static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
174{
175 u32 ps;
176
177 /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
178 for (ps = 0; div > 8; ps++)
179 div >>= 1;
180
181 return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
182}
183
184/**
185 * Calculate and set the ratio for Ideal Ratio mode only
186 *
187 * The ratio is a 32-bit fixed point value with 26 fractional bits.
188 */
189static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
190 int inrate, int outrate)
191{
192 struct fsl_asrc *asrc_priv = pair->asrc_priv;
193 enum asrc_pair_index index = pair->index;
194 unsigned long ratio;
195 int i;
196
197 if (!outrate) {
198 pair_err("output rate should not be zero\n");
199 return -EINVAL;
200 }
201
202 /* Calculate the intergal part of the ratio */
203 ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
204
205 /* ... and then the 26 depth decimal part */
206 inrate %= outrate;
207
208 for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
209 inrate <<= 1;
210
211 if (inrate < outrate)
212 continue;
213
214 ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
215 inrate -= outrate;
216
217 if (!inrate)
218 break;
219 }
220
221 regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio);
222 regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24);
223
224 return 0;
225}
226
227/**
228 * Configure the assigned ASRC pair
229 *
230 * It configures those ASRC registers according to a configuration instance
231 * of struct asrc_config which includes in/output sample rate, width, channel
232 * and clock settings.
233 */
234static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair)
235{
236 struct asrc_config *config = pair->config;
237 struct fsl_asrc *asrc_priv = pair->asrc_priv;
238 enum asrc_pair_index index = pair->index;
4e13eb72 239 u32 inrate, outrate, indiv, outdiv;
3117bb31
NC		 240 u32 clk_index[2], div[2];
241 int in, out, channels;
242 struct clk *clk;
4e13eb72 243 bool ideal;
3117bb31
NC		 244
245 if (!config) {
246 pair_err("invalid pair config\n");
247 return -EINVAL;
248 }
249
250 /* Validate channels */
251 if (config->channel_num < 1 || config->channel_num > 10) {
252 pair_err("does not support %d channels\n", config->channel_num);
253 return -EINVAL;
254 }
255
256 /* Validate output width */
257 if (config->output_word_width == ASRC_WIDTH_8_BIT) {
258 pair_err("does not support 8bit width output\n");
259 return -EINVAL;
260 }
261
4e13eb72
NC		 262 inrate = config->input_sample_rate;
263 outrate = config->output_sample_rate;
264 ideal = config->inclk == INCLK_NONE;
265
3117bb31
NC		 266 /* Validate input and output sample rates */
267 for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++)
268 if (inrate == supported_input_rate[in])
269 break;
270
271 if (in == ARRAY_SIZE(supported_input_rate)) {
272 pair_err("unsupported input sample rate: %dHz\n", inrate);
273 return -EINVAL;
274 }
275
276 for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
277 if (outrate == supported_asrc_rate[out])
278 break;
279
280 if (out == ARRAY_SIZE(supported_asrc_rate)) {
281 pair_err("unsupported output sample rate: %dHz\n", outrate);
282 return -EINVAL;
283 }
284
fff6e03c
ZW		 285 if ((outrate > 8000 && outrate < 30000) &&
286 (outrate/inrate > 24 || inrate/outrate > 8)) {
287 pair_err("exceed supported ratio range [1/24, 8] for \
288 inrate/outrate: %d/%d\n", inrate, outrate);
289 return -EINVAL;
290 }
291
3117bb31
NC		 292 /* Validate input and output clock sources */
293 clk_index[IN] = clk_map[IN][config->inclk];
294 clk_index[OUT] = clk_map[OUT][config->outclk];
295
296 /* We only have output clock for ideal ratio mode */
297 clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
298
299 div[IN] = clk_get_rate(clk) / inrate;
300 if (div[IN] == 0) {
301 pair_err("failed to support input sample rate %dHz by asrck_%x\n",
302 inrate, clk_index[ideal ? OUT : IN]);
303 return -EINVAL;
304 }
305
306 clk = asrc_priv->asrck_clk[clk_index[OUT]];
307
308 /* Use fixed output rate for Ideal Ratio mode (INCLK_NONE) */
309 if (ideal)
310 div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE;
311 else
312 div[OUT] = clk_get_rate(clk) / outrate;
313
314 if (div[OUT] == 0) {
315 pair_err("failed to support output sample rate %dHz by asrck_%x\n",
316 outrate, clk_index[OUT]);
317 return -EINVAL;
318 }
319
320 /* Set the channel number */
321 channels = config->channel_num;
322
323 if (asrc_priv->channel_bits < 4)
324 channels /= 2;
325
326 /* Update channels for current pair */
327 regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR,
328 ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits),
329 ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits));
330
331 /* Default setting: Automatic selection for processing mode */
332 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
333 ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
334 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
335 ASRCTR_USRi_MASK(index), 0);
336
337 /* Set the input and output clock sources */
338 regmap_update_bits(asrc_priv->regmap, REG_ASRCSR,
339 ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
340 ASRCSR_AICS(index, clk_index[IN]) |
341 ASRCSR_AOCS(index, clk_index[OUT]));
342
343 /* Calculate the input clock divisors */
344 indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
345 outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
346
347 /* Suppose indiv and outdiv includes prescaler, so add its MASK too */
348 regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index),
349 ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
350 ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
351 ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
352
353 /* Implement word_width configurations */
354 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index),
355 ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
356 ASRMCR1i_OW16(config->output_word_width) |
357 ASRMCR1i_IWD(config->input_word_width));
358
359 /* Enable BUFFER STALL */
360 regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
361 ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
362
363 /* Set default thresholds for input and output FIFO */
364 fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
365 ASRC_INPUTFIFO_THRESHOLD);
366
4091fb95 367 /* Configure the following only for Ideal Ratio mode */
3117bb31
NC		 368 if (!ideal)
369 return 0;
370
371 /* Clear ASTSx bit to use Ideal Ratio mode */
372 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
373 ASRCTR_ATSi_MASK(index), 0);
374
375 /* Enable Ideal Ratio mode */
376 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
377 ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
378 ASRCTR_IDR(index) | ASRCTR_USR(index));
379
380 /* Apply configurations for pre- and post-processing */
381 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
382 ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
383 ASRCFG_PREMOD(index, process_option[in][out][0]) |
384 ASRCFG_POSTMOD(index, process_option[in][out][1]));
385
386 return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
387}
388
389/**
390 * Start the assigned ASRC pair
391 *
392 * It enables the assigned pair and makes it stopped at the stall level.
393 */
394static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
395{
396 struct fsl_asrc *asrc_priv = pair->asrc_priv;
397 enum asrc_pair_index index = pair->index;
398 int reg, retry = 10, i;
399
400 /* Enable the current pair */
401 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
402 ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
403
404 /* Wait for status of initialization */
405 do {
406 udelay(5);
407 regmap_read(asrc_priv->regmap, REG_ASRCFG, &reg);
408 reg &= ASRCFG_INIRQi_MASK(index);
409 } while (!reg && --retry);
410
411 /* Make the input fifo to ASRC STALL level */
412 regmap_read(asrc_priv->regmap, REG_ASRCNCR, &reg);
413 for (i = 0; i < pair->channels * 4; i++)
414 regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0);
415
416 /* Enable overload interrupt */
417 regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE);
418}
419
420/**
421 * Stop the assigned ASRC pair
422 */
423static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
424{
425 struct fsl_asrc *asrc_priv = pair->asrc_priv;
426 enum asrc_pair_index index = pair->index;
427
428 /* Stop the current pair */
429 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
430 ASRCTR_ASRCEi_MASK(index), 0);
431}
432
433/**
434 * Get DMA channel according to the pair and direction.
435 */
436struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir)
437{
438 struct fsl_asrc *asrc_priv = pair->asrc_priv;
439 enum asrc_pair_index index = pair->index;
440 char name[4];
441
442 sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
443
444 return dma_request_slave_channel(&asrc_priv->pdev->dev, name);
445}
446EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel);
447
448static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
449 struct snd_pcm_hw_params *params,
450 struct snd_soc_dai *dai)
451{
452 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
4ca73043 453 int width = params_width(params);
3117bb31
NC		 454 struct snd_pcm_runtime *runtime = substream->runtime;
455 struct fsl_asrc_pair *pair = runtime->private_data;
456 unsigned int channels = params_channels(params);
457 unsigned int rate = params_rate(params);
458 struct asrc_config config;
459 int word_width, ret;
460
461 ret = fsl_asrc_request_pair(channels, pair);
462 if (ret) {
463 dev_err(dai->dev, "fail to request asrc pair\n");
464 return ret;
465 }
466
467 pair->config = &config;
468
469 if (width == 16)
470 width = ASRC_WIDTH_16_BIT;
471 else
472 width = ASRC_WIDTH_24_BIT;
473
474 if (asrc_priv->asrc_width == 16)
475 word_width = ASRC_WIDTH_16_BIT;
476 else
477 word_width = ASRC_WIDTH_24_BIT;
478
479 config.pair = pair->index;
480 config.channel_num = channels;
481 config.inclk = INCLK_NONE;
482 config.outclk = OUTCLK_ASRCK1_CLK;
483
484 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
485 config.input_word_width = width;
486 config.output_word_width = word_width;
487 config.input_sample_rate = rate;
488 config.output_sample_rate = asrc_priv->asrc_rate;
489 } else {
490 config.input_word_width = word_width;
491 config.output_word_width = width;
492 config.input_sample_rate = asrc_priv->asrc_rate;
493 config.output_sample_rate = rate;
494 }
495
496 ret = fsl_asrc_config_pair(pair);
497 if (ret) {
498 dev_err(dai->dev, "fail to config asrc pair\n");
499 return ret;
500 }
501
502 return 0;
503}
504
505static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
506 struct snd_soc_dai *dai)
507{
508 struct snd_pcm_runtime *runtime = substream->runtime;
509 struct fsl_asrc_pair *pair = runtime->private_data;
510
511 if (pair)
512 fsl_asrc_release_pair(pair);
513
514 return 0;
515}
516
517static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
518 struct snd_soc_dai *dai)
519{
520 struct snd_pcm_runtime *runtime = substream->runtime;
521 struct fsl_asrc_pair *pair = runtime->private_data;
522
523 switch (cmd) {
524 case SNDRV_PCM_TRIGGER_START:
525 case SNDRV_PCM_TRIGGER_RESUME:
526 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
527 fsl_asrc_start_pair(pair);
528 break;
529 case SNDRV_PCM_TRIGGER_STOP:
530 case SNDRV_PCM_TRIGGER_SUSPEND:
531 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
532 fsl_asrc_stop_pair(pair);
533 break;
534 default:
535 return -EINVAL;
536 }
537
538 return 0;
539}
540
29a22ebf 541static const struct snd_soc_dai_ops fsl_asrc_dai_ops = {
3117bb31
NC		 542 .hw_params = fsl_asrc_dai_hw_params,
543 .hw_free = fsl_asrc_dai_hw_free,
544 .trigger = fsl_asrc_dai_trigger,
545};
546
547static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
548{
549 struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
550
551 snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx,
552 &asrc_priv->dma_params_rx);
553
554 return 0;
555}
556
557#define FSL_ASRC_RATES SNDRV_PCM_RATE_8000_192000
558#define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
559 SNDRV_PCM_FMTBIT_S16_LE | \
d526416c 560 SNDRV_PCM_FMTBIT_S20_3LE)
3117bb31
NC		 561
562static struct snd_soc_dai_driver fsl_asrc_dai = {
563 .probe = fsl_asrc_dai_probe,
564 .playback = {
565 .stream_name = "ASRC-Playback",
566 .channels_min = 1,
567 .channels_max = 10,
568 .rates = FSL_ASRC_RATES,
569 .formats = FSL_ASRC_FORMATS,
570 },
571 .capture = {
572 .stream_name = "ASRC-Capture",
573 .channels_min = 1,
574 .channels_max = 10,
575 .rates = FSL_ASRC_RATES,
576 .formats = FSL_ASRC_FORMATS,
577 },
578 .ops = &fsl_asrc_dai_ops,
579};
580
3117bb31
NC		 581static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
582{
583 switch (reg) {
584 case REG_ASRCTR:
585 case REG_ASRIER:
586 case REG_ASRCNCR:
587 case REG_ASRCFG:
588 case REG_ASRCSR:
589 case REG_ASRCDR1:
590 case REG_ASRCDR2:
591 case REG_ASRSTR:
592 case REG_ASRPM1:
593 case REG_ASRPM2:
594 case REG_ASRPM3:
595 case REG_ASRPM4:
596 case REG_ASRPM5:
597 case REG_ASRTFR1:
598 case REG_ASRCCR:
599 case REG_ASRDOA:
600 case REG_ASRDOB:
601 case REG_ASRDOC:
602 case REG_ASRIDRHA:
603 case REG_ASRIDRLA:
604 case REG_ASRIDRHB:
605 case REG_ASRIDRLB:
606 case REG_ASRIDRHC:
607 case REG_ASRIDRLC:
608 case REG_ASR76K:
609 case REG_ASR56K:
610 case REG_ASRMCRA:
611 case REG_ASRFSTA:
612 case REG_ASRMCRB:
613 case REG_ASRFSTB:
614 case REG_ASRMCRC:
615 case REG_ASRFSTC:
616 case REG_ASRMCR1A:
617 case REG_ASRMCR1B:
618 case REG_ASRMCR1C:
619 return true;
620 default:
621 return false;
622 }
623}
624
625static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
626{
627 switch (reg) {
628 case REG_ASRSTR:
629 case REG_ASRDIA:
630 case REG_ASRDIB:
631 case REG_ASRDIC:
632 case REG_ASRDOA:
633 case REG_ASRDOB:
634 case REG_ASRDOC:
635 case REG_ASRFSTA:
636 case REG_ASRFSTB:
637 case REG_ASRFSTC:
638 case REG_ASRCFG:
639 return true;
640 default:
641 return false;
642 }
643}
644
645static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
646{
647 switch (reg) {
648 case REG_ASRCTR:
649 case REG_ASRIER:
650 case REG_ASRCNCR:
651 case REG_ASRCFG:
652 case REG_ASRCSR:
653 case REG_ASRCDR1:
654 case REG_ASRCDR2:
655 case REG_ASRSTR:
656 case REG_ASRPM1:
657 case REG_ASRPM2:
658 case REG_ASRPM3:
659 case REG_ASRPM4:
660 case REG_ASRPM5:
661 case REG_ASRTFR1:
662 case REG_ASRCCR:
663 case REG_ASRDIA:
664 case REG_ASRDIB:
665 case REG_ASRDIC:
666 case REG_ASRIDRHA:
667 case REG_ASRIDRLA:
668 case REG_ASRIDRHB:
669 case REG_ASRIDRLB:
670 case REG_ASRIDRHC:
671 case REG_ASRIDRLC:
672 case REG_ASR76K:
673 case REG_ASR56K:
674 case REG_ASRMCRA:
675 case REG_ASRMCRB:
676 case REG_ASRMCRC:
677 case REG_ASRMCR1A:
678 case REG_ASRMCR1B:
679 case REG_ASRMCR1C:
680 return true;
681 default:
682 return false;
683 }
684}
685
86a570c5
NC		 686static struct reg_default fsl_asrc_reg[] = {
687 { REG_ASRCTR, 0x0000 }, { REG_ASRIER, 0x0000 },
688 { REG_ASRCNCR, 0x0000 }, { REG_ASRCFG, 0x0000 },
689 { REG_ASRCSR, 0x0000 }, { REG_ASRCDR1, 0x0000 },
690 { REG_ASRCDR2, 0x0000 }, { REG_ASRSTR, 0x0000 },
691 { REG_ASRRA, 0x0000 }, { REG_ASRRB, 0x0000 },
692 { REG_ASRRC, 0x0000 }, { REG_ASRPM1, 0x0000 },
693 { REG_ASRPM2, 0x0000 }, { REG_ASRPM3, 0x0000 },
694 { REG_ASRPM4, 0x0000 }, { REG_ASRPM5, 0x0000 },
695 { REG_ASRTFR1, 0x0000 }, { REG_ASRCCR, 0x0000 },
696 { REG_ASRDIA, 0x0000 }, { REG_ASRDOA, 0x0000 },
697 { REG_ASRDIB, 0x0000 }, { REG_ASRDOB, 0x0000 },
698 { REG_ASRDIC, 0x0000 }, { REG_ASRDOC, 0x0000 },
699 { REG_ASRIDRHA, 0x0000 }, { REG_ASRIDRLA, 0x0000 },
700 { REG_ASRIDRHB, 0x0000 }, { REG_ASRIDRLB, 0x0000 },
701 { REG_ASRIDRHC, 0x0000 }, { REG_ASRIDRLC, 0x0000 },
702 { REG_ASR76K, 0x0A47 }, { REG_ASR56K, 0x0DF3 },
703 { REG_ASRMCRA, 0x0000 }, { REG_ASRFSTA, 0x0000 },
704 { REG_ASRMCRB, 0x0000 }, { REG_ASRFSTB, 0x0000 },
705 { REG_ASRMCRC, 0x0000 }, { REG_ASRFSTC, 0x0000 },
706 { REG_ASRMCR1A, 0x0000 }, { REG_ASRMCR1B, 0x0000 },
707 { REG_ASRMCR1C, 0x0000 },
708};
709
bf16d883 710static const struct regmap_config fsl_asrc_regmap_config = {
3117bb31
NC		 711 .reg_bits = 32,
712 .reg_stride = 4,
713 .val_bits = 32,
714
715 .max_register = REG_ASRMCR1C,
86a570c5
NC		 716 .reg_defaults = fsl_asrc_reg,
717 .num_reg_defaults = ARRAY_SIZE(fsl_asrc_reg),
3117bb31
NC		 718 .readable_reg = fsl_asrc_readable_reg,
719 .volatile_reg = fsl_asrc_volatile_reg,
720 .writeable_reg = fsl_asrc_writeable_reg,
b4138868 721 .cache_type = REGCACHE_FLAT,
3117bb31
NC		 722};
723
724/**
725 * Initialize ASRC registers with a default configurations
726 */
727static int fsl_asrc_init(struct fsl_asrc *asrc_priv)
728{
729 /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
730 regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
731
732 /* Disable interrupt by default */
733 regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0);
734
735 /* Apply recommended settings for parameters from Reference Manual */
736 regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff);
737 regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555);
738 regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280);
739 regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280);
740 regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280);
741
742 /* Base address for task queue FIFO. Set to 0x7C */
743 regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1,
744 ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
745
746 /* Set the processing clock for 76KHz to 133M */
747 regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6);
748
749 /* Set the processing clock for 56KHz to 133M */
750 return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947);
751}
752
753/**
754 * Interrupt handler for ASRC
755 */
756static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
757{
758 struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id;
759 struct device *dev = &asrc_priv->pdev->dev;
760 enum asrc_pair_index index;
761 u32 status;
762
763 regmap_read(asrc_priv->regmap, REG_ASRSTR, &status);
764
765 /* Clean overload error */
766 regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE);
767
768 /*
769 * We here use dev_dbg() for all exceptions because ASRC itself does
770 * not care if FIFO overflowed or underrun while a warning in the
771 * interrupt would result a ridged conversion.
772 */
773 for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
774 if (!asrc_priv->pair[index])
775 continue;
776
777 if (status & ASRSTR_ATQOL) {
778 asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
779 dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
780 }
781
782 if (status & ASRSTR_AOOL(index)) {
783 asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
784 pair_dbg("Output Task Overload\n");
785 }
786
787 if (status & ASRSTR_AIOL(index)) {
788 asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
789 pair_dbg("Input Task Overload\n");
790 }
791
792 if (status & ASRSTR_AODO(index)) {
793 asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
794 pair_dbg("Output Data Buffer has overflowed\n");
795 }
796
797 if (status & ASRSTR_AIDU(index)) {
798 asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
799 pair_dbg("Input Data Buffer has underflowed\n");
800 }
801 }
802
803 return IRQ_HANDLED;
804}
805
806static int fsl_asrc_probe(struct platform_device *pdev)
807{
808 struct device_node *np = pdev->dev.of_node;
809 struct fsl_asrc *asrc_priv;
810 struct resource *res;
811 void __iomem *regs;
812 int irq, ret, i;
813 char tmp[16];
814
815 asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
816 if (!asrc_priv)
817 return -ENOMEM;
818
819 asrc_priv->pdev = pdev;
3117bb31
NC		 820
821 /* Get the addresses and IRQ */
822 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
823 regs = devm_ioremap_resource(&pdev->dev, res);
824 if (IS_ERR(regs))
825 return PTR_ERR(regs);
826
827 asrc_priv->paddr = res->start;
828
3117bb31
NC		 829 asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
830 &fsl_asrc_regmap_config);
831 if (IS_ERR(asrc_priv->regmap)) {
832 dev_err(&pdev->dev, "failed to init regmap\n");
833 return PTR_ERR(asrc_priv->regmap);
834 }
835
836 irq = platform_get_irq(pdev, 0);
837 if (irq < 0) {
f03038e5 838 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
3117bb31
NC		 839 return irq;
840 }
841
842 ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
888c819d 843 dev_name(&pdev->dev), asrc_priv);
3117bb31
NC		 844 if (ret) {
845 dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
846 return ret;
847 }
848
849 asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem");
850 if (IS_ERR(asrc_priv->mem_clk)) {
851 dev_err(&pdev->dev, "failed to get mem clock\n");
d387dd08 852 return PTR_ERR(asrc_priv->mem_clk);
3117bb31
NC		 853 }
854
855 asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
856 if (IS_ERR(asrc_priv->ipg_clk)) {
857 dev_err(&pdev->dev, "failed to get ipg clock\n");
858 return PTR_ERR(asrc_priv->ipg_clk);
859 }
860
13b8a97a
SW		 861 asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba");
862 if (IS_ERR(asrc_priv->spba_clk))
863 dev_warn(&pdev->dev, "failed to get spba clock\n");
864
3117bb31
NC		 865 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
866 sprintf(tmp, "asrck_%x", i);
867 asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
868 if (IS_ERR(asrc_priv->asrck_clk[i])) {
869 dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
870 return PTR_ERR(asrc_priv->asrck_clk[i]);
871 }
872 }
873
f3d8ac8c 874 if (of_device_is_compatible(np, "fsl,imx35-asrc")) {
3117bb31
NC		 875 asrc_priv->channel_bits = 3;
876 clk_map[IN] = input_clk_map_imx35;
877 clk_map[OUT] = output_clk_map_imx35;
878 } else {
879 asrc_priv->channel_bits = 4;
880 clk_map[IN] = input_clk_map_imx53;
881 clk_map[OUT] = output_clk_map_imx53;
882 }
883
884 ret = fsl_asrc_init(asrc_priv);
885 if (ret) {
886 dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
c0296950 887 return ret;
3117bb31
NC		 888 }
889
890 asrc_priv->channel_avail = 10;
891
892 ret = of_property_read_u32(np, "fsl,asrc-rate",
893 &asrc_priv->asrc_rate);
894 if (ret) {
895 dev_err(&pdev->dev, "failed to get output rate\n");
c0296950 896 return ret;
3117bb31
NC		 897 }
898
899 ret = of_property_read_u32(np, "fsl,asrc-width",
900 &asrc_priv->asrc_width);
901 if (ret) {
902 dev_err(&pdev->dev, "failed to get output width\n");
c0296950 903 return ret;
3117bb31
NC		 904 }
905
906 if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) {
907 dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n");
908 asrc_priv->asrc_width = 24;
909 }
910
911 platform_set_drvdata(pdev, asrc_priv);
912 pm_runtime_enable(&pdev->dev);
913 spin_lock_init(&asrc_priv->lock);
914
915 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
916 &fsl_asrc_dai, 1);
917 if (ret) {
918 dev_err(&pdev->dev, "failed to register ASoC DAI\n");
919 return ret;
920 }
921
3117bb31
NC		 922 return 0;
923}
924
641d334b 925#ifdef CONFIG_PM
3117bb31
NC		 926static int fsl_asrc_runtime_resume(struct device *dev)
927{
928 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
b1ade0f2 929 int i, ret;
3117bb31 930
b1ade0f2
FE		 931 ret = clk_prepare_enable(asrc_priv->mem_clk);
932 if (ret)
933 return ret;
934 ret = clk_prepare_enable(asrc_priv->ipg_clk);
935 if (ret)
936 goto disable_mem_clk;
13b8a97a
SW		 937 if (!IS_ERR(asrc_priv->spba_clk)) {
938 ret = clk_prepare_enable(asrc_priv->spba_clk);
939 if (ret)
940 goto disable_ipg_clk;
941 }
b1ade0f2
FE		 942 for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
943 ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
944 if (ret)
945 goto disable_asrck_clk;
946 }
3117bb31
NC		 947
948 return 0;
b1ade0f2
FE		 949
950disable_asrck_clk:
951 for (i--; i >= 0; i--)
952 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
13b8a97a
SW		 953 if (!IS_ERR(asrc_priv->spba_clk))
954 clk_disable_unprepare(asrc_priv->spba_clk);
955disable_ipg_clk:
b1ade0f2
FE		 956 clk_disable_unprepare(asrc_priv->ipg_clk);
957disable_mem_clk:
958 clk_disable_unprepare(asrc_priv->mem_clk);
959 return ret;
3117bb31
NC		 960}
961
962static int fsl_asrc_runtime_suspend(struct device *dev)
963{
964 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
965 int i;
966
967 for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
968 clk_disable_unprepare(asrc_priv->asrck_clk[i]);
13b8a97a
SW		 969 if (!IS_ERR(asrc_priv->spba_clk))
970 clk_disable_unprepare(asrc_priv->spba_clk);
3117bb31
NC		 971 clk_disable_unprepare(asrc_priv->ipg_clk);
972 clk_disable_unprepare(asrc_priv->mem_clk);
973
974 return 0;
975}
641d334b 976#endif /* CONFIG_PM */
3117bb31 977
d3dacda9 978#ifdef CONFIG_PM_SLEEP
3117bb31
NC		 979static int fsl_asrc_suspend(struct device *dev)
980{
981 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
982
d44c6114
ZW		 983 regmap_read(asrc_priv->regmap, REG_ASRCFG,
984 &asrc_priv->regcache_cfg);
985
3117bb31
NC		 986 regcache_cache_only(asrc_priv->regmap, true);
987 regcache_mark_dirty(asrc_priv->regmap);
988
989 return 0;
990}
991
992static int fsl_asrc_resume(struct device *dev)
993{
994 struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
995 u32 asrctr;
996
997 /* Stop all pairs provisionally */
998 regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr);
999 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1000 ASRCTR_ASRCEi_ALL_MASK, 0);
1001
1002 /* Restore all registers */
1003 regcache_cache_only(asrc_priv->regmap, false);
1004 regcache_sync(asrc_priv->regmap);
1005
d44c6114
ZW		 1006 regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
1007 ASRCFG_NDPRi_ALL_MASK | ASRCFG_POSTMODi_ALL_MASK |
1008 ASRCFG_PREMODi_ALL_MASK, asrc_priv->regcache_cfg);
1009
3117bb31
NC		 1010 /* Restart enabled pairs */
1011 regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
1012 ASRCTR_ASRCEi_ALL_MASK, asrctr);
1013
1014 return 0;
1015}
1016#endif /* CONFIG_PM_SLEEP */
1017
1018static const struct dev_pm_ops fsl_asrc_pm = {
1019 SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
1020 SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume)
1021};
1022
1023static const struct of_device_id fsl_asrc_ids[] = {
1024 { .compatible = "fsl,imx35-asrc", },
1025 { .compatible = "fsl,imx53-asrc", },
1026 {}
1027};
1028MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
1029
1030static struct platform_driver fsl_asrc_driver = {
1031 .probe = fsl_asrc_probe,
1032 .driver = {
1033 .name = "fsl-asrc",
1034 .of_match_table = fsl_asrc_ids,
1035 .pm = &fsl_asrc_pm,
1036 },
1037};
1038module_platform_driver(fsl_asrc_driver);
1039
1040MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
1041MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>");
1042MODULE_ALIAS("platform:fsl-asrc");
1043MODULE_LICENSE("GPL v2");
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