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79361b2b JA |
1 | /* |
2 | * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com) | |
3 | * | |
4 | * This file is licensed under the terms of the GNU General Public | |
5 | * License version 2. This program is licensed "as is" without any | |
6 | * warranty of any kind, whether express or implied. | |
7 | */ | |
8 | ||
9 | #ifndef __DESIGNWARE_LOCAL_H | |
10 | #define __DESIGNWARE_LOCAL_H | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/device.h> | |
14 | #include <linux/types.h> | |
15 | #include <sound/dmaengine_pcm.h> | |
16 | #include <sound/pcm.h> | |
17 | #include <sound/designware_i2s.h> | |
18 | ||
19 | /* common register for all channel */ | |
20 | #define IER 0x000 | |
21 | #define IRER 0x004 | |
22 | #define ITER 0x008 | |
23 | #define CER 0x00C | |
24 | #define CCR 0x010 | |
25 | #define RXFFR 0x014 | |
26 | #define TXFFR 0x018 | |
27 | ||
221acc16 MK |
28 | /* Enable register fields */ |
29 | #define IER_TDM_SLOTS_SHIFT 8 | |
30 | #define IER_FRAME_OFF_SHIFT 5 | |
31 | #define IER_FRAME_OFF BIT(5) | |
32 | #define IER_INTF_TYPE BIT(1) | |
33 | #define IER_IEN BIT(0) | |
34 | ||
79361b2b JA |
35 | /* Interrupt status register fields */ |
36 | #define ISR_TXFO BIT(5) | |
37 | #define ISR_TXFE BIT(4) | |
38 | #define ISR_RXFO BIT(1) | |
39 | #define ISR_RXDA BIT(0) | |
40 | ||
41 | /* I2STxRxRegisters for all channels */ | |
42 | #define LRBR_LTHR(x) (0x40 * x + 0x020) | |
43 | #define RRBR_RTHR(x) (0x40 * x + 0x024) | |
44 | #define RER(x) (0x40 * x + 0x028) | |
45 | #define TER(x) (0x40 * x + 0x02C) | |
46 | #define RCR(x) (0x40 * x + 0x030) | |
47 | #define TCR(x) (0x40 * x + 0x034) | |
48 | #define ISR(x) (0x40 * x + 0x038) | |
49 | #define IMR(x) (0x40 * x + 0x03C) | |
50 | #define ROR(x) (0x40 * x + 0x040) | |
51 | #define TOR(x) (0x40 * x + 0x044) | |
52 | #define RFCR(x) (0x40 * x + 0x048) | |
53 | #define TFCR(x) (0x40 * x + 0x04C) | |
54 | #define RFF(x) (0x40 * x + 0x050) | |
55 | #define TFF(x) (0x40 * x + 0x054) | |
221acc16 MK |
56 | #define RSLOT_TSLOT(x) (0x4 * (x) + 0x224) |
57 | ||
58 | /* Receive enable register fields */ | |
59 | #define RER_RXSLOT_SHIFT 8 | |
60 | #define RER_RXCHEN BIT(0) | |
61 | ||
62 | /* Transmit enable register fields */ | |
63 | #define TER_TXSLOT_SHIFT 8 | |
64 | #define TER_TXCHEN BIT(0) | |
79361b2b JA |
65 | |
66 | /* I2SCOMPRegisters */ | |
67 | #define I2S_COMP_PARAM_2 0x01F0 | |
68 | #define I2S_COMP_PARAM_1 0x01F4 | |
69 | #define I2S_COMP_VERSION 0x01F8 | |
70 | #define I2S_COMP_TYPE 0x01FC | |
71 | ||
a42e988b MK |
72 | #define I2S_RRXDMA 0x01C4 |
73 | #define I2S_RTXDMA 0x01CC | |
74 | #define I2S_DMACR 0x0200 | |
75 | #define I2S_DMAEN_RXBLOCK (1 << 16) | |
76 | #define I2S_DMAEN_TXBLOCK (1 << 17) | |
77 | ||
79361b2b JA |
78 | /* |
79 | * Component parameter register fields - define the I2S block's | |
80 | * configuration. | |
81 | */ | |
82 | #define COMP1_TX_WORDSIZE_3(r) (((r) & GENMASK(27, 25)) >> 25) | |
83 | #define COMP1_TX_WORDSIZE_2(r) (((r) & GENMASK(24, 22)) >> 22) | |
84 | #define COMP1_TX_WORDSIZE_1(r) (((r) & GENMASK(21, 19)) >> 19) | |
85 | #define COMP1_TX_WORDSIZE_0(r) (((r) & GENMASK(18, 16)) >> 16) | |
86 | #define COMP1_TX_CHANNELS(r) (((r) & GENMASK(10, 9)) >> 9) | |
87 | #define COMP1_RX_CHANNELS(r) (((r) & GENMASK(8, 7)) >> 7) | |
88 | #define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6) | |
89 | #define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5) | |
90 | #define COMP1_MODE_EN(r) (((r) & BIT(4)) >> 4) | |
91 | #define COMP1_FIFO_DEPTH_GLOBAL(r) (((r) & GENMASK(3, 2)) >> 2) | |
92 | #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0) | |
93 | ||
94 | #define COMP2_RX_WORDSIZE_3(r) (((r) & GENMASK(12, 10)) >> 10) | |
95 | #define COMP2_RX_WORDSIZE_2(r) (((r) & GENMASK(9, 7)) >> 7) | |
96 | #define COMP2_RX_WORDSIZE_1(r) (((r) & GENMASK(5, 3)) >> 3) | |
97 | #define COMP2_RX_WORDSIZE_0(r) (((r) & GENMASK(2, 0)) >> 0) | |
98 | ||
99 | /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */ | |
100 | #define COMP_MAX_WORDSIZE (1 << 3) | |
101 | #define COMP_MAX_DATA_WIDTH (1 << 2) | |
102 | ||
103 | #define MAX_CHANNEL_NUM 8 | |
104 | #define MIN_CHANNEL_NUM 2 | |
105 | ||
106 | union dw_i2s_snd_dma_data { | |
107 | struct i2s_dma_data pd; | |
108 | struct snd_dmaengine_dai_dma_data dt; | |
109 | }; | |
110 | ||
111 | struct dw_i2s_dev { | |
112 | void __iomem *i2s_base; | |
113 | struct clk *clk; | |
c00018ca | 114 | struct reset_control *reset; |
79361b2b JA |
115 | int active; |
116 | unsigned int capability; | |
117 | unsigned int quirks; | |
118 | unsigned int i2s_reg_comp1; | |
119 | unsigned int i2s_reg_comp2; | |
120 | struct device *dev; | |
121 | u32 ccr; | |
122 | u32 xfer_resolution; | |
123 | u32 fifo_th; | |
221acc16 MK |
124 | u32 l_reg; |
125 | u32 r_reg; | |
52ea7c05 | 126 | bool is_jh7110; /* Flag for StarFive JH7110 SoC */ |
79361b2b JA |
127 | |
128 | /* data related to DMA transfers b/w i2s and DMAC */ | |
129 | union dw_i2s_snd_dma_data play_dma_data; | |
130 | union dw_i2s_snd_dma_data capture_dma_data; | |
131 | struct i2s_clk_config_data config; | |
132 | int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); | |
133 | ||
e2f748e0 | 134 | /* data related to PIO transfers */ |
79361b2b | 135 | bool use_pio; |
221acc16 MK |
136 | |
137 | /* data related to TDM mode */ | |
138 | u32 tdm_slots; | |
139 | u32 tdm_mask; | |
140 | u32 frame_offset; | |
141 | ||
79361b2b | 142 | struct snd_pcm_substream __rcu *tx_substream; |
e2f748e0 | 143 | struct snd_pcm_substream __rcu *rx_substream; |
79361b2b JA |
144 | unsigned int (*tx_fn)(struct dw_i2s_dev *dev, |
145 | struct snd_pcm_runtime *runtime, unsigned int tx_ptr, | |
146 | bool *period_elapsed); | |
e2f748e0 JA |
147 | unsigned int (*rx_fn)(struct dw_i2s_dev *dev, |
148 | struct snd_pcm_runtime *runtime, unsigned int rx_ptr, | |
149 | bool *period_elapsed); | |
79361b2b | 150 | unsigned int tx_ptr; |
e2f748e0 | 151 | unsigned int rx_ptr; |
79361b2b JA |
152 | }; |
153 | ||
154 | #if IS_ENABLED(CONFIG_SND_DESIGNWARE_PCM) | |
155 | void dw_pcm_push_tx(struct dw_i2s_dev *dev); | |
e2f748e0 | 156 | void dw_pcm_pop_rx(struct dw_i2s_dev *dev); |
79361b2b JA |
157 | int dw_pcm_register(struct platform_device *pdev); |
158 | #else | |
0803a5cb Y |
159 | static inline void dw_pcm_push_tx(struct dw_i2s_dev *dev) { } |
160 | static inline void dw_pcm_pop_rx(struct dw_i2s_dev *dev) { } | |
161 | static inline int dw_pcm_register(struct platform_device *pdev) | |
79361b2b JA |
162 | { |
163 | return -EINVAL; | |
164 | } | |
165 | #endif | |
166 | ||
167 | #endif |