projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: Remove unused 'saved_value' field from snd_soc_dapm_widget struct
[linux-2.6-block.git] / sound / soc / davinci / davinci-mcasp.c
CommitLineData
b67f4487
C		 1/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
5a0e3ad6 21#include <linux/slab.h>
b67f4487
C		 22#include <linux/delay.h>
23#include <linux/io.h>
10884347 24#include <linux/pm_runtime.h>
3e3b8c34
HG		 25#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/of_device.h>
b67f4487
C		 28
29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/initval.h>
33#include <sound/soc.h>
34
35#include "davinci-pcm.h"
36#include "davinci-mcasp.h"
37
38/*
39 * McASP register definitions
40 */
41#define DAVINCI_MCASP_PID_REG 0x00
42#define DAVINCI_MCASP_PWREMUMGT_REG 0x04
43
44#define DAVINCI_MCASP_PFUNC_REG 0x10
45#define DAVINCI_MCASP_PDIR_REG 0x14
46#define DAVINCI_MCASP_PDOUT_REG 0x18
47#define DAVINCI_MCASP_PDSET_REG 0x1c
48
49#define DAVINCI_MCASP_PDCLR_REG 0x20
50
51#define DAVINCI_MCASP_TLGC_REG 0x30
52#define DAVINCI_MCASP_TLMR_REG 0x34
53
54#define DAVINCI_MCASP_GBLCTL_REG 0x44
55#define DAVINCI_MCASP_AMUTE_REG 0x48
56#define DAVINCI_MCASP_LBCTL_REG 0x4c
57
58#define DAVINCI_MCASP_TXDITCTL_REG 0x50
59
60#define DAVINCI_MCASP_GBLCTLR_REG 0x60
61#define DAVINCI_MCASP_RXMASK_REG 0x64
62#define DAVINCI_MCASP_RXFMT_REG 0x68
63#define DAVINCI_MCASP_RXFMCTL_REG 0x6c
64
65#define DAVINCI_MCASP_ACLKRCTL_REG 0x70
66#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
67#define DAVINCI_MCASP_RXTDM_REG 0x78
68#define DAVINCI_MCASP_EVTCTLR_REG 0x7c
69
70#define DAVINCI_MCASP_RXSTAT_REG 0x80
71#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
72#define DAVINCI_MCASP_RXCLKCHK_REG 0x88
73#define DAVINCI_MCASP_REVTCTL_REG 0x8c
74
75#define DAVINCI_MCASP_GBLCTLX_REG 0xa0
76#define DAVINCI_MCASP_TXMASK_REG 0xa4
77#define DAVINCI_MCASP_TXFMT_REG 0xa8
78#define DAVINCI_MCASP_TXFMCTL_REG 0xac
79
80#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
81#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
82#define DAVINCI_MCASP_TXTDM_REG 0xb8
83#define DAVINCI_MCASP_EVTCTLX_REG 0xbc
84
85#define DAVINCI_MCASP_TXSTAT_REG 0xc0
86#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
87#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
88#define DAVINCI_MCASP_XEVTCTL_REG 0xcc
89
90/* Left(even TDM Slot) Channel Status Register File */
91#define DAVINCI_MCASP_DITCSRA_REG 0x100
92/* Right(odd TDM slot) Channel Status Register File */
93#define DAVINCI_MCASP_DITCSRB_REG 0x118
94/* Left(even TDM slot) User Data Register File */
95#define DAVINCI_MCASP_DITUDRA_REG 0x130
96/* Right(odd TDM Slot) User Data Register File */
97#define DAVINCI_MCASP_DITUDRB_REG 0x148
98
99/* Serializer n Control Register */
100#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
101#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
102 (n << 2))
103
104/* Transmit Buffer for Serializer n */
105#define DAVINCI_MCASP_TXBUF_REG 0x200
106/* Receive Buffer for Serializer n */
107#define DAVINCI_MCASP_RXBUF_REG 0x280
108
6a99fb5f
C		 109/* McASP FIFO Registers */
110#define DAVINCI_MCASP_WFIFOCTL (0x1010)
111#define DAVINCI_MCASP_WFIFOSTS (0x1014)
112#define DAVINCI_MCASP_RFIFOCTL (0x1018)
113#define DAVINCI_MCASP_RFIFOSTS (0x101C)
b67f4487
C		 114
115/*
116 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
117 * Register Bits
118 */
119#define MCASP_FREE BIT(0)
120#define MCASP_SOFT BIT(1)
121
122/*
123 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
124 */
125#define AXR(n) (1<<n)
126#define PFUNC_AMUTE BIT(25)
127#define ACLKX BIT(26)
128#define AHCLKX BIT(27)
129#define AFSX BIT(28)
130#define ACLKR BIT(29)
131#define AHCLKR BIT(30)
132#define AFSR BIT(31)
133
134/*
135 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
136 */
137#define AXR(n) (1<<n)
138#define PDIR_AMUTE BIT(25)
139#define ACLKX BIT(26)
140#define AHCLKX BIT(27)
141#define AFSX BIT(28)
142#define ACLKR BIT(29)
143#define AHCLKR BIT(30)
144#define AFSR BIT(31)
145
146/*
147 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
148 */
149#define DITEN BIT(0) /* Transmit DIT mode enable/disable */
150#define VA BIT(2)
151#define VB BIT(3)
152
153/*
154 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
155 */
156#define TXROT(val) (val)
157#define TXSEL BIT(3)
158#define TXSSZ(val) (val<<4)
159#define TXPBIT(val) (val<<8)
160#define TXPAD(val) (val<<13)
161#define TXORD BIT(15)
162#define FSXDLY(val) (val<<16)
163
164/*
165 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
166 */
167#define RXROT(val) (val)
168#define RXSEL BIT(3)
169#define RXSSZ(val) (val<<4)
170#define RXPBIT(val) (val<<8)
171#define RXPAD(val) (val<<13)
172#define RXORD BIT(15)
173#define FSRDLY(val) (val<<16)
174
175/*
176 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
177 */
178#define FSXPOL BIT(0)
179#define AFSXE BIT(1)
180#define FSXDUR BIT(4)
181#define FSXMOD(val) (val<<7)
182
183/*
184 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
185 */
186#define FSRPOL BIT(0)
187#define AFSRE BIT(1)
188#define FSRDUR BIT(4)
189#define FSRMOD(val) (val<<7)
190
191/*
192 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
193 */
194#define ACLKXDIV(val) (val)
195#define ACLKXE BIT(5)
196#define TX_ASYNC BIT(6)
197#define ACLKXPOL BIT(7)
198
199/*
200 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
201 */
202#define ACLKRDIV(val) (val)
203#define ACLKRE BIT(5)
204#define RX_ASYNC BIT(6)
205#define ACLKRPOL BIT(7)
206
207/*
208 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
209 * Register Bits
210 */
211#define AHCLKXDIV(val) (val)
212#define AHCLKXPOL BIT(14)
213#define AHCLKXE BIT(15)
214
215/*
216 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
217 * Register Bits
218 */
219#define AHCLKRDIV(val) (val)
220#define AHCLKRPOL BIT(14)
221#define AHCLKRE BIT(15)
222
223/*
224 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
225 */
226#define MODE(val) (val)
227#define DISMOD (val)(val<<2)
228#define TXSTATE BIT(4)
229#define RXSTATE BIT(5)
230
231/*
232 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
233 */
234#define LBEN BIT(0)
235#define LBORD BIT(1)
236#define LBGENMODE(val) (val<<2)
237
238/*
239 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
240 */
241#define TXTDMS(n) (1<<n)
242
243/*
244 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
245 */
246#define RXTDMS(n) (1<<n)
247
248/*
249 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
250 */
251#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
252#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
253#define RXSERCLR BIT(2) /* Receiver Serializer Clear */
254#define RXSMRST BIT(3) /* Receiver State Machine Reset */
255#define RXFSRST BIT(4) /* Frame Sync Generator Reset */
256#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
257#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
258#define TXSERCLR BIT(10) /* Transmit Serializer Clear */
259#define TXSMRST BIT(11) /* Transmitter State Machine Reset */
260#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
261
262/*
263 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
264 */
265#define MUTENA(val) (val)
266#define MUTEINPOL BIT(2)
267#define MUTEINENA BIT(3)
268#define MUTEIN BIT(4)
269#define MUTER BIT(5)
270#define MUTEX BIT(6)
271#define MUTEFSR BIT(7)
272#define MUTEFSX BIT(8)
273#define MUTEBADCLKR BIT(9)
274#define MUTEBADCLKX BIT(10)
275#define MUTERXDMAERR BIT(11)
276#define MUTETXDMAERR BIT(12)
277
278/*
279 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
280 */
281#define RXDATADMADIS BIT(0)
282
283/*
284 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
285 */
286#define TXDATADMADIS BIT(0)
287
6a99fb5f
C		 288/*
289 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
290 */
291#define FIFO_ENABLE BIT(16)
292#define NUMEVT_MASK (0xFF << 8)
293#define NUMDMA_MASK (0xFF)
294
b67f4487
C		 295#define DAVINCI_MCASP_NUM_SERIALIZER 16
296
297static inline void mcasp_set_bits(void __iomem *reg, u32 val)
298{
299 __raw_writel(__raw_readl(reg) | val, reg);
300}
301
302static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
303{
304 __raw_writel((__raw_readl(reg) & ~(val)), reg);
305}
306
307static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
308{
309 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
310}
311
312static inline void mcasp_set_reg(void __iomem *reg, u32 val)
313{
314 __raw_writel(val, reg);
315}
316
317static inline u32 mcasp_get_reg(void __iomem *reg)
318{
319 return (unsigned int)__raw_readl(reg);
320}
321
322static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
323{
324 int i = 0;
325
326 mcasp_set_bits(regs, val);
327
328 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
329 /* loop count is to avoid the lock-up */
330 for (i = 0; i < 1000; i++) {
331 if ((mcasp_get_reg(regs) & val) == val)
332 break;
333 }
334
335 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
336 printk(KERN_ERR "GBLCTL write error\n");
337}
338
b67f4487
C		 339static void mcasp_start_rx(struct davinci_audio_dev *dev)
340{
341 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
342 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
343 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
344 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
345
346 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
347 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
348 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
349
350 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
352}
353
354static void mcasp_start_tx(struct davinci_audio_dev *dev)
355{
6a99fb5f
C		 356 u8 offset = 0, i;
357 u32 cnt;
358
b67f4487
C		 359 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
360 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
361 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
362 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
363
364 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
365 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
366 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
6a99fb5f
C		 367 for (i = 0; i < dev->num_serializer; i++) {
368 if (dev->serial_dir[i] == TX_MODE) {
369 offset = i;
370 break;
371 }
372 }
373
374 /* wait for TX ready */
375 cnt = 0;
376 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
377 TXSTATE) && (cnt < 100000))
378 cnt++;
379
b67f4487
C		 380 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
381}
382
383static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
384{
539d3d8c 385 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
0d624275
VB		 386 if (dev->txnumevt) { /* enable FIFO */
387 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
388 FIFO_ENABLE);
539d3d8c
C		 389 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
390 FIFO_ENABLE);
0d624275 391 }
b67f4487 392 mcasp_start_tx(dev);
539d3d8c 393 } else {
0d624275
VB		 394 if (dev->rxnumevt) { /* enable FIFO */
395 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
396 FIFO_ENABLE);
539d3d8c
C		 397 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
398 FIFO_ENABLE);
0d624275 399 }
b67f4487 400 mcasp_start_rx(dev);
539d3d8c 401 }
b67f4487
C		 402}
403
404static void mcasp_stop_rx(struct davinci_audio_dev *dev)
405{
406 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
407 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
408}
409
410static void mcasp_stop_tx(struct davinci_audio_dev *dev)
411{
412 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
413 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
414}
415
416static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
417{
539d3d8c
C		 418 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
419 if (dev->txnumevt) /* disable FIFO */
420 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
421 FIFO_ENABLE);
b67f4487 422 mcasp_stop_tx(dev);
539d3d8c
C		 423 } else {
424 if (dev->rxnumevt) /* disable FIFO */
425 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
426 FIFO_ENABLE);
b67f4487 427 mcasp_stop_rx(dev);
539d3d8c 428 }
b67f4487
C		 429}
430
431static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
432 unsigned int fmt)
433{
f0fba2ad 434 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 435 void __iomem *base = dev->base;
436
437 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
438 case SND_SOC_DAIFMT_CBS_CFS:
439 /* codec is clock and frame slave */
440 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
441 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
442
443 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
444 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
445
9595c8f0
BG		 446 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
447 ACLKX | AHCLKX | AFSX);
b67f4487 448 break;
517ee6cf
C		 449 case SND_SOC_DAIFMT_CBM_CFS:
450 /* codec is clock master and frame slave */
a90f549e 451 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
517ee6cf
C		 452 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
453
a90f549e 454 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
517ee6cf
C		 455 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
456
db92f437
BG		 457 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
458 ACLKX | ACLKR);
9595c8f0 459 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
db92f437 460 AFSX | AFSR);
517ee6cf 461 break;
b67f4487
C		 462 case SND_SOC_DAIFMT_CBM_CFM:
463 /* codec is clock and frame master */
464 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
465 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
466
467 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
468 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
469
9595c8f0
BG		 470 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
471 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
b67f4487
C		 472 break;
473
474 default:
475 return -EINVAL;
476 }
477
478 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
479 case SND_SOC_DAIFMT_IB_NF:
480 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
481 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
482
483 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
484 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
485 break;
486
487 case SND_SOC_DAIFMT_NB_IF:
488 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
489 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
490
491 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
492 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
493 break;
494
495 case SND_SOC_DAIFMT_IB_IF:
496 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
497 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
498
499 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
500 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
501 break;
502
503 case SND_SOC_DAIFMT_NB_NF:
504 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
505 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
506
507 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
508 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
509 break;
510
511 default:
512 return -EINVAL;
513 }
514
515 return 0;
516}
517
518static int davinci_config_channel_size(struct davinci_audio_dev *dev,
519 int channel_size)
520{
521 u32 fmt = 0;
0c31cf3e 522 u32 mask, rotate;
b67f4487
C		 523
524 switch (channel_size) {
525 case DAVINCI_AUDIO_WORD_8:
526 fmt = 0x03;
0c31cf3e
C		 527 rotate = 6;
528 mask = 0x000000ff;
b67f4487
C		 529 break;
530
531 case DAVINCI_AUDIO_WORD_12:
532 fmt = 0x05;
0c31cf3e
C		 533 rotate = 5;
534 mask = 0x00000fff;
b67f4487
C		 535 break;
536
537 case DAVINCI_AUDIO_WORD_16:
538 fmt = 0x07;
0c31cf3e
C		 539 rotate = 4;
540 mask = 0x0000ffff;
b67f4487
C		 541 break;
542
543 case DAVINCI_AUDIO_WORD_20:
544 fmt = 0x09;
0c31cf3e
C		 545 rotate = 3;
546 mask = 0x000fffff;
b67f4487
C		 547 break;
548
549 case DAVINCI_AUDIO_WORD_24:
550 fmt = 0x0B;
0c31cf3e
C		 551 rotate = 2;
552 mask = 0x00ffffff;
b67f4487
C		 553 break;
554
555 case DAVINCI_AUDIO_WORD_28:
556 fmt = 0x0D;
0c31cf3e
C		 557 rotate = 1;
558 mask = 0x0fffffff;
b67f4487
C		 559 break;
560
561 case DAVINCI_AUDIO_WORD_32:
562 fmt = 0x0F;
0c31cf3e
C		 563 rotate = 0;
564 mask = 0xffffffff;
b67f4487
C		 565 break;
566
567 default:
568 return -EINVAL;
569 }
570
571 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
572 RXSSZ(fmt), RXSSZ(0x0F));
573 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
574 TXSSZ(fmt), TXSSZ(0x0F));
0c31cf3e
C		 575 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
576 TXROT(7));
577 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
578 RXROT(7));
579 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
580 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
581
b67f4487
C		 582 return 0;
583}
584
585static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
586{
587 int i;
6a99fb5f
C		 588 u8 tx_ser = 0;
589 u8 rx_ser = 0;
b67f4487
C		 590
591 /* Default configuration */
592 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
593
594 /* All PINS as McASP */
595 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
596
597 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
598 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
599 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
600 TXDATADMADIS);
601 } else {
602 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
603 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
604 RXDATADMADIS);
605 }
606
607 for (i = 0; i < dev->num_serializer; i++) {
608 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
609 dev->serial_dir[i]);
6a99fb5f 610 if (dev->serial_dir[i] == TX_MODE) {
b67f4487
C		 611 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
612 AXR(i));
6a99fb5f
C		 613 tx_ser++;
614 } else if (dev->serial_dir[i] == RX_MODE) {
b67f4487
C		 615 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
616 AXR(i));
6a99fb5f
C		 617 rx_ser++;
618 }
619 }
620
621 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
622 if (dev->txnumevt * tx_ser > 64)
623 dev->txnumevt = 1;
624
625 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, tx_ser,
626 NUMDMA_MASK);
627 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
628 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
6a99fb5f
C		 629 }
630
631 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
632 if (dev->rxnumevt * rx_ser > 64)
633 dev->rxnumevt = 1;
634
635 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, rx_ser,
636 NUMDMA_MASK);
637 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
638 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
b67f4487
C		 639 }
640}
641
642static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
643{
644 int i, active_slots;
645 u32 mask = 0;
646
647 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
648 for (i = 0; i < active_slots; i++)
649 mask |= (1 << i);
650
6a99fb5f
C		 651 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
652
b67f4487
C		 653 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
654 /* bit stream is MSB first with no delay */
655 /* DSP_B mode */
656 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
657 AHCLKXE);
658 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
659 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
660
049cfaaa 661 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
b67f4487
C		 662 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
663 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
664 else
665 printk(KERN_ERR "playback tdm slot %d not supported\n",
666 dev->tdm_slots);
667
b67f4487
C		 668 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
669 } else {
670 /* bit stream is MSB first with no delay */
671 /* DSP_B mode */
672 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
673 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
674 AHCLKRE);
675 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
676
049cfaaa 677 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
b67f4487
C		 678 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
679 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
680 else
681 printk(KERN_ERR "capture tdm slot %d not supported\n",
682 dev->tdm_slots);
683
b67f4487
C		 684 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
685 }
686}
687
688/* S/PDIF */
689static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
690{
691 /* Set the PDIR for Serialiser as output */
692 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
693
694 /* TXMASK for 24 bits */
695 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
696
697 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
698 and LSB first */
699 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
700 TXROT(6) | TXSSZ(15));
701
702 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
703 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
704 AFSXE | FSXMOD(0x180));
705
706 /* Set the TX tdm : for all the slots */
707 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
708
709 /* Set the TX clock controls : div = 1 and internal */
710 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
711 ACLKXE | TX_ASYNC);
712
713 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
714
715 /* Only 44100 and 48000 are valid, both have the same setting */
716 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
717
718 /* Enable the DIT */
719 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
720}
721
722static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
723 struct snd_pcm_hw_params *params,
724 struct snd_soc_dai *cpu_dai)
725{
f0fba2ad 726 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487 727 struct davinci_pcm_dma_params *dma_params =
92e2a6f6 728 &dev->dma_params[substream->stream];
b67f4487 729 int word_length;
4fa9c1a5 730 u8 fifo_level;
b67f4487
C		 731
732 davinci_hw_common_param(dev, substream->stream);
6a99fb5f 733 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4fa9c1a5 734 fifo_level = dev->txnumevt;
6a99fb5f 735 else
4fa9c1a5 736 fifo_level = dev->rxnumevt;
b67f4487
C		 737
738 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
739 davinci_hw_dit_param(dev);
740 else
741 davinci_hw_param(dev, substream->stream);
742
743 switch (params_format(params)) {
0a9d1385 744 case SNDRV_PCM_FORMAT_U8:
b67f4487
C		 745 case SNDRV_PCM_FORMAT_S8:
746 dma_params->data_type = 1;
747 word_length = DAVINCI_AUDIO_WORD_8;
748 break;
749
0a9d1385 750 case SNDRV_PCM_FORMAT_U16_LE:
b67f4487
C		 751 case SNDRV_PCM_FORMAT_S16_LE:
752 dma_params->data_type = 2;
753 word_length = DAVINCI_AUDIO_WORD_16;
754 break;
755
0a9d1385 756 case SNDRV_PCM_FORMAT_U32_LE:
b67f4487
C		 757 case SNDRV_PCM_FORMAT_S32_LE:
758 dma_params->data_type = 4;
759 word_length = DAVINCI_AUDIO_WORD_32;
760 break;
761
762 default:
763 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
764 return -EINVAL;
765 }
6a99fb5f 766
4fa9c1a5
C		 767 if (dev->version == MCASP_VERSION_2 && !fifo_level)
768 dma_params->acnt = 4;
769 else
6a99fb5f
C		 770 dma_params->acnt = dma_params->data_type;
771
4fa9c1a5 772 dma_params->fifo_level = fifo_level;
b67f4487
C		 773 davinci_config_channel_size(dev, word_length);
774
775 return 0;
776}
777
778static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
779 int cmd, struct snd_soc_dai *cpu_dai)
780{
f0fba2ad 781 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 782 int ret = 0;
783
784 switch (cmd) {
b67f4487 785 case SNDRV_PCM_TRIGGER_RESUME:
e473b847
C		 786 case SNDRV_PCM_TRIGGER_START:
787 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
10884347
HG		 788 ret = pm_runtime_get_sync(dev->dev);
789 if (IS_ERR_VALUE(ret))
790 dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
b67f4487
C		 791 davinci_mcasp_start(dev, substream->stream);
792 break;
793
b67f4487 794 case SNDRV_PCM_TRIGGER_SUSPEND:
a47979b5 795 davinci_mcasp_stop(dev, substream->stream);
10884347
HG		 796 ret = pm_runtime_put_sync(dev->dev);
797 if (IS_ERR_VALUE(ret))
798 dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
a47979b5
C		 799 break;
800
801 case SNDRV_PCM_TRIGGER_STOP:
b67f4487
C		 802 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
803 davinci_mcasp_stop(dev, substream->stream);
804 break;
805
806 default:
807 ret = -EINVAL;
808 }
809
810 return ret;
811}
812
bedad0ca
CPE		 813static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
814 struct snd_soc_dai *dai)
815{
816 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
817
818 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
819 return 0;
820}
821
85e7652d 822static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
bedad0ca 823 .startup = davinci_mcasp_startup,
b67f4487
C		 824 .trigger = davinci_mcasp_trigger,
825 .hw_params = davinci_mcasp_hw_params,
826 .set_fmt = davinci_mcasp_set_dai_fmt,
827
828};
829
0a9d1385
BG		 830#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
831 SNDRV_PCM_FMTBIT_U8 | \
832 SNDRV_PCM_FMTBIT_S16_LE | \
833 SNDRV_PCM_FMTBIT_U16_LE | \
834 SNDRV_PCM_FMTBIT_S32_LE | \
835 SNDRV_PCM_FMTBIT_U32_LE)
836
f0fba2ad 837static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
b67f4487 838 {
f0fba2ad 839 .name = "davinci-mcasp.0",
b67f4487
C		 840 .playback = {
841 .channels_min = 2,
842 .channels_max = 2,
843 .rates = DAVINCI_MCASP_RATES,
0a9d1385 844 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 845 },
846 .capture = {
847 .channels_min = 2,
848 .channels_max = 2,
849 .rates = DAVINCI_MCASP_RATES,
0a9d1385 850 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 851 },
852 .ops = &davinci_mcasp_dai_ops,
853
854 },
855 {
f0fba2ad 856 "davinci-mcasp.1",
b67f4487
C		 857 .playback = {
858 .channels_min = 1,
859 .channels_max = 384,
860 .rates = DAVINCI_MCASP_RATES,
0a9d1385 861 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 862 },
863 .ops = &davinci_mcasp_dai_ops,
864 },
865
866};
b67f4487 867
3e3b8c34
HG		 868static const struct of_device_id mcasp_dt_ids[] = {
869 {
870 .compatible = "ti,dm646x-mcasp-audio",
871 .data = (void *)MCASP_VERSION_1,
872 },
873 {
874 .compatible = "ti,da830-mcasp-audio",
875 .data = (void *)MCASP_VERSION_2,
876 },
877 { /* sentinel */ }
878};
879MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
880
881static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
882 struct platform_device *pdev)
883{
884 struct device_node *np = pdev->dev.of_node;
885 struct snd_platform_data *pdata = NULL;
886 const struct of_device_id *match =
887 of_match_device(of_match_ptr(mcasp_dt_ids), &pdev->dev);
888
889 const u32 *of_serial_dir32;
890 u8 *of_serial_dir;
891 u32 val;
892 int i, ret = 0;
893
894 if (pdev->dev.platform_data) {
895 pdata = pdev->dev.platform_data;
896 return pdata;
897 } else if (match) {
898 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
899 if (!pdata) {
900 ret = -ENOMEM;
901 goto nodata;
902 }
903 } else {
904 /* control shouldn't reach here. something is wrong */
905 ret = -EINVAL;
906 goto nodata;
907 }
908
909 if (match->data)
910 pdata->version = (u8)((int)match->data);
911
912 ret = of_property_read_u32(np, "op-mode", &val);
913 if (ret >= 0)
914 pdata->op_mode = val;
915
916 ret = of_property_read_u32(np, "tdm-slots", &val);
917 if (ret >= 0)
918 pdata->tdm_slots = val;
919
920 ret = of_property_read_u32(np, "num-serializer", &val);
921 if (ret >= 0)
922 pdata->num_serializer = val;
923
924 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
925 val /= sizeof(u32);
926 if (val != pdata->num_serializer) {
927 dev_err(&pdev->dev,
928 "num-serializer(%d) != serial-dir size(%d)\n",
929 pdata->num_serializer, val);
930 ret = -EINVAL;
931 goto nodata;
932 }
933
934 if (of_serial_dir32) {
935 of_serial_dir = devm_kzalloc(&pdev->dev,
936 (sizeof(*of_serial_dir) * val),
937 GFP_KERNEL);
938 if (!of_serial_dir) {
939 ret = -ENOMEM;
940 goto nodata;
941 }
942
943 for (i = 0; i < pdata->num_serializer; i++)
944 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
945
946 pdata->serial_dir = of_serial_dir;
947 }
948
949 ret = of_property_read_u32(np, "tx-num-evt", &val);
950 if (ret >= 0)
951 pdata->txnumevt = val;
952
953 ret = of_property_read_u32(np, "rx-num-evt", &val);
954 if (ret >= 0)
955 pdata->rxnumevt = val;
956
957 ret = of_property_read_u32(np, "sram-size-playback", &val);
958 if (ret >= 0)
959 pdata->sram_size_playback = val;
960
961 ret = of_property_read_u32(np, "sram-size-capture", &val);
962 if (ret >= 0)
963 pdata->sram_size_capture = val;
964
965 return pdata;
966
967nodata:
968 if (ret < 0) {
969 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
970 ret);
971 pdata = NULL;
972 }
973 return pdata;
974}
975
b67f4487
C		 976static int davinci_mcasp_probe(struct platform_device *pdev)
977{
978 struct davinci_pcm_dma_params *dma_data;
979 struct resource *mem, *ioarea, *res;
980 struct snd_platform_data *pdata;
981 struct davinci_audio_dev *dev;
96d31e2b 982 int ret;
b67f4487 983
3e3b8c34
HG		 984 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
985 dev_err(&pdev->dev, "No platform data supplied\n");
986 return -EINVAL;
987 }
988
96d31e2b
JL		 989 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
990 GFP_KERNEL);
b67f4487
C		 991 if (!dev)
992 return -ENOMEM;
993
3e3b8c34
HG		 994 pdata = davinci_mcasp_set_pdata_from_of(pdev);
995 if (!pdata) {
996 dev_err(&pdev->dev, "no platform data\n");
997 return -EINVAL;
998 }
999
b67f4487
C		 1000 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1001 if (!mem) {
1002 dev_err(&pdev->dev, "no mem resource?\n");
96d31e2b 1003 return -ENODEV;
b67f4487
C		 1004 }
1005
96d31e2b 1006 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
d852f446 1007 resource_size(mem), pdev->name);
b67f4487
C		 1008 if (!ioarea) {
1009 dev_err(&pdev->dev, "Audio region already claimed\n");
96d31e2b 1010 return -EBUSY;
b67f4487
C		 1011 }
1012
10884347 1013 pm_runtime_enable(&pdev->dev);
b67f4487 1014
10884347
HG		 1015 ret = pm_runtime_get_sync(&pdev->dev);
1016 if (IS_ERR_VALUE(ret)) {
1017 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1018 return ret;
1019 }
b67f4487 1020
96d31e2b 1021 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
4f82f028
VB		 1022 if (!dev->base) {
1023 dev_err(&pdev->dev, "ioremap failed\n");
1024 ret = -ENOMEM;
1025 goto err_release_clk;
1026 }
1027
b67f4487
C		 1028 dev->op_mode = pdata->op_mode;
1029 dev->tdm_slots = pdata->tdm_slots;
1030 dev->num_serializer = pdata->num_serializer;
1031 dev->serial_dir = pdata->serial_dir;
1032 dev->codec_fmt = pdata->codec_fmt;
6a99fb5f
C		 1033 dev->version = pdata->version;
1034 dev->txnumevt = pdata->txnumevt;
1035 dev->rxnumevt = pdata->rxnumevt;
10884347 1036 dev->dev = &pdev->dev;
b67f4487 1037
92e2a6f6 1038 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
48519f0a
SN		 1039 dma_data->asp_chan_q = pdata->asp_chan_q;
1040 dma_data->ram_chan_q = pdata->ram_chan_q;
a0c83263 1041 dma_data->sram_size = pdata->sram_size_playback;
92e2a6f6 1042 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
4f82f028 1043 mem->start);
b67f4487
C		 1044
1045 /* first TX, then RX */
1046 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1047 if (!res) {
1048 dev_err(&pdev->dev, "no DMA resource\n");
02ffc5f3 1049 ret = -ENODEV;
96d31e2b 1050 goto err_release_clk;
b67f4487
C		 1051 }
1052
92e2a6f6
TK		 1053 dma_data->channel = res->start;
1054
1055 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
48519f0a
SN		 1056 dma_data->asp_chan_q = pdata->asp_chan_q;
1057 dma_data->ram_chan_q = pdata->ram_chan_q;
a0c83263 1058 dma_data->sram_size = pdata->sram_size_capture;
92e2a6f6 1059 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
4f82f028 1060 mem->start);
b67f4487
C		 1061
1062 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1063 if (!res) {
1064 dev_err(&pdev->dev, "no DMA resource\n");
02ffc5f3 1065 ret = -ENODEV;
96d31e2b 1066 goto err_release_clk;
b67f4487
C		 1067 }
1068
92e2a6f6 1069 dma_data->channel = res->start;
f0fba2ad
LG		 1070 dev_set_drvdata(&pdev->dev, dev);
1071 ret = snd_soc_register_dai(&pdev->dev, &davinci_mcasp_dai[pdata->op_mode]);
b67f4487
C		 1072
1073 if (ret != 0)
96d31e2b 1074 goto err_release_clk;
f08095a4
HG		 1075
1076 ret = davinci_soc_platform_register(&pdev->dev);
1077 if (ret) {
1078 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1079 goto err_unregister_dai;
1080 }
1081
b67f4487
C		 1082 return 0;
1083
f08095a4
HG		 1084err_unregister_dai:
1085 snd_soc_unregister_dai(&pdev->dev);
eef6d7b8 1086err_release_clk:
10884347
HG		 1087 pm_runtime_put_sync(&pdev->dev);
1088 pm_runtime_disable(&pdev->dev);
b67f4487
C		 1089 return ret;
1090}
1091
1092static int davinci_mcasp_remove(struct platform_device *pdev)
1093{
b67f4487 1094
f0fba2ad 1095 snd_soc_unregister_dai(&pdev->dev);
f08095a4 1096 davinci_soc_platform_unregister(&pdev->dev);
10884347
HG		 1097
1098 pm_runtime_put_sync(&pdev->dev);
1099 pm_runtime_disable(&pdev->dev);
b67f4487 1100
b67f4487
C		 1101 return 0;
1102}
1103
1104static struct platform_driver davinci_mcasp_driver = {
1105 .probe = davinci_mcasp_probe,
1106 .remove = davinci_mcasp_remove,
1107 .driver = {
1108 .name = "davinci-mcasp",
1109 .owner = THIS_MODULE,
3e3b8c34 1110 .of_match_table = of_match_ptr(mcasp_dt_ids),
b67f4487
C		 1111 },
1112};
1113
f9b8a514 1114module_platform_driver(davinci_mcasp_driver);
b67f4487
C		 1115
1116MODULE_AUTHOR("Steve Chen");
1117MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1118MODULE_LICENSE("GPL");
1119
Linux 6.x block layer and io_uring tree(s)