projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Linux 3.16-rc1
[linux-2.6-block.git] / sound / soc / davinci / davinci-mcasp.c
CommitLineData
b67f4487
C		 1/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
5a0e3ad6 21#include <linux/slab.h>
b67f4487
C		 22#include <linux/delay.h>
23#include <linux/io.h>
ae726e93 24#include <linux/clk.h>
10884347 25#include <linux/pm_runtime.h>
3e3b8c34
HG		 26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/of_device.h>
b67f4487
C		 29
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/initval.h>
34#include <sound/soc.h>
453c4990 35#include <sound/dmaengine_pcm.h>
87c19364 36#include <sound/omap-pcm.h>
b67f4487
C		 37
38#include "davinci-pcm.h"
39#include "davinci-mcasp.h"
40
0bf0e8ae
PU		 41#define MCASP_MAX_AFIFO_DEPTH 64
42
790bb94b
PU		 43struct davinci_mcasp_context {
44 u32 txfmtctl;
45 u32 rxfmtctl;
46 u32 txfmt;
47 u32 rxfmt;
48 u32 aclkxctl;
49 u32 aclkrctl;
50 u32 pdir;
51};
52
70091a3e 53struct davinci_mcasp {
21400a72 54 struct davinci_pcm_dma_params dma_params[2];
453c4990 55 struct snd_dmaengine_dai_dma_data dma_data[2];
21400a72 56 void __iomem *base;
487dce88 57 u32 fifo_base;
21400a72
PU		 58 struct device *dev;
59
60 /* McASP specific data */
61 int tdm_slots;
62 u8 op_mode;
63 u8 num_serializer;
64 u8 *serial_dir;
65 u8 version;
66 u16 bclk_lrclk_ratio;
4dcb5a0b 67 int streams;
21400a72 68
ab8b14b6
JS		 69 int sysclk_freq;
70 bool bclk_master;
71
21400a72
PU		 72 /* McASP FIFO related */
73 u8 txnumevt;
74 u8 rxnumevt;
75
cbc7956c
PU		 76 bool dat_port;
77
21400a72 78#ifdef CONFIG_PM_SLEEP
790bb94b 79 struct davinci_mcasp_context context;
21400a72
PU		 80#endif
81};
82
f68205a7
PU		 83static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
84 u32 val)
b67f4487 85{
f68205a7 86 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 87 __raw_writel(__raw_readl(reg) | val, reg);
88}
89
f68205a7
PU		 90static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
91 u32 val)
b67f4487 92{
f68205a7 93 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 94 __raw_writel((__raw_readl(reg) & ~(val)), reg);
95}
96
f68205a7
PU		 97static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
98 u32 val, u32 mask)
b67f4487 99{
f68205a7 100 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 101 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
102}
103
f68205a7
PU		 104static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
105 u32 val)
b67f4487 106{
f68205a7 107 __raw_writel(val, mcasp->base + offset);
b67f4487
C		 108}
109
f68205a7 110static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
b67f4487 111{
f68205a7 112 return (u32)__raw_readl(mcasp->base + offset);
b67f4487
C		 113}
114
f68205a7 115static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
b67f4487
C		 116{
117 int i = 0;
118
f68205a7 119 mcasp_set_bits(mcasp, ctl_reg, val);
b67f4487
C		 120
121 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
122 /* loop count is to avoid the lock-up */
123 for (i = 0; i < 1000; i++) {
f68205a7 124 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
b67f4487
C		 125 break;
126 }
127
f68205a7 128 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
b67f4487
C		 129 printk(KERN_ERR "GBLCTL write error\n");
130}
131
4dcb5a0b
PU		 132static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
133{
f68205a7
PU		 134 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
135 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
4dcb5a0b
PU		 136
137 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
138}
139
70091a3e 140static void mcasp_start_rx(struct davinci_mcasp *mcasp)
b67f4487 141{
f68205a7
PU		 142 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
143 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
4dcb5a0b
PU		 144
145 /*
146 * When ASYNC == 0 the transmit and receive sections operate
147 * synchronously from the transmit clock and frame sync. We need to make
148 * sure that the TX signlas are enabled when starting reception.
149 */
150 if (mcasp_is_synchronous(mcasp)) {
f68205a7
PU		 151 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
152 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
4dcb5a0b
PU		 153 }
154
f68205a7
PU		 155 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
156 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
b67f4487 157
f68205a7
PU		 158 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
159 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
160 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
b67f4487 161
f68205a7
PU		 162 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
163 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
4dcb5a0b
PU		 164
165 if (mcasp_is_synchronous(mcasp))
f68205a7 166 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
b67f4487
C		 167}
168
70091a3e 169static void mcasp_start_tx(struct davinci_mcasp *mcasp)
b67f4487 170{
6a99fb5f
C		 171 u8 offset = 0, i;
172 u32 cnt;
173
f68205a7
PU		 174 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
175 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
176 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
177 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
b67f4487 178
f68205a7
PU		 179 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
180 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
181 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
70091a3e
PU		 182 for (i = 0; i < mcasp->num_serializer; i++) {
183 if (mcasp->serial_dir[i] == TX_MODE) {
6a99fb5f
C		 184 offset = i;
185 break;
186 }
187 }
188
189 /* wait for TX ready */
190 cnt = 0;
f68205a7 191 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
6a99fb5f
C		 192 TXSTATE) && (cnt < 100000))
193 cnt++;
194
f68205a7 195 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
b67f4487
C		 196}
197
70091a3e 198static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
b67f4487 199{
487dce88
PU		 200 u32 reg;
201
4dcb5a0b
PU		 202 mcasp->streams++;
203
539d3d8c 204 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
70091a3e 205 if (mcasp->txnumevt) { /* enable FIFO */
487dce88 206 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
f68205a7
PU		 207 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
208 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
0d624275 209 }
70091a3e 210 mcasp_start_tx(mcasp);
539d3d8c 211 } else {
70091a3e 212 if (mcasp->rxnumevt) { /* enable FIFO */
487dce88 213 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
f68205a7
PU		 214 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
215 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
0d624275 216 }
70091a3e 217 mcasp_start_rx(mcasp);
539d3d8c 218 }
b67f4487
C		 219}
220
70091a3e 221static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
b67f4487 222{
4dcb5a0b
PU		 223 /*
224 * In synchronous mode stop the TX clocks if no other stream is
225 * running
226 */
227 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
f68205a7 228 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
4dcb5a0b 229
f68205a7
PU		 230 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
231 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
b67f4487
C		 232}
233
70091a3e 234static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
b67f4487 235{
4dcb5a0b
PU		 236 u32 val = 0;
237
238 /*
239 * In synchronous mode keep TX clocks running if the capture stream is
240 * still running.
241 */
242 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
243 val = TXHCLKRST | TXCLKRST | TXFSRST;
244
f68205a7
PU		 245 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
246 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
b67f4487
C		 247}
248
70091a3e 249static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
b67f4487 250{
487dce88
PU		 251 u32 reg;
252
4dcb5a0b
PU		 253 mcasp->streams--;
254
539d3d8c 255 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
70091a3e 256 if (mcasp->txnumevt) { /* disable FIFO */
487dce88 257 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
f68205a7 258 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
e5ec69da 259 }
70091a3e 260 mcasp_stop_tx(mcasp);
539d3d8c 261 } else {
70091a3e 262 if (mcasp->rxnumevt) { /* disable FIFO */
487dce88 263 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
f68205a7 264 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
e5ec69da 265 }
70091a3e 266 mcasp_stop_rx(mcasp);
539d3d8c 267 }
b67f4487
C		 268}
269
270static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
271 unsigned int fmt)
272{
70091a3e 273 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1d17a04e 274 int ret = 0;
6dfa9a4e 275 u32 data_delay;
83f12503 276 bool fs_pol_rising;
ffd950f7 277 bool inv_fs = false;
b67f4487 278
1d17a04e 279 pm_runtime_get_sync(mcasp->dev);
5296cf2d 280 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
188edc59
PU		 281 case SND_SOC_DAIFMT_DSP_A:
282 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
283 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
188edc59
PU		 284 /* 1st data bit occur one ACLK cycle after the frame sync */
285 data_delay = 1;
286 break;
5296cf2d
DM		 287 case SND_SOC_DAIFMT_DSP_B:
288 case SND_SOC_DAIFMT_AC97:
f68205a7
PU		 289 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
290 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
6dfa9a4e
PU		 291 /* No delay after FS */
292 data_delay = 0;
5296cf2d 293 break;
ffd950f7 294 case SND_SOC_DAIFMT_I2S:
5296cf2d 295 /* configure a full-word SYNC pulse (LRCLK) */
f68205a7
PU		 296 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
297 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
6dfa9a4e
PU		 298 /* 1st data bit occur one ACLK cycle after the frame sync */
299 data_delay = 1;
ffd950f7
PU		 300 /* FS need to be inverted */
301 inv_fs = true;
5296cf2d 302 break;
423761e0
PU		 303 case SND_SOC_DAIFMT_LEFT_J:
304 /* configure a full-word SYNC pulse (LRCLK) */
305 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
306 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
307 /* No delay after FS */
308 data_delay = 0;
309 break;
ffd950f7
PU		 310 default:
311 ret = -EINVAL;
312 goto out;
5296cf2d
DM		 313 }
314
6dfa9a4e
PU		 315 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
316 FSXDLY(3));
317 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
318 FSRDLY(3));
319
b67f4487
C		 320 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
321 case SND_SOC_DAIFMT_CBS_CFS:
322 /* codec is clock and frame slave */
f68205a7
PU		 323 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
324 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 325
f68205a7
PU		 326 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
327 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 328
f68205a7
PU		 329 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
330 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
ab8b14b6 331 mcasp->bclk_master = 1;
b67f4487 332 break;
517ee6cf
C		 333 case SND_SOC_DAIFMT_CBM_CFS:
334 /* codec is clock master and frame slave */
f68205a7
PU		 335 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
336 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517ee6cf 337
f68205a7
PU		 338 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
339 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
517ee6cf 340
f68205a7
PU		 341 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
342 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
ab8b14b6 343 mcasp->bclk_master = 0;
517ee6cf 344 break;
b67f4487
C		 345 case SND_SOC_DAIFMT_CBM_CFM:
346 /* codec is clock and frame master */
f68205a7
PU		 347 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
348 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 349
f68205a7
PU		 350 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
351 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 352
f68205a7
PU		 353 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
354 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
ab8b14b6 355 mcasp->bclk_master = 0;
b67f4487 356 break;
b67f4487 357 default:
1d17a04e
PU		 358 ret = -EINVAL;
359 goto out;
b67f4487
C		 360 }
361
362 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
363 case SND_SOC_DAIFMT_IB_NF:
f68205a7 364 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 365 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 366 fs_pol_rising = true;
b67f4487 367 break;
b67f4487 368 case SND_SOC_DAIFMT_NB_IF:
f68205a7 369 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 370 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 371 fs_pol_rising = false;
b67f4487 372 break;
b67f4487 373 case SND_SOC_DAIFMT_IB_IF:
f68205a7 374 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 375 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 376 fs_pol_rising = false;
b67f4487 377 break;
b67f4487 378 case SND_SOC_DAIFMT_NB_NF:
f68205a7 379 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
f68205a7 380 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 381 fs_pol_rising = true;
b67f4487 382 break;
b67f4487 383 default:
1d17a04e 384 ret = -EINVAL;
83f12503
PU		 385 goto out;
386 }
387
ffd950f7
PU		 388 if (inv_fs)
389 fs_pol_rising = !fs_pol_rising;
390
83f12503
PU		 391 if (fs_pol_rising) {
392 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
393 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
394 } else {
395 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
396 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
b67f4487 397 }
1d17a04e
PU		 398out:
399 pm_runtime_put_sync(mcasp->dev);
400 return ret;
b67f4487
C		 401}
402
4ed8c9b7
DM		 403static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
404{
70091a3e 405 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
4ed8c9b7
DM		 406
407 switch (div_id) {
408 case 0: /* MCLK divider */
f68205a7 409 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
4ed8c9b7 410 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
f68205a7 411 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
4ed8c9b7
DM		 412 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
413 break;
414
415 case 1: /* BCLK divider */
f68205a7 416 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
4ed8c9b7 417 ACLKXDIV(div - 1), ACLKXDIV_MASK);
f68205a7 418 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
4ed8c9b7
DM		 419 ACLKRDIV(div - 1), ACLKRDIV_MASK);
420 break;
421
1b3bc060 422 case 2: /* BCLK/LRCLK ratio */
70091a3e 423 mcasp->bclk_lrclk_ratio = div;
1b3bc060
DM		 424 break;
425
4ed8c9b7
DM		 426 default:
427 return -EINVAL;
428 }
429
430 return 0;
431}
432
5b66aa2d
DM		 433static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
434 unsigned int freq, int dir)
435{
70091a3e 436 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
5b66aa2d
DM		 437
438 if (dir == SND_SOC_CLOCK_OUT) {
f68205a7
PU		 439 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
440 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
441 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
5b66aa2d 442 } else {
f68205a7
PU		 443 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
444 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
445 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
5b66aa2d
DM		 446 }
447
ab8b14b6
JS		 448 mcasp->sysclk_freq = freq;
449
5b66aa2d
DM		 450 return 0;
451}
452
70091a3e 453static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
ba764b3d 454 int word_length)
b67f4487 455{
ba764b3d 456 u32 fmt;
79671892
DM		 457 u32 tx_rotate = (word_length / 4) & 0x7;
458 u32 rx_rotate = (32 - word_length) / 4;
ba764b3d 459 u32 mask = (1ULL << word_length) - 1;
b67f4487 460
1b3bc060
DM		 461 /*
462 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
463 * callback, take it into account here. That allows us to for example
464 * send 32 bits per channel to the codec, while only 16 of them carry
465 * audio payload.
d486fea6
MB		 466 * The clock ratio is given for a full period of data (for I2S format
467 * both left and right channels), so it has to be divided by number of
468 * tdm-slots (for I2S - divided by 2).
1b3bc060 469 */
70091a3e
PU		 470 if (mcasp->bclk_lrclk_ratio)
471 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
1b3bc060 472
ba764b3d
DM		 473 /* mapping of the XSSZ bit-field as described in the datasheet */
474 fmt = (word_length >> 1) - 1;
b67f4487 475
70091a3e 476 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
f68205a7
PU		 477 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
478 RXSSZ(0x0F));
479 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
480 TXSSZ(0x0F));
481 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
482 TXROT(7));
483 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
484 RXROT(7));
485 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
f5023af6
YY		 486 }
487
f68205a7 488 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
0c31cf3e 489
b67f4487
C		 490 return 0;
491}
492
662ffae9 493static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
dd093a0f 494 int period_words, int channels)
b67f4487 495{
5f04c603
PU		 496 struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream];
497 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
b67f4487 498 int i;
6a99fb5f
C		 499 u8 tx_ser = 0;
500 u8 rx_ser = 0;
70091a3e 501 u8 slots = mcasp->tdm_slots;
2952b27e 502 u8 max_active_serializers = (channels + slots - 1) / slots;
dd093a0f 503 int active_serializers, numevt, n;
487dce88 504 u32 reg;
b67f4487 505 /* Default configuration */
40448e5e 506 if (mcasp->version < MCASP_VERSION_3)
f68205a7 507 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
b67f4487
C		 508
509 /* All PINS as McASP */
f68205a7 510 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
b67f4487
C		 511
512 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f68205a7
PU		 513 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487 515 } else {
f68205a7
PU		 516 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
517 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
b67f4487
C		 518 }
519
70091a3e 520 for (i = 0; i < mcasp->num_serializer; i++) {
f68205a7
PU		 521 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
522 mcasp->serial_dir[i]);
70091a3e 523 if (mcasp->serial_dir[i] == TX_MODE &&
2952b27e 524 tx_ser < max_active_serializers) {
f68205a7 525 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
6a99fb5f 526 tx_ser++;
70091a3e 527 } else if (mcasp->serial_dir[i] == RX_MODE &&
2952b27e 528 rx_ser < max_active_serializers) {
f68205a7 529 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
6a99fb5f 530 rx_ser++;
2952b27e 531 } else {
f68205a7
PU		 532 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
533 SRMOD_INACTIVE, SRMOD_MASK);
6a99fb5f
C		 534 }
535 }
536
0bf0e8ae
PU		 537 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
538 active_serializers = tx_ser;
539 numevt = mcasp->txnumevt;
540 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
541 } else {
542 active_serializers = rx_ser;
543 numevt = mcasp->rxnumevt;
544 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
545 }
ecf327c7 546
0bf0e8ae 547 if (active_serializers < max_active_serializers) {
70091a3e 548 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
0bf0e8ae
PU		 549 "enabled in mcasp (%d)\n", channels,
550 active_serializers * slots);
ecf327c7
DM		 551 return -EINVAL;
552 }
553
0bf0e8ae 554 /* AFIFO is not in use */
5f04c603
PU		 555 if (!numevt) {
556 /* Configure the burst size for platform drivers */
33445643
PU		 557 if (active_serializers > 1) {
558 /*
559 * If more than one serializers are in use we have one
560 * DMA request to provide data for all serializers.
561 * For example if three serializers are enabled the DMA
562 * need to transfer three words per DMA request.
563 */
564 dma_params->fifo_level = active_serializers;
565 dma_data->maxburst = active_serializers;
566 } else {
567 dma_params->fifo_level = 0;
568 dma_data->maxburst = 0;
569 }
0bf0e8ae 570 return 0;
5f04c603 571 }
6a99fb5f 572
dd093a0f
PU		 573 if (period_words % active_serializers) {
574 dev_err(mcasp->dev, "Invalid combination of period words and "
575 "active serializers: %d, %d\n", period_words,
576 active_serializers);
577 return -EINVAL;
578 }
579
580 /*
581 * Calculate the optimal AFIFO depth for platform side:
582 * The number of words for numevt need to be in steps of active
583 * serializers.
584 */
585 n = numevt % active_serializers;
586 if (n)
587 numevt += (active_serializers - n);
588 while (period_words % numevt && numevt > 0)
589 numevt -= active_serializers;
590 if (numevt <= 0)
0bf0e8ae 591 numevt = active_serializers;
487dce88 592
0bf0e8ae
PU		 593 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
594 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
2952b27e 595
5f04c603 596 /* Configure the burst size for platform drivers */
33445643
PU		 597 if (numevt == 1)
598 numevt = 0;
5f04c603
PU		 599 dma_params->fifo_level = numevt;
600 dma_data->maxburst = numevt;
601
2952b27e 602 return 0;
b67f4487
C		 603}
604
2c56c4c2 605static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
b67f4487
C		 606{
607 int i, active_slots;
608 u32 mask = 0;
cbc7956c 609 u32 busel = 0;
b67f4487 610
2c56c4c2
PU		 611 if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
612 dev_err(mcasp->dev, "tdm slot %d not supported\n",
613 mcasp->tdm_slots);
614 return -EINVAL;
615 }
616
70091a3e 617 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
b67f4487
C		 618 for (i = 0; i < active_slots; i++)
619 mask |= (1 << i);
620
f68205a7 621 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
6a99fb5f 622
cbc7956c
PU		 623 if (!mcasp->dat_port)
624 busel = TXSEL;
625
2c56c4c2
PU		 626 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
627 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
628 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
629 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
630
631 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
632 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
633 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
634 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
635
636 return 0;
b67f4487
C		 637}
638
639/* S/PDIF */
2c56c4c2 640static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
b67f4487 641{
b67f4487
C		 642 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
643 and LSB first */
f68205a7 644 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
b67f4487
C		 645
646 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
f68205a7 647 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
b67f4487
C		 648
649 /* Set the TX tdm : for all the slots */
f68205a7 650 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
b67f4487
C		 651
652 /* Set the TX clock controls : div = 1 and internal */
f68205a7 653 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
b67f4487 654
f68205a7 655 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487
C		 656
657 /* Only 44100 and 48000 are valid, both have the same setting */
f68205a7 658 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
b67f4487
C		 659
660 /* Enable the DIT */
f68205a7 661 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
2c56c4c2
PU		 662
663 return 0;
b67f4487
C		 664}
665
666static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
667 struct snd_pcm_hw_params *params,
668 struct snd_soc_dai *cpu_dai)
669{
70091a3e 670 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487 671 struct davinci_pcm_dma_params *dma_params =
70091a3e 672 &mcasp->dma_params[substream->stream];
b67f4487 673 int word_length;
a7e46bd9 674 int channels = params_channels(params);
dd093a0f 675 int period_size = params_period_size(params);
2c56c4c2 676 int ret;
ab8b14b6
JS		 677
678 /* If mcasp is BCLK master we need to set BCLK divider */
679 if (mcasp->bclk_master) {
680 unsigned int bclk_freq = snd_soc_params_to_bclk(params);
681 if (mcasp->sysclk_freq % bclk_freq != 0) {
f5b02b4a 682 dev_err(mcasp->dev, "Can't produce required BCLK\n");
ab8b14b6
JS		 683 return -EINVAL;
684 }
685 davinci_mcasp_set_clkdiv(
686 cpu_dai, 1, mcasp->sysclk_freq / bclk_freq);
687 }
688
dd093a0f
PU		 689 ret = mcasp_common_hw_param(mcasp, substream->stream,
690 period_size * channels, channels);
0f7d9a63
PU		 691 if (ret)
692 return ret;
693
70091a3e 694 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
2c56c4c2 695 ret = mcasp_dit_hw_param(mcasp);
b67f4487 696 else
2c56c4c2
PU		 697 ret = mcasp_i2s_hw_param(mcasp, substream->stream);
698
699 if (ret)
700 return ret;
b67f4487
C		 701
702 switch (params_format(params)) {
0a9d1385 703 case SNDRV_PCM_FORMAT_U8:
b67f4487
C		 704 case SNDRV_PCM_FORMAT_S8:
705 dma_params->data_type = 1;
ba764b3d 706 word_length = 8;
b67f4487
C		 707 break;
708
0a9d1385 709 case SNDRV_PCM_FORMAT_U16_LE:
b67f4487
C		 710 case SNDRV_PCM_FORMAT_S16_LE:
711 dma_params->data_type = 2;
ba764b3d 712 word_length = 16;
b67f4487
C		 713 break;
714
21eb24d8
DM		 715 case SNDRV_PCM_FORMAT_U24_3LE:
716 case SNDRV_PCM_FORMAT_S24_3LE:
21eb24d8 717 dma_params->data_type = 3;
ba764b3d 718 word_length = 24;
21eb24d8
DM		 719 break;
720
6b7fa011
DM		 721 case SNDRV_PCM_FORMAT_U24_LE:
722 case SNDRV_PCM_FORMAT_S24_LE:
0a9d1385 723 case SNDRV_PCM_FORMAT_U32_LE:
b67f4487
C		 724 case SNDRV_PCM_FORMAT_S32_LE:
725 dma_params->data_type = 4;
ba764b3d 726 word_length = 32;
b67f4487
C		 727 break;
728
729 default:
730 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
731 return -EINVAL;
732 }
6a99fb5f 733
5f04c603 734 if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level)
4fa9c1a5
C		 735 dma_params->acnt = 4;
736 else
6a99fb5f
C		 737 dma_params->acnt = dma_params->data_type;
738
70091a3e 739 davinci_config_channel_size(mcasp, word_length);
b67f4487
C		 740
741 return 0;
742}
743
744static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
745 int cmd, struct snd_soc_dai *cpu_dai)
746{
70091a3e 747 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 748 int ret = 0;
749
750 switch (cmd) {
b67f4487 751 case SNDRV_PCM_TRIGGER_RESUME:
e473b847
C		 752 case SNDRV_PCM_TRIGGER_START:
753 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
70091a3e 754 davinci_mcasp_start(mcasp, substream->stream);
b67f4487 755 break;
b67f4487 756 case SNDRV_PCM_TRIGGER_SUSPEND:
a47979b5 757 case SNDRV_PCM_TRIGGER_STOP:
b67f4487 758 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
70091a3e 759 davinci_mcasp_stop(mcasp, substream->stream);
b67f4487
C		 760 break;
761
762 default:
763 ret = -EINVAL;
764 }
765
766 return ret;
767}
768
85e7652d 769static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
b67f4487
C		 770 .trigger = davinci_mcasp_trigger,
771 .hw_params = davinci_mcasp_hw_params,
772 .set_fmt = davinci_mcasp_set_dai_fmt,
4ed8c9b7 773 .set_clkdiv = davinci_mcasp_set_clkdiv,
5b66aa2d 774 .set_sysclk = davinci_mcasp_set_sysclk,
b67f4487
C		 775};
776
d5902f69
PU		 777static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
778{
779 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
780
781 if (mcasp->version == MCASP_VERSION_4) {
782 /* Using dmaengine PCM */
783 dai->playback_dma_data =
784 &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
785 dai->capture_dma_data =
786 &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
787 } else {
788 /* Using davinci-pcm */
789 dai->playback_dma_data = mcasp->dma_params;
790 dai->capture_dma_data = mcasp->dma_params;
791 }
792
793 return 0;
794}
795
135014ad
PU		 796#ifdef CONFIG_PM_SLEEP
797static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
798{
799 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
790bb94b 800 struct davinci_mcasp_context *context = &mcasp->context;
135014ad 801
790bb94b
PU		 802 context->txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
803 context->rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
804 context->txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
805 context->rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
806 context->aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
807 context->aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
808 context->pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
135014ad
PU		 809
810 return 0;
811}
812
813static int davinci_mcasp_resume(struct snd_soc_dai *dai)
814{
815 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
790bb94b
PU		 816 struct davinci_mcasp_context *context = &mcasp->context;
817
818 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, context->txfmtctl);
819 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, context->rxfmtctl);
820 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, context->txfmt);
821 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, context->rxfmt);
822 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, context->aclkxctl);
823 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, context->aclkrctl);
824 mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, context->pdir);
135014ad
PU		 825
826 return 0;
827}
828#else
829#define davinci_mcasp_suspend NULL
830#define davinci_mcasp_resume NULL
831#endif
832
ed29cd5e
PU		 833#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
834
0a9d1385
BG		 835#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
836 SNDRV_PCM_FMTBIT_U8 | \
837 SNDRV_PCM_FMTBIT_S16_LE | \
838 SNDRV_PCM_FMTBIT_U16_LE | \
21eb24d8
DM		 839 SNDRV_PCM_FMTBIT_S24_LE | \
840 SNDRV_PCM_FMTBIT_U24_LE | \
841 SNDRV_PCM_FMTBIT_S24_3LE | \
842 SNDRV_PCM_FMTBIT_U24_3LE | \
0a9d1385
BG		 843 SNDRV_PCM_FMTBIT_S32_LE | \
844 SNDRV_PCM_FMTBIT_U32_LE)
845
f0fba2ad 846static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
b67f4487 847 {
f0fba2ad 848 .name = "davinci-mcasp.0",
d5902f69 849 .probe = davinci_mcasp_dai_probe,
135014ad
PU		 850 .suspend = davinci_mcasp_suspend,
851 .resume = davinci_mcasp_resume,
b67f4487
C		 852 .playback = {
853 .channels_min = 2,
2952b27e 854 .channels_max = 32 * 16,
b67f4487 855 .rates = DAVINCI_MCASP_RATES,
0a9d1385 856 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 857 },
858 .capture = {
859 .channels_min = 2,
2952b27e 860 .channels_max = 32 * 16,
b67f4487 861 .rates = DAVINCI_MCASP_RATES,
0a9d1385 862 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 863 },
864 .ops = &davinci_mcasp_dai_ops,
865
866 },
867 {
58e48d97 868 .name = "davinci-mcasp.1",
d5902f69 869 .probe = davinci_mcasp_dai_probe,
b67f4487
C		 870 .playback = {
871 .channels_min = 1,
872 .channels_max = 384,
873 .rates = DAVINCI_MCASP_RATES,
0a9d1385 874 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 875 },
876 .ops = &davinci_mcasp_dai_ops,
877 },
878
879};
b67f4487 880
eeef0eda
KM		 881static const struct snd_soc_component_driver davinci_mcasp_component = {
882 .name = "davinci-mcasp",
883};
884
256ba181 885/* Some HW specific values and defaults. The rest is filled in from DT. */
d1debafc 886static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
256ba181
JS		 887 .tx_dma_offset = 0x400,
888 .rx_dma_offset = 0x400,
889 .asp_chan_q = EVENTQ_0,
890 .version = MCASP_VERSION_1,
891};
892
d1debafc 893static struct davinci_mcasp_pdata da830_mcasp_pdata = {
256ba181
JS		 894 .tx_dma_offset = 0x2000,
895 .rx_dma_offset = 0x2000,
896 .asp_chan_q = EVENTQ_0,
897 .version = MCASP_VERSION_2,
898};
899
d1debafc 900static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
256ba181
JS		 901 .tx_dma_offset = 0,
902 .rx_dma_offset = 0,
903 .asp_chan_q = EVENTQ_0,
904 .version = MCASP_VERSION_3,
905};
906
d1debafc 907static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
453c4990
PU		 908 .tx_dma_offset = 0x200,
909 .rx_dma_offset = 0x284,
910 .asp_chan_q = EVENTQ_0,
911 .version = MCASP_VERSION_4,
912};
913
3e3b8c34
HG		 914static const struct of_device_id mcasp_dt_ids[] = {
915 {
916 .compatible = "ti,dm646x-mcasp-audio",
256ba181 917 .data = &dm646x_mcasp_pdata,
3e3b8c34
HG		 918 },
919 {
920 .compatible = "ti,da830-mcasp-audio",
256ba181 921 .data = &da830_mcasp_pdata,
3e3b8c34 922 },
e5ec69da 923 {
3af9e031 924 .compatible = "ti,am33xx-mcasp-audio",
b14899da 925 .data = &am33xx_mcasp_pdata,
e5ec69da 926 },
453c4990
PU		 927 {
928 .compatible = "ti,dra7-mcasp-audio",
929 .data = &dra7_mcasp_pdata,
930 },
3e3b8c34
HG		 931 { /* sentinel */ }
932};
933MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
934
ae726e93
PU		 935static int mcasp_reparent_fck(struct platform_device *pdev)
936{
937 struct device_node *node = pdev->dev.of_node;
938 struct clk *gfclk, *parent_clk;
939 const char *parent_name;
940 int ret;
941
942 if (!node)
943 return 0;
944
945 parent_name = of_get_property(node, "fck_parent", NULL);
946 if (!parent_name)
947 return 0;
948
949 gfclk = clk_get(&pdev->dev, "fck");
950 if (IS_ERR(gfclk)) {
951 dev_err(&pdev->dev, "failed to get fck\n");
952 return PTR_ERR(gfclk);
953 }
954
955 parent_clk = clk_get(NULL, parent_name);
956 if (IS_ERR(parent_clk)) {
957 dev_err(&pdev->dev, "failed to get parent clock\n");
958 ret = PTR_ERR(parent_clk);
959 goto err1;
960 }
961
962 ret = clk_set_parent(gfclk, parent_clk);
963 if (ret) {
964 dev_err(&pdev->dev, "failed to reparent fck\n");
965 goto err2;
966 }
967
968err2:
969 clk_put(parent_clk);
970err1:
971 clk_put(gfclk);
972 return ret;
973}
974
d1debafc 975static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
3e3b8c34
HG		 976 struct platform_device *pdev)
977{
978 struct device_node *np = pdev->dev.of_node;
d1debafc 979 struct davinci_mcasp_pdata *pdata = NULL;
3e3b8c34 980 const struct of_device_id *match =
ea421eb1 981 of_match_device(mcasp_dt_ids, &pdev->dev);
4023fe6f 982 struct of_phandle_args dma_spec;
3e3b8c34
HG		 983
984 const u32 *of_serial_dir32;
3e3b8c34
HG		 985 u32 val;
986 int i, ret = 0;
987
988 if (pdev->dev.platform_data) {
989 pdata = pdev->dev.platform_data;
990 return pdata;
991 } else if (match) {
d1debafc 992 pdata = (struct davinci_mcasp_pdata*) match->data;
3e3b8c34
HG		 993 } else {
994 /* control shouldn't reach here. something is wrong */
995 ret = -EINVAL;
996 goto nodata;
997 }
998
3e3b8c34
HG		 999 ret = of_property_read_u32(np, "op-mode", &val);
1000 if (ret >= 0)
1001 pdata->op_mode = val;
1002
1003 ret = of_property_read_u32(np, "tdm-slots", &val);
2952b27e
MB		 1004 if (ret >= 0) {
1005 if (val < 2 || val > 32) {
1006 dev_err(&pdev->dev,
1007 "tdm-slots must be in rage [2-32]\n");
1008 ret = -EINVAL;
1009 goto nodata;
1010 }
1011
3e3b8c34 1012 pdata->tdm_slots = val;
2952b27e 1013 }
3e3b8c34 1014
3e3b8c34
HG		 1015 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1016 val /= sizeof(u32);
3e3b8c34 1017 if (of_serial_dir32) {
1427e660
PU		 1018 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1019 (sizeof(*of_serial_dir) * val),
1020 GFP_KERNEL);
3e3b8c34
HG		 1021 if (!of_serial_dir) {
1022 ret = -ENOMEM;
1023 goto nodata;
1024 }
1025
1427e660 1026 for (i = 0; i < val; i++)
3e3b8c34
HG		 1027 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1028
1427e660 1029 pdata->num_serializer = val;
3e3b8c34
HG		 1030 pdata->serial_dir = of_serial_dir;
1031 }
1032
4023fe6f
JS		 1033 ret = of_property_match_string(np, "dma-names", "tx");
1034 if (ret < 0)
1035 goto nodata;
1036
1037 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1038 &dma_spec);
1039 if (ret < 0)
1040 goto nodata;
1041
1042 pdata->tx_dma_channel = dma_spec.args[0];
1043
1044 ret = of_property_match_string(np, "dma-names", "rx");
1045 if (ret < 0)
1046 goto nodata;
1047
1048 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1049 &dma_spec);
1050 if (ret < 0)
1051 goto nodata;
1052
1053 pdata->rx_dma_channel = dma_spec.args[0];
1054
3e3b8c34
HG		 1055 ret = of_property_read_u32(np, "tx-num-evt", &val);
1056 if (ret >= 0)
1057 pdata->txnumevt = val;
1058
1059 ret = of_property_read_u32(np, "rx-num-evt", &val);
1060 if (ret >= 0)
1061 pdata->rxnumevt = val;
1062
1063 ret = of_property_read_u32(np, "sram-size-playback", &val);
1064 if (ret >= 0)
1065 pdata->sram_size_playback = val;
1066
1067 ret = of_property_read_u32(np, "sram-size-capture", &val);
1068 if (ret >= 0)
1069 pdata->sram_size_capture = val;
1070
1071 return pdata;
1072
1073nodata:
1074 if (ret < 0) {
1075 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1076 ret);
1077 pdata = NULL;
1078 }
1079 return pdata;
1080}
1081
b67f4487
C		 1082static int davinci_mcasp_probe(struct platform_device *pdev)
1083{
64ebdec3 1084 struct davinci_pcm_dma_params *dma_params;
8de131f2 1085 struct snd_dmaengine_dai_dma_data *dma_data;
256ba181 1086 struct resource *mem, *ioarea, *res, *dat;
d1debafc 1087 struct davinci_mcasp_pdata *pdata;
70091a3e 1088 struct davinci_mcasp *mcasp;
96d31e2b 1089 int ret;
b67f4487 1090
3e3b8c34
HG		 1091 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1092 dev_err(&pdev->dev, "No platform data supplied\n");
1093 return -EINVAL;
1094 }
1095
70091a3e 1096 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
96d31e2b 1097 GFP_KERNEL);
70091a3e 1098 if (!mcasp)
b67f4487
C		 1099 return -ENOMEM;
1100
3e3b8c34
HG		 1101 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1102 if (!pdata) {
1103 dev_err(&pdev->dev, "no platform data\n");
1104 return -EINVAL;
1105 }
1106
256ba181 1107 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
b67f4487 1108 if (!mem) {
70091a3e 1109 dev_warn(mcasp->dev,
256ba181
JS		 1110 "\"mpu\" mem resource not found, using index 0\n");
1111 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1112 if (!mem) {
1113 dev_err(&pdev->dev, "no mem resource?\n");
1114 return -ENODEV;
1115 }
b67f4487
C		 1116 }
1117
96d31e2b 1118 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
d852f446 1119 resource_size(mem), pdev->name);
b67f4487
C		 1120 if (!ioarea) {
1121 dev_err(&pdev->dev, "Audio region already claimed\n");
96d31e2b 1122 return -EBUSY;
b67f4487
C		 1123 }
1124
10884347 1125 pm_runtime_enable(&pdev->dev);
b67f4487 1126
10884347
HG		 1127 ret = pm_runtime_get_sync(&pdev->dev);
1128 if (IS_ERR_VALUE(ret)) {
1129 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1130 return ret;
1131 }
b67f4487 1132
70091a3e
PU		 1133 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1134 if (!mcasp->base) {
4f82f028
VB		 1135 dev_err(&pdev->dev, "ioremap failed\n");
1136 ret = -ENOMEM;
b6bb3709 1137 goto err;
4f82f028
VB		 1138 }
1139
70091a3e
PU		 1140 mcasp->op_mode = pdata->op_mode;
1141 mcasp->tdm_slots = pdata->tdm_slots;
1142 mcasp->num_serializer = pdata->num_serializer;
1143 mcasp->serial_dir = pdata->serial_dir;
1144 mcasp->version = pdata->version;
1145 mcasp->txnumevt = pdata->txnumevt;
1146 mcasp->rxnumevt = pdata->rxnumevt;
487dce88 1147
70091a3e 1148 mcasp->dev = &pdev->dev;
b67f4487 1149
256ba181 1150 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
cbc7956c
PU		 1151 if (dat)
1152 mcasp->dat_port = true;
256ba181 1153
64ebdec3 1154 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
8de131f2 1155 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
64ebdec3
PU		 1156 dma_params->asp_chan_q = pdata->asp_chan_q;
1157 dma_params->ram_chan_q = pdata->ram_chan_q;
1158 dma_params->sram_pool = pdata->sram_pool;
1159 dma_params->sram_size = pdata->sram_size_playback;
cbc7956c 1160 if (dat)
64ebdec3 1161 dma_params->dma_addr = dat->start;
cbc7956c 1162 else
64ebdec3 1163 dma_params->dma_addr = mem->start + pdata->tx_dma_offset;
b67f4487 1164
453c4990 1165 /* Unconditional dmaengine stuff */
8de131f2 1166 dma_data->addr = dma_params->dma_addr;
453c4990 1167
b67f4487 1168 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
4023fe6f 1169 if (res)
64ebdec3 1170 dma_params->channel = res->start;
4023fe6f 1171 else
64ebdec3 1172 dma_params->channel = pdata->tx_dma_channel;
92e2a6f6 1173
8de131f2
PU		 1174 /* dmaengine filter data for DT and non-DT boot */
1175 if (pdev->dev.of_node)
1176 dma_data->filter_data = "tx";
1177 else
1178 dma_data->filter_data = &dma_params->channel;
1179
64ebdec3 1180 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
8de131f2 1181 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
64ebdec3
PU		 1182 dma_params->asp_chan_q = pdata->asp_chan_q;
1183 dma_params->ram_chan_q = pdata->ram_chan_q;
1184 dma_params->sram_pool = pdata->sram_pool;
1185 dma_params->sram_size = pdata->sram_size_capture;
cbc7956c 1186 if (dat)
64ebdec3 1187 dma_params->dma_addr = dat->start;
cbc7956c 1188 else
64ebdec3 1189 dma_params->dma_addr = mem->start + pdata->rx_dma_offset;
cbc7956c 1190
453c4990 1191 /* Unconditional dmaengine stuff */
8de131f2 1192 dma_data->addr = dma_params->dma_addr;
453c4990 1193
cbc7956c
PU		 1194 if (mcasp->version < MCASP_VERSION_3) {
1195 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
64ebdec3 1196 /* dma_params->dma_addr is pointing to the data port address */
cbc7956c
PU		 1197 mcasp->dat_port = true;
1198 } else {
1199 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1200 }
b67f4487
C		 1201
1202 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
4023fe6f 1203 if (res)
64ebdec3 1204 dma_params->channel = res->start;
4023fe6f 1205 else
64ebdec3 1206 dma_params->channel = pdata->rx_dma_channel;
b67f4487 1207
8de131f2
PU		 1208 /* dmaengine filter data for DT and non-DT boot */
1209 if (pdev->dev.of_node)
1210 dma_data->filter_data = "rx";
1211 else
1212 dma_data->filter_data = &dma_params->channel;
453c4990 1213
70091a3e 1214 dev_set_drvdata(&pdev->dev, mcasp);
ae726e93
PU		 1215
1216 mcasp_reparent_fck(pdev);
1217
b6bb3709
PU		 1218 ret = devm_snd_soc_register_component(&pdev->dev,
1219 &davinci_mcasp_component,
1220 &davinci_mcasp_dai[pdata->op_mode], 1);
b67f4487
C		 1221
1222 if (ret != 0)
b6bb3709 1223 goto err;
f08095a4 1224
d5c6c59a
PU		 1225 switch (mcasp->version) {
1226 case MCASP_VERSION_1:
1227 case MCASP_VERSION_2:
1228 case MCASP_VERSION_3:
453c4990 1229 ret = davinci_soc_platform_register(&pdev->dev);
d5c6c59a
PU		 1230 break;
1231 case MCASP_VERSION_4:
1232 ret = omap_pcm_platform_register(&pdev->dev);
1233 break;
1234 default:
1235 dev_err(&pdev->dev, "Invalid McASP version: %d\n",
1236 mcasp->version);
1237 ret = -EINVAL;
1238 break;
1239 }
1240
1241 if (ret) {
1242 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
b6bb3709 1243 goto err;
f08095a4
HG		 1244 }
1245
b67f4487
C		 1246 return 0;
1247
b6bb3709 1248err:
10884347
HG		 1249 pm_runtime_put_sync(&pdev->dev);
1250 pm_runtime_disable(&pdev->dev);
b67f4487
C		 1251 return ret;
1252}
1253
1254static int davinci_mcasp_remove(struct platform_device *pdev)
1255{
10884347
HG		 1256 pm_runtime_put_sync(&pdev->dev);
1257 pm_runtime_disable(&pdev->dev);
b67f4487 1258
b67f4487
C		 1259 return 0;
1260}
1261
1262static struct platform_driver davinci_mcasp_driver = {
1263 .probe = davinci_mcasp_probe,
1264 .remove = davinci_mcasp_remove,
1265 .driver = {
1266 .name = "davinci-mcasp",
1267 .owner = THIS_MODULE,
ea421eb1 1268 .of_match_table = mcasp_dt_ids,
b67f4487
C		 1269 },
1270};
1271
f9b8a514 1272module_platform_driver(davinci_mcasp_driver);
b67f4487
C		 1273
1274MODULE_AUTHOR("Steve Chen");
1275MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1276MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)