Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
b67f4487 | 29 | |
6479285d | 30 | #include <sound/asoundef.h> |
b67f4487 C |
31 | #include <sound/core.h> |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/initval.h> | |
35 | #include <sound/soc.h> | |
453c4990 | 36 | #include <sound/dmaengine_pcm.h> |
87c19364 | 37 | #include <sound/omap-pcm.h> |
b67f4487 C |
38 | |
39 | #include "davinci-pcm.h" | |
f3f9cfa8 | 40 | #include "edma-pcm.h" |
b67f4487 C |
41 | #include "davinci-mcasp.h" |
42 | ||
0bf0e8ae PU |
43 | #define MCASP_MAX_AFIFO_DEPTH 64 |
44 | ||
1cc0c054 PU |
45 | static u32 context_regs[] = { |
46 | DAVINCI_MCASP_TXFMCTL_REG, | |
47 | DAVINCI_MCASP_RXFMCTL_REG, | |
48 | DAVINCI_MCASP_TXFMT_REG, | |
49 | DAVINCI_MCASP_RXFMT_REG, | |
50 | DAVINCI_MCASP_ACLKXCTL_REG, | |
51 | DAVINCI_MCASP_ACLKRCTL_REG, | |
f114ce60 PU |
52 | DAVINCI_MCASP_AHCLKXCTL_REG, |
53 | DAVINCI_MCASP_AHCLKRCTL_REG, | |
1cc0c054 | 54 | DAVINCI_MCASP_PDIR_REG, |
f114ce60 PU |
55 | DAVINCI_MCASP_RXMASK_REG, |
56 | DAVINCI_MCASP_TXMASK_REG, | |
57 | DAVINCI_MCASP_RXTDM_REG, | |
58 | DAVINCI_MCASP_TXTDM_REG, | |
1cc0c054 PU |
59 | }; |
60 | ||
790bb94b | 61 | struct davinci_mcasp_context { |
1cc0c054 | 62 | u32 config_regs[ARRAY_SIZE(context_regs)]; |
f114ce60 PU |
63 | u32 afifo_regs[2]; /* for read/write fifo control registers */ |
64 | u32 *xrsr_regs; /* for serializer configuration */ | |
790bb94b PU |
65 | }; |
66 | ||
70091a3e | 67 | struct davinci_mcasp { |
21400a72 | 68 | struct davinci_pcm_dma_params dma_params[2]; |
453c4990 | 69 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 70 | void __iomem *base; |
487dce88 | 71 | u32 fifo_base; |
21400a72 | 72 | struct device *dev; |
a7a3324a | 73 | struct snd_pcm_substream *substreams[2]; |
21400a72 PU |
74 | |
75 | /* McASP specific data */ | |
76 | int tdm_slots; | |
77 | u8 op_mode; | |
78 | u8 num_serializer; | |
79 | u8 *serial_dir; | |
80 | u8 version; | |
8267525c | 81 | u8 bclk_div; |
21400a72 | 82 | u16 bclk_lrclk_ratio; |
4dcb5a0b | 83 | int streams; |
a7a3324a | 84 | u32 irq_request[2]; |
21400a72 | 85 | |
ab8b14b6 JS |
86 | int sysclk_freq; |
87 | bool bclk_master; | |
88 | ||
21400a72 PU |
89 | /* McASP FIFO related */ |
90 | u8 txnumevt; | |
91 | u8 rxnumevt; | |
92 | ||
cbc7956c PU |
93 | bool dat_port; |
94 | ||
11277833 PU |
95 | /* Used for comstraint setting on the second stream */ |
96 | u32 channels; | |
97 | ||
21400a72 | 98 | #ifdef CONFIG_PM_SLEEP |
790bb94b | 99 | struct davinci_mcasp_context context; |
21400a72 PU |
100 | #endif |
101 | }; | |
102 | ||
f68205a7 PU |
103 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
104 | u32 val) | |
b67f4487 | 105 | { |
f68205a7 | 106 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
107 | __raw_writel(__raw_readl(reg) | val, reg); |
108 | } | |
109 | ||
f68205a7 PU |
110 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
111 | u32 val) | |
b67f4487 | 112 | { |
f68205a7 | 113 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
114 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
115 | } | |
116 | ||
f68205a7 PU |
117 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
118 | u32 val, u32 mask) | |
b67f4487 | 119 | { |
f68205a7 | 120 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
121 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
122 | } | |
123 | ||
f68205a7 PU |
124 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
125 | u32 val) | |
b67f4487 | 126 | { |
f68205a7 | 127 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
128 | } |
129 | ||
f68205a7 | 130 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 131 | { |
f68205a7 | 132 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
133 | } |
134 | ||
f68205a7 | 135 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
136 | { |
137 | int i = 0; | |
138 | ||
f68205a7 | 139 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
140 | |
141 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
142 | /* loop count is to avoid the lock-up */ | |
143 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 144 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
145 | break; |
146 | } | |
147 | ||
f68205a7 | 148 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
149 | printk(KERN_ERR "GBLCTL write error\n"); |
150 | } | |
151 | ||
4dcb5a0b PU |
152 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
153 | { | |
f68205a7 PU |
154 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
155 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
156 | |
157 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
158 | } | |
159 | ||
70091a3e | 160 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 161 | { |
bb372af0 PU |
162 | if (mcasp->rxnumevt) { /* enable FIFO */ |
163 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
164 | ||
165 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
166 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
167 | } | |
168 | ||
44982735 | 169 | /* Start clocks */ |
f68205a7 PU |
170 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
171 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
172 | /* |
173 | * When ASYNC == 0 the transmit and receive sections operate | |
174 | * synchronously from the transmit clock and frame sync. We need to make | |
175 | * sure that the TX signlas are enabled when starting reception. | |
176 | */ | |
177 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
178 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
179 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
180 | } |
181 | ||
44982735 | 182 | /* Activate serializer(s) */ |
f68205a7 | 183 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
44982735 | 184 | /* Release RX state machine */ |
f68205a7 | 185 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
44982735 | 186 | /* Release Frame Sync generator */ |
f68205a7 | 187 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
4dcb5a0b | 188 | if (mcasp_is_synchronous(mcasp)) |
f68205a7 | 189 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
a7a3324a MLC |
190 | |
191 | /* enable receive IRQs */ | |
192 | mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, | |
193 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); | |
b67f4487 C |
194 | } |
195 | ||
70091a3e | 196 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 197 | { |
6a99fb5f C |
198 | u32 cnt; |
199 | ||
bb372af0 PU |
200 | if (mcasp->txnumevt) { /* enable FIFO */ |
201 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
202 | ||
203 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
204 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
205 | } | |
206 | ||
36bcecd0 | 207 | /* Start clocks */ |
f68205a7 PU |
208 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
209 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
36bcecd0 | 210 | /* Activate serializer(s) */ |
f68205a7 | 211 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); |
b67f4487 | 212 | |
36bcecd0 | 213 | /* wait for XDATA to be cleared */ |
6a99fb5f | 214 | cnt = 0; |
36bcecd0 PU |
215 | while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & |
216 | ~XRDATA) && (cnt < 100000)) | |
6a99fb5f C |
217 | cnt++; |
218 | ||
36bcecd0 PU |
219 | /* Release TX state machine */ |
220 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); | |
221 | /* Release Frame Sync generator */ | |
222 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
a7a3324a MLC |
223 | |
224 | /* enable transmit IRQs */ | |
225 | mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, | |
226 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); | |
b67f4487 C |
227 | } |
228 | ||
70091a3e | 229 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 230 | { |
4dcb5a0b PU |
231 | mcasp->streams++; |
232 | ||
bb372af0 | 233 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 234 | mcasp_start_tx(mcasp); |
bb372af0 | 235 | else |
70091a3e | 236 | mcasp_start_rx(mcasp); |
b67f4487 C |
237 | } |
238 | ||
70091a3e | 239 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 240 | { |
a7a3324a MLC |
241 | /* disable IRQ sources */ |
242 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, | |
243 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); | |
244 | ||
4dcb5a0b PU |
245 | /* |
246 | * In synchronous mode stop the TX clocks if no other stream is | |
247 | * running | |
248 | */ | |
249 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) | |
f68205a7 | 250 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
4dcb5a0b | 251 | |
f68205a7 PU |
252 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
253 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
254 | |
255 | if (mcasp->rxnumevt) { /* disable FIFO */ | |
256 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
257 | ||
258 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
259 | } | |
b67f4487 C |
260 | } |
261 | ||
70091a3e | 262 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 263 | { |
4dcb5a0b PU |
264 | u32 val = 0; |
265 | ||
a7a3324a MLC |
266 | /* disable IRQ sources */ |
267 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, | |
268 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); | |
269 | ||
4dcb5a0b PU |
270 | /* |
271 | * In synchronous mode keep TX clocks running if the capture stream is | |
272 | * still running. | |
273 | */ | |
274 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
275 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
276 | ||
f68205a7 PU |
277 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
278 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
279 | |
280 | if (mcasp->txnumevt) { /* disable FIFO */ | |
281 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
282 | ||
283 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
284 | } | |
b67f4487 C |
285 | } |
286 | ||
70091a3e | 287 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 288 | { |
4dcb5a0b PU |
289 | mcasp->streams--; |
290 | ||
0380866a | 291 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 292 | mcasp_stop_tx(mcasp); |
0380866a | 293 | else |
70091a3e | 294 | mcasp_stop_rx(mcasp); |
b67f4487 C |
295 | } |
296 | ||
a7a3324a MLC |
297 | static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) |
298 | { | |
299 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
300 | struct snd_pcm_substream *substream; | |
301 | u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; | |
302 | u32 handled_mask = 0; | |
303 | u32 stat; | |
304 | ||
305 | stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); | |
306 | if (stat & XUNDRN & irq_mask) { | |
307 | dev_warn(mcasp->dev, "Transmit buffer underflow\n"); | |
308 | handled_mask |= XUNDRN; | |
309 | ||
310 | substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; | |
311 | if (substream) { | |
312 | snd_pcm_stream_lock_irq(substream); | |
313 | if (snd_pcm_running(substream)) | |
314 | snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); | |
315 | snd_pcm_stream_unlock_irq(substream); | |
316 | } | |
317 | } | |
318 | ||
319 | if (!handled_mask) | |
320 | dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", | |
321 | stat); | |
322 | ||
323 | if (stat & XRERR) | |
324 | handled_mask |= XRERR; | |
325 | ||
326 | /* Ack the handled event only */ | |
327 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); | |
328 | ||
329 | return IRQ_RETVAL(handled_mask); | |
330 | } | |
331 | ||
332 | static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) | |
333 | { | |
334 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
335 | struct snd_pcm_substream *substream; | |
336 | u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; | |
337 | u32 handled_mask = 0; | |
338 | u32 stat; | |
339 | ||
340 | stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); | |
341 | if (stat & ROVRN & irq_mask) { | |
342 | dev_warn(mcasp->dev, "Receive buffer overflow\n"); | |
343 | handled_mask |= ROVRN; | |
344 | ||
345 | substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; | |
346 | if (substream) { | |
347 | snd_pcm_stream_lock_irq(substream); | |
348 | if (snd_pcm_running(substream)) | |
349 | snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); | |
350 | snd_pcm_stream_unlock_irq(substream); | |
351 | } | |
352 | } | |
353 | ||
354 | if (!handled_mask) | |
355 | dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", | |
356 | stat); | |
357 | ||
358 | if (stat & XRERR) | |
359 | handled_mask |= XRERR; | |
360 | ||
361 | /* Ack the handled event only */ | |
362 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); | |
363 | ||
364 | return IRQ_RETVAL(handled_mask); | |
365 | } | |
366 | ||
5a1b8a80 PU |
367 | static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) |
368 | { | |
369 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
370 | irqreturn_t ret = IRQ_NONE; | |
371 | ||
372 | if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) | |
373 | ret = davinci_mcasp_tx_irq_handler(irq, data); | |
374 | ||
375 | if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) | |
376 | ret |= davinci_mcasp_rx_irq_handler(irq, data); | |
377 | ||
378 | return ret; | |
379 | } | |
380 | ||
b67f4487 C |
381 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
382 | unsigned int fmt) | |
383 | { | |
70091a3e | 384 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 385 | int ret = 0; |
6dfa9a4e | 386 | u32 data_delay; |
83f12503 | 387 | bool fs_pol_rising; |
ffd950f7 | 388 | bool inv_fs = false; |
b67f4487 | 389 | |
1d17a04e | 390 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d | 391 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
188edc59 PU |
392 | case SND_SOC_DAIFMT_DSP_A: |
393 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
394 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
188edc59 PU |
395 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
396 | data_delay = 1; | |
397 | break; | |
5296cf2d DM |
398 | case SND_SOC_DAIFMT_DSP_B: |
399 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
400 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
401 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
402 | /* No delay after FS */ |
403 | data_delay = 0; | |
5296cf2d | 404 | break; |
ffd950f7 | 405 | case SND_SOC_DAIFMT_I2S: |
5296cf2d | 406 | /* configure a full-word SYNC pulse (LRCLK) */ |
f68205a7 PU |
407 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
408 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
409 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
410 | data_delay = 1; | |
ffd950f7 PU |
411 | /* FS need to be inverted */ |
412 | inv_fs = true; | |
5296cf2d | 413 | break; |
423761e0 PU |
414 | case SND_SOC_DAIFMT_LEFT_J: |
415 | /* configure a full-word SYNC pulse (LRCLK) */ | |
416 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
417 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
418 | /* No delay after FS */ | |
419 | data_delay = 0; | |
420 | break; | |
ffd950f7 PU |
421 | default: |
422 | ret = -EINVAL; | |
423 | goto out; | |
5296cf2d DM |
424 | } |
425 | ||
6dfa9a4e PU |
426 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), |
427 | FSXDLY(3)); | |
428 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), | |
429 | FSRDLY(3)); | |
430 | ||
b67f4487 C |
431 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
432 | case SND_SOC_DAIFMT_CBS_CFS: | |
433 | /* codec is clock and frame slave */ | |
f68205a7 PU |
434 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
435 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 436 | |
f68205a7 PU |
437 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
438 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 439 | |
f68205a7 PU |
440 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
441 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 442 | mcasp->bclk_master = 1; |
b67f4487 | 443 | break; |
517ee6cf C |
444 | case SND_SOC_DAIFMT_CBM_CFS: |
445 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
446 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
447 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 448 | |
f68205a7 PU |
449 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
450 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 451 | |
f68205a7 PU |
452 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR); |
453 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR); | |
ab8b14b6 | 454 | mcasp->bclk_master = 0; |
517ee6cf | 455 | break; |
b67f4487 C |
456 | case SND_SOC_DAIFMT_CBM_CFM: |
457 | /* codec is clock and frame master */ | |
f68205a7 PU |
458 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
459 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 460 | |
f68205a7 PU |
461 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
462 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 463 | |
f68205a7 PU |
464 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, |
465 | ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR); | |
ab8b14b6 | 466 | mcasp->bclk_master = 0; |
b67f4487 | 467 | break; |
b67f4487 | 468 | default: |
1d17a04e PU |
469 | ret = -EINVAL; |
470 | goto out; | |
b67f4487 C |
471 | } |
472 | ||
473 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
474 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 | 475 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 476 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 477 | fs_pol_rising = true; |
b67f4487 | 478 | break; |
b67f4487 | 479 | case SND_SOC_DAIFMT_NB_IF: |
f68205a7 | 480 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 481 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 482 | fs_pol_rising = false; |
b67f4487 | 483 | break; |
b67f4487 | 484 | case SND_SOC_DAIFMT_IB_IF: |
f68205a7 | 485 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 486 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 487 | fs_pol_rising = false; |
b67f4487 | 488 | break; |
b67f4487 | 489 | case SND_SOC_DAIFMT_NB_NF: |
f68205a7 | 490 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
f68205a7 | 491 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 492 | fs_pol_rising = true; |
b67f4487 | 493 | break; |
b67f4487 | 494 | default: |
1d17a04e | 495 | ret = -EINVAL; |
83f12503 PU |
496 | goto out; |
497 | } | |
498 | ||
ffd950f7 PU |
499 | if (inv_fs) |
500 | fs_pol_rising = !fs_pol_rising; | |
501 | ||
83f12503 PU |
502 | if (fs_pol_rising) { |
503 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
504 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
505 | } else { | |
506 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
507 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 | 508 | } |
1d17a04e PU |
509 | out: |
510 | pm_runtime_put_sync(mcasp->dev); | |
511 | return ret; | |
b67f4487 C |
512 | } |
513 | ||
8813543e JS |
514 | static int __davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
515 | int div, bool explicit) | |
4ed8c9b7 | 516 | { |
70091a3e | 517 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
4ed8c9b7 DM |
518 | |
519 | switch (div_id) { | |
520 | case 0: /* MCLK divider */ | |
f68205a7 | 521 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 522 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 523 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
524 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
525 | break; | |
526 | ||
527 | case 1: /* BCLK divider */ | |
f68205a7 | 528 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 529 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 530 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 | 531 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
8813543e JS |
532 | if (explicit) |
533 | mcasp->bclk_div = div; | |
4ed8c9b7 DM |
534 | break; |
535 | ||
1b3bc060 | 536 | case 2: /* BCLK/LRCLK ratio */ |
70091a3e | 537 | mcasp->bclk_lrclk_ratio = div; |
1b3bc060 DM |
538 | break; |
539 | ||
4ed8c9b7 DM |
540 | default: |
541 | return -EINVAL; | |
542 | } | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
8813543e JS |
547 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
548 | int div) | |
549 | { | |
550 | return __davinci_mcasp_set_clkdiv(dai, div_id, div, 1); | |
551 | } | |
552 | ||
5b66aa2d DM |
553 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
554 | unsigned int freq, int dir) | |
555 | { | |
70091a3e | 556 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d DM |
557 | |
558 | if (dir == SND_SOC_CLOCK_OUT) { | |
f68205a7 PU |
559 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
560 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
561 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d | 562 | } else { |
f68205a7 PU |
563 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
564 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
565 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX); | |
5b66aa2d DM |
566 | } |
567 | ||
ab8b14b6 JS |
568 | mcasp->sysclk_freq = freq; |
569 | ||
5b66aa2d DM |
570 | return 0; |
571 | } | |
572 | ||
70091a3e | 573 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
ba764b3d | 574 | int word_length) |
b67f4487 | 575 | { |
ba764b3d | 576 | u32 fmt; |
79671892 | 577 | u32 tx_rotate = (word_length / 4) & 0x7; |
ba764b3d | 578 | u32 mask = (1ULL << word_length) - 1; |
fe0a29e1 PU |
579 | /* |
580 | * For captured data we should not rotate, inversion and masking is | |
581 | * enoguh to get the data to the right position: | |
582 | * Format data from bus after reverse (XRBUF) | |
583 | * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| | |
584 | * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
585 | * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
586 | * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| | |
587 | */ | |
588 | u32 rx_rotate = 0; | |
b67f4487 | 589 | |
1b3bc060 DM |
590 | /* |
591 | * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv() | |
592 | * callback, take it into account here. That allows us to for example | |
593 | * send 32 bits per channel to the codec, while only 16 of them carry | |
594 | * audio payload. | |
d486fea6 MB |
595 | * The clock ratio is given for a full period of data (for I2S format |
596 | * both left and right channels), so it has to be divided by number of | |
597 | * tdm-slots (for I2S - divided by 2). | |
1b3bc060 | 598 | */ |
d742b925 PU |
599 | if (mcasp->bclk_lrclk_ratio) { |
600 | u32 slot_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots; | |
601 | ||
602 | /* | |
603 | * When we have more bclk then it is needed for the data, we | |
604 | * need to use the rotation to move the received samples to have | |
605 | * correct alignment. | |
606 | */ | |
607 | rx_rotate = (slot_length - word_length) / 4; | |
608 | word_length = slot_length; | |
609 | } | |
1b3bc060 | 610 | |
ba764b3d DM |
611 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
612 | fmt = (word_length >> 1) - 1; | |
b67f4487 | 613 | |
70091a3e | 614 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
615 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
616 | RXSSZ(0x0F)); | |
617 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
618 | TXSSZ(0x0F)); | |
619 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
620 | TXROT(7)); | |
621 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
622 | RXROT(7)); | |
623 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
624 | } |
625 | ||
f68205a7 | 626 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 627 | |
b67f4487 C |
628 | return 0; |
629 | } | |
630 | ||
662ffae9 | 631 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
dd093a0f | 632 | int period_words, int channels) |
b67f4487 | 633 | { |
5f04c603 PU |
634 | struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream]; |
635 | struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; | |
b67f4487 | 636 | int i; |
6a99fb5f C |
637 | u8 tx_ser = 0; |
638 | u8 rx_ser = 0; | |
70091a3e | 639 | u8 slots = mcasp->tdm_slots; |
2952b27e | 640 | u8 max_active_serializers = (channels + slots - 1) / slots; |
dd093a0f | 641 | int active_serializers, numevt, n; |
487dce88 | 642 | u32 reg; |
b67f4487 | 643 | /* Default configuration */ |
40448e5e | 644 | if (mcasp->version < MCASP_VERSION_3) |
f68205a7 | 645 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
646 | |
647 | /* All PINS as McASP */ | |
f68205a7 | 648 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
649 | |
650 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
651 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
652 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 653 | } else { |
f68205a7 PU |
654 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
655 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
656 | } |
657 | ||
70091a3e | 658 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
659 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
660 | mcasp->serial_dir[i]); | |
70091a3e | 661 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 662 | tx_ser < max_active_serializers) { |
f68205a7 | 663 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 664 | tx_ser++; |
70091a3e | 665 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 666 | rx_ser < max_active_serializers) { |
f68205a7 | 667 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i)); |
6a99fb5f | 668 | rx_ser++; |
2952b27e | 669 | } else { |
f68205a7 PU |
670 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
671 | SRMOD_INACTIVE, SRMOD_MASK); | |
6a99fb5f C |
672 | } |
673 | } | |
674 | ||
0bf0e8ae PU |
675 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
676 | active_serializers = tx_ser; | |
677 | numevt = mcasp->txnumevt; | |
678 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
679 | } else { | |
680 | active_serializers = rx_ser; | |
681 | numevt = mcasp->rxnumevt; | |
682 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
683 | } | |
ecf327c7 | 684 | |
0bf0e8ae | 685 | if (active_serializers < max_active_serializers) { |
70091a3e | 686 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
0bf0e8ae PU |
687 | "enabled in mcasp (%d)\n", channels, |
688 | active_serializers * slots); | |
ecf327c7 DM |
689 | return -EINVAL; |
690 | } | |
691 | ||
0bf0e8ae | 692 | /* AFIFO is not in use */ |
5f04c603 PU |
693 | if (!numevt) { |
694 | /* Configure the burst size for platform drivers */ | |
33445643 PU |
695 | if (active_serializers > 1) { |
696 | /* | |
697 | * If more than one serializers are in use we have one | |
698 | * DMA request to provide data for all serializers. | |
699 | * For example if three serializers are enabled the DMA | |
700 | * need to transfer three words per DMA request. | |
701 | */ | |
702 | dma_params->fifo_level = active_serializers; | |
703 | dma_data->maxburst = active_serializers; | |
704 | } else { | |
705 | dma_params->fifo_level = 0; | |
706 | dma_data->maxburst = 0; | |
707 | } | |
0bf0e8ae | 708 | return 0; |
5f04c603 | 709 | } |
6a99fb5f | 710 | |
dd093a0f PU |
711 | if (period_words % active_serializers) { |
712 | dev_err(mcasp->dev, "Invalid combination of period words and " | |
713 | "active serializers: %d, %d\n", period_words, | |
714 | active_serializers); | |
715 | return -EINVAL; | |
716 | } | |
717 | ||
718 | /* | |
719 | * Calculate the optimal AFIFO depth for platform side: | |
720 | * The number of words for numevt need to be in steps of active | |
721 | * serializers. | |
722 | */ | |
723 | n = numevt % active_serializers; | |
724 | if (n) | |
725 | numevt += (active_serializers - n); | |
726 | while (period_words % numevt && numevt > 0) | |
727 | numevt -= active_serializers; | |
728 | if (numevt <= 0) | |
0bf0e8ae | 729 | numevt = active_serializers; |
487dce88 | 730 | |
0bf0e8ae PU |
731 | mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); |
732 | mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); | |
2952b27e | 733 | |
5f04c603 | 734 | /* Configure the burst size for platform drivers */ |
33445643 PU |
735 | if (numevt == 1) |
736 | numevt = 0; | |
5f04c603 PU |
737 | dma_params->fifo_level = numevt; |
738 | dma_data->maxburst = numevt; | |
739 | ||
2952b27e | 740 | return 0; |
b67f4487 C |
741 | } |
742 | ||
18a4f557 MLC |
743 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, |
744 | int channels) | |
b67f4487 C |
745 | { |
746 | int i, active_slots; | |
18a4f557 MLC |
747 | int total_slots; |
748 | int active_serializers; | |
b67f4487 | 749 | u32 mask = 0; |
cbc7956c | 750 | u32 busel = 0; |
b67f4487 | 751 | |
18a4f557 MLC |
752 | total_slots = mcasp->tdm_slots; |
753 | ||
754 | /* | |
755 | * If more than one serializer is needed, then use them with | |
756 | * their specified tdm_slots count. Otherwise, one serializer | |
757 | * can cope with the transaction using as many slots as channels | |
758 | * in the stream, requires channels symmetry | |
759 | */ | |
760 | active_serializers = (channels + total_slots - 1) / total_slots; | |
761 | if (active_serializers == 1) | |
762 | active_slots = channels; | |
763 | else | |
764 | active_slots = total_slots; | |
765 | ||
b67f4487 C |
766 | for (i = 0; i < active_slots; i++) |
767 | mask |= (1 << i); | |
768 | ||
f68205a7 | 769 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 770 | |
cbc7956c PU |
771 | if (!mcasp->dat_port) |
772 | busel = TXSEL; | |
773 | ||
2c56c4c2 PU |
774 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); |
775 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
776 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
18a4f557 | 777 | FSXMOD(total_slots), FSXMOD(0x1FF)); |
2c56c4c2 PU |
778 | |
779 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
780 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
781 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
18a4f557 | 782 | FSRMOD(total_slots), FSRMOD(0x1FF)); |
2c56c4c2 PU |
783 | |
784 | return 0; | |
b67f4487 C |
785 | } |
786 | ||
787 | /* S/PDIF */ | |
6479285d DM |
788 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, |
789 | unsigned int rate) | |
b67f4487 | 790 | { |
6479285d DM |
791 | u32 cs_value = 0; |
792 | u8 *cs_bytes = (u8*) &cs_value; | |
793 | ||
b67f4487 C |
794 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
795 | and LSB first */ | |
f68205a7 | 796 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
797 | |
798 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 799 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
800 | |
801 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 802 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
803 | |
804 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 805 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 806 | |
f68205a7 | 807 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
808 | |
809 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 810 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
811 | |
812 | /* Enable the DIT */ | |
f68205a7 | 813 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 | 814 | |
6479285d DM |
815 | /* Set S/PDIF channel status bits */ |
816 | cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; | |
817 | cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; | |
818 | ||
819 | switch (rate) { | |
820 | case 22050: | |
821 | cs_bytes[3] |= IEC958_AES3_CON_FS_22050; | |
822 | break; | |
823 | case 24000: | |
824 | cs_bytes[3] |= IEC958_AES3_CON_FS_24000; | |
825 | break; | |
826 | case 32000: | |
827 | cs_bytes[3] |= IEC958_AES3_CON_FS_32000; | |
828 | break; | |
829 | case 44100: | |
830 | cs_bytes[3] |= IEC958_AES3_CON_FS_44100; | |
831 | break; | |
832 | case 48000: | |
833 | cs_bytes[3] |= IEC958_AES3_CON_FS_48000; | |
834 | break; | |
835 | case 88200: | |
836 | cs_bytes[3] |= IEC958_AES3_CON_FS_88200; | |
837 | break; | |
838 | case 96000: | |
839 | cs_bytes[3] |= IEC958_AES3_CON_FS_96000; | |
840 | break; | |
841 | case 176400: | |
842 | cs_bytes[3] |= IEC958_AES3_CON_FS_176400; | |
843 | break; | |
844 | case 192000: | |
845 | cs_bytes[3] |= IEC958_AES3_CON_FS_192000; | |
846 | break; | |
847 | default: | |
848 | printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); | |
849 | return -EINVAL; | |
850 | } | |
851 | ||
852 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); | |
853 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); | |
854 | ||
2c56c4c2 | 855 | return 0; |
b67f4487 C |
856 | } |
857 | ||
858 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, | |
859 | struct snd_pcm_hw_params *params, | |
860 | struct snd_soc_dai *cpu_dai) | |
861 | { | |
70091a3e | 862 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 863 | struct davinci_pcm_dma_params *dma_params = |
70091a3e | 864 | &mcasp->dma_params[substream->stream]; |
b67f4487 | 865 | int word_length; |
a7e46bd9 | 866 | int channels = params_channels(params); |
dd093a0f | 867 | int period_size = params_period_size(params); |
2c56c4c2 | 868 | int ret; |
ab8b14b6 | 869 | |
8267525c DM |
870 | /* |
871 | * If mcasp is BCLK master, and a BCLK divider was not provided by | |
872 | * the machine driver, we need to calculate the ratio. | |
873 | */ | |
874 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
ab8b14b6 | 875 | unsigned int bclk_freq = snd_soc_params_to_bclk(params); |
0929878f | 876 | unsigned int div = mcasp->sysclk_freq / bclk_freq; |
ab8b14b6 | 877 | if (mcasp->sysclk_freq % bclk_freq != 0) { |
0929878f JS |
878 | if (((mcasp->sysclk_freq / div) - bclk_freq) > |
879 | (bclk_freq - (mcasp->sysclk_freq / (div+1)))) | |
880 | div++; | |
881 | dev_warn(mcasp->dev, | |
882 | "Inaccurate BCLK: %u Hz / %u != %u Hz\n", | |
883 | mcasp->sysclk_freq, div, bclk_freq); | |
ab8b14b6 | 884 | } |
8813543e | 885 | __davinci_mcasp_set_clkdiv(cpu_dai, 1, div, 0); |
ab8b14b6 JS |
886 | } |
887 | ||
dd093a0f PU |
888 | ret = mcasp_common_hw_param(mcasp, substream->stream, |
889 | period_size * channels, channels); | |
0f7d9a63 PU |
890 | if (ret) |
891 | return ret; | |
892 | ||
70091a3e | 893 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
6479285d | 894 | ret = mcasp_dit_hw_param(mcasp, params_rate(params)); |
b67f4487 | 895 | else |
18a4f557 MLC |
896 | ret = mcasp_i2s_hw_param(mcasp, substream->stream, |
897 | channels); | |
2c56c4c2 PU |
898 | |
899 | if (ret) | |
900 | return ret; | |
b67f4487 C |
901 | |
902 | switch (params_format(params)) { | |
0a9d1385 | 903 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 C |
904 | case SNDRV_PCM_FORMAT_S8: |
905 | dma_params->data_type = 1; | |
ba764b3d | 906 | word_length = 8; |
b67f4487 C |
907 | break; |
908 | ||
0a9d1385 | 909 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 C |
910 | case SNDRV_PCM_FORMAT_S16_LE: |
911 | dma_params->data_type = 2; | |
ba764b3d | 912 | word_length = 16; |
b67f4487 C |
913 | break; |
914 | ||
21eb24d8 DM |
915 | case SNDRV_PCM_FORMAT_U24_3LE: |
916 | case SNDRV_PCM_FORMAT_S24_3LE: | |
21eb24d8 | 917 | dma_params->data_type = 3; |
ba764b3d | 918 | word_length = 24; |
21eb24d8 DM |
919 | break; |
920 | ||
6b7fa011 DM |
921 | case SNDRV_PCM_FORMAT_U24_LE: |
922 | case SNDRV_PCM_FORMAT_S24_LE: | |
182bef86 PU |
923 | dma_params->data_type = 4; |
924 | word_length = 24; | |
925 | break; | |
926 | ||
0a9d1385 | 927 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 C |
928 | case SNDRV_PCM_FORMAT_S32_LE: |
929 | dma_params->data_type = 4; | |
ba764b3d | 930 | word_length = 32; |
b67f4487 C |
931 | break; |
932 | ||
933 | default: | |
934 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
935 | return -EINVAL; | |
936 | } | |
6a99fb5f | 937 | |
5f04c603 | 938 | if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level) |
4fa9c1a5 C |
939 | dma_params->acnt = 4; |
940 | else | |
6a99fb5f C |
941 | dma_params->acnt = dma_params->data_type; |
942 | ||
70091a3e | 943 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 | 944 | |
11277833 PU |
945 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) |
946 | mcasp->channels = channels; | |
947 | ||
b67f4487 C |
948 | return 0; |
949 | } | |
950 | ||
951 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
952 | int cmd, struct snd_soc_dai *cpu_dai) | |
953 | { | |
70091a3e | 954 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
955 | int ret = 0; |
956 | ||
957 | switch (cmd) { | |
b67f4487 | 958 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
959 | case SNDRV_PCM_TRIGGER_START: |
960 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 961 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 962 | break; |
b67f4487 | 963 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 964 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 965 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 966 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
967 | break; |
968 | ||
969 | default: | |
970 | ret = -EINVAL; | |
971 | } | |
972 | ||
973 | return ret; | |
974 | } | |
975 | ||
11277833 PU |
976 | static int davinci_mcasp_startup(struct snd_pcm_substream *substream, |
977 | struct snd_soc_dai *cpu_dai) | |
978 | { | |
979 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
980 | u32 max_channels = 0; | |
981 | int i, dir; | |
982 | ||
a7a3324a MLC |
983 | mcasp->substreams[substream->stream] = substream; |
984 | ||
11277833 PU |
985 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
986 | return 0; | |
987 | ||
988 | /* | |
989 | * Limit the maximum allowed channels for the first stream: | |
990 | * number of serializers for the direction * tdm slots per serializer | |
991 | */ | |
992 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
993 | dir = TX_MODE; | |
994 | else | |
995 | dir = RX_MODE; | |
996 | ||
997 | for (i = 0; i < mcasp->num_serializer; i++) { | |
998 | if (mcasp->serial_dir[i] == dir) | |
999 | max_channels++; | |
1000 | } | |
1001 | max_channels *= mcasp->tdm_slots; | |
1002 | /* | |
1003 | * If the already active stream has less channels than the calculated | |
1004 | * limnit based on the seirializers * tdm_slots, we need to use that as | |
1005 | * a constraint for the second stream. | |
1006 | * Otherwise (first stream or less allowed channels) we use the | |
1007 | * calculated constraint. | |
1008 | */ | |
1009 | if (mcasp->channels && mcasp->channels < max_channels) | |
1010 | max_channels = mcasp->channels; | |
1011 | ||
1012 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1013 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1014 | 2, max_channels); | |
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, | |
1019 | struct snd_soc_dai *cpu_dai) | |
1020 | { | |
1021 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
1022 | ||
a7a3324a MLC |
1023 | mcasp->substreams[substream->stream] = NULL; |
1024 | ||
11277833 PU |
1025 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
1026 | return; | |
1027 | ||
1028 | if (!cpu_dai->active) | |
1029 | mcasp->channels = 0; | |
1030 | } | |
1031 | ||
85e7652d | 1032 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
11277833 PU |
1033 | .startup = davinci_mcasp_startup, |
1034 | .shutdown = davinci_mcasp_shutdown, | |
b67f4487 C |
1035 | .trigger = davinci_mcasp_trigger, |
1036 | .hw_params = davinci_mcasp_hw_params, | |
1037 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 1038 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 1039 | .set_sysclk = davinci_mcasp_set_sysclk, |
b67f4487 C |
1040 | }; |
1041 | ||
d5902f69 PU |
1042 | static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) |
1043 | { | |
1044 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
1045 | ||
f3f9cfa8 | 1046 | if (mcasp->version >= MCASP_VERSION_3) { |
d5902f69 PU |
1047 | /* Using dmaengine PCM */ |
1048 | dai->playback_dma_data = | |
1049 | &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; | |
1050 | dai->capture_dma_data = | |
1051 | &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; | |
1052 | } else { | |
1053 | /* Using davinci-pcm */ | |
1054 | dai->playback_dma_data = mcasp->dma_params; | |
1055 | dai->capture_dma_data = mcasp->dma_params; | |
1056 | } | |
1057 | ||
1058 | return 0; | |
1059 | } | |
1060 | ||
135014ad PU |
1061 | #ifdef CONFIG_PM_SLEEP |
1062 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
1063 | { | |
1064 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 1065 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 1066 | u32 reg; |
1cc0c054 | 1067 | int i; |
135014ad | 1068 | |
1cc0c054 PU |
1069 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
1070 | context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); | |
135014ad | 1071 | |
f114ce60 PU |
1072 | if (mcasp->txnumevt) { |
1073 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
1074 | context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); | |
1075 | } | |
1076 | if (mcasp->rxnumevt) { | |
1077 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
1078 | context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); | |
1079 | } | |
135014ad | 1080 | |
f114ce60 PU |
1081 | for (i = 0; i < mcasp->num_serializer; i++) |
1082 | context->xrsr_regs[i] = mcasp_get_reg(mcasp, | |
1083 | DAVINCI_MCASP_XRSRCTL_REG(i)); | |
135014ad PU |
1084 | |
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
1089 | { | |
1090 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 1091 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 1092 | u32 reg; |
1cc0c054 | 1093 | int i; |
790bb94b | 1094 | |
1cc0c054 PU |
1095 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
1096 | mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); | |
135014ad | 1097 | |
f114ce60 PU |
1098 | if (mcasp->txnumevt) { |
1099 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
1100 | mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); | |
1101 | } | |
1102 | if (mcasp->rxnumevt) { | |
1103 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
1104 | mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); | |
1105 | } | |
790bb94b | 1106 | |
f114ce60 PU |
1107 | for (i = 0; i < mcasp->num_serializer; i++) |
1108 | mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), | |
1109 | context->xrsr_regs[i]); | |
135014ad PU |
1110 | |
1111 | return 0; | |
1112 | } | |
1113 | #else | |
1114 | #define davinci_mcasp_suspend NULL | |
1115 | #define davinci_mcasp_resume NULL | |
1116 | #endif | |
1117 | ||
ed29cd5e PU |
1118 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
1119 | ||
0a9d1385 BG |
1120 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
1121 | SNDRV_PCM_FMTBIT_U8 | \ | |
1122 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
1123 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
1124 | SNDRV_PCM_FMTBIT_S24_LE | \ |
1125 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
1126 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
1127 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
1128 | SNDRV_PCM_FMTBIT_S32_LE | \ |
1129 | SNDRV_PCM_FMTBIT_U32_LE) | |
1130 | ||
f0fba2ad | 1131 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 1132 | { |
f0fba2ad | 1133 | .name = "davinci-mcasp.0", |
d5902f69 | 1134 | .probe = davinci_mcasp_dai_probe, |
135014ad PU |
1135 | .suspend = davinci_mcasp_suspend, |
1136 | .resume = davinci_mcasp_resume, | |
b67f4487 C |
1137 | .playback = { |
1138 | .channels_min = 2, | |
2952b27e | 1139 | .channels_max = 32 * 16, |
b67f4487 | 1140 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 1141 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1142 | }, |
1143 | .capture = { | |
1144 | .channels_min = 2, | |
2952b27e | 1145 | .channels_max = 32 * 16, |
b67f4487 | 1146 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 1147 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1148 | }, |
1149 | .ops = &davinci_mcasp_dai_ops, | |
1150 | ||
d75249f5 | 1151 | .symmetric_samplebits = 1, |
b67f4487 C |
1152 | }, |
1153 | { | |
58e48d97 | 1154 | .name = "davinci-mcasp.1", |
d5902f69 | 1155 | .probe = davinci_mcasp_dai_probe, |
b67f4487 C |
1156 | .playback = { |
1157 | .channels_min = 1, | |
1158 | .channels_max = 384, | |
1159 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 1160 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1161 | }, |
1162 | .ops = &davinci_mcasp_dai_ops, | |
1163 | }, | |
1164 | ||
1165 | }; | |
b67f4487 | 1166 | |
eeef0eda KM |
1167 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
1168 | .name = "davinci-mcasp", | |
1169 | }; | |
1170 | ||
256ba181 | 1171 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
d1debafc | 1172 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
256ba181 JS |
1173 | .tx_dma_offset = 0x400, |
1174 | .rx_dma_offset = 0x400, | |
1175 | .asp_chan_q = EVENTQ_0, | |
1176 | .version = MCASP_VERSION_1, | |
1177 | }; | |
1178 | ||
d1debafc | 1179 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
256ba181 JS |
1180 | .tx_dma_offset = 0x2000, |
1181 | .rx_dma_offset = 0x2000, | |
1182 | .asp_chan_q = EVENTQ_0, | |
1183 | .version = MCASP_VERSION_2, | |
1184 | }; | |
1185 | ||
d1debafc | 1186 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
256ba181 JS |
1187 | .tx_dma_offset = 0, |
1188 | .rx_dma_offset = 0, | |
1189 | .asp_chan_q = EVENTQ_0, | |
1190 | .version = MCASP_VERSION_3, | |
1191 | }; | |
1192 | ||
d1debafc | 1193 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
453c4990 PU |
1194 | .tx_dma_offset = 0x200, |
1195 | .rx_dma_offset = 0x284, | |
1196 | .asp_chan_q = EVENTQ_0, | |
1197 | .version = MCASP_VERSION_4, | |
1198 | }; | |
1199 | ||
3e3b8c34 HG |
1200 | static const struct of_device_id mcasp_dt_ids[] = { |
1201 | { | |
1202 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 1203 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
1204 | }, |
1205 | { | |
1206 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 1207 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 1208 | }, |
e5ec69da | 1209 | { |
3af9e031 | 1210 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 1211 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 1212 | }, |
453c4990 PU |
1213 | { |
1214 | .compatible = "ti,dra7-mcasp-audio", | |
1215 | .data = &dra7_mcasp_pdata, | |
1216 | }, | |
3e3b8c34 HG |
1217 | { /* sentinel */ } |
1218 | }; | |
1219 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
1220 | ||
ae726e93 PU |
1221 | static int mcasp_reparent_fck(struct platform_device *pdev) |
1222 | { | |
1223 | struct device_node *node = pdev->dev.of_node; | |
1224 | struct clk *gfclk, *parent_clk; | |
1225 | const char *parent_name; | |
1226 | int ret; | |
1227 | ||
1228 | if (!node) | |
1229 | return 0; | |
1230 | ||
1231 | parent_name = of_get_property(node, "fck_parent", NULL); | |
1232 | if (!parent_name) | |
1233 | return 0; | |
1234 | ||
1235 | gfclk = clk_get(&pdev->dev, "fck"); | |
1236 | if (IS_ERR(gfclk)) { | |
1237 | dev_err(&pdev->dev, "failed to get fck\n"); | |
1238 | return PTR_ERR(gfclk); | |
1239 | } | |
1240 | ||
1241 | parent_clk = clk_get(NULL, parent_name); | |
1242 | if (IS_ERR(parent_clk)) { | |
1243 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
1244 | ret = PTR_ERR(parent_clk); | |
1245 | goto err1; | |
1246 | } | |
1247 | ||
1248 | ret = clk_set_parent(gfclk, parent_clk); | |
1249 | if (ret) { | |
1250 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
1251 | goto err2; | |
1252 | } | |
1253 | ||
1254 | err2: | |
1255 | clk_put(parent_clk); | |
1256 | err1: | |
1257 | clk_put(gfclk); | |
1258 | return ret; | |
1259 | } | |
1260 | ||
d1debafc | 1261 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
3e3b8c34 HG |
1262 | struct platform_device *pdev) |
1263 | { | |
1264 | struct device_node *np = pdev->dev.of_node; | |
d1debafc | 1265 | struct davinci_mcasp_pdata *pdata = NULL; |
3e3b8c34 | 1266 | const struct of_device_id *match = |
ea421eb1 | 1267 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 1268 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
1269 | |
1270 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
1271 | u32 val; |
1272 | int i, ret = 0; | |
1273 | ||
1274 | if (pdev->dev.platform_data) { | |
1275 | pdata = pdev->dev.platform_data; | |
1276 | return pdata; | |
1277 | } else if (match) { | |
d1debafc | 1278 | pdata = (struct davinci_mcasp_pdata*) match->data; |
3e3b8c34 HG |
1279 | } else { |
1280 | /* control shouldn't reach here. something is wrong */ | |
1281 | ret = -EINVAL; | |
1282 | goto nodata; | |
1283 | } | |
1284 | ||
3e3b8c34 HG |
1285 | ret = of_property_read_u32(np, "op-mode", &val); |
1286 | if (ret >= 0) | |
1287 | pdata->op_mode = val; | |
1288 | ||
1289 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
1290 | if (ret >= 0) { |
1291 | if (val < 2 || val > 32) { | |
1292 | dev_err(&pdev->dev, | |
1293 | "tdm-slots must be in rage [2-32]\n"); | |
1294 | ret = -EINVAL; | |
1295 | goto nodata; | |
1296 | } | |
1297 | ||
3e3b8c34 | 1298 | pdata->tdm_slots = val; |
2952b27e | 1299 | } |
3e3b8c34 | 1300 | |
3e3b8c34 HG |
1301 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
1302 | val /= sizeof(u32); | |
3e3b8c34 | 1303 | if (of_serial_dir32) { |
1427e660 PU |
1304 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
1305 | (sizeof(*of_serial_dir) * val), | |
1306 | GFP_KERNEL); | |
3e3b8c34 HG |
1307 | if (!of_serial_dir) { |
1308 | ret = -ENOMEM; | |
1309 | goto nodata; | |
1310 | } | |
1311 | ||
1427e660 | 1312 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
1313 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
1314 | ||
1427e660 | 1315 | pdata->num_serializer = val; |
3e3b8c34 HG |
1316 | pdata->serial_dir = of_serial_dir; |
1317 | } | |
1318 | ||
4023fe6f JS |
1319 | ret = of_property_match_string(np, "dma-names", "tx"); |
1320 | if (ret < 0) | |
1321 | goto nodata; | |
1322 | ||
1323 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1324 | &dma_spec); | |
1325 | if (ret < 0) | |
1326 | goto nodata; | |
1327 | ||
1328 | pdata->tx_dma_channel = dma_spec.args[0]; | |
1329 | ||
1330 | ret = of_property_match_string(np, "dma-names", "rx"); | |
1331 | if (ret < 0) | |
1332 | goto nodata; | |
1333 | ||
1334 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1335 | &dma_spec); | |
1336 | if (ret < 0) | |
1337 | goto nodata; | |
1338 | ||
1339 | pdata->rx_dma_channel = dma_spec.args[0]; | |
1340 | ||
3e3b8c34 HG |
1341 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
1342 | if (ret >= 0) | |
1343 | pdata->txnumevt = val; | |
1344 | ||
1345 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1346 | if (ret >= 0) | |
1347 | pdata->rxnumevt = val; | |
1348 | ||
1349 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1350 | if (ret >= 0) | |
1351 | pdata->sram_size_playback = val; | |
1352 | ||
1353 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1354 | if (ret >= 0) | |
1355 | pdata->sram_size_capture = val; | |
1356 | ||
1357 | return pdata; | |
1358 | ||
1359 | nodata: | |
1360 | if (ret < 0) { | |
1361 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1362 | ret); | |
1363 | pdata = NULL; | |
1364 | } | |
1365 | return pdata; | |
1366 | } | |
1367 | ||
b67f4487 C |
1368 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1369 | { | |
64ebdec3 | 1370 | struct davinci_pcm_dma_params *dma_params; |
8de131f2 | 1371 | struct snd_dmaengine_dai_dma_data *dma_data; |
256ba181 | 1372 | struct resource *mem, *ioarea, *res, *dat; |
d1debafc | 1373 | struct davinci_mcasp_pdata *pdata; |
70091a3e | 1374 | struct davinci_mcasp *mcasp; |
a7a3324a MLC |
1375 | char *irq_name; |
1376 | int irq; | |
96d31e2b | 1377 | int ret; |
b67f4487 | 1378 | |
3e3b8c34 HG |
1379 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1380 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1381 | return -EINVAL; | |
1382 | } | |
1383 | ||
70091a3e | 1384 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1385 | GFP_KERNEL); |
70091a3e | 1386 | if (!mcasp) |
b67f4487 C |
1387 | return -ENOMEM; |
1388 | ||
3e3b8c34 HG |
1389 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1390 | if (!pdata) { | |
1391 | dev_err(&pdev->dev, "no platform data\n"); | |
1392 | return -EINVAL; | |
1393 | } | |
1394 | ||
256ba181 | 1395 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1396 | if (!mem) { |
70091a3e | 1397 | dev_warn(mcasp->dev, |
256ba181 JS |
1398 | "\"mpu\" mem resource not found, using index 0\n"); |
1399 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1400 | if (!mem) { | |
1401 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1402 | return -ENODEV; | |
1403 | } | |
b67f4487 C |
1404 | } |
1405 | ||
96d31e2b | 1406 | ioarea = devm_request_mem_region(&pdev->dev, mem->start, |
d852f446 | 1407 | resource_size(mem), pdev->name); |
b67f4487 C |
1408 | if (!ioarea) { |
1409 | dev_err(&pdev->dev, "Audio region already claimed\n"); | |
96d31e2b | 1410 | return -EBUSY; |
b67f4487 C |
1411 | } |
1412 | ||
10884347 | 1413 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1414 | |
10884347 HG |
1415 | ret = pm_runtime_get_sync(&pdev->dev); |
1416 | if (IS_ERR_VALUE(ret)) { | |
1417 | dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n"); | |
7771ef32 | 1418 | pm_runtime_disable(&pdev->dev); |
10884347 HG |
1419 | return ret; |
1420 | } | |
b67f4487 | 1421 | |
70091a3e PU |
1422 | mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); |
1423 | if (!mcasp->base) { | |
4f82f028 VB |
1424 | dev_err(&pdev->dev, "ioremap failed\n"); |
1425 | ret = -ENOMEM; | |
b6bb3709 | 1426 | goto err; |
4f82f028 VB |
1427 | } |
1428 | ||
70091a3e | 1429 | mcasp->op_mode = pdata->op_mode; |
1a5923da PU |
1430 | /* sanity check for tdm slots parameter */ |
1431 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { | |
1432 | if (pdata->tdm_slots < 2) { | |
1433 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1434 | pdata->tdm_slots); | |
1435 | mcasp->tdm_slots = 2; | |
1436 | } else if (pdata->tdm_slots > 32) { | |
1437 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1438 | pdata->tdm_slots); | |
1439 | mcasp->tdm_slots = 32; | |
1440 | } else { | |
1441 | mcasp->tdm_slots = pdata->tdm_slots; | |
1442 | } | |
1443 | } | |
1444 | ||
70091a3e | 1445 | mcasp->num_serializer = pdata->num_serializer; |
f114ce60 PU |
1446 | #ifdef CONFIG_PM_SLEEP |
1447 | mcasp->context.xrsr_regs = devm_kzalloc(&pdev->dev, | |
1448 | sizeof(u32) * mcasp->num_serializer, | |
1449 | GFP_KERNEL); | |
1450 | #endif | |
70091a3e PU |
1451 | mcasp->serial_dir = pdata->serial_dir; |
1452 | mcasp->version = pdata->version; | |
1453 | mcasp->txnumevt = pdata->txnumevt; | |
1454 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1455 | |
70091a3e | 1456 | mcasp->dev = &pdev->dev; |
b67f4487 | 1457 | |
5a1b8a80 PU |
1458 | irq = platform_get_irq_byname(pdev, "common"); |
1459 | if (irq >= 0) { | |
1460 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common\n", | |
1461 | dev_name(&pdev->dev)); | |
1462 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1463 | davinci_mcasp_common_irq_handler, | |
1464 | IRQF_ONESHOT, irq_name, mcasp); | |
1465 | if (ret) { | |
1466 | dev_err(&pdev->dev, "common IRQ request failed\n"); | |
1467 | goto err; | |
1468 | } | |
1469 | ||
1470 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; | |
1471 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; | |
1472 | } | |
1473 | ||
a7a3324a MLC |
1474 | irq = platform_get_irq_byname(pdev, "rx"); |
1475 | if (irq >= 0) { | |
1476 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx\n", | |
1477 | dev_name(&pdev->dev)); | |
1478 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1479 | davinci_mcasp_rx_irq_handler, | |
1480 | IRQF_ONESHOT, irq_name, mcasp); | |
1481 | if (ret) { | |
1482 | dev_err(&pdev->dev, "RX IRQ request failed\n"); | |
1483 | goto err; | |
1484 | } | |
1485 | ||
1486 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; | |
1487 | } | |
1488 | ||
1489 | irq = platform_get_irq_byname(pdev, "tx"); | |
1490 | if (irq >= 0) { | |
1491 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx\n", | |
1492 | dev_name(&pdev->dev)); | |
1493 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1494 | davinci_mcasp_tx_irq_handler, | |
1495 | IRQF_ONESHOT, irq_name, mcasp); | |
1496 | if (ret) { | |
1497 | dev_err(&pdev->dev, "TX IRQ request failed\n"); | |
1498 | goto err; | |
1499 | } | |
1500 | ||
1501 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; | |
1502 | } | |
1503 | ||
256ba181 | 1504 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
1505 | if (dat) |
1506 | mcasp->dat_port = true; | |
256ba181 | 1507 | |
64ebdec3 | 1508 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; |
8de131f2 | 1509 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
64ebdec3 PU |
1510 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1511 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1512 | dma_params->sram_pool = pdata->sram_pool; | |
1513 | dma_params->sram_size = pdata->sram_size_playback; | |
cbc7956c | 1514 | if (dat) |
64ebdec3 | 1515 | dma_params->dma_addr = dat->start; |
cbc7956c | 1516 | else |
64ebdec3 | 1517 | dma_params->dma_addr = mem->start + pdata->tx_dma_offset; |
b67f4487 | 1518 | |
453c4990 | 1519 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1520 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1521 | |
b67f4487 | 1522 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f | 1523 | if (res) |
64ebdec3 | 1524 | dma_params->channel = res->start; |
4023fe6f | 1525 | else |
64ebdec3 | 1526 | dma_params->channel = pdata->tx_dma_channel; |
92e2a6f6 | 1527 | |
8de131f2 PU |
1528 | /* dmaengine filter data for DT and non-DT boot */ |
1529 | if (pdev->dev.of_node) | |
1530 | dma_data->filter_data = "tx"; | |
1531 | else | |
1532 | dma_data->filter_data = &dma_params->channel; | |
1533 | ||
64ebdec3 | 1534 | dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE]; |
8de131f2 | 1535 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
64ebdec3 PU |
1536 | dma_params->asp_chan_q = pdata->asp_chan_q; |
1537 | dma_params->ram_chan_q = pdata->ram_chan_q; | |
1538 | dma_params->sram_pool = pdata->sram_pool; | |
1539 | dma_params->sram_size = pdata->sram_size_capture; | |
cbc7956c | 1540 | if (dat) |
64ebdec3 | 1541 | dma_params->dma_addr = dat->start; |
cbc7956c | 1542 | else |
64ebdec3 | 1543 | dma_params->dma_addr = mem->start + pdata->rx_dma_offset; |
cbc7956c | 1544 | |
453c4990 | 1545 | /* Unconditional dmaengine stuff */ |
8de131f2 | 1546 | dma_data->addr = dma_params->dma_addr; |
453c4990 | 1547 | |
cbc7956c PU |
1548 | if (mcasp->version < MCASP_VERSION_3) { |
1549 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
64ebdec3 | 1550 | /* dma_params->dma_addr is pointing to the data port address */ |
cbc7956c PU |
1551 | mcasp->dat_port = true; |
1552 | } else { | |
1553 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
1554 | } | |
b67f4487 C |
1555 | |
1556 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
4023fe6f | 1557 | if (res) |
64ebdec3 | 1558 | dma_params->channel = res->start; |
4023fe6f | 1559 | else |
64ebdec3 | 1560 | dma_params->channel = pdata->rx_dma_channel; |
b67f4487 | 1561 | |
8de131f2 PU |
1562 | /* dmaengine filter data for DT and non-DT boot */ |
1563 | if (pdev->dev.of_node) | |
1564 | dma_data->filter_data = "rx"; | |
1565 | else | |
1566 | dma_data->filter_data = &dma_params->channel; | |
453c4990 | 1567 | |
70091a3e | 1568 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
1569 | |
1570 | mcasp_reparent_fck(pdev); | |
1571 | ||
b6bb3709 PU |
1572 | ret = devm_snd_soc_register_component(&pdev->dev, |
1573 | &davinci_mcasp_component, | |
1574 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
1575 | |
1576 | if (ret != 0) | |
b6bb3709 | 1577 | goto err; |
f08095a4 | 1578 | |
d5c6c59a | 1579 | switch (mcasp->version) { |
7f28f357 JS |
1580 | #if IS_BUILTIN(CONFIG_SND_DAVINCI_SOC) || \ |
1581 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1582 | IS_MODULE(CONFIG_SND_DAVINCI_SOC)) | |
d5c6c59a PU |
1583 | case MCASP_VERSION_1: |
1584 | case MCASP_VERSION_2: | |
453c4990 | 1585 | ret = davinci_soc_platform_register(&pdev->dev); |
d5c6c59a | 1586 | break; |
7f28f357 | 1587 | #endif |
f3f9cfa8 PU |
1588 | #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \ |
1589 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1590 | IS_MODULE(CONFIG_SND_EDMA_SOC)) | |
1591 | case MCASP_VERSION_3: | |
1592 | ret = edma_pcm_platform_register(&pdev->dev); | |
1593 | break; | |
1594 | #endif | |
7f28f357 JS |
1595 | #if IS_BUILTIN(CONFIG_SND_OMAP_SOC) || \ |
1596 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
1597 | IS_MODULE(CONFIG_SND_OMAP_SOC)) | |
d5c6c59a PU |
1598 | case MCASP_VERSION_4: |
1599 | ret = omap_pcm_platform_register(&pdev->dev); | |
1600 | break; | |
7f28f357 | 1601 | #endif |
d5c6c59a PU |
1602 | default: |
1603 | dev_err(&pdev->dev, "Invalid McASP version: %d\n", | |
1604 | mcasp->version); | |
1605 | ret = -EINVAL; | |
1606 | break; | |
1607 | } | |
1608 | ||
1609 | if (ret) { | |
1610 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
b6bb3709 | 1611 | goto err; |
f08095a4 HG |
1612 | } |
1613 | ||
b67f4487 C |
1614 | return 0; |
1615 | ||
b6bb3709 | 1616 | err: |
10884347 HG |
1617 | pm_runtime_put_sync(&pdev->dev); |
1618 | pm_runtime_disable(&pdev->dev); | |
b67f4487 C |
1619 | return ret; |
1620 | } | |
1621 | ||
1622 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
1623 | { | |
10884347 HG |
1624 | pm_runtime_put_sync(&pdev->dev); |
1625 | pm_runtime_disable(&pdev->dev); | |
b67f4487 | 1626 | |
b67f4487 C |
1627 | return 0; |
1628 | } | |
1629 | ||
1630 | static struct platform_driver davinci_mcasp_driver = { | |
1631 | .probe = davinci_mcasp_probe, | |
1632 | .remove = davinci_mcasp_remove, | |
1633 | .driver = { | |
1634 | .name = "davinci-mcasp", | |
ea421eb1 | 1635 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
1636 | }, |
1637 | }; | |
1638 | ||
f9b8a514 | 1639 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
1640 | |
1641 | MODULE_AUTHOR("Steve Chen"); | |
1642 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
1643 | MODULE_LICENSE("GPL"); |