projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: davinci-mcasp: Remove excess empty lines from davinci_mcasp_set_dai_fmt()
[linux-2.6-block.git] / sound / soc / davinci / davinci-mcasp.c
CommitLineData
b67f4487
C		 1/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
5a0e3ad6 21#include <linux/slab.h>
b67f4487
C		 22#include <linux/delay.h>
23#include <linux/io.h>
ae726e93 24#include <linux/clk.h>
10884347 25#include <linux/pm_runtime.h>
3e3b8c34
HG		 26#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/of_device.h>
b67f4487
C		 29
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/initval.h>
34#include <sound/soc.h>
453c4990 35#include <sound/dmaengine_pcm.h>
b67f4487
C		 36
37#include "davinci-pcm.h"
38#include "davinci-mcasp.h"
39
0bf0e8ae
PU		 40#define MCASP_MAX_AFIFO_DEPTH 64
41
790bb94b
PU		 42struct davinci_mcasp_context {
43 u32 txfmtctl;
44 u32 rxfmtctl;
45 u32 txfmt;
46 u32 rxfmt;
47 u32 aclkxctl;
48 u32 aclkrctl;
49 u32 pdir;
50};
51
70091a3e 52struct davinci_mcasp {
21400a72 53 struct davinci_pcm_dma_params dma_params[2];
453c4990 54 struct snd_dmaengine_dai_dma_data dma_data[2];
21400a72 55 void __iomem *base;
487dce88 56 u32 fifo_base;
21400a72
PU		 57 struct device *dev;
58
59 /* McASP specific data */
60 int tdm_slots;
61 u8 op_mode;
62 u8 num_serializer;
63 u8 *serial_dir;
64 u8 version;
65 u16 bclk_lrclk_ratio;
4dcb5a0b 66 int streams;
21400a72 67
ab8b14b6
JS		 68 int sysclk_freq;
69 bool bclk_master;
70
21400a72
PU		 71 /* McASP FIFO related */
72 u8 txnumevt;
73 u8 rxnumevt;
74
cbc7956c
PU		 75 bool dat_port;
76
21400a72 77#ifdef CONFIG_PM_SLEEP
790bb94b 78 struct davinci_mcasp_context context;
21400a72
PU		 79#endif
80};
81
f68205a7
PU		 82static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
83 u32 val)
b67f4487 84{
f68205a7 85 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 86 __raw_writel(__raw_readl(reg) | val, reg);
87}
88
f68205a7
PU		 89static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
90 u32 val)
b67f4487 91{
f68205a7 92 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 93 __raw_writel((__raw_readl(reg) & ~(val)), reg);
94}
95
f68205a7
PU		 96static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
97 u32 val, u32 mask)
b67f4487 98{
f68205a7 99 void __iomem *reg = mcasp->base + offset;
b67f4487
C		 100 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
101}
102
f68205a7
PU		 103static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
104 u32 val)
b67f4487 105{
f68205a7 106 __raw_writel(val, mcasp->base + offset);
b67f4487
C		 107}
108
f68205a7 109static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
b67f4487 110{
f68205a7 111 return (u32)__raw_readl(mcasp->base + offset);
b67f4487
C		 112}
113
f68205a7 114static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
b67f4487
C		 115{
116 int i = 0;
117
f68205a7 118 mcasp_set_bits(mcasp, ctl_reg, val);
b67f4487
C		 119
120 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
121 /* loop count is to avoid the lock-up */
122 for (i = 0; i < 1000; i++) {
f68205a7 123 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
b67f4487
C		 124 break;
125 }
126
f68205a7 127 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
b67f4487
C		 128 printk(KERN_ERR "GBLCTL write error\n");
129}
130
4dcb5a0b
PU		 131static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
132{
f68205a7
PU		 133 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
134 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
4dcb5a0b
PU		 135
136 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
137}
138
70091a3e 139static void mcasp_start_rx(struct davinci_mcasp *mcasp)
b67f4487 140{
f68205a7
PU		 141 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
142 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
4dcb5a0b
PU		 143
144 /*
145 * When ASYNC == 0 the transmit and receive sections operate
146 * synchronously from the transmit clock and frame sync. We need to make
147 * sure that the TX signlas are enabled when starting reception.
148 */
149 if (mcasp_is_synchronous(mcasp)) {
f68205a7
PU		 150 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
151 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
4dcb5a0b
PU		 152 }
153
f68205a7
PU		 154 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
155 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
b67f4487 156
f68205a7
PU		 157 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
158 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
159 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
b67f4487 160
f68205a7
PU		 161 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
162 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
4dcb5a0b
PU		 163
164 if (mcasp_is_synchronous(mcasp))
f68205a7 165 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
b67f4487
C		 166}
167
70091a3e 168static void mcasp_start_tx(struct davinci_mcasp *mcasp)
b67f4487 169{
6a99fb5f
C		 170 u8 offset = 0, i;
171 u32 cnt;
172
f68205a7
PU		 173 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
174 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
175 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
176 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
b67f4487 177
f68205a7
PU		 178 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
179 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
180 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
70091a3e
PU		 181 for (i = 0; i < mcasp->num_serializer; i++) {
182 if (mcasp->serial_dir[i] == TX_MODE) {
6a99fb5f
C		 183 offset = i;
184 break;
185 }
186 }
187
188 /* wait for TX ready */
189 cnt = 0;
f68205a7 190 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
6a99fb5f
C		 191 TXSTATE) && (cnt < 100000))
192 cnt++;
193
f68205a7 194 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
b67f4487
C		 195}
196
70091a3e 197static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
b67f4487 198{
487dce88
PU		 199 u32 reg;
200
4dcb5a0b
PU		 201 mcasp->streams++;
202
539d3d8c 203 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
70091a3e 204 if (mcasp->txnumevt) { /* enable FIFO */
487dce88 205 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
f68205a7
PU		 206 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
207 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
0d624275 208 }
70091a3e 209 mcasp_start_tx(mcasp);
539d3d8c 210 } else {
70091a3e 211 if (mcasp->rxnumevt) { /* enable FIFO */
487dce88 212 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
f68205a7
PU		 213 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
214 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
0d624275 215 }
70091a3e 216 mcasp_start_rx(mcasp);
539d3d8c 217 }
b67f4487
C		 218}
219
70091a3e 220static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
b67f4487 221{
4dcb5a0b
PU		 222 /*
223 * In synchronous mode stop the TX clocks if no other stream is
224 * running
225 */
226 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
f68205a7 227 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
4dcb5a0b 228
f68205a7
PU		 229 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
230 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
b67f4487
C		 231}
232
70091a3e 233static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
b67f4487 234{
4dcb5a0b
PU		 235 u32 val = 0;
236
237 /*
238 * In synchronous mode keep TX clocks running if the capture stream is
239 * still running.
240 */
241 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
242 val = TXHCLKRST | TXCLKRST | TXFSRST;
243
f68205a7
PU		 244 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
245 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
b67f4487
C		 246}
247
70091a3e 248static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
b67f4487 249{
487dce88
PU		 250 u32 reg;
251
4dcb5a0b
PU		 252 mcasp->streams--;
253
539d3d8c 254 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
70091a3e 255 if (mcasp->txnumevt) { /* disable FIFO */
487dce88 256 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
f68205a7 257 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
e5ec69da 258 }
70091a3e 259 mcasp_stop_tx(mcasp);
539d3d8c 260 } else {
70091a3e 261 if (mcasp->rxnumevt) { /* disable FIFO */
487dce88 262 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
f68205a7 263 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
e5ec69da 264 }
70091a3e 265 mcasp_stop_rx(mcasp);
539d3d8c 266 }
b67f4487
C		 267}
268
269static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
270 unsigned int fmt)
271{
70091a3e 272 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1d17a04e 273 int ret = 0;
6dfa9a4e 274 u32 data_delay;
83f12503 275 bool fs_pol_rising;
ffd950f7 276 bool inv_fs = false;
b67f4487 277
1d17a04e 278 pm_runtime_get_sync(mcasp->dev);
5296cf2d 279 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
188edc59
PU		 280 case SND_SOC_DAIFMT_DSP_A:
281 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
282 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
188edc59
PU		 283 /* 1st data bit occur one ACLK cycle after the frame sync */
284 data_delay = 1;
285 break;
5296cf2d
DM		 286 case SND_SOC_DAIFMT_DSP_B:
287 case SND_SOC_DAIFMT_AC97:
f68205a7
PU		 288 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
289 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
6dfa9a4e
PU		 290 /* No delay after FS */
291 data_delay = 0;
5296cf2d 292 break;
ffd950f7 293 case SND_SOC_DAIFMT_I2S:
5296cf2d 294 /* configure a full-word SYNC pulse (LRCLK) */
f68205a7
PU		 295 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
296 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
6dfa9a4e
PU		 297 /* 1st data bit occur one ACLK cycle after the frame sync */
298 data_delay = 1;
ffd950f7
PU		 299 /* FS need to be inverted */
300 inv_fs = true;
5296cf2d 301 break;
423761e0
PU		 302 case SND_SOC_DAIFMT_LEFT_J:
303 /* configure a full-word SYNC pulse (LRCLK) */
304 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
305 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
306 /* No delay after FS */
307 data_delay = 0;
308 break;
ffd950f7
PU		 309 default:
310 ret = -EINVAL;
311 goto out;
5296cf2d
DM		 312 }
313
6dfa9a4e
PU		 314 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
315 FSXDLY(3));
316 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
317 FSRDLY(3));
318
b67f4487
C		 319 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
320 case SND_SOC_DAIFMT_CBS_CFS:
321 /* codec is clock and frame slave */
f68205a7
PU		 322 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
323 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 324
f68205a7
PU		 325 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
326 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 327
f68205a7
PU		 328 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
329 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
ab8b14b6 330 mcasp->bclk_master = 1;
b67f4487 331 break;
517ee6cf
C		 332 case SND_SOC_DAIFMT_CBM_CFS:
333 /* codec is clock master and frame slave */
f68205a7
PU		 334 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
335 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
517ee6cf 336
f68205a7
PU		 337 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
338 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
517ee6cf 339
f68205a7
PU		 340 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
341 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
ab8b14b6 342 mcasp->bclk_master = 0;
517ee6cf 343 break;
b67f4487
C		 344 case SND_SOC_DAIFMT_CBM_CFM:
345 /* codec is clock and frame master */
f68205a7
PU		 346 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
347 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
b67f4487 348
f68205a7
PU		 349 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
350 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
b67f4487 351
f68205a7
PU		 352 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
353 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
ab8b14b6 354 mcasp->bclk_master = 0;
b67f4487 355 break;
b67f4487 356 default:
1d17a04e
PU		 357 ret = -EINVAL;
358 goto out;
b67f4487
C		 359 }
360
361 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
362 case SND_SOC_DAIFMT_IB_NF:
f68205a7 363 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 364 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 365 fs_pol_rising = true;
b67f4487 366 break;
b67f4487 367 case SND_SOC_DAIFMT_NB_IF:
f68205a7 368 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 369 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 370 fs_pol_rising = false;
b67f4487 371 break;
b67f4487 372 case SND_SOC_DAIFMT_IB_IF:
f68205a7 373 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
74ddd8c4 374 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 375 fs_pol_rising = false;
b67f4487 376 break;
b67f4487 377 case SND_SOC_DAIFMT_NB_NF:
f68205a7 378 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
f68205a7 379 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
83f12503 380 fs_pol_rising = true;
b67f4487 381 break;
b67f4487 382 default:
1d17a04e 383 ret = -EINVAL;
83f12503
PU		 384 goto out;
385 }
386
ffd950f7
PU		 387 if (inv_fs)
388 fs_pol_rising = !fs_pol_rising;
389
83f12503
PU		 390 if (fs_pol_rising) {
391 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
392 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
393 } else {
394 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
395 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
b67f4487 396 }
1d17a04e
PU		 397out:
398 pm_runtime_put_sync(mcasp->dev);
399 return ret;
b67f4487
C		 400}
401
4ed8c9b7
DM		 402static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
403{
70091a3e 404 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
4ed8c9b7
DM		 405
406 switch (div_id) {
407 case 0: /* MCLK divider */
f68205a7 408 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
4ed8c9b7 409 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
f68205a7 410 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
4ed8c9b7
DM		 411 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
412 break;
413
414 case 1: /* BCLK divider */
f68205a7 415 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
4ed8c9b7 416 ACLKXDIV(div - 1), ACLKXDIV_MASK);
f68205a7 417 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
4ed8c9b7
DM		 418 ACLKRDIV(div - 1), ACLKRDIV_MASK);
419 break;
420
1b3bc060 421 case 2: /* BCLK/LRCLK ratio */
70091a3e 422 mcasp->bclk_lrclk_ratio = div;
1b3bc060
DM		 423 break;
424
4ed8c9b7
DM		 425 default:
426 return -EINVAL;
427 }
428
429 return 0;
430}
431
5b66aa2d
DM		 432static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
433 unsigned int freq, int dir)
434{
70091a3e 435 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
5b66aa2d
DM		 436
437 if (dir == SND_SOC_CLOCK_OUT) {
f68205a7
PU		 438 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
439 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
440 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
5b66aa2d 441 } else {
f68205a7
PU		 442 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
443 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
444 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
5b66aa2d
DM		 445 }
446
ab8b14b6
JS		 447 mcasp->sysclk_freq = freq;
448
5b66aa2d
DM		 449 return 0;
450}
451
70091a3e 452static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
ba764b3d 453 int word_length)
b67f4487 454{
ba764b3d 455 u32 fmt;
79671892
DM		 456 u32 tx_rotate = (word_length / 4) & 0x7;
457 u32 rx_rotate = (32 - word_length) / 4;
ba764b3d 458 u32 mask = (1ULL << word_length) - 1;
b67f4487 459
1b3bc060
DM		 460 /*
461 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
462 * callback, take it into account here. That allows us to for example
463 * send 32 bits per channel to the codec, while only 16 of them carry
464 * audio payload.
d486fea6
MB		 465 * The clock ratio is given for a full period of data (for I2S format
466 * both left and right channels), so it has to be divided by number of
467 * tdm-slots (for I2S - divided by 2).
1b3bc060 468 */
70091a3e
PU		 469 if (mcasp->bclk_lrclk_ratio)
470 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
1b3bc060 471
ba764b3d
DM		 472 /* mapping of the XSSZ bit-field as described in the datasheet */
473 fmt = (word_length >> 1) - 1;
b67f4487 474
70091a3e 475 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
f68205a7
PU		 476 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
477 RXSSZ(0x0F));
478 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
479 TXSSZ(0x0F));
480 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
481 TXROT(7));
482 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
483 RXROT(7));
484 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
f5023af6
YY		 485 }
486
f68205a7 487 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
0c31cf3e 488
b67f4487
C		 489 return 0;
490}
491
662ffae9 492static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
dd093a0f 493 int period_words, int channels)
b67f4487 494{
5f04c603
PU		 495 struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream];
496 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
b67f4487 497 int i;
6a99fb5f
C		 498 u8 tx_ser = 0;
499 u8 rx_ser = 0;
70091a3e 500 u8 slots = mcasp->tdm_slots;
2952b27e 501 u8 max_active_serializers = (channels + slots - 1) / slots;
dd093a0f 502 int active_serializers, numevt, n;
487dce88 503 u32 reg;
b67f4487 504 /* Default configuration */
453c4990 505 if (mcasp->version != MCASP_VERSION_4)
f68205a7 506 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
b67f4487
C		 507
508 /* All PINS as McASP */
f68205a7 509 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
b67f4487
C		 510
511 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
f68205a7
PU		 512 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
513 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487 514 } else {
f68205a7
PU		 515 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
516 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
b67f4487
C		 517 }
518
70091a3e 519 for (i = 0; i < mcasp->num_serializer; i++) {
f68205a7
PU		 520 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
521 mcasp->serial_dir[i]);
70091a3e 522 if (mcasp->serial_dir[i] == TX_MODE &&
2952b27e 523 tx_ser < max_active_serializers) {
f68205a7 524 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
6a99fb5f 525 tx_ser++;
70091a3e 526 } else if (mcasp->serial_dir[i] == RX_MODE &&
2952b27e 527 rx_ser < max_active_serializers) {
f68205a7 528 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
6a99fb5f 529 rx_ser++;
2952b27e 530 } else {
f68205a7
PU		 531 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
532 SRMOD_INACTIVE, SRMOD_MASK);
6a99fb5f
C		 533 }
534 }
535
0bf0e8ae
PU		 536 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
537 active_serializers = tx_ser;
538 numevt = mcasp->txnumevt;
539 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
540 } else {
541 active_serializers = rx_ser;
542 numevt = mcasp->rxnumevt;
543 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
544 }
ecf327c7 545
0bf0e8ae 546 if (active_serializers < max_active_serializers) {
70091a3e 547 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
0bf0e8ae
PU		 548 "enabled in mcasp (%d)\n", channels,
549 active_serializers * slots);
ecf327c7
DM		 550 return -EINVAL;
551 }
552
0bf0e8ae 553 /* AFIFO is not in use */
5f04c603
PU		 554 if (!numevt) {
555 /* Configure the burst size for platform drivers */
33445643
PU		 556 if (active_serializers > 1) {
557 /*
558 * If more than one serializers are in use we have one
559 * DMA request to provide data for all serializers.
560 * For example if three serializers are enabled the DMA
561 * need to transfer three words per DMA request.
562 */
563 dma_params->fifo_level = active_serializers;
564 dma_data->maxburst = active_serializers;
565 } else {
566 dma_params->fifo_level = 0;
567 dma_data->maxburst = 0;
568 }
0bf0e8ae 569 return 0;
5f04c603 570 }
6a99fb5f 571
dd093a0f
PU		 572 if (period_words % active_serializers) {
573 dev_err(mcasp->dev, "Invalid combination of period words and "
574 "active serializers: %d, %d\n", period_words,
575 active_serializers);
576 return -EINVAL;
577 }
578
579 /*
580 * Calculate the optimal AFIFO depth for platform side:
581 * The number of words for numevt need to be in steps of active
582 * serializers.
583 */
584 n = numevt % active_serializers;
585 if (n)
586 numevt += (active_serializers - n);
587 while (period_words % numevt && numevt > 0)
588 numevt -= active_serializers;
589 if (numevt <= 0)
0bf0e8ae 590 numevt = active_serializers;
487dce88 591
0bf0e8ae
PU		 592 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
593 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
2952b27e 594
5f04c603 595 /* Configure the burst size for platform drivers */
33445643
PU		 596 if (numevt == 1)
597 numevt = 0;
5f04c603
PU		 598 dma_params->fifo_level = numevt;
599 dma_data->maxburst = numevt;
600
2952b27e 601 return 0;
b67f4487
C		 602}
603
2c56c4c2 604static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
b67f4487
C		 605{
606 int i, active_slots;
607 u32 mask = 0;
cbc7956c 608 u32 busel = 0;
b67f4487 609
2c56c4c2
PU		 610 if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
611 dev_err(mcasp->dev, "tdm slot %d not supported\n",
612 mcasp->tdm_slots);
613 return -EINVAL;
614 }
615
70091a3e 616 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
b67f4487
C		 617 for (i = 0; i < active_slots; i++)
618 mask |= (1 << i);
619
f68205a7 620 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
6a99fb5f 621
cbc7956c
PU		 622 if (!mcasp->dat_port)
623 busel = TXSEL;
624
2c56c4c2
PU		 625 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
626 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
627 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
628 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
629
630 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
631 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
632 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
633 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
634
635 return 0;
b67f4487
C		 636}
637
638/* S/PDIF */
2c56c4c2 639static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
b67f4487 640{
b67f4487
C		 641 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
642 and LSB first */
f68205a7 643 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
b67f4487
C		 644
645 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
f68205a7 646 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
b67f4487
C		 647
648 /* Set the TX tdm : for all the slots */
f68205a7 649 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
b67f4487
C		 650
651 /* Set the TX clock controls : div = 1 and internal */
f68205a7 652 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
b67f4487 653
f68205a7 654 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
b67f4487
C		 655
656 /* Only 44100 and 48000 are valid, both have the same setting */
f68205a7 657 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
b67f4487
C		 658
659 /* Enable the DIT */
f68205a7 660 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
2c56c4c2
PU		 661
662 return 0;
b67f4487
C		 663}
664
665static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
666 struct snd_pcm_hw_params *params,
667 struct snd_soc_dai *cpu_dai)
668{
70091a3e 669 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487 670 struct davinci_pcm_dma_params *dma_params =
70091a3e 671 &mcasp->dma_params[substream->stream];
b67f4487 672 int word_length;
a7e46bd9 673 int channels = params_channels(params);
dd093a0f 674 int period_size = params_period_size(params);
2c56c4c2 675 int ret;
ab8b14b6
JS		 676
677 /* If mcasp is BCLK master we need to set BCLK divider */
678 if (mcasp->bclk_master) {
679 unsigned int bclk_freq = snd_soc_params_to_bclk(params);
680 if (mcasp->sysclk_freq % bclk_freq != 0) {
f5b02b4a 681 dev_err(mcasp->dev, "Can't produce required BCLK\n");
ab8b14b6
JS		 682 return -EINVAL;
683 }
684 davinci_mcasp_set_clkdiv(
685 cpu_dai, 1, mcasp->sysclk_freq / bclk_freq);
686 }
687
dd093a0f
PU		 688 ret = mcasp_common_hw_param(mcasp, substream->stream,
689 period_size * channels, channels);
0f7d9a63
PU		 690 if (ret)
691 return ret;
692
70091a3e 693 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
2c56c4c2 694 ret = mcasp_dit_hw_param(mcasp);
b67f4487 695 else
2c56c4c2
PU		 696 ret = mcasp_i2s_hw_param(mcasp, substream->stream);
697
698 if (ret)
699 return ret;
b67f4487
C		 700
701 switch (params_format(params)) {
0a9d1385 702 case SNDRV_PCM_FORMAT_U8:
b67f4487
C		 703 case SNDRV_PCM_FORMAT_S8:
704 dma_params->data_type = 1;
ba764b3d 705 word_length = 8;
b67f4487
C		 706 break;
707
0a9d1385 708 case SNDRV_PCM_FORMAT_U16_LE:
b67f4487
C		 709 case SNDRV_PCM_FORMAT_S16_LE:
710 dma_params->data_type = 2;
ba764b3d 711 word_length = 16;
b67f4487
C		 712 break;
713
21eb24d8
DM		 714 case SNDRV_PCM_FORMAT_U24_3LE:
715 case SNDRV_PCM_FORMAT_S24_3LE:
21eb24d8 716 dma_params->data_type = 3;
ba764b3d 717 word_length = 24;
21eb24d8
DM		 718 break;
719
6b7fa011
DM		 720 case SNDRV_PCM_FORMAT_U24_LE:
721 case SNDRV_PCM_FORMAT_S24_LE:
0a9d1385 722 case SNDRV_PCM_FORMAT_U32_LE:
b67f4487
C		 723 case SNDRV_PCM_FORMAT_S32_LE:
724 dma_params->data_type = 4;
ba764b3d 725 word_length = 32;
b67f4487
C		 726 break;
727
728 default:
729 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
730 return -EINVAL;
731 }
6a99fb5f 732
5f04c603 733 if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level)
4fa9c1a5
C		 734 dma_params->acnt = 4;
735 else
6a99fb5f
C		 736 dma_params->acnt = dma_params->data_type;
737
70091a3e 738 davinci_config_channel_size(mcasp, word_length);
b67f4487
C		 739
740 return 0;
741}
742
743static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
744 int cmd, struct snd_soc_dai *cpu_dai)
745{
70091a3e 746 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
b67f4487
C		 747 int ret = 0;
748
749 switch (cmd) {
b67f4487 750 case SNDRV_PCM_TRIGGER_RESUME:
e473b847
C		 751 case SNDRV_PCM_TRIGGER_START:
752 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
70091a3e 753 davinci_mcasp_start(mcasp, substream->stream);
b67f4487 754 break;
b67f4487 755 case SNDRV_PCM_TRIGGER_SUSPEND:
a47979b5 756 case SNDRV_PCM_TRIGGER_STOP:
b67f4487 757 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
70091a3e 758 davinci_mcasp_stop(mcasp, substream->stream);
b67f4487
C		 759 break;
760
761 default:
762 ret = -EINVAL;
763 }
764
765 return ret;
766}
767
85e7652d 768static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
b67f4487
C		 769 .trigger = davinci_mcasp_trigger,
770 .hw_params = davinci_mcasp_hw_params,
771 .set_fmt = davinci_mcasp_set_dai_fmt,
4ed8c9b7 772 .set_clkdiv = davinci_mcasp_set_clkdiv,
5b66aa2d 773 .set_sysclk = davinci_mcasp_set_sysclk,
b67f4487
C		 774};
775
d5902f69
PU		 776static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
777{
778 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
779
780 if (mcasp->version == MCASP_VERSION_4) {
781 /* Using dmaengine PCM */
782 dai->playback_dma_data =
783 &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
784 dai->capture_dma_data =
785 &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
786 } else {
787 /* Using davinci-pcm */
788 dai->playback_dma_data = mcasp->dma_params;
789 dai->capture_dma_data = mcasp->dma_params;
790 }
791
792 return 0;
793}
794
135014ad
PU		 795#ifdef CONFIG_PM_SLEEP
796static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
797{
798 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
790bb94b 799 struct davinci_mcasp_context *context = &mcasp->context;
135014ad 800
790bb94b
PU		 801 context->txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
802 context->rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
803 context->txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
804 context->rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
805 context->aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
806 context->aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
807 context->pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
135014ad
PU		 808
809 return 0;
810}
811
812static int davinci_mcasp_resume(struct snd_soc_dai *dai)
813{
814 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
790bb94b
PU		 815 struct davinci_mcasp_context *context = &mcasp->context;
816
817 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, context->txfmtctl);
818 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, context->rxfmtctl);
819 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, context->txfmt);
820 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, context->rxfmt);
821 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, context->aclkxctl);
822 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, context->aclkrctl);
823 mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, context->pdir);
135014ad
PU		 824
825 return 0;
826}
827#else
828#define davinci_mcasp_suspend NULL
829#define davinci_mcasp_resume NULL
830#endif
831
ed29cd5e
PU		 832#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
833
0a9d1385
BG		 834#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
835 SNDRV_PCM_FMTBIT_U8 | \
836 SNDRV_PCM_FMTBIT_S16_LE | \
837 SNDRV_PCM_FMTBIT_U16_LE | \
21eb24d8
DM		 838 SNDRV_PCM_FMTBIT_S24_LE | \
839 SNDRV_PCM_FMTBIT_U24_LE | \
840 SNDRV_PCM_FMTBIT_S24_3LE | \
841 SNDRV_PCM_FMTBIT_U24_3LE | \
0a9d1385
BG		 842 SNDRV_PCM_FMTBIT_S32_LE | \
843 SNDRV_PCM_FMTBIT_U32_LE)
844
f0fba2ad 845static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
b67f4487 846 {
f0fba2ad 847 .name = "davinci-mcasp.0",
d5902f69 848 .probe = davinci_mcasp_dai_probe,
135014ad
PU		 849 .suspend = davinci_mcasp_suspend,
850 .resume = davinci_mcasp_resume,
b67f4487
C		 851 .playback = {
852 .channels_min = 2,
2952b27e 853 .channels_max = 32 * 16,
b67f4487 854 .rates = DAVINCI_MCASP_RATES,
0a9d1385 855 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 856 },
857 .capture = {
858 .channels_min = 2,
2952b27e 859 .channels_max = 32 * 16,
b67f4487 860 .rates = DAVINCI_MCASP_RATES,
0a9d1385 861 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 862 },
863 .ops = &davinci_mcasp_dai_ops,
864
865 },
866 {
58e48d97 867 .name = "davinci-mcasp.1",
d5902f69 868 .probe = davinci_mcasp_dai_probe,
b67f4487
C		 869 .playback = {
870 .channels_min = 1,
871 .channels_max = 384,
872 .rates = DAVINCI_MCASP_RATES,
0a9d1385 873 .formats = DAVINCI_MCASP_PCM_FMTS,
b67f4487
C		 874 },
875 .ops = &davinci_mcasp_dai_ops,
876 },
877
878};
b67f4487 879
eeef0eda
KM		 880static const struct snd_soc_component_driver davinci_mcasp_component = {
881 .name = "davinci-mcasp",
882};
883
256ba181 884/* Some HW specific values and defaults. The rest is filled in from DT. */
d1debafc 885static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
256ba181
JS		 886 .tx_dma_offset = 0x400,
887 .rx_dma_offset = 0x400,
888 .asp_chan_q = EVENTQ_0,
889 .version = MCASP_VERSION_1,
890};
891
d1debafc 892static struct davinci_mcasp_pdata da830_mcasp_pdata = {
256ba181
JS		 893 .tx_dma_offset = 0x2000,
894 .rx_dma_offset = 0x2000,
895 .asp_chan_q = EVENTQ_0,
896 .version = MCASP_VERSION_2,
897};
898
d1debafc 899static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
256ba181
JS		 900 .tx_dma_offset = 0,
901 .rx_dma_offset = 0,
902 .asp_chan_q = EVENTQ_0,
903 .version = MCASP_VERSION_3,
904};
905
d1debafc 906static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
453c4990
PU		 907 .tx_dma_offset = 0x200,
908 .rx_dma_offset = 0x284,
909 .asp_chan_q = EVENTQ_0,
910 .version = MCASP_VERSION_4,
911};
912
3e3b8c34
HG		 913static const struct of_device_id mcasp_dt_ids[] = {
914 {
915 .compatible = "ti,dm646x-mcasp-audio",
256ba181 916 .data = &dm646x_mcasp_pdata,
3e3b8c34
HG		 917 },
918 {
919 .compatible = "ti,da830-mcasp-audio",
256ba181 920 .data = &da830_mcasp_pdata,
3e3b8c34 921 },
e5ec69da 922 {
3af9e031 923 .compatible = "ti,am33xx-mcasp-audio",
b14899da 924 .data = &am33xx_mcasp_pdata,
e5ec69da 925 },
453c4990
PU		 926 {
927 .compatible = "ti,dra7-mcasp-audio",
928 .data = &dra7_mcasp_pdata,
929 },
3e3b8c34
HG		 930 { /* sentinel */ }
931};
932MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
933
ae726e93
PU		 934static int mcasp_reparent_fck(struct platform_device *pdev)
935{
936 struct device_node *node = pdev->dev.of_node;
937 struct clk *gfclk, *parent_clk;
938 const char *parent_name;
939 int ret;
940
941 if (!node)
942 return 0;
943
944 parent_name = of_get_property(node, "fck_parent", NULL);
945 if (!parent_name)
946 return 0;
947
948 gfclk = clk_get(&pdev->dev, "fck");
949 if (IS_ERR(gfclk)) {
950 dev_err(&pdev->dev, "failed to get fck\n");
951 return PTR_ERR(gfclk);
952 }
953
954 parent_clk = clk_get(NULL, parent_name);
955 if (IS_ERR(parent_clk)) {
956 dev_err(&pdev->dev, "failed to get parent clock\n");
957 ret = PTR_ERR(parent_clk);
958 goto err1;
959 }
960
961 ret = clk_set_parent(gfclk, parent_clk);
962 if (ret) {
963 dev_err(&pdev->dev, "failed to reparent fck\n");
964 goto err2;
965 }
966
967err2:
968 clk_put(parent_clk);
969err1:
970 clk_put(gfclk);
971 return ret;
972}
973
d1debafc 974static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
3e3b8c34
HG		 975 struct platform_device *pdev)
976{
977 struct device_node *np = pdev->dev.of_node;
d1debafc 978 struct davinci_mcasp_pdata *pdata = NULL;
3e3b8c34 979 const struct of_device_id *match =
ea421eb1 980 of_match_device(mcasp_dt_ids, &pdev->dev);
4023fe6f 981 struct of_phandle_args dma_spec;
3e3b8c34
HG		 982
983 const u32 *of_serial_dir32;
3e3b8c34
HG		 984 u32 val;
985 int i, ret = 0;
986
987 if (pdev->dev.platform_data) {
988 pdata = pdev->dev.platform_data;
989 return pdata;
990 } else if (match) {
d1debafc 991 pdata = (struct davinci_mcasp_pdata*) match->data;
3e3b8c34
HG		 992 } else {
993 /* control shouldn't reach here. something is wrong */
994 ret = -EINVAL;
995 goto nodata;
996 }
997
3e3b8c34
HG		 998 ret = of_property_read_u32(np, "op-mode", &val);
999 if (ret >= 0)
1000 pdata->op_mode = val;
1001
1002 ret = of_property_read_u32(np, "tdm-slots", &val);
2952b27e
MB		 1003 if (ret >= 0) {
1004 if (val < 2 || val > 32) {
1005 dev_err(&pdev->dev,
1006 "tdm-slots must be in rage [2-32]\n");
1007 ret = -EINVAL;
1008 goto nodata;
1009 }
1010
3e3b8c34 1011 pdata->tdm_slots = val;
2952b27e 1012 }
3e3b8c34 1013
3e3b8c34
HG		 1014 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1015 val /= sizeof(u32);
3e3b8c34 1016 if (of_serial_dir32) {
1427e660
PU		 1017 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1018 (sizeof(*of_serial_dir) * val),
1019 GFP_KERNEL);
3e3b8c34
HG		 1020 if (!of_serial_dir) {
1021 ret = -ENOMEM;
1022 goto nodata;
1023 }
1024
1427e660 1025 for (i = 0; i < val; i++)
3e3b8c34
HG		 1026 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1027
1427e660 1028 pdata->num_serializer = val;
3e3b8c34
HG		 1029 pdata->serial_dir = of_serial_dir;
1030 }
1031
4023fe6f
JS		 1032 ret = of_property_match_string(np, "dma-names", "tx");
1033 if (ret < 0)
1034 goto nodata;
1035
1036 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1037 &dma_spec);
1038 if (ret < 0)
1039 goto nodata;
1040
1041 pdata->tx_dma_channel = dma_spec.args[0];
1042
1043 ret = of_property_match_string(np, "dma-names", "rx");
1044 if (ret < 0)
1045 goto nodata;
1046
1047 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1048 &dma_spec);
1049 if (ret < 0)
1050 goto nodata;
1051
1052 pdata->rx_dma_channel = dma_spec.args[0];
1053
3e3b8c34
HG		 1054 ret = of_property_read_u32(np, "tx-num-evt", &val);
1055 if (ret >= 0)
1056 pdata->txnumevt = val;
1057
1058 ret = of_property_read_u32(np, "rx-num-evt", &val);
1059 if (ret >= 0)
1060 pdata->rxnumevt = val;
1061
1062 ret = of_property_read_u32(np, "sram-size-playback", &val);
1063 if (ret >= 0)
1064 pdata->sram_size_playback = val;
1065
1066 ret = of_property_read_u32(np, "sram-size-capture", &val);
1067 if (ret >= 0)
1068 pdata->sram_size_capture = val;
1069
1070 return pdata;
1071
1072nodata:
1073 if (ret < 0) {
1074 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1075 ret);
1076 pdata = NULL;
1077 }
1078 return pdata;
1079}
1080
b67f4487
C		 1081static int davinci_mcasp_probe(struct platform_device *pdev)
1082{
64ebdec3 1083 struct davinci_pcm_dma_params *dma_params;
8de131f2 1084 struct snd_dmaengine_dai_dma_data *dma_data;
256ba181 1085 struct resource *mem, *ioarea, *res, *dat;
d1debafc 1086 struct davinci_mcasp_pdata *pdata;
70091a3e 1087 struct davinci_mcasp *mcasp;
96d31e2b 1088 int ret;
b67f4487 1089
3e3b8c34
HG		 1090 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1091 dev_err(&pdev->dev, "No platform data supplied\n");
1092 return -EINVAL;
1093 }
1094
70091a3e 1095 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
96d31e2b 1096 GFP_KERNEL);
70091a3e 1097 if (!mcasp)
b67f4487
C		 1098 return -ENOMEM;
1099
3e3b8c34
HG		 1100 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1101 if (!pdata) {
1102 dev_err(&pdev->dev, "no platform data\n");
1103 return -EINVAL;
1104 }
1105
256ba181 1106 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
b67f4487 1107 if (!mem) {
70091a3e 1108 dev_warn(mcasp->dev,
256ba181
JS		 1109 "\"mpu\" mem resource not found, using index 0\n");
1110 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1111 if (!mem) {
1112 dev_err(&pdev->dev, "no mem resource?\n");
1113 return -ENODEV;
1114 }
b67f4487
C		 1115 }
1116
96d31e2b 1117 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
d852f446 1118 resource_size(mem), pdev->name);
b67f4487
C		 1119 if (!ioarea) {
1120 dev_err(&pdev->dev, "Audio region already claimed\n");
96d31e2b 1121 return -EBUSY;
b67f4487
C		 1122 }
1123
10884347 1124 pm_runtime_enable(&pdev->dev);
b67f4487 1125
10884347
HG		 1126 ret = pm_runtime_get_sync(&pdev->dev);
1127 if (IS_ERR_VALUE(ret)) {
1128 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1129 return ret;
1130 }
b67f4487 1131
70091a3e
PU		 1132 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1133 if (!mcasp->base) {
4f82f028
VB		 1134 dev_err(&pdev->dev, "ioremap failed\n");
1135 ret = -ENOMEM;
1136 goto err_release_clk;
1137 }
1138
70091a3e
PU		 1139 mcasp->op_mode = pdata->op_mode;
1140 mcasp->tdm_slots = pdata->tdm_slots;
1141 mcasp->num_serializer = pdata->num_serializer;
1142 mcasp->serial_dir = pdata->serial_dir;
1143 mcasp->version = pdata->version;
1144 mcasp->txnumevt = pdata->txnumevt;
1145 mcasp->rxnumevt = pdata->rxnumevt;
487dce88 1146
70091a3e 1147 mcasp->dev = &pdev->dev;
b67f4487 1148
256ba181 1149 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
cbc7956c
PU		 1150 if (dat)
1151 mcasp->dat_port = true;
256ba181 1152
64ebdec3 1153 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
8de131f2 1154 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
64ebdec3
PU		 1155 dma_params->asp_chan_q = pdata->asp_chan_q;
1156 dma_params->ram_chan_q = pdata->ram_chan_q;
1157 dma_params->sram_pool = pdata->sram_pool;
1158 dma_params->sram_size = pdata->sram_size_playback;
cbc7956c 1159 if (dat)
64ebdec3 1160 dma_params->dma_addr = dat->start;
cbc7956c 1161 else
64ebdec3 1162 dma_params->dma_addr = mem->start + pdata->tx_dma_offset;
b67f4487 1163
453c4990 1164 /* Unconditional dmaengine stuff */
8de131f2 1165 dma_data->addr = dma_params->dma_addr;
453c4990 1166
b67f4487 1167 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
4023fe6f 1168 if (res)
64ebdec3 1169 dma_params->channel = res->start;
4023fe6f 1170 else
64ebdec3 1171 dma_params->channel = pdata->tx_dma_channel;
92e2a6f6 1172
8de131f2
PU		 1173 /* dmaengine filter data for DT and non-DT boot */
1174 if (pdev->dev.of_node)
1175 dma_data->filter_data = "tx";
1176 else
1177 dma_data->filter_data = &dma_params->channel;
1178
64ebdec3 1179 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
8de131f2 1180 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
64ebdec3
PU		 1181 dma_params->asp_chan_q = pdata->asp_chan_q;
1182 dma_params->ram_chan_q = pdata->ram_chan_q;
1183 dma_params->sram_pool = pdata->sram_pool;
1184 dma_params->sram_size = pdata->sram_size_capture;
cbc7956c 1185 if (dat)
64ebdec3 1186 dma_params->dma_addr = dat->start;
cbc7956c 1187 else
64ebdec3 1188 dma_params->dma_addr = mem->start + pdata->rx_dma_offset;
cbc7956c 1189
453c4990 1190 /* Unconditional dmaengine stuff */
8de131f2 1191 dma_data->addr = dma_params->dma_addr;
453c4990 1192
cbc7956c
PU		 1193 if (mcasp->version < MCASP_VERSION_3) {
1194 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
64ebdec3 1195 /* dma_params->dma_addr is pointing to the data port address */
cbc7956c
PU		 1196 mcasp->dat_port = true;
1197 } else {
1198 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1199 }
b67f4487
C		 1200
1201 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
4023fe6f 1202 if (res)
64ebdec3 1203 dma_params->channel = res->start;
4023fe6f 1204 else
64ebdec3 1205 dma_params->channel = pdata->rx_dma_channel;
b67f4487 1206
8de131f2
PU		 1207 /* dmaengine filter data for DT and non-DT boot */
1208 if (pdev->dev.of_node)
1209 dma_data->filter_data = "rx";
1210 else
1211 dma_data->filter_data = &dma_params->channel;
453c4990 1212
70091a3e 1213 dev_set_drvdata(&pdev->dev, mcasp);
ae726e93
PU		 1214
1215 mcasp_reparent_fck(pdev);
1216
eeef0eda
KM		 1217 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1218 &davinci_mcasp_dai[pdata->op_mode], 1);
b67f4487
C		 1219
1220 if (ret != 0)
96d31e2b 1221 goto err_release_clk;
f08095a4 1222
453c4990
PU		 1223 if (mcasp->version != MCASP_VERSION_4) {
1224 ret = davinci_soc_platform_register(&pdev->dev);
1225 if (ret) {
1226 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1227 goto err_unregister_component;
1228 }
f08095a4
HG		 1229 }
1230
b67f4487
C		 1231 return 0;
1232
eeef0eda
KM		 1233err_unregister_component:
1234 snd_soc_unregister_component(&pdev->dev);
eef6d7b8 1235err_release_clk:
10884347
HG		 1236 pm_runtime_put_sync(&pdev->dev);
1237 pm_runtime_disable(&pdev->dev);
b67f4487
C		 1238 return ret;
1239}
1240
1241static int davinci_mcasp_remove(struct platform_device *pdev)
1242{
453c4990 1243 struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
b67f4487 1244
eeef0eda 1245 snd_soc_unregister_component(&pdev->dev);
453c4990
PU		 1246 if (mcasp->version != MCASP_VERSION_4)
1247 davinci_soc_platform_unregister(&pdev->dev);
10884347
HG		 1248
1249 pm_runtime_put_sync(&pdev->dev);
1250 pm_runtime_disable(&pdev->dev);
b67f4487 1251
b67f4487
C		 1252 return 0;
1253}
1254
1255static struct platform_driver davinci_mcasp_driver = {
1256 .probe = davinci_mcasp_probe,
1257 .remove = davinci_mcasp_remove,
1258 .driver = {
1259 .name = "davinci-mcasp",
1260 .owner = THIS_MODULE,
ea421eb1 1261 .of_match_table = mcasp_dt_ids,
b67f4487
C		 1262 },
1263};
1264
f9b8a514 1265module_platform_driver(davinci_mcasp_driver);
b67f4487
C		 1266
1267MODULE_AUTHOR("Steve Chen");
1268MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1269MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)