Commit | Line | Data |
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b67f4487 C |
1 | /* |
2 | * ALSA SoC McASP Audio Layer for TI DAVINCI processor | |
3 | * | |
4 | * Multi-channel Audio Serial Port Driver | |
5 | * | |
6 | * Author: Nirmal Pandey <n-pandey@ti.com>, | |
7 | * Suresh Rajashekara <suresh.r@ti.com> | |
8 | * Steve Chen <schen@.mvista.com> | |
9 | * | |
10 | * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> | |
11 | * Copyright: (C) 2009 Texas Instruments, India | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b67f4487 C |
22 | #include <linux/delay.h> |
23 | #include <linux/io.h> | |
ae726e93 | 24 | #include <linux/clk.h> |
10884347 | 25 | #include <linux/pm_runtime.h> |
3e3b8c34 HG |
26 | #include <linux/of.h> |
27 | #include <linux/of_platform.h> | |
28 | #include <linux/of_device.h> | |
9759e7ef | 29 | #include <linux/platform_data/davinci_asp.h> |
a75a053f | 30 | #include <linux/math64.h> |
ca3d9433 | 31 | #include <linux/bitmap.h> |
b67f4487 | 32 | |
6479285d | 33 | #include <sound/asoundef.h> |
b67f4487 C |
34 | #include <sound/core.h> |
35 | #include <sound/pcm.h> | |
36 | #include <sound/pcm_params.h> | |
37 | #include <sound/initval.h> | |
38 | #include <sound/soc.h> | |
453c4990 | 39 | #include <sound/dmaengine_pcm.h> |
b67f4487 | 40 | |
f3f9cfa8 | 41 | #include "edma-pcm.h" |
077a403d | 42 | #include "../omap/sdma-pcm.h" |
b67f4487 C |
43 | #include "davinci-mcasp.h" |
44 | ||
0bf0e8ae PU |
45 | #define MCASP_MAX_AFIFO_DEPTH 64 |
46 | ||
1cc0c054 PU |
47 | static u32 context_regs[] = { |
48 | DAVINCI_MCASP_TXFMCTL_REG, | |
49 | DAVINCI_MCASP_RXFMCTL_REG, | |
50 | DAVINCI_MCASP_TXFMT_REG, | |
51 | DAVINCI_MCASP_RXFMT_REG, | |
52 | DAVINCI_MCASP_ACLKXCTL_REG, | |
53 | DAVINCI_MCASP_ACLKRCTL_REG, | |
f114ce60 PU |
54 | DAVINCI_MCASP_AHCLKXCTL_REG, |
55 | DAVINCI_MCASP_AHCLKRCTL_REG, | |
1cc0c054 | 56 | DAVINCI_MCASP_PDIR_REG, |
f114ce60 PU |
57 | DAVINCI_MCASP_RXMASK_REG, |
58 | DAVINCI_MCASP_TXMASK_REG, | |
59 | DAVINCI_MCASP_RXTDM_REG, | |
60 | DAVINCI_MCASP_TXTDM_REG, | |
1cc0c054 PU |
61 | }; |
62 | ||
790bb94b | 63 | struct davinci_mcasp_context { |
1cc0c054 | 64 | u32 config_regs[ARRAY_SIZE(context_regs)]; |
f114ce60 PU |
65 | u32 afifo_regs[2]; /* for read/write fifo control registers */ |
66 | u32 *xrsr_regs; /* for serializer configuration */ | |
6afda7f5 | 67 | bool pm_state; |
790bb94b PU |
68 | }; |
69 | ||
a75a053f JS |
70 | struct davinci_mcasp_ruledata { |
71 | struct davinci_mcasp *mcasp; | |
72 | int serializers; | |
73 | }; | |
74 | ||
70091a3e | 75 | struct davinci_mcasp { |
453c4990 | 76 | struct snd_dmaengine_dai_dma_data dma_data[2]; |
21400a72 | 77 | void __iomem *base; |
487dce88 | 78 | u32 fifo_base; |
21400a72 | 79 | struct device *dev; |
a7a3324a | 80 | struct snd_pcm_substream *substreams[2]; |
4a11ff26 | 81 | unsigned int dai_fmt; |
21400a72 PU |
82 | |
83 | /* McASP specific data */ | |
84 | int tdm_slots; | |
dd55ff83 JS |
85 | u32 tdm_mask[2]; |
86 | int slot_width; | |
21400a72 PU |
87 | u8 op_mode; |
88 | u8 num_serializer; | |
89 | u8 *serial_dir; | |
90 | u8 version; | |
8267525c | 91 | u8 bclk_div; |
4dcb5a0b | 92 | int streams; |
a7a3324a | 93 | u32 irq_request[2]; |
9759e7ef | 94 | int dma_request[2]; |
21400a72 | 95 | |
ab8b14b6 JS |
96 | int sysclk_freq; |
97 | bool bclk_master; | |
98 | ||
ca3d9433 PU |
99 | unsigned long pdir; /* Pin direction bitfield */ |
100 | ||
21400a72 PU |
101 | /* McASP FIFO related */ |
102 | u8 txnumevt; | |
103 | u8 rxnumevt; | |
104 | ||
cbc7956c PU |
105 | bool dat_port; |
106 | ||
11277833 PU |
107 | /* Used for comstraint setting on the second stream */ |
108 | u32 channels; | |
109 | ||
21400a72 | 110 | #ifdef CONFIG_PM_SLEEP |
790bb94b | 111 | struct davinci_mcasp_context context; |
21400a72 | 112 | #endif |
a75a053f JS |
113 | |
114 | struct davinci_mcasp_ruledata ruledata[2]; | |
5935a056 | 115 | struct snd_pcm_hw_constraint_list chconstr[2]; |
21400a72 PU |
116 | }; |
117 | ||
f68205a7 PU |
118 | static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, |
119 | u32 val) | |
b67f4487 | 120 | { |
f68205a7 | 121 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
122 | __raw_writel(__raw_readl(reg) | val, reg); |
123 | } | |
124 | ||
f68205a7 PU |
125 | static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, |
126 | u32 val) | |
b67f4487 | 127 | { |
f68205a7 | 128 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
129 | __raw_writel((__raw_readl(reg) & ~(val)), reg); |
130 | } | |
131 | ||
f68205a7 PU |
132 | static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, |
133 | u32 val, u32 mask) | |
b67f4487 | 134 | { |
f68205a7 | 135 | void __iomem *reg = mcasp->base + offset; |
b67f4487 C |
136 | __raw_writel((__raw_readl(reg) & ~mask) | val, reg); |
137 | } | |
138 | ||
f68205a7 PU |
139 | static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, |
140 | u32 val) | |
b67f4487 | 141 | { |
f68205a7 | 142 | __raw_writel(val, mcasp->base + offset); |
b67f4487 C |
143 | } |
144 | ||
f68205a7 | 145 | static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) |
b67f4487 | 146 | { |
f68205a7 | 147 | return (u32)__raw_readl(mcasp->base + offset); |
b67f4487 C |
148 | } |
149 | ||
f68205a7 | 150 | static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) |
b67f4487 C |
151 | { |
152 | int i = 0; | |
153 | ||
f68205a7 | 154 | mcasp_set_bits(mcasp, ctl_reg, val); |
b67f4487 C |
155 | |
156 | /* programming GBLCTL needs to read back from GBLCTL and verfiy */ | |
157 | /* loop count is to avoid the lock-up */ | |
158 | for (i = 0; i < 1000; i++) { | |
f68205a7 | 159 | if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) |
b67f4487 C |
160 | break; |
161 | } | |
162 | ||
f68205a7 | 163 | if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) |
b67f4487 C |
164 | printk(KERN_ERR "GBLCTL write error\n"); |
165 | } | |
166 | ||
4dcb5a0b PU |
167 | static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) |
168 | { | |
f68205a7 PU |
169 | u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); |
170 | u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); | |
4dcb5a0b PU |
171 | |
172 | return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE; | |
173 | } | |
174 | ||
ca3d9433 PU |
175 | static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) |
176 | { | |
177 | u32 bit = PIN_BIT_AMUTE; | |
178 | ||
179 | for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { | |
180 | if (enable) | |
181 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); | |
182 | else | |
183 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); | |
184 | } | |
185 | } | |
186 | ||
187 | static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) | |
188 | { | |
189 | u32 bit; | |
190 | ||
191 | for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AFSR) { | |
192 | if (enable) | |
193 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); | |
194 | else | |
195 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); | |
196 | } | |
197 | } | |
198 | ||
70091a3e | 199 | static void mcasp_start_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 200 | { |
bb372af0 PU |
201 | if (mcasp->rxnumevt) { /* enable FIFO */ |
202 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
203 | ||
204 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
205 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
206 | } | |
207 | ||
44982735 | 208 | /* Start clocks */ |
f68205a7 PU |
209 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); |
210 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); | |
4dcb5a0b PU |
211 | /* |
212 | * When ASYNC == 0 the transmit and receive sections operate | |
213 | * synchronously from the transmit clock and frame sync. We need to make | |
214 | * sure that the TX signlas are enabled when starting reception. | |
215 | */ | |
216 | if (mcasp_is_synchronous(mcasp)) { | |
f68205a7 PU |
217 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
218 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
4dcb5a0b PU |
219 | } |
220 | ||
44982735 | 221 | /* Activate serializer(s) */ |
1003c27a | 222 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
f68205a7 | 223 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); |
44982735 | 224 | /* Release RX state machine */ |
f68205a7 | 225 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); |
44982735 | 226 | /* Release Frame Sync generator */ |
f68205a7 | 227 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); |
4dcb5a0b | 228 | if (mcasp_is_synchronous(mcasp)) |
f68205a7 | 229 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); |
a7a3324a MLC |
230 | |
231 | /* enable receive IRQs */ | |
232 | mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, | |
233 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); | |
b67f4487 C |
234 | } |
235 | ||
70091a3e | 236 | static void mcasp_start_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 237 | { |
6a99fb5f C |
238 | u32 cnt; |
239 | ||
bb372af0 PU |
240 | if (mcasp->txnumevt) { /* enable FIFO */ |
241 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
242 | ||
243 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
244 | mcasp_set_bits(mcasp, reg, FIFO_ENABLE); | |
245 | } | |
246 | ||
36bcecd0 | 247 | /* Start clocks */ |
f68205a7 PU |
248 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); |
249 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); | |
ca3d9433 PU |
250 | mcasp_set_clk_pdir(mcasp, true); |
251 | ||
36bcecd0 | 252 | /* Activate serializer(s) */ |
1003c27a | 253 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
f68205a7 | 254 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); |
b67f4487 | 255 | |
36bcecd0 | 256 | /* wait for XDATA to be cleared */ |
6a99fb5f | 257 | cnt = 0; |
e2a0c9fa PU |
258 | while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && |
259 | (cnt < 100000)) | |
6a99fb5f C |
260 | cnt++; |
261 | ||
ca3d9433 PU |
262 | mcasp_set_axr_pdir(mcasp, true); |
263 | ||
36bcecd0 PU |
264 | /* Release TX state machine */ |
265 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); | |
266 | /* Release Frame Sync generator */ | |
267 | mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); | |
a7a3324a MLC |
268 | |
269 | /* enable transmit IRQs */ | |
270 | mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, | |
271 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); | |
b67f4487 C |
272 | } |
273 | ||
70091a3e | 274 | static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 275 | { |
4dcb5a0b PU |
276 | mcasp->streams++; |
277 | ||
bb372af0 | 278 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 279 | mcasp_start_tx(mcasp); |
bb372af0 | 280 | else |
70091a3e | 281 | mcasp_start_rx(mcasp); |
b67f4487 C |
282 | } |
283 | ||
70091a3e | 284 | static void mcasp_stop_rx(struct davinci_mcasp *mcasp) |
b67f4487 | 285 | { |
a7a3324a MLC |
286 | /* disable IRQ sources */ |
287 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, | |
288 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); | |
289 | ||
4dcb5a0b PU |
290 | /* |
291 | * In synchronous mode stop the TX clocks if no other stream is | |
292 | * running | |
293 | */ | |
ca3d9433 PU |
294 | if (mcasp_is_synchronous(mcasp) && !mcasp->streams) { |
295 | mcasp_set_clk_pdir(mcasp, false); | |
f68205a7 | 296 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); |
ca3d9433 | 297 | } |
4dcb5a0b | 298 | |
f68205a7 PU |
299 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); |
300 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
301 | |
302 | if (mcasp->rxnumevt) { /* disable FIFO */ | |
303 | u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
304 | ||
305 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
306 | } | |
b67f4487 C |
307 | } |
308 | ||
70091a3e | 309 | static void mcasp_stop_tx(struct davinci_mcasp *mcasp) |
b67f4487 | 310 | { |
4dcb5a0b PU |
311 | u32 val = 0; |
312 | ||
a7a3324a MLC |
313 | /* disable IRQ sources */ |
314 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, | |
315 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); | |
316 | ||
4dcb5a0b PU |
317 | /* |
318 | * In synchronous mode keep TX clocks running if the capture stream is | |
319 | * still running. | |
320 | */ | |
321 | if (mcasp_is_synchronous(mcasp) && mcasp->streams) | |
322 | val = TXHCLKRST | TXCLKRST | TXFSRST; | |
ca3d9433 PU |
323 | else |
324 | mcasp_set_clk_pdir(mcasp, false); | |
325 | ||
4dcb5a0b | 326 | |
f68205a7 PU |
327 | mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); |
328 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); | |
0380866a PU |
329 | |
330 | if (mcasp->txnumevt) { /* disable FIFO */ | |
331 | u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
332 | ||
333 | mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); | |
334 | } | |
ca3d9433 PU |
335 | |
336 | mcasp_set_axr_pdir(mcasp, false); | |
b67f4487 C |
337 | } |
338 | ||
70091a3e | 339 | static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) |
b67f4487 | 340 | { |
4dcb5a0b PU |
341 | mcasp->streams--; |
342 | ||
0380866a | 343 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) |
70091a3e | 344 | mcasp_stop_tx(mcasp); |
0380866a | 345 | else |
70091a3e | 346 | mcasp_stop_rx(mcasp); |
b67f4487 C |
347 | } |
348 | ||
a7a3324a MLC |
349 | static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) |
350 | { | |
351 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
352 | struct snd_pcm_substream *substream; | |
353 | u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; | |
354 | u32 handled_mask = 0; | |
355 | u32 stat; | |
356 | ||
357 | stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); | |
358 | if (stat & XUNDRN & irq_mask) { | |
359 | dev_warn(mcasp->dev, "Transmit buffer underflow\n"); | |
360 | handled_mask |= XUNDRN; | |
361 | ||
362 | substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; | |
dae35d1f TI |
363 | if (substream) |
364 | snd_pcm_stop_xrun(substream); | |
a7a3324a MLC |
365 | } |
366 | ||
367 | if (!handled_mask) | |
368 | dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", | |
369 | stat); | |
370 | ||
371 | if (stat & XRERR) | |
372 | handled_mask |= XRERR; | |
373 | ||
374 | /* Ack the handled event only */ | |
375 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); | |
376 | ||
377 | return IRQ_RETVAL(handled_mask); | |
378 | } | |
379 | ||
380 | static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) | |
381 | { | |
382 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
383 | struct snd_pcm_substream *substream; | |
384 | u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; | |
385 | u32 handled_mask = 0; | |
386 | u32 stat; | |
387 | ||
388 | stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); | |
389 | if (stat & ROVRN & irq_mask) { | |
390 | dev_warn(mcasp->dev, "Receive buffer overflow\n"); | |
391 | handled_mask |= ROVRN; | |
392 | ||
393 | substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; | |
dae35d1f TI |
394 | if (substream) |
395 | snd_pcm_stop_xrun(substream); | |
a7a3324a MLC |
396 | } |
397 | ||
398 | if (!handled_mask) | |
399 | dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", | |
400 | stat); | |
401 | ||
402 | if (stat & XRERR) | |
403 | handled_mask |= XRERR; | |
404 | ||
405 | /* Ack the handled event only */ | |
406 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); | |
407 | ||
408 | return IRQ_RETVAL(handled_mask); | |
409 | } | |
410 | ||
5a1b8a80 PU |
411 | static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) |
412 | { | |
413 | struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; | |
414 | irqreturn_t ret = IRQ_NONE; | |
415 | ||
416 | if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) | |
417 | ret = davinci_mcasp_tx_irq_handler(irq, data); | |
418 | ||
419 | if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) | |
420 | ret |= davinci_mcasp_rx_irq_handler(irq, data); | |
421 | ||
422 | return ret; | |
423 | } | |
424 | ||
b67f4487 C |
425 | static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, |
426 | unsigned int fmt) | |
427 | { | |
70091a3e | 428 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
1d17a04e | 429 | int ret = 0; |
6dfa9a4e | 430 | u32 data_delay; |
83f12503 | 431 | bool fs_pol_rising; |
ffd950f7 | 432 | bool inv_fs = false; |
b67f4487 | 433 | |
4a11ff26 PU |
434 | if (!fmt) |
435 | return 0; | |
436 | ||
1d17a04e | 437 | pm_runtime_get_sync(mcasp->dev); |
5296cf2d | 438 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
188edc59 PU |
439 | case SND_SOC_DAIFMT_DSP_A: |
440 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
441 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
188edc59 PU |
442 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
443 | data_delay = 1; | |
444 | break; | |
5296cf2d DM |
445 | case SND_SOC_DAIFMT_DSP_B: |
446 | case SND_SOC_DAIFMT_AC97: | |
f68205a7 PU |
447 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
448 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
449 | /* No delay after FS */ |
450 | data_delay = 0; | |
5296cf2d | 451 | break; |
ffd950f7 | 452 | case SND_SOC_DAIFMT_I2S: |
5296cf2d | 453 | /* configure a full-word SYNC pulse (LRCLK) */ |
f68205a7 PU |
454 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); |
455 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
6dfa9a4e PU |
456 | /* 1st data bit occur one ACLK cycle after the frame sync */ |
457 | data_delay = 1; | |
ffd950f7 PU |
458 | /* FS need to be inverted */ |
459 | inv_fs = true; | |
5296cf2d | 460 | break; |
423761e0 PU |
461 | case SND_SOC_DAIFMT_LEFT_J: |
462 | /* configure a full-word SYNC pulse (LRCLK) */ | |
463 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); | |
464 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); | |
465 | /* No delay after FS */ | |
466 | data_delay = 0; | |
467 | break; | |
ffd950f7 PU |
468 | default: |
469 | ret = -EINVAL; | |
470 | goto out; | |
5296cf2d DM |
471 | } |
472 | ||
6dfa9a4e PU |
473 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), |
474 | FSXDLY(3)); | |
475 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), | |
476 | FSRDLY(3)); | |
477 | ||
b67f4487 C |
478 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
479 | case SND_SOC_DAIFMT_CBS_CFS: | |
480 | /* codec is clock and frame slave */ | |
f68205a7 PU |
481 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
482 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 483 | |
f68205a7 PU |
484 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
485 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 486 | |
ca3d9433 PU |
487 | /* BCLK */ |
488 | set_bit(PIN_BIT_ACLKX, &mcasp->pdir); | |
489 | set_bit(PIN_BIT_ACLKR, &mcasp->pdir); | |
490 | /* Frame Sync */ | |
491 | set_bit(PIN_BIT_AFSX, &mcasp->pdir); | |
492 | set_bit(PIN_BIT_AFSR, &mcasp->pdir); | |
493 | ||
ab8b14b6 | 494 | mcasp->bclk_master = 1; |
b67f4487 | 495 | break; |
226e2f1b PU |
496 | case SND_SOC_DAIFMT_CBS_CFM: |
497 | /* codec is clock slave and frame master */ | |
498 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); | |
499 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
500 | ||
501 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); | |
502 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
503 | ||
ca3d9433 PU |
504 | /* BCLK */ |
505 | set_bit(PIN_BIT_ACLKX, &mcasp->pdir); | |
506 | set_bit(PIN_BIT_ACLKR, &mcasp->pdir); | |
507 | /* Frame Sync */ | |
508 | clear_bit(PIN_BIT_AFSX, &mcasp->pdir); | |
509 | clear_bit(PIN_BIT_AFSR, &mcasp->pdir); | |
510 | ||
226e2f1b PU |
511 | mcasp->bclk_master = 1; |
512 | break; | |
517ee6cf C |
513 | case SND_SOC_DAIFMT_CBM_CFS: |
514 | /* codec is clock master and frame slave */ | |
f68205a7 PU |
515 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
516 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
517ee6cf | 517 | |
f68205a7 PU |
518 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
519 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
517ee6cf | 520 | |
ca3d9433 PU |
521 | /* BCLK */ |
522 | clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); | |
523 | clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); | |
524 | /* Frame Sync */ | |
525 | set_bit(PIN_BIT_AFSX, &mcasp->pdir); | |
526 | set_bit(PIN_BIT_AFSR, &mcasp->pdir); | |
527 | ||
ab8b14b6 | 528 | mcasp->bclk_master = 0; |
517ee6cf | 529 | break; |
b67f4487 C |
530 | case SND_SOC_DAIFMT_CBM_CFM: |
531 | /* codec is clock and frame master */ | |
f68205a7 PU |
532 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); |
533 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); | |
b67f4487 | 534 | |
f68205a7 PU |
535 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); |
536 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); | |
b67f4487 | 537 | |
ca3d9433 PU |
538 | /* BCLK */ |
539 | clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); | |
540 | clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); | |
541 | /* Frame Sync */ | |
542 | clear_bit(PIN_BIT_AFSX, &mcasp->pdir); | |
543 | clear_bit(PIN_BIT_AFSR, &mcasp->pdir); | |
544 | ||
ab8b14b6 | 545 | mcasp->bclk_master = 0; |
b67f4487 | 546 | break; |
b67f4487 | 547 | default: |
1d17a04e PU |
548 | ret = -EINVAL; |
549 | goto out; | |
b67f4487 C |
550 | } |
551 | ||
552 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
553 | case SND_SOC_DAIFMT_IB_NF: | |
f68205a7 | 554 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 555 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 556 | fs_pol_rising = true; |
b67f4487 | 557 | break; |
b67f4487 | 558 | case SND_SOC_DAIFMT_NB_IF: |
f68205a7 | 559 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 560 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 561 | fs_pol_rising = false; |
b67f4487 | 562 | break; |
b67f4487 | 563 | case SND_SOC_DAIFMT_IB_IF: |
f68205a7 | 564 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
74ddd8c4 | 565 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 566 | fs_pol_rising = false; |
b67f4487 | 567 | break; |
b67f4487 | 568 | case SND_SOC_DAIFMT_NB_NF: |
f68205a7 | 569 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); |
f68205a7 | 570 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); |
83f12503 | 571 | fs_pol_rising = true; |
b67f4487 | 572 | break; |
b67f4487 | 573 | default: |
1d17a04e | 574 | ret = -EINVAL; |
83f12503 PU |
575 | goto out; |
576 | } | |
577 | ||
ffd950f7 PU |
578 | if (inv_fs) |
579 | fs_pol_rising = !fs_pol_rising; | |
580 | ||
83f12503 PU |
581 | if (fs_pol_rising) { |
582 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
583 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
584 | } else { | |
585 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); | |
586 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); | |
b67f4487 | 587 | } |
4a11ff26 PU |
588 | |
589 | mcasp->dai_fmt = fmt; | |
1d17a04e | 590 | out: |
6afda7f5 | 591 | pm_runtime_put(mcasp->dev); |
1d17a04e | 592 | return ret; |
b67f4487 C |
593 | } |
594 | ||
226e73e2 | 595 | static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, |
8813543e | 596 | int div, bool explicit) |
4ed8c9b7 | 597 | { |
6afda7f5 | 598 | pm_runtime_get_sync(mcasp->dev); |
4ed8c9b7 | 599 | switch (div_id) { |
20d4b107 | 600 | case MCASP_CLKDIV_AUXCLK: /* MCLK divider */ |
f68205a7 | 601 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, |
4ed8c9b7 | 602 | AHCLKXDIV(div - 1), AHCLKXDIV_MASK); |
f68205a7 | 603 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, |
4ed8c9b7 DM |
604 | AHCLKRDIV(div - 1), AHCLKRDIV_MASK); |
605 | break; | |
606 | ||
20d4b107 | 607 | case MCASP_CLKDIV_BCLK: /* BCLK divider */ |
f68205a7 | 608 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, |
4ed8c9b7 | 609 | ACLKXDIV(div - 1), ACLKXDIV_MASK); |
f68205a7 | 610 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, |
4ed8c9b7 | 611 | ACLKRDIV(div - 1), ACLKRDIV_MASK); |
8813543e JS |
612 | if (explicit) |
613 | mcasp->bclk_div = div; | |
4ed8c9b7 DM |
614 | break; |
615 | ||
20d4b107 PU |
616 | case MCASP_CLKDIV_BCLK_FS_RATIO: |
617 | /* | |
14a998be JS |
618 | * BCLK/LRCLK ratio descries how many bit-clock cycles |
619 | * fit into one frame. The clock ratio is given for a | |
620 | * full period of data (for I2S format both left and | |
621 | * right channels), so it has to be divided by number | |
622 | * of tdm-slots (for I2S - divided by 2). | |
623 | * Instead of storing this ratio, we calculate a new | |
624 | * tdm_slot width by dividing the the ratio by the | |
625 | * number of configured tdm slots. | |
626 | */ | |
627 | mcasp->slot_width = div / mcasp->tdm_slots; | |
628 | if (div % mcasp->tdm_slots) | |
629 | dev_warn(mcasp->dev, | |
630 | "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots", | |
631 | __func__, div, mcasp->tdm_slots); | |
1b3bc060 DM |
632 | break; |
633 | ||
4ed8c9b7 DM |
634 | default: |
635 | return -EINVAL; | |
636 | } | |
637 | ||
6afda7f5 | 638 | pm_runtime_put(mcasp->dev); |
4ed8c9b7 DM |
639 | return 0; |
640 | } | |
641 | ||
8813543e JS |
642 | static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, |
643 | int div) | |
644 | { | |
226e73e2 PU |
645 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
646 | ||
647 | return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); | |
8813543e JS |
648 | } |
649 | ||
5b66aa2d DM |
650 | static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
651 | unsigned int freq, int dir) | |
652 | { | |
70091a3e | 653 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); |
5b66aa2d | 654 | |
6afda7f5 | 655 | pm_runtime_get_sync(mcasp->dev); |
5b66aa2d | 656 | if (dir == SND_SOC_CLOCK_OUT) { |
f68205a7 PU |
657 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
658 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
ca3d9433 | 659 | set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); |
5b66aa2d | 660 | } else { |
f68205a7 PU |
661 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); |
662 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); | |
ca3d9433 | 663 | clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); |
5b66aa2d DM |
664 | } |
665 | ||
ab8b14b6 JS |
666 | mcasp->sysclk_freq = freq; |
667 | ||
6afda7f5 | 668 | pm_runtime_put(mcasp->dev); |
5b66aa2d DM |
669 | return 0; |
670 | } | |
671 | ||
dd55ff83 JS |
672 | /* All serializers must have equal number of channels */ |
673 | static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, | |
674 | int serializers) | |
675 | { | |
676 | struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; | |
677 | unsigned int *list = (unsigned int *) cl->list; | |
678 | int slots = mcasp->tdm_slots; | |
679 | int i, count = 0; | |
680 | ||
681 | if (mcasp->tdm_mask[stream]) | |
682 | slots = hweight32(mcasp->tdm_mask[stream]); | |
683 | ||
e4798d26 | 684 | for (i = 1; i <= slots; i++) |
dd55ff83 JS |
685 | list[count++] = i; |
686 | ||
687 | for (i = 2; i <= serializers; i++) | |
688 | list[count++] = i*slots; | |
689 | ||
690 | cl->count = count; | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
695 | static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) | |
696 | { | |
697 | int rx_serializers = 0, tx_serializers = 0, ret, i; | |
698 | ||
699 | for (i = 0; i < mcasp->num_serializer; i++) | |
700 | if (mcasp->serial_dir[i] == TX_MODE) | |
701 | tx_serializers++; | |
702 | else if (mcasp->serial_dir[i] == RX_MODE) | |
703 | rx_serializers++; | |
704 | ||
705 | ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, | |
706 | tx_serializers); | |
707 | if (ret) | |
708 | return ret; | |
709 | ||
710 | ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, | |
711 | rx_serializers); | |
712 | ||
713 | return ret; | |
714 | } | |
715 | ||
716 | ||
717 | static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, | |
718 | unsigned int tx_mask, | |
719 | unsigned int rx_mask, | |
720 | int slots, int slot_width) | |
721 | { | |
722 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
723 | ||
724 | dev_dbg(mcasp->dev, | |
725 | "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", | |
726 | __func__, tx_mask, rx_mask, slots, slot_width); | |
727 | ||
728 | if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { | |
729 | dev_err(mcasp->dev, | |
730 | "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", | |
731 | tx_mask, rx_mask, slots); | |
732 | return -EINVAL; | |
733 | } | |
734 | ||
735 | if (slot_width && | |
736 | (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { | |
737 | dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", | |
738 | __func__, slot_width); | |
739 | return -EINVAL; | |
740 | } | |
741 | ||
742 | mcasp->tdm_slots = slots; | |
1bdd5932 AD |
743 | mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; |
744 | mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; | |
dd55ff83 JS |
745 | mcasp->slot_width = slot_width; |
746 | ||
747 | return davinci_mcasp_set_ch_constraints(mcasp); | |
748 | } | |
749 | ||
70091a3e | 750 | static int davinci_config_channel_size(struct davinci_mcasp *mcasp, |
14a998be | 751 | int sample_width) |
b67f4487 | 752 | { |
ba764b3d | 753 | u32 fmt; |
14a998be JS |
754 | u32 tx_rotate = (sample_width / 4) & 0x7; |
755 | u32 mask = (1ULL << sample_width) - 1; | |
756 | u32 slot_width = sample_width; | |
757 | ||
fe0a29e1 PU |
758 | /* |
759 | * For captured data we should not rotate, inversion and masking is | |
760 | * enoguh to get the data to the right position: | |
761 | * Format data from bus after reverse (XRBUF) | |
762 | * S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB| | |
763 | * S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
764 | * S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB| | |
765 | * S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB| | |
766 | */ | |
767 | u32 rx_rotate = 0; | |
b67f4487 | 768 | |
1b3bc060 | 769 | /* |
14a998be JS |
770 | * Setting the tdm slot width either with set_clkdiv() or |
771 | * set_tdm_slot() allows us to for example send 32 bits per | |
772 | * channel to the codec, while only 16 of them carry audio | |
773 | * payload. | |
1b3bc060 | 774 | */ |
14a998be | 775 | if (mcasp->slot_width) { |
d742b925 | 776 | /* |
14a998be JS |
777 | * When we have more bclk then it is needed for the |
778 | * data, we need to use the rotation to move the | |
779 | * received samples to have correct alignment. | |
d742b925 | 780 | */ |
14a998be JS |
781 | slot_width = mcasp->slot_width; |
782 | rx_rotate = (slot_width - sample_width) / 4; | |
d742b925 | 783 | } |
1b3bc060 | 784 | |
ba764b3d | 785 | /* mapping of the XSSZ bit-field as described in the datasheet */ |
14a998be | 786 | fmt = (slot_width >> 1) - 1; |
b67f4487 | 787 | |
70091a3e | 788 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { |
f68205a7 PU |
789 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), |
790 | RXSSZ(0x0F)); | |
791 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), | |
792 | TXSSZ(0x0F)); | |
793 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), | |
794 | TXROT(7)); | |
795 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), | |
796 | RXROT(7)); | |
797 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); | |
f5023af6 YY |
798 | } |
799 | ||
f68205a7 | 800 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); |
0c31cf3e | 801 | |
b67f4487 C |
802 | return 0; |
803 | } | |
804 | ||
662ffae9 | 805 | static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, |
dd093a0f | 806 | int period_words, int channels) |
b67f4487 | 807 | { |
5f04c603 | 808 | struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; |
b67f4487 | 809 | int i; |
6a99fb5f C |
810 | u8 tx_ser = 0; |
811 | u8 rx_ser = 0; | |
70091a3e | 812 | u8 slots = mcasp->tdm_slots; |
2952b27e | 813 | u8 max_active_serializers = (channels + slots - 1) / slots; |
72383192 | 814 | int active_serializers, numevt; |
487dce88 | 815 | u32 reg; |
b67f4487 | 816 | /* Default configuration */ |
40448e5e | 817 | if (mcasp->version < MCASP_VERSION_3) |
f68205a7 | 818 | mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); |
b67f4487 C |
819 | |
820 | /* All PINS as McASP */ | |
f68205a7 | 821 | mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); |
b67f4487 C |
822 | |
823 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
f68205a7 PU |
824 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); |
825 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); | |
b67f4487 | 826 | } else { |
f68205a7 PU |
827 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); |
828 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); | |
b67f4487 C |
829 | } |
830 | ||
70091a3e | 831 | for (i = 0; i < mcasp->num_serializer; i++) { |
f68205a7 PU |
832 | mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
833 | mcasp->serial_dir[i]); | |
70091a3e | 834 | if (mcasp->serial_dir[i] == TX_MODE && |
2952b27e | 835 | tx_ser < max_active_serializers) { |
19db62ea MLC |
836 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
837 | DISMOD_LOW, DISMOD_MASK); | |
ca3d9433 | 838 | set_bit(PIN_BIT_AXR(i), &mcasp->pdir); |
6a99fb5f | 839 | tx_ser++; |
70091a3e | 840 | } else if (mcasp->serial_dir[i] == RX_MODE && |
2952b27e | 841 | rx_ser < max_active_serializers) { |
ca3d9433 | 842 | clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); |
6a99fb5f | 843 | rx_ser++; |
096a8f83 | 844 | } else if (mcasp->serial_dir[i] == INACTIVE_MODE) { |
f68205a7 PU |
845 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), |
846 | SRMOD_INACTIVE, SRMOD_MASK); | |
ca3d9433 PU |
847 | clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); |
848 | } else if (mcasp->serial_dir[i] == TX_MODE) { | |
849 | /* Unused TX pins, clear PDIR */ | |
850 | clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); | |
6a99fb5f C |
851 | } |
852 | } | |
853 | ||
0bf0e8ae PU |
854 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
855 | active_serializers = tx_ser; | |
856 | numevt = mcasp->txnumevt; | |
857 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
858 | } else { | |
859 | active_serializers = rx_ser; | |
860 | numevt = mcasp->rxnumevt; | |
861 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
862 | } | |
ecf327c7 | 863 | |
0bf0e8ae | 864 | if (active_serializers < max_active_serializers) { |
70091a3e | 865 | dev_warn(mcasp->dev, "stream has more channels (%d) than are " |
0bf0e8ae PU |
866 | "enabled in mcasp (%d)\n", channels, |
867 | active_serializers * slots); | |
ecf327c7 DM |
868 | return -EINVAL; |
869 | } | |
870 | ||
0bf0e8ae | 871 | /* AFIFO is not in use */ |
5f04c603 PU |
872 | if (!numevt) { |
873 | /* Configure the burst size for platform drivers */ | |
33445643 PU |
874 | if (active_serializers > 1) { |
875 | /* | |
876 | * If more than one serializers are in use we have one | |
877 | * DMA request to provide data for all serializers. | |
878 | * For example if three serializers are enabled the DMA | |
879 | * need to transfer three words per DMA request. | |
880 | */ | |
33445643 PU |
881 | dma_data->maxburst = active_serializers; |
882 | } else { | |
33445643 PU |
883 | dma_data->maxburst = 0; |
884 | } | |
0bf0e8ae | 885 | return 0; |
5f04c603 | 886 | } |
6a99fb5f | 887 | |
dd093a0f PU |
888 | if (period_words % active_serializers) { |
889 | dev_err(mcasp->dev, "Invalid combination of period words and " | |
890 | "active serializers: %d, %d\n", period_words, | |
891 | active_serializers); | |
892 | return -EINVAL; | |
893 | } | |
894 | ||
895 | /* | |
896 | * Calculate the optimal AFIFO depth for platform side: | |
897 | * The number of words for numevt need to be in steps of active | |
898 | * serializers. | |
899 | */ | |
72383192 PU |
900 | numevt = (numevt / active_serializers) * active_serializers; |
901 | ||
dd093a0f PU |
902 | while (period_words % numevt && numevt > 0) |
903 | numevt -= active_serializers; | |
904 | if (numevt <= 0) | |
0bf0e8ae | 905 | numevt = active_serializers; |
487dce88 | 906 | |
0bf0e8ae PU |
907 | mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); |
908 | mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); | |
2952b27e | 909 | |
5f04c603 | 910 | /* Configure the burst size for platform drivers */ |
33445643 PU |
911 | if (numevt == 1) |
912 | numevt = 0; | |
5f04c603 PU |
913 | dma_data->maxburst = numevt; |
914 | ||
2952b27e | 915 | return 0; |
b67f4487 C |
916 | } |
917 | ||
18a4f557 MLC |
918 | static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, |
919 | int channels) | |
b67f4487 C |
920 | { |
921 | int i, active_slots; | |
18a4f557 MLC |
922 | int total_slots; |
923 | int active_serializers; | |
b67f4487 | 924 | u32 mask = 0; |
cbc7956c | 925 | u32 busel = 0; |
b67f4487 | 926 | |
18a4f557 MLC |
927 | total_slots = mcasp->tdm_slots; |
928 | ||
929 | /* | |
930 | * If more than one serializer is needed, then use them with | |
dd55ff83 JS |
931 | * all the specified tdm_slots. Otherwise, one serializer can |
932 | * cope with the transaction using just as many slots as there | |
933 | * are channels in the stream. | |
18a4f557 | 934 | */ |
dd55ff83 JS |
935 | if (mcasp->tdm_mask[stream]) { |
936 | active_slots = hweight32(mcasp->tdm_mask[stream]); | |
937 | active_serializers = (channels + active_slots - 1) / | |
938 | active_slots; | |
939 | if (active_serializers == 1) { | |
940 | active_slots = channels; | |
941 | for (i = 0; i < total_slots; i++) { | |
942 | if ((1 << i) & mcasp->tdm_mask[stream]) { | |
943 | mask |= (1 << i); | |
944 | if (--active_slots <= 0) | |
945 | break; | |
946 | } | |
947 | } | |
948 | } | |
949 | } else { | |
950 | active_serializers = (channels + total_slots - 1) / total_slots; | |
951 | if (active_serializers == 1) | |
952 | active_slots = channels; | |
953 | else | |
954 | active_slots = total_slots; | |
b67f4487 | 955 | |
dd55ff83 JS |
956 | for (i = 0; i < active_slots; i++) |
957 | mask |= (1 << i); | |
958 | } | |
f68205a7 | 959 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); |
6a99fb5f | 960 | |
cbc7956c PU |
961 | if (!mcasp->dat_port) |
962 | busel = TXSEL; | |
963 | ||
dd55ff83 JS |
964 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
965 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); | |
966 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); | |
967 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
968 | FSXMOD(total_slots), FSXMOD(0x1FF)); | |
969 | } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { | |
970 | mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); | |
971 | mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); | |
972 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, | |
973 | FSRMOD(total_slots), FSRMOD(0x1FF)); | |
0ad7d3a0 PU |
974 | /* |
975 | * If McASP is set to be TX/RX synchronous and the playback is | |
976 | * not running already we need to configure the TX slots in | |
977 | * order to have correct FSX on the bus | |
978 | */ | |
979 | if (mcasp_is_synchronous(mcasp) && !mcasp->channels) | |
980 | mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, | |
981 | FSXMOD(total_slots), FSXMOD(0x1FF)); | |
dd55ff83 | 982 | } |
2c56c4c2 PU |
983 | |
984 | return 0; | |
b67f4487 C |
985 | } |
986 | ||
987 | /* S/PDIF */ | |
6479285d DM |
988 | static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, |
989 | unsigned int rate) | |
b67f4487 | 990 | { |
6479285d DM |
991 | u32 cs_value = 0; |
992 | u8 *cs_bytes = (u8*) &cs_value; | |
993 | ||
b67f4487 C |
994 | /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 |
995 | and LSB first */ | |
f68205a7 | 996 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15)); |
b67f4487 C |
997 | |
998 | /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ | |
f68205a7 | 999 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); |
b67f4487 C |
1000 | |
1001 | /* Set the TX tdm : for all the slots */ | |
f68205a7 | 1002 | mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); |
b67f4487 C |
1003 | |
1004 | /* Set the TX clock controls : div = 1 and internal */ | |
f68205a7 | 1005 | mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); |
b67f4487 | 1006 | |
f68205a7 | 1007 | mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); |
b67f4487 C |
1008 | |
1009 | /* Only 44100 and 48000 are valid, both have the same setting */ | |
f68205a7 | 1010 | mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); |
b67f4487 C |
1011 | |
1012 | /* Enable the DIT */ | |
f68205a7 | 1013 | mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); |
2c56c4c2 | 1014 | |
6479285d DM |
1015 | /* Set S/PDIF channel status bits */ |
1016 | cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT; | |
1017 | cs_bytes[1] = IEC958_AES1_CON_PCM_CODER; | |
1018 | ||
1019 | switch (rate) { | |
1020 | case 22050: | |
1021 | cs_bytes[3] |= IEC958_AES3_CON_FS_22050; | |
1022 | break; | |
1023 | case 24000: | |
1024 | cs_bytes[3] |= IEC958_AES3_CON_FS_24000; | |
1025 | break; | |
1026 | case 32000: | |
1027 | cs_bytes[3] |= IEC958_AES3_CON_FS_32000; | |
1028 | break; | |
1029 | case 44100: | |
1030 | cs_bytes[3] |= IEC958_AES3_CON_FS_44100; | |
1031 | break; | |
1032 | case 48000: | |
1033 | cs_bytes[3] |= IEC958_AES3_CON_FS_48000; | |
1034 | break; | |
1035 | case 88200: | |
1036 | cs_bytes[3] |= IEC958_AES3_CON_FS_88200; | |
1037 | break; | |
1038 | case 96000: | |
1039 | cs_bytes[3] |= IEC958_AES3_CON_FS_96000; | |
1040 | break; | |
1041 | case 176400: | |
1042 | cs_bytes[3] |= IEC958_AES3_CON_FS_176400; | |
1043 | break; | |
1044 | case 192000: | |
1045 | cs_bytes[3] |= IEC958_AES3_CON_FS_192000; | |
1046 | break; | |
1047 | default: | |
1048 | printk(KERN_WARNING "unsupported sampling rate: %d\n", rate); | |
1049 | return -EINVAL; | |
1050 | } | |
1051 | ||
1052 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value); | |
1053 | mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value); | |
1054 | ||
2c56c4c2 | 1055 | return 0; |
b67f4487 C |
1056 | } |
1057 | ||
a75a053f | 1058 | static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, |
3e9bee11 | 1059 | unsigned int bclk_freq, bool set) |
a75a053f | 1060 | { |
3e9bee11 | 1061 | int error_ppm; |
ddecd149 PU |
1062 | unsigned int sysclk_freq = mcasp->sysclk_freq; |
1063 | u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG); | |
1064 | int div = sysclk_freq / bclk_freq; | |
1065 | int rem = sysclk_freq % bclk_freq; | |
1066 | int aux_div = 1; | |
1067 | ||
1068 | if (div > (ACLKXDIV_MASK + 1)) { | |
1069 | if (reg & AHCLKXE) { | |
1070 | aux_div = div / (ACLKXDIV_MASK + 1); | |
1071 | if (div % (ACLKXDIV_MASK + 1)) | |
1072 | aux_div++; | |
1073 | ||
1074 | sysclk_freq /= aux_div; | |
1075 | div = sysclk_freq / bclk_freq; | |
1076 | rem = sysclk_freq % bclk_freq; | |
1077 | } else if (set) { | |
1078 | dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", | |
1079 | sysclk_freq); | |
1080 | } | |
1081 | } | |
a75a053f JS |
1082 | |
1083 | if (rem != 0) { | |
1084 | if (div == 0 || | |
ddecd149 PU |
1085 | ((sysclk_freq / div) - bclk_freq) > |
1086 | (bclk_freq - (sysclk_freq / (div+1)))) { | |
a75a053f JS |
1087 | div++; |
1088 | rem = rem - bclk_freq; | |
1089 | } | |
1090 | } | |
3e9bee11 PU |
1091 | error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem, |
1092 | (int)bclk_freq)) / div - 1000000; | |
a75a053f | 1093 | |
3e9bee11 PU |
1094 | if (set) { |
1095 | if (error_ppm) | |
1096 | dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", | |
1097 | error_ppm); | |
1098 | ||
1099 | __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0); | |
ddecd149 PU |
1100 | if (reg & AHCLKXE) |
1101 | __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK, | |
1102 | aux_div, 0); | |
3e9bee11 | 1103 | } |
a75a053f | 1104 | |
3e9bee11 | 1105 | return error_ppm; |
a75a053f JS |
1106 | } |
1107 | ||
5fcb457a PU |
1108 | static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) |
1109 | { | |
1110 | if (!mcasp->txnumevt) | |
1111 | return 0; | |
1112 | ||
1113 | return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); | |
1114 | } | |
1115 | ||
1116 | static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) | |
1117 | { | |
1118 | if (!mcasp->rxnumevt) | |
1119 | return 0; | |
1120 | ||
1121 | return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); | |
1122 | } | |
1123 | ||
1124 | static snd_pcm_sframes_t davinci_mcasp_delay( | |
1125 | struct snd_pcm_substream *substream, | |
1126 | struct snd_soc_dai *cpu_dai) | |
1127 | { | |
1128 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
1129 | u32 fifo_use; | |
1130 | ||
1131 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1132 | fifo_use = davinci_mcasp_tx_delay(mcasp); | |
1133 | else | |
1134 | fifo_use = davinci_mcasp_rx_delay(mcasp); | |
1135 | ||
1136 | /* | |
1137 | * Divide the used locations with the channel count to get the | |
1138 | * FIFO usage in samples (don't care about partial samples in the | |
1139 | * buffer). | |
1140 | */ | |
1141 | return fifo_use / substream->runtime->channels; | |
1142 | } | |
1143 | ||
b67f4487 C |
1144 | static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, |
1145 | struct snd_pcm_hw_params *params, | |
1146 | struct snd_soc_dai *cpu_dai) | |
1147 | { | |
70091a3e | 1148 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 | 1149 | int word_length; |
a7e46bd9 | 1150 | int channels = params_channels(params); |
dd093a0f | 1151 | int period_size = params_period_size(params); |
2c56c4c2 | 1152 | int ret; |
ab8b14b6 | 1153 | |
4a11ff26 PU |
1154 | ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); |
1155 | if (ret) | |
1156 | return ret; | |
1157 | ||
8267525c DM |
1158 | /* |
1159 | * If mcasp is BCLK master, and a BCLK divider was not provided by | |
1160 | * the machine driver, we need to calculate the ratio. | |
1161 | */ | |
1162 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
1f114f77 | 1163 | int slots = mcasp->tdm_slots; |
a75a053f JS |
1164 | int rate = params_rate(params); |
1165 | int sbits = params_width(params); | |
a75a053f | 1166 | |
dd55ff83 JS |
1167 | if (mcasp->slot_width) |
1168 | sbits = mcasp->slot_width; | |
1169 | ||
3e9bee11 | 1170 | davinci_mcasp_calc_clk_div(mcasp, rate * sbits * slots, true); |
ab8b14b6 JS |
1171 | } |
1172 | ||
dd093a0f PU |
1173 | ret = mcasp_common_hw_param(mcasp, substream->stream, |
1174 | period_size * channels, channels); | |
0f7d9a63 PU |
1175 | if (ret) |
1176 | return ret; | |
1177 | ||
70091a3e | 1178 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
6479285d | 1179 | ret = mcasp_dit_hw_param(mcasp, params_rate(params)); |
b67f4487 | 1180 | else |
18a4f557 MLC |
1181 | ret = mcasp_i2s_hw_param(mcasp, substream->stream, |
1182 | channels); | |
2c56c4c2 PU |
1183 | |
1184 | if (ret) | |
1185 | return ret; | |
b67f4487 C |
1186 | |
1187 | switch (params_format(params)) { | |
0a9d1385 | 1188 | case SNDRV_PCM_FORMAT_U8: |
b67f4487 | 1189 | case SNDRV_PCM_FORMAT_S8: |
ba764b3d | 1190 | word_length = 8; |
b67f4487 C |
1191 | break; |
1192 | ||
0a9d1385 | 1193 | case SNDRV_PCM_FORMAT_U16_LE: |
b67f4487 | 1194 | case SNDRV_PCM_FORMAT_S16_LE: |
ba764b3d | 1195 | word_length = 16; |
b67f4487 C |
1196 | break; |
1197 | ||
21eb24d8 DM |
1198 | case SNDRV_PCM_FORMAT_U24_3LE: |
1199 | case SNDRV_PCM_FORMAT_S24_3LE: | |
ba764b3d | 1200 | word_length = 24; |
21eb24d8 DM |
1201 | break; |
1202 | ||
6b7fa011 DM |
1203 | case SNDRV_PCM_FORMAT_U24_LE: |
1204 | case SNDRV_PCM_FORMAT_S24_LE: | |
182bef86 PU |
1205 | word_length = 24; |
1206 | break; | |
1207 | ||
0a9d1385 | 1208 | case SNDRV_PCM_FORMAT_U32_LE: |
b67f4487 | 1209 | case SNDRV_PCM_FORMAT_S32_LE: |
ba764b3d | 1210 | word_length = 32; |
b67f4487 C |
1211 | break; |
1212 | ||
1213 | default: | |
1214 | printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); | |
1215 | return -EINVAL; | |
1216 | } | |
6a99fb5f | 1217 | |
70091a3e | 1218 | davinci_config_channel_size(mcasp, word_length); |
b67f4487 | 1219 | |
11277833 PU |
1220 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) |
1221 | mcasp->channels = channels; | |
1222 | ||
b67f4487 C |
1223 | return 0; |
1224 | } | |
1225 | ||
1226 | static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, | |
1227 | int cmd, struct snd_soc_dai *cpu_dai) | |
1228 | { | |
70091a3e | 1229 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); |
b67f4487 C |
1230 | int ret = 0; |
1231 | ||
1232 | switch (cmd) { | |
b67f4487 | 1233 | case SNDRV_PCM_TRIGGER_RESUME: |
e473b847 C |
1234 | case SNDRV_PCM_TRIGGER_START: |
1235 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
70091a3e | 1236 | davinci_mcasp_start(mcasp, substream->stream); |
b67f4487 | 1237 | break; |
b67f4487 | 1238 | case SNDRV_PCM_TRIGGER_SUSPEND: |
a47979b5 | 1239 | case SNDRV_PCM_TRIGGER_STOP: |
b67f4487 | 1240 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
70091a3e | 1241 | davinci_mcasp_stop(mcasp, substream->stream); |
b67f4487 C |
1242 | break; |
1243 | ||
1244 | default: | |
1245 | ret = -EINVAL; | |
1246 | } | |
1247 | ||
1248 | return ret; | |
1249 | } | |
1250 | ||
a75a053f JS |
1251 | static const unsigned int davinci_mcasp_dai_rates[] = { |
1252 | 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, | |
1253 | 88200, 96000, 176400, 192000, | |
1254 | }; | |
1255 | ||
1256 | #define DAVINCI_MAX_RATE_ERROR_PPM 1000 | |
1257 | ||
1258 | static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, | |
1259 | struct snd_pcm_hw_rule *rule) | |
1260 | { | |
1261 | struct davinci_mcasp_ruledata *rd = rule->private; | |
1262 | struct snd_interval *ri = | |
1263 | hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); | |
1264 | int sbits = params_width(params); | |
1f114f77 | 1265 | int slots = rd->mcasp->tdm_slots; |
518f6bab JS |
1266 | struct snd_interval range; |
1267 | int i; | |
a75a053f | 1268 | |
dd55ff83 JS |
1269 | if (rd->mcasp->slot_width) |
1270 | sbits = rd->mcasp->slot_width; | |
1271 | ||
518f6bab JS |
1272 | snd_interval_any(&range); |
1273 | range.empty = 1; | |
a75a053f JS |
1274 | |
1275 | for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { | |
518f6bab | 1276 | if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { |
1f114f77 | 1277 | uint bclk_freq = sbits*slots* |
a75a053f JS |
1278 | davinci_mcasp_dai_rates[i]; |
1279 | int ppm; | |
1280 | ||
3e9bee11 PU |
1281 | ppm = davinci_mcasp_calc_clk_div(rd->mcasp, bclk_freq, |
1282 | false); | |
518f6bab JS |
1283 | if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { |
1284 | if (range.empty) { | |
1285 | range.min = davinci_mcasp_dai_rates[i]; | |
1286 | range.empty = 0; | |
1287 | } | |
1288 | range.max = davinci_mcasp_dai_rates[i]; | |
1289 | } | |
a75a053f JS |
1290 | } |
1291 | } | |
518f6bab | 1292 | |
a75a053f | 1293 | dev_dbg(rd->mcasp->dev, |
518f6bab JS |
1294 | "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", |
1295 | ri->min, ri->max, range.min, range.max, sbits, slots); | |
a75a053f | 1296 | |
518f6bab JS |
1297 | return snd_interval_refine(hw_param_interval(params, rule->var), |
1298 | &range); | |
a75a053f JS |
1299 | } |
1300 | ||
1301 | static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, | |
1302 | struct snd_pcm_hw_rule *rule) | |
1303 | { | |
1304 | struct davinci_mcasp_ruledata *rd = rule->private; | |
1305 | struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); | |
1306 | struct snd_mask nfmt; | |
1307 | int rate = params_rate(params); | |
1f114f77 | 1308 | int slots = rd->mcasp->tdm_slots; |
a75a053f JS |
1309 | int i, count = 0; |
1310 | ||
1311 | snd_mask_none(&nfmt); | |
1312 | ||
9be072a6 | 1313 | for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { |
a75a053f | 1314 | if (snd_mask_test(fmt, i)) { |
dd55ff83 | 1315 | uint sbits = snd_pcm_format_width(i); |
a75a053f JS |
1316 | int ppm; |
1317 | ||
dd55ff83 JS |
1318 | if (rd->mcasp->slot_width) |
1319 | sbits = rd->mcasp->slot_width; | |
1320 | ||
3e9bee11 PU |
1321 | ppm = davinci_mcasp_calc_clk_div(rd->mcasp, |
1322 | sbits * slots * rate, | |
1323 | false); | |
a75a053f JS |
1324 | if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { |
1325 | snd_mask_set(&nfmt, i); | |
1326 | count++; | |
1327 | } | |
1328 | } | |
1329 | } | |
1330 | dev_dbg(rd->mcasp->dev, | |
1f114f77 JS |
1331 | "%d possible sample format for %d Hz and %d tdm slots\n", |
1332 | count, rate, slots); | |
a75a053f JS |
1333 | |
1334 | return snd_mask_refine(fmt, &nfmt); | |
1335 | } | |
1336 | ||
d43c17da PU |
1337 | static int davinci_mcasp_hw_rule_min_periodsize( |
1338 | struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) | |
1339 | { | |
1340 | struct snd_interval *period_size = hw_param_interval(params, | |
1341 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE); | |
1342 | struct snd_interval frames; | |
1343 | ||
1344 | snd_interval_any(&frames); | |
1345 | frames.min = 64; | |
1346 | frames.integer = 1; | |
1347 | ||
1348 | return snd_interval_refine(period_size, &frames); | |
1349 | } | |
1350 | ||
11277833 PU |
1351 | static int davinci_mcasp_startup(struct snd_pcm_substream *substream, |
1352 | struct snd_soc_dai *cpu_dai) | |
1353 | { | |
1354 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
4cd9db08 PU |
1355 | struct davinci_mcasp_ruledata *ruledata = |
1356 | &mcasp->ruledata[substream->stream]; | |
11277833 PU |
1357 | u32 max_channels = 0; |
1358 | int i, dir; | |
dd55ff83 JS |
1359 | int tdm_slots = mcasp->tdm_slots; |
1360 | ||
19357366 PU |
1361 | /* Do not allow more then one stream per direction */ |
1362 | if (mcasp->substreams[substream->stream]) | |
1363 | return -EBUSY; | |
11277833 | 1364 | |
a7a3324a MLC |
1365 | mcasp->substreams[substream->stream] = substream; |
1366 | ||
19357366 PU |
1367 | if (mcasp->tdm_mask[substream->stream]) |
1368 | tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); | |
1369 | ||
11277833 PU |
1370 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
1371 | return 0; | |
1372 | ||
1373 | /* | |
1374 | * Limit the maximum allowed channels for the first stream: | |
1375 | * number of serializers for the direction * tdm slots per serializer | |
1376 | */ | |
1377 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1378 | dir = TX_MODE; | |
1379 | else | |
1380 | dir = RX_MODE; | |
1381 | ||
1382 | for (i = 0; i < mcasp->num_serializer; i++) { | |
1383 | if (mcasp->serial_dir[i] == dir) | |
1384 | max_channels++; | |
1385 | } | |
4cd9db08 | 1386 | ruledata->serializers = max_channels; |
dd55ff83 | 1387 | max_channels *= tdm_slots; |
11277833 PU |
1388 | /* |
1389 | * If the already active stream has less channels than the calculated | |
1390 | * limnit based on the seirializers * tdm_slots, we need to use that as | |
1391 | * a constraint for the second stream. | |
1392 | * Otherwise (first stream or less allowed channels) we use the | |
1393 | * calculated constraint. | |
1394 | */ | |
1395 | if (mcasp->channels && mcasp->channels < max_channels) | |
1396 | max_channels = mcasp->channels; | |
dd55ff83 JS |
1397 | /* |
1398 | * But we can always allow channels upto the amount of | |
1399 | * the available tdm_slots. | |
1400 | */ | |
1401 | if (max_channels < tdm_slots) | |
1402 | max_channels = tdm_slots; | |
11277833 PU |
1403 | |
1404 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1405 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
e4798d26 | 1406 | 0, max_channels); |
a75a053f | 1407 | |
dd55ff83 JS |
1408 | snd_pcm_hw_constraint_list(substream->runtime, |
1409 | 0, SNDRV_PCM_HW_PARAM_CHANNELS, | |
1410 | &mcasp->chconstr[substream->stream]); | |
1411 | ||
1412 | if (mcasp->slot_width) | |
1413 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1414 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
1415 | 8, mcasp->slot_width); | |
5935a056 | 1416 | |
a75a053f JS |
1417 | /* |
1418 | * If we rely on implicit BCLK divider setting we should | |
1419 | * set constraints based on what we can provide. | |
1420 | */ | |
1421 | if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) { | |
1422 | int ret; | |
1423 | ||
4cd9db08 | 1424 | ruledata->mcasp = mcasp; |
a75a053f JS |
1425 | |
1426 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, | |
1427 | SNDRV_PCM_HW_PARAM_RATE, | |
1428 | davinci_mcasp_hw_rule_rate, | |
4cd9db08 | 1429 | ruledata, |
1f114f77 | 1430 | SNDRV_PCM_HW_PARAM_FORMAT, -1); |
a75a053f JS |
1431 | if (ret) |
1432 | return ret; | |
1433 | ret = snd_pcm_hw_rule_add(substream->runtime, 0, | |
1434 | SNDRV_PCM_HW_PARAM_FORMAT, | |
1435 | davinci_mcasp_hw_rule_format, | |
4cd9db08 | 1436 | ruledata, |
1f114f77 | 1437 | SNDRV_PCM_HW_PARAM_RATE, -1); |
a75a053f JS |
1438 | if (ret) |
1439 | return ret; | |
1440 | } | |
1441 | ||
d43c17da PU |
1442 | snd_pcm_hw_rule_add(substream->runtime, 0, |
1443 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, | |
1444 | davinci_mcasp_hw_rule_min_periodsize, NULL, | |
1445 | SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); | |
1446 | ||
11277833 PU |
1447 | return 0; |
1448 | } | |
1449 | ||
1450 | static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, | |
1451 | struct snd_soc_dai *cpu_dai) | |
1452 | { | |
1453 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); | |
1454 | ||
a7a3324a MLC |
1455 | mcasp->substreams[substream->stream] = NULL; |
1456 | ||
11277833 PU |
1457 | if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) |
1458 | return; | |
1459 | ||
1460 | if (!cpu_dai->active) | |
1461 | mcasp->channels = 0; | |
1462 | } | |
1463 | ||
85e7652d | 1464 | static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { |
11277833 PU |
1465 | .startup = davinci_mcasp_startup, |
1466 | .shutdown = davinci_mcasp_shutdown, | |
b67f4487 | 1467 | .trigger = davinci_mcasp_trigger, |
5fcb457a | 1468 | .delay = davinci_mcasp_delay, |
b67f4487 C |
1469 | .hw_params = davinci_mcasp_hw_params, |
1470 | .set_fmt = davinci_mcasp_set_dai_fmt, | |
4ed8c9b7 | 1471 | .set_clkdiv = davinci_mcasp_set_clkdiv, |
5b66aa2d | 1472 | .set_sysclk = davinci_mcasp_set_sysclk, |
dd55ff83 | 1473 | .set_tdm_slot = davinci_mcasp_set_tdm_slot, |
b67f4487 C |
1474 | }; |
1475 | ||
d5902f69 PU |
1476 | static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) |
1477 | { | |
1478 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
1479 | ||
9759e7ef PU |
1480 | dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
1481 | dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; | |
d5902f69 PU |
1482 | |
1483 | return 0; | |
1484 | } | |
1485 | ||
135014ad PU |
1486 | #ifdef CONFIG_PM_SLEEP |
1487 | static int davinci_mcasp_suspend(struct snd_soc_dai *dai) | |
1488 | { | |
1489 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 1490 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 1491 | u32 reg; |
1cc0c054 | 1492 | int i; |
135014ad | 1493 | |
27796e75 | 1494 | context->pm_state = pm_runtime_active(mcasp->dev); |
6afda7f5 PU |
1495 | if (!context->pm_state) |
1496 | pm_runtime_get_sync(mcasp->dev); | |
1497 | ||
1cc0c054 PU |
1498 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
1499 | context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); | |
135014ad | 1500 | |
f114ce60 PU |
1501 | if (mcasp->txnumevt) { |
1502 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
1503 | context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); | |
1504 | } | |
1505 | if (mcasp->rxnumevt) { | |
1506 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
1507 | context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); | |
1508 | } | |
135014ad | 1509 | |
f114ce60 PU |
1510 | for (i = 0; i < mcasp->num_serializer; i++) |
1511 | context->xrsr_regs[i] = mcasp_get_reg(mcasp, | |
1512 | DAVINCI_MCASP_XRSRCTL_REG(i)); | |
135014ad | 1513 | |
6afda7f5 PU |
1514 | pm_runtime_put_sync(mcasp->dev); |
1515 | ||
135014ad PU |
1516 | return 0; |
1517 | } | |
1518 | ||
1519 | static int davinci_mcasp_resume(struct snd_soc_dai *dai) | |
1520 | { | |
1521 | struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); | |
790bb94b | 1522 | struct davinci_mcasp_context *context = &mcasp->context; |
f114ce60 | 1523 | u32 reg; |
1cc0c054 | 1524 | int i; |
790bb94b | 1525 | |
6afda7f5 PU |
1526 | pm_runtime_get_sync(mcasp->dev); |
1527 | ||
1cc0c054 PU |
1528 | for (i = 0; i < ARRAY_SIZE(context_regs); i++) |
1529 | mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); | |
135014ad | 1530 | |
f114ce60 PU |
1531 | if (mcasp->txnumevt) { |
1532 | reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; | |
1533 | mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); | |
1534 | } | |
1535 | if (mcasp->rxnumevt) { | |
1536 | reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; | |
1537 | mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); | |
1538 | } | |
790bb94b | 1539 | |
f114ce60 PU |
1540 | for (i = 0; i < mcasp->num_serializer; i++) |
1541 | mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), | |
1542 | context->xrsr_regs[i]); | |
135014ad | 1543 | |
6afda7f5 PU |
1544 | if (!context->pm_state) |
1545 | pm_runtime_put_sync(mcasp->dev); | |
1546 | ||
135014ad PU |
1547 | return 0; |
1548 | } | |
1549 | #else | |
1550 | #define davinci_mcasp_suspend NULL | |
1551 | #define davinci_mcasp_resume NULL | |
1552 | #endif | |
1553 | ||
ed29cd5e PU |
1554 | #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 |
1555 | ||
0a9d1385 BG |
1556 | #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ |
1557 | SNDRV_PCM_FMTBIT_U8 | \ | |
1558 | SNDRV_PCM_FMTBIT_S16_LE | \ | |
1559 | SNDRV_PCM_FMTBIT_U16_LE | \ | |
21eb24d8 DM |
1560 | SNDRV_PCM_FMTBIT_S24_LE | \ |
1561 | SNDRV_PCM_FMTBIT_U24_LE | \ | |
1562 | SNDRV_PCM_FMTBIT_S24_3LE | \ | |
1563 | SNDRV_PCM_FMTBIT_U24_3LE | \ | |
0a9d1385 BG |
1564 | SNDRV_PCM_FMTBIT_S32_LE | \ |
1565 | SNDRV_PCM_FMTBIT_U32_LE) | |
1566 | ||
f0fba2ad | 1567 | static struct snd_soc_dai_driver davinci_mcasp_dai[] = { |
b67f4487 | 1568 | { |
f0fba2ad | 1569 | .name = "davinci-mcasp.0", |
d5902f69 | 1570 | .probe = davinci_mcasp_dai_probe, |
135014ad PU |
1571 | .suspend = davinci_mcasp_suspend, |
1572 | .resume = davinci_mcasp_resume, | |
b67f4487 | 1573 | .playback = { |
e4798d26 | 1574 | .channels_min = 1, |
2952b27e | 1575 | .channels_max = 32 * 16, |
b67f4487 | 1576 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 1577 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1578 | }, |
1579 | .capture = { | |
e4798d26 | 1580 | .channels_min = 1, |
2952b27e | 1581 | .channels_max = 32 * 16, |
b67f4487 | 1582 | .rates = DAVINCI_MCASP_RATES, |
0a9d1385 | 1583 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1584 | }, |
1585 | .ops = &davinci_mcasp_dai_ops, | |
1586 | ||
d75249f5 | 1587 | .symmetric_samplebits = 1, |
295c3405 | 1588 | .symmetric_rates = 1, |
b67f4487 C |
1589 | }, |
1590 | { | |
58e48d97 | 1591 | .name = "davinci-mcasp.1", |
d5902f69 | 1592 | .probe = davinci_mcasp_dai_probe, |
b67f4487 C |
1593 | .playback = { |
1594 | .channels_min = 1, | |
1595 | .channels_max = 384, | |
1596 | .rates = DAVINCI_MCASP_RATES, | |
0a9d1385 | 1597 | .formats = DAVINCI_MCASP_PCM_FMTS, |
b67f4487 C |
1598 | }, |
1599 | .ops = &davinci_mcasp_dai_ops, | |
1600 | }, | |
1601 | ||
1602 | }; | |
b67f4487 | 1603 | |
eeef0eda KM |
1604 | static const struct snd_soc_component_driver davinci_mcasp_component = { |
1605 | .name = "davinci-mcasp", | |
1606 | }; | |
1607 | ||
256ba181 | 1608 | /* Some HW specific values and defaults. The rest is filled in from DT. */ |
d1debafc | 1609 | static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { |
256ba181 JS |
1610 | .tx_dma_offset = 0x400, |
1611 | .rx_dma_offset = 0x400, | |
256ba181 JS |
1612 | .version = MCASP_VERSION_1, |
1613 | }; | |
1614 | ||
d1debafc | 1615 | static struct davinci_mcasp_pdata da830_mcasp_pdata = { |
256ba181 JS |
1616 | .tx_dma_offset = 0x2000, |
1617 | .rx_dma_offset = 0x2000, | |
256ba181 JS |
1618 | .version = MCASP_VERSION_2, |
1619 | }; | |
1620 | ||
d1debafc | 1621 | static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { |
256ba181 JS |
1622 | .tx_dma_offset = 0, |
1623 | .rx_dma_offset = 0, | |
256ba181 JS |
1624 | .version = MCASP_VERSION_3, |
1625 | }; | |
1626 | ||
d1debafc | 1627 | static struct davinci_mcasp_pdata dra7_mcasp_pdata = { |
9ac0013c PU |
1628 | /* The CFG port offset will be calculated if it is needed */ |
1629 | .tx_dma_offset = 0, | |
1630 | .rx_dma_offset = 0, | |
453c4990 PU |
1631 | .version = MCASP_VERSION_4, |
1632 | }; | |
1633 | ||
3e3b8c34 HG |
1634 | static const struct of_device_id mcasp_dt_ids[] = { |
1635 | { | |
1636 | .compatible = "ti,dm646x-mcasp-audio", | |
256ba181 | 1637 | .data = &dm646x_mcasp_pdata, |
3e3b8c34 HG |
1638 | }, |
1639 | { | |
1640 | .compatible = "ti,da830-mcasp-audio", | |
256ba181 | 1641 | .data = &da830_mcasp_pdata, |
3e3b8c34 | 1642 | }, |
e5ec69da | 1643 | { |
3af9e031 | 1644 | .compatible = "ti,am33xx-mcasp-audio", |
b14899da | 1645 | .data = &am33xx_mcasp_pdata, |
e5ec69da | 1646 | }, |
453c4990 PU |
1647 | { |
1648 | .compatible = "ti,dra7-mcasp-audio", | |
1649 | .data = &dra7_mcasp_pdata, | |
1650 | }, | |
3e3b8c34 HG |
1651 | { /* sentinel */ } |
1652 | }; | |
1653 | MODULE_DEVICE_TABLE(of, mcasp_dt_ids); | |
1654 | ||
ae726e93 PU |
1655 | static int mcasp_reparent_fck(struct platform_device *pdev) |
1656 | { | |
1657 | struct device_node *node = pdev->dev.of_node; | |
1658 | struct clk *gfclk, *parent_clk; | |
1659 | const char *parent_name; | |
1660 | int ret; | |
1661 | ||
1662 | if (!node) | |
1663 | return 0; | |
1664 | ||
1665 | parent_name = of_get_property(node, "fck_parent", NULL); | |
1666 | if (!parent_name) | |
1667 | return 0; | |
1668 | ||
c670254f PU |
1669 | dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); |
1670 | ||
ae726e93 PU |
1671 | gfclk = clk_get(&pdev->dev, "fck"); |
1672 | if (IS_ERR(gfclk)) { | |
1673 | dev_err(&pdev->dev, "failed to get fck\n"); | |
1674 | return PTR_ERR(gfclk); | |
1675 | } | |
1676 | ||
1677 | parent_clk = clk_get(NULL, parent_name); | |
1678 | if (IS_ERR(parent_clk)) { | |
1679 | dev_err(&pdev->dev, "failed to get parent clock\n"); | |
1680 | ret = PTR_ERR(parent_clk); | |
1681 | goto err1; | |
1682 | } | |
1683 | ||
1684 | ret = clk_set_parent(gfclk, parent_clk); | |
1685 | if (ret) { | |
1686 | dev_err(&pdev->dev, "failed to reparent fck\n"); | |
1687 | goto err2; | |
1688 | } | |
1689 | ||
1690 | err2: | |
1691 | clk_put(parent_clk); | |
1692 | err1: | |
1693 | clk_put(gfclk); | |
1694 | return ret; | |
1695 | } | |
1696 | ||
d1debafc | 1697 | static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of( |
3e3b8c34 HG |
1698 | struct platform_device *pdev) |
1699 | { | |
1700 | struct device_node *np = pdev->dev.of_node; | |
d1debafc | 1701 | struct davinci_mcasp_pdata *pdata = NULL; |
3e3b8c34 | 1702 | const struct of_device_id *match = |
ea421eb1 | 1703 | of_match_device(mcasp_dt_ids, &pdev->dev); |
4023fe6f | 1704 | struct of_phandle_args dma_spec; |
3e3b8c34 HG |
1705 | |
1706 | const u32 *of_serial_dir32; | |
3e3b8c34 HG |
1707 | u32 val; |
1708 | int i, ret = 0; | |
1709 | ||
1710 | if (pdev->dev.platform_data) { | |
1711 | pdata = pdev->dev.platform_data; | |
1712 | return pdata; | |
1713 | } else if (match) { | |
272ee030 PU |
1714 | pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata), |
1715 | GFP_KERNEL); | |
1716 | if (!pdata) { | |
272ee030 PU |
1717 | ret = -ENOMEM; |
1718 | return pdata; | |
1719 | } | |
3e3b8c34 HG |
1720 | } else { |
1721 | /* control shouldn't reach here. something is wrong */ | |
1722 | ret = -EINVAL; | |
1723 | goto nodata; | |
1724 | } | |
1725 | ||
3e3b8c34 HG |
1726 | ret = of_property_read_u32(np, "op-mode", &val); |
1727 | if (ret >= 0) | |
1728 | pdata->op_mode = val; | |
1729 | ||
1730 | ret = of_property_read_u32(np, "tdm-slots", &val); | |
2952b27e MB |
1731 | if (ret >= 0) { |
1732 | if (val < 2 || val > 32) { | |
1733 | dev_err(&pdev->dev, | |
1734 | "tdm-slots must be in rage [2-32]\n"); | |
1735 | ret = -EINVAL; | |
1736 | goto nodata; | |
1737 | } | |
1738 | ||
3e3b8c34 | 1739 | pdata->tdm_slots = val; |
2952b27e | 1740 | } |
3e3b8c34 | 1741 | |
3e3b8c34 HG |
1742 | of_serial_dir32 = of_get_property(np, "serial-dir", &val); |
1743 | val /= sizeof(u32); | |
3e3b8c34 | 1744 | if (of_serial_dir32) { |
1427e660 PU |
1745 | u8 *of_serial_dir = devm_kzalloc(&pdev->dev, |
1746 | (sizeof(*of_serial_dir) * val), | |
1747 | GFP_KERNEL); | |
3e3b8c34 HG |
1748 | if (!of_serial_dir) { |
1749 | ret = -ENOMEM; | |
1750 | goto nodata; | |
1751 | } | |
1752 | ||
1427e660 | 1753 | for (i = 0; i < val; i++) |
3e3b8c34 HG |
1754 | of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); |
1755 | ||
1427e660 | 1756 | pdata->num_serializer = val; |
3e3b8c34 HG |
1757 | pdata->serial_dir = of_serial_dir; |
1758 | } | |
1759 | ||
4023fe6f JS |
1760 | ret = of_property_match_string(np, "dma-names", "tx"); |
1761 | if (ret < 0) | |
1762 | goto nodata; | |
1763 | ||
1764 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, | |
1765 | &dma_spec); | |
1766 | if (ret < 0) | |
1767 | goto nodata; | |
1768 | ||
1769 | pdata->tx_dma_channel = dma_spec.args[0]; | |
1770 | ||
caa1d794 PU |
1771 | /* RX is not valid in DIT mode */ |
1772 | if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) { | |
1773 | ret = of_property_match_string(np, "dma-names", "rx"); | |
1774 | if (ret < 0) | |
1775 | goto nodata; | |
4023fe6f | 1776 | |
caa1d794 PU |
1777 | ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret, |
1778 | &dma_spec); | |
1779 | if (ret < 0) | |
1780 | goto nodata; | |
4023fe6f | 1781 | |
caa1d794 PU |
1782 | pdata->rx_dma_channel = dma_spec.args[0]; |
1783 | } | |
4023fe6f | 1784 | |
3e3b8c34 HG |
1785 | ret = of_property_read_u32(np, "tx-num-evt", &val); |
1786 | if (ret >= 0) | |
1787 | pdata->txnumevt = val; | |
1788 | ||
1789 | ret = of_property_read_u32(np, "rx-num-evt", &val); | |
1790 | if (ret >= 0) | |
1791 | pdata->rxnumevt = val; | |
1792 | ||
1793 | ret = of_property_read_u32(np, "sram-size-playback", &val); | |
1794 | if (ret >= 0) | |
1795 | pdata->sram_size_playback = val; | |
1796 | ||
1797 | ret = of_property_read_u32(np, "sram-size-capture", &val); | |
1798 | if (ret >= 0) | |
1799 | pdata->sram_size_capture = val; | |
1800 | ||
1801 | return pdata; | |
1802 | ||
1803 | nodata: | |
1804 | if (ret < 0) { | |
1805 | dev_err(&pdev->dev, "Error populating platform data, err %d\n", | |
1806 | ret); | |
1807 | pdata = NULL; | |
1808 | } | |
1809 | return pdata; | |
1810 | } | |
1811 | ||
9fbd58cf JS |
1812 | enum { |
1813 | PCM_EDMA, | |
1814 | PCM_SDMA, | |
1815 | }; | |
1816 | static const char *sdma_prefix = "ti,omap"; | |
1817 | ||
1818 | static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) | |
1819 | { | |
1820 | struct dma_chan *chan; | |
1821 | const char *tmp; | |
1822 | int ret = PCM_EDMA; | |
1823 | ||
1824 | if (!mcasp->dev->of_node) | |
1825 | return PCM_EDMA; | |
1826 | ||
1827 | tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; | |
1828 | chan = dma_request_slave_channel_reason(mcasp->dev, tmp); | |
1829 | if (IS_ERR(chan)) { | |
1830 | if (PTR_ERR(chan) != -EPROBE_DEFER) | |
1831 | dev_err(mcasp->dev, | |
1832 | "Can't verify DMA configuration (%ld)\n", | |
1833 | PTR_ERR(chan)); | |
1834 | return PTR_ERR(chan); | |
1835 | } | |
befff4fb TI |
1836 | if (WARN_ON(!chan->device || !chan->device->dev)) |
1837 | return -EINVAL; | |
9fbd58cf JS |
1838 | |
1839 | if (chan->device->dev->of_node) | |
1840 | ret = of_property_read_string(chan->device->dev->of_node, | |
1841 | "compatible", &tmp); | |
1842 | else | |
1843 | dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); | |
1844 | ||
1845 | dma_release_channel(chan); | |
1846 | if (ret) | |
1847 | return ret; | |
1848 | ||
1849 | dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); | |
1850 | if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) | |
1851 | return PCM_SDMA; | |
1852 | ||
1853 | return PCM_EDMA; | |
1854 | } | |
1855 | ||
9ac0013c PU |
1856 | static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata) |
1857 | { | |
1858 | int i; | |
1859 | u32 offset = 0; | |
1860 | ||
1861 | if (pdata->version != MCASP_VERSION_4) | |
1862 | return pdata->tx_dma_offset; | |
1863 | ||
1864 | for (i = 0; i < pdata->num_serializer; i++) { | |
1865 | if (pdata->serial_dir[i] == TX_MODE) { | |
1866 | if (!offset) { | |
1867 | offset = DAVINCI_MCASP_TXBUF_REG(i); | |
1868 | } else { | |
1869 | pr_err("%s: Only one serializer allowed!\n", | |
1870 | __func__); | |
1871 | break; | |
1872 | } | |
1873 | } | |
1874 | } | |
1875 | ||
1876 | return offset; | |
1877 | } | |
1878 | ||
1879 | static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) | |
1880 | { | |
1881 | int i; | |
1882 | u32 offset = 0; | |
1883 | ||
1884 | if (pdata->version != MCASP_VERSION_4) | |
1885 | return pdata->rx_dma_offset; | |
1886 | ||
1887 | for (i = 0; i < pdata->num_serializer; i++) { | |
1888 | if (pdata->serial_dir[i] == RX_MODE) { | |
1889 | if (!offset) { | |
1890 | offset = DAVINCI_MCASP_RXBUF_REG(i); | |
1891 | } else { | |
1892 | pr_err("%s: Only one serializer allowed!\n", | |
1893 | __func__); | |
1894 | break; | |
1895 | } | |
1896 | } | |
1897 | } | |
1898 | ||
1899 | return offset; | |
1900 | } | |
1901 | ||
b67f4487 C |
1902 | static int davinci_mcasp_probe(struct platform_device *pdev) |
1903 | { | |
8de131f2 | 1904 | struct snd_dmaengine_dai_dma_data *dma_data; |
508a43fd | 1905 | struct resource *mem, *res, *dat; |
d1debafc | 1906 | struct davinci_mcasp_pdata *pdata; |
70091a3e | 1907 | struct davinci_mcasp *mcasp; |
a7a3324a | 1908 | char *irq_name; |
9759e7ef | 1909 | int *dma; |
a7a3324a | 1910 | int irq; |
96d31e2b | 1911 | int ret; |
b67f4487 | 1912 | |
3e3b8c34 HG |
1913 | if (!pdev->dev.platform_data && !pdev->dev.of_node) { |
1914 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
1915 | return -EINVAL; | |
1916 | } | |
1917 | ||
70091a3e | 1918 | mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), |
96d31e2b | 1919 | GFP_KERNEL); |
70091a3e | 1920 | if (!mcasp) |
b67f4487 C |
1921 | return -ENOMEM; |
1922 | ||
3e3b8c34 HG |
1923 | pdata = davinci_mcasp_set_pdata_from_of(pdev); |
1924 | if (!pdata) { | |
1925 | dev_err(&pdev->dev, "no platform data\n"); | |
1926 | return -EINVAL; | |
1927 | } | |
1928 | ||
256ba181 | 1929 | mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); |
b67f4487 | 1930 | if (!mem) { |
70091a3e | 1931 | dev_warn(mcasp->dev, |
256ba181 JS |
1932 | "\"mpu\" mem resource not found, using index 0\n"); |
1933 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1934 | if (!mem) { | |
1935 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1936 | return -ENODEV; | |
1937 | } | |
b67f4487 C |
1938 | } |
1939 | ||
508a43fd AL |
1940 | mcasp->base = devm_ioremap_resource(&pdev->dev, mem); |
1941 | if (IS_ERR(mcasp->base)) | |
1942 | return PTR_ERR(mcasp->base); | |
b67f4487 | 1943 | |
10884347 | 1944 | pm_runtime_enable(&pdev->dev); |
b67f4487 | 1945 | |
70091a3e | 1946 | mcasp->op_mode = pdata->op_mode; |
1a5923da PU |
1947 | /* sanity check for tdm slots parameter */ |
1948 | if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { | |
1949 | if (pdata->tdm_slots < 2) { | |
1950 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1951 | pdata->tdm_slots); | |
1952 | mcasp->tdm_slots = 2; | |
1953 | } else if (pdata->tdm_slots > 32) { | |
1954 | dev_err(&pdev->dev, "invalid tdm slots: %d\n", | |
1955 | pdata->tdm_slots); | |
1956 | mcasp->tdm_slots = 32; | |
1957 | } else { | |
1958 | mcasp->tdm_slots = pdata->tdm_slots; | |
1959 | } | |
1960 | } | |
1961 | ||
70091a3e | 1962 | mcasp->num_serializer = pdata->num_serializer; |
f114ce60 | 1963 | #ifdef CONFIG_PM_SLEEP |
a86854d0 KC |
1964 | mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, |
1965 | mcasp->num_serializer, sizeof(u32), | |
f114ce60 | 1966 | GFP_KERNEL); |
4243e045 CJ |
1967 | if (!mcasp->context.xrsr_regs) { |
1968 | ret = -ENOMEM; | |
1969 | goto err; | |
1970 | } | |
f114ce60 | 1971 | #endif |
70091a3e PU |
1972 | mcasp->serial_dir = pdata->serial_dir; |
1973 | mcasp->version = pdata->version; | |
1974 | mcasp->txnumevt = pdata->txnumevt; | |
1975 | mcasp->rxnumevt = pdata->rxnumevt; | |
487dce88 | 1976 | |
70091a3e | 1977 | mcasp->dev = &pdev->dev; |
b67f4487 | 1978 | |
5a1b8a80 PU |
1979 | irq = platform_get_irq_byname(pdev, "common"); |
1980 | if (irq >= 0) { | |
ab1fffe3 | 1981 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", |
5a1b8a80 | 1982 | dev_name(&pdev->dev)); |
0c8b794c AY |
1983 | if (!irq_name) { |
1984 | ret = -ENOMEM; | |
1985 | goto err; | |
1986 | } | |
5a1b8a80 PU |
1987 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, |
1988 | davinci_mcasp_common_irq_handler, | |
8f511ffb PU |
1989 | IRQF_ONESHOT | IRQF_SHARED, |
1990 | irq_name, mcasp); | |
5a1b8a80 PU |
1991 | if (ret) { |
1992 | dev_err(&pdev->dev, "common IRQ request failed\n"); | |
1993 | goto err; | |
1994 | } | |
1995 | ||
1996 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; | |
1997 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; | |
1998 | } | |
1999 | ||
a7a3324a MLC |
2000 | irq = platform_get_irq_byname(pdev, "rx"); |
2001 | if (irq >= 0) { | |
ab1fffe3 | 2002 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", |
a7a3324a | 2003 | dev_name(&pdev->dev)); |
0c8b794c AY |
2004 | if (!irq_name) { |
2005 | ret = -ENOMEM; | |
2006 | goto err; | |
2007 | } | |
a7a3324a MLC |
2008 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, |
2009 | davinci_mcasp_rx_irq_handler, | |
2010 | IRQF_ONESHOT, irq_name, mcasp); | |
2011 | if (ret) { | |
2012 | dev_err(&pdev->dev, "RX IRQ request failed\n"); | |
2013 | goto err; | |
2014 | } | |
2015 | ||
2016 | mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; | |
2017 | } | |
2018 | ||
2019 | irq = platform_get_irq_byname(pdev, "tx"); | |
2020 | if (irq >= 0) { | |
ab1fffe3 | 2021 | irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", |
a7a3324a | 2022 | dev_name(&pdev->dev)); |
0c8b794c AY |
2023 | if (!irq_name) { |
2024 | ret = -ENOMEM; | |
2025 | goto err; | |
2026 | } | |
a7a3324a MLC |
2027 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, |
2028 | davinci_mcasp_tx_irq_handler, | |
2029 | IRQF_ONESHOT, irq_name, mcasp); | |
2030 | if (ret) { | |
2031 | dev_err(&pdev->dev, "TX IRQ request failed\n"); | |
2032 | goto err; | |
2033 | } | |
2034 | ||
2035 | mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; | |
2036 | } | |
2037 | ||
256ba181 | 2038 | dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); |
cbc7956c PU |
2039 | if (dat) |
2040 | mcasp->dat_port = true; | |
256ba181 | 2041 | |
8de131f2 | 2042 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; |
cbc7956c | 2043 | if (dat) |
9759e7ef | 2044 | dma_data->addr = dat->start; |
cbc7956c | 2045 | else |
9ac0013c | 2046 | dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata); |
453c4990 | 2047 | |
9759e7ef | 2048 | dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK]; |
b67f4487 | 2049 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
4023fe6f | 2050 | if (res) |
9759e7ef | 2051 | *dma = res->start; |
4023fe6f | 2052 | else |
9759e7ef | 2053 | *dma = pdata->tx_dma_channel; |
92e2a6f6 | 2054 | |
8de131f2 PU |
2055 | /* dmaengine filter data for DT and non-DT boot */ |
2056 | if (pdev->dev.of_node) | |
2057 | dma_data->filter_data = "tx"; | |
2058 | else | |
9759e7ef | 2059 | dma_data->filter_data = dma; |
8de131f2 | 2060 | |
caa1d794 PU |
2061 | /* RX is not valid in DIT mode */ |
2062 | if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { | |
caa1d794 | 2063 | dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; |
caa1d794 | 2064 | if (dat) |
9759e7ef | 2065 | dma_data->addr = dat->start; |
caa1d794 | 2066 | else |
9ac0013c PU |
2067 | dma_data->addr = |
2068 | mem->start + davinci_mcasp_rxdma_offset(pdata); | |
caa1d794 | 2069 | |
9759e7ef | 2070 | dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE]; |
caa1d794 PU |
2071 | res = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
2072 | if (res) | |
9759e7ef | 2073 | *dma = res->start; |
caa1d794 | 2074 | else |
9759e7ef | 2075 | *dma = pdata->rx_dma_channel; |
caa1d794 PU |
2076 | |
2077 | /* dmaengine filter data for DT and non-DT boot */ | |
2078 | if (pdev->dev.of_node) | |
2079 | dma_data->filter_data = "rx"; | |
2080 | else | |
9759e7ef | 2081 | dma_data->filter_data = dma; |
caa1d794 | 2082 | } |
453c4990 | 2083 | |
cbc7956c PU |
2084 | if (mcasp->version < MCASP_VERSION_3) { |
2085 | mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; | |
64ebdec3 | 2086 | /* dma_params->dma_addr is pointing to the data port address */ |
cbc7956c PU |
2087 | mcasp->dat_port = true; |
2088 | } else { | |
2089 | mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; | |
2090 | } | |
b67f4487 | 2091 | |
dd55ff83 JS |
2092 | /* Allocate memory for long enough list for all possible |
2093 | * scenarios. Maximum number tdm slots is 32 and there cannot | |
2094 | * be more serializers than given in the configuration. The | |
2095 | * serializer directions could be taken into account, but it | |
2096 | * would make code much more complex and save only couple of | |
2097 | * bytes. | |
2098 | */ | |
2099 | mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = | |
a86854d0 KC |
2100 | devm_kcalloc(mcasp->dev, |
2101 | 32 + mcasp->num_serializer - 1, | |
2102 | sizeof(unsigned int), | |
dd55ff83 JS |
2103 | GFP_KERNEL); |
2104 | ||
2105 | mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = | |
a86854d0 KC |
2106 | devm_kcalloc(mcasp->dev, |
2107 | 32 + mcasp->num_serializer - 1, | |
2108 | sizeof(unsigned int), | |
dd55ff83 JS |
2109 | GFP_KERNEL); |
2110 | ||
2111 | if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || | |
1b8b68b0 CJ |
2112 | !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { |
2113 | ret = -ENOMEM; | |
2114 | goto err; | |
2115 | } | |
dd55ff83 JS |
2116 | |
2117 | ret = davinci_mcasp_set_ch_constraints(mcasp); | |
5935a056 JS |
2118 | if (ret) |
2119 | goto err; | |
2120 | ||
70091a3e | 2121 | dev_set_drvdata(&pdev->dev, mcasp); |
ae726e93 PU |
2122 | |
2123 | mcasp_reparent_fck(pdev); | |
2124 | ||
b6bb3709 PU |
2125 | ret = devm_snd_soc_register_component(&pdev->dev, |
2126 | &davinci_mcasp_component, | |
2127 | &davinci_mcasp_dai[pdata->op_mode], 1); | |
b67f4487 C |
2128 | |
2129 | if (ret != 0) | |
b6bb3709 | 2130 | goto err; |
f08095a4 | 2131 | |
9fbd58cf JS |
2132 | ret = davinci_mcasp_get_dma_type(mcasp); |
2133 | switch (ret) { | |
2134 | case PCM_EDMA: | |
f3f9cfa8 PU |
2135 | #if IS_BUILTIN(CONFIG_SND_EDMA_SOC) || \ |
2136 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ | |
2137 | IS_MODULE(CONFIG_SND_EDMA_SOC)) | |
f3f9cfa8 | 2138 | ret = edma_pcm_platform_register(&pdev->dev); |
9fbd58cf JS |
2139 | #else |
2140 | dev_err(&pdev->dev, "Missing SND_EDMA_SOC\n"); | |
2141 | ret = -EINVAL; | |
2142 | goto err; | |
f3f9cfa8 | 2143 | #endif |
9fbd58cf JS |
2144 | break; |
2145 | case PCM_SDMA: | |
077a403d | 2146 | #if IS_BUILTIN(CONFIG_SND_SDMA_SOC) || \ |
7f28f357 | 2147 | (IS_MODULE(CONFIG_SND_DAVINCI_SOC_MCASP) && \ |
077a403d PU |
2148 | IS_MODULE(CONFIG_SND_SDMA_SOC)) |
2149 | ret = sdma_pcm_platform_register(&pdev->dev, NULL, NULL); | |
9fbd58cf JS |
2150 | #else |
2151 | dev_err(&pdev->dev, "Missing SND_SDMA_SOC\n"); | |
2152 | ret = -EINVAL; | |
2153 | goto err; | |
7f28f357 | 2154 | #endif |
9fbd58cf | 2155 | break; |
d5c6c59a | 2156 | default: |
9fbd58cf JS |
2157 | dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); |
2158 | case -EPROBE_DEFER: | |
2159 | goto err; | |
d5c6c59a PU |
2160 | break; |
2161 | } | |
2162 | ||
2163 | if (ret) { | |
2164 | dev_err(&pdev->dev, "register PCM failed: %d\n", ret); | |
b6bb3709 | 2165 | goto err; |
f08095a4 HG |
2166 | } |
2167 | ||
b67f4487 C |
2168 | return 0; |
2169 | ||
b6bb3709 | 2170 | err: |
10884347 | 2171 | pm_runtime_disable(&pdev->dev); |
b67f4487 C |
2172 | return ret; |
2173 | } | |
2174 | ||
2175 | static int davinci_mcasp_remove(struct platform_device *pdev) | |
2176 | { | |
10884347 | 2177 | pm_runtime_disable(&pdev->dev); |
b67f4487 | 2178 | |
b67f4487 C |
2179 | return 0; |
2180 | } | |
2181 | ||
2182 | static struct platform_driver davinci_mcasp_driver = { | |
2183 | .probe = davinci_mcasp_probe, | |
2184 | .remove = davinci_mcasp_remove, | |
2185 | .driver = { | |
2186 | .name = "davinci-mcasp", | |
ea421eb1 | 2187 | .of_match_table = mcasp_dt_ids, |
b67f4487 C |
2188 | }, |
2189 | }; | |
2190 | ||
f9b8a514 | 2191 | module_platform_driver(davinci_mcasp_driver); |
b67f4487 C |
2192 | |
2193 | MODULE_AUTHOR("Steve Chen"); | |
2194 | MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); | |
2195 | MODULE_LICENSE("GPL"); |