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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
83ac08c0 LG |
2 | /* |
3 | * wm9713.h -- WM9713 Soc Audio driver | |
4 | */ | |
5 | ||
6 | #ifndef _WM9713_H | |
7 | #define _WM9713_H | |
8 | ||
9 | /* clock inputs */ | |
10 | #define WM9713_CLKA_PIN 0 | |
11 | #define WM9713_CLKB_PIN 1 | |
12 | ||
13 | /* clock divider ID's */ | |
14 | #define WM9713_PCMCLK_DIV 0 | |
15 | #define WM9713_CLKA_MULT 1 | |
16 | #define WM9713_CLKB_MULT 2 | |
17 | #define WM9713_HIFI_DIV 3 | |
18 | #define WM9713_PCMBCLK_DIV 4 | |
19 | #define WM9713_PCMCLK_PLL_DIV 5 | |
20 | #define WM9713_HIFI_PLL_DIV 6 | |
21 | ||
22 | /* Calculate the appropriate bit mask for the external PCM clock divider */ | |
23 | #define WM9713_PCMDIV(x) ((x - 1) << 8) | |
24 | ||
25 | /* Calculate the appropriate bit mask for the external HiFi clock divider */ | |
26 | #define WM9713_HIFIDIV(x) ((x - 1) << 12) | |
27 | ||
28 | /* MCLK clock mulitipliers */ | |
29 | #define WM9713_CLKA_X1 (0 << 1) | |
30 | #define WM9713_CLKA_X2 (1 << 1) | |
31 | #define WM9713_CLKB_X1 (0 << 2) | |
32 | #define WM9713_CLKB_X2 (1 << 2) | |
33 | ||
34 | /* MCLK clock MUX */ | |
35 | #define WM9713_CLK_MUX_A (0 << 0) | |
36 | #define WM9713_CLK_MUX_B (1 << 0) | |
37 | ||
38 | /* Voice DAI BCLK divider */ | |
39 | #define WM9713_PCMBCLK_DIV_1 (0 << 9) | |
40 | #define WM9713_PCMBCLK_DIV_2 (1 << 9) | |
41 | #define WM9713_PCMBCLK_DIV_4 (2 << 9) | |
42 | #define WM9713_PCMBCLK_DIV_8 (3 << 9) | |
43 | #define WM9713_PCMBCLK_DIV_16 (4 << 9) | |
44 | ||
83ac08c0 | 45 | #endif |