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ASoC: core: Add support for masking out parts of coefficient blocks
[linux-2.6-block.git] / sound / soc / codecs / wm8996.c
CommitLineData
a9ba6151
MB		 1/*
2 * wm8996.c - WM8996 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
79172746 22#include <linux/regmap.h>
a9ba6151
MB		 23#include <linux/regulator/consumer.h>
24#include <linux/slab.h>
25#include <linux/workqueue.h>
26#include <sound/core.h>
27#include <sound/jack.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <trace/events/asoc.h>
34
35#include <sound/wm8996.h>
36#include "wm8996.h"
37
38#define WM8996_AIFS 2
39
40#define HPOUT1L 1
41#define HPOUT1R 2
42#define HPOUT2L 4
43#define HPOUT2R 8
44
c83495af 45#define WM8996_NUM_SUPPLIES 3
a9ba6151
MB		 46static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
47 "DBVDD",
48 "AVDD1",
49 "AVDD2",
a9ba6151
MB		 50};
51
52struct wm8996_priv {
b2d1e233 53 struct device *dev;
ee5f3872 54 struct regmap *regmap;
a9ba6151
MB		 55 struct snd_soc_codec *codec;
56
57 int ldo1ena;
58
59 int sysclk;
60 int sysclk_src;
61
62 int fll_src;
63 int fll_fref;
64 int fll_fout;
65
66 struct completion fll_lock;
67
68 u16 dcs_pending;
69 struct completion dcs_done;
70
71 u16 hpout_ena;
72 u16 hpout_pending;
73
74 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
75 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
ded71dcb 76 int bg_ena;
a9ba6151
MB		 77
78 struct wm8996_pdata pdata;
79
80 int rx_rate[WM8996_AIFS];
81 int bclk_rate[WM8996_AIFS];
82
83 /* Platform dependant ReTune mobile configuration */
84 int num_retune_mobile_texts;
85 const char **retune_mobile_texts;
86 int retune_mobile_cfg[2];
87 struct soc_enum retune_mobile_enum;
88
89 struct snd_soc_jack *jack;
90 bool detecting;
91 bool jack_mic;
d7b35570 92 int jack_flips;
a9ba6151
MB		 93 wm8996_polarity_fn polarity_cb;
94
95#ifdef CONFIG_GPIOLIB
96 struct gpio_chip gpio_chip;
97#endif
98};
99
100/* We can't use the same notifier block for more than one supply and
101 * there's no way I can see to get from a callback to the caller
102 * except container_of().
103 */
104#define WM8996_REGULATOR_EVENT(n) \
105static int wm8996_regulator_event_##n(struct notifier_block *nb, \
106 unsigned long event, void *data) \
107{ \
108 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
109 disable_nb[n]); \
110 if (event & REGULATOR_EVENT_DISABLE) { \
1b76d2ee 111 regcache_mark_dirty(wm8996->regmap); \
a9ba6151
MB		 112 } \
113 return 0; \
114}
115
116WM8996_REGULATOR_EVENT(0)
117WM8996_REGULATOR_EVENT(1)
118WM8996_REGULATOR_EVENT(2)
a9ba6151 119
79172746
MB		 120static struct reg_default wm8996_reg[] = {
121 { WM8996_SOFTWARE_RESET, 0x8996 },
122 { WM8996_POWER_MANAGEMENT_1, 0x0 },
123 { WM8996_POWER_MANAGEMENT_2, 0x0 },
124 { WM8996_POWER_MANAGEMENT_3, 0x0 },
125 { WM8996_POWER_MANAGEMENT_4, 0x0 },
126 { WM8996_POWER_MANAGEMENT_5, 0x0 },
127 { WM8996_POWER_MANAGEMENT_6, 0x0 },
128 { WM8996_POWER_MANAGEMENT_7, 0x10 },
129 { WM8996_POWER_MANAGEMENT_8, 0x0 },
130 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
131 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
132 { WM8996_LINE_INPUT_CONTROL, 0x0 },
133 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
134 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
135 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
136 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
137 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
138 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
139 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
140 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
141 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
142 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
143 { WM8996_MICBIAS_1, 0x39 },
144 { WM8996_MICBIAS_2, 0x39 },
145 { WM8996_LDO_1, 0x3 },
146 { WM8996_LDO_2, 0x13 },
147 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
148 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
149 { WM8996_HEADPHONE_DETECT_1, 0x20 },
150 { WM8996_HEADPHONE_DETECT_2, 0x0 },
151 { WM8996_MIC_DETECT_1, 0x7600 },
152 { WM8996_MIC_DETECT_2, 0xbf },
153 { WM8996_CHARGE_PUMP_1, 0x1f25 },
154 { WM8996_CHARGE_PUMP_2, 0xab19 },
155 { WM8996_DC_SERVO_1, 0x0 },
156 { WM8996_DC_SERVO_2, 0x0 },
157 { WM8996_DC_SERVO_3, 0x0 },
158 { WM8996_DC_SERVO_5, 0x2a2a },
159 { WM8996_DC_SERVO_6, 0x0 },
160 { WM8996_DC_SERVO_7, 0x0 },
161 { WM8996_ANALOGUE_HP_1, 0x0 },
162 { WM8996_ANALOGUE_HP_2, 0x0 },
163 { WM8996_CONTROL_INTERFACE_1, 0x8004 },
164 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
165 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
166 { WM8996_AIF_CLOCKING_1, 0x0 },
167 { WM8996_AIF_CLOCKING_2, 0x0 },
168 { WM8996_CLOCKING_1, 0x10 },
169 { WM8996_CLOCKING_2, 0x0 },
170 { WM8996_AIF_RATE, 0x83 },
171 { WM8996_FLL_CONTROL_1, 0x0 },
172 { WM8996_FLL_CONTROL_2, 0x0 },
173 { WM8996_FLL_CONTROL_3, 0x0 },
174 { WM8996_FLL_CONTROL_4, 0x5dc0 },
175 { WM8996_FLL_CONTROL_5, 0xc84 },
176 { WM8996_FLL_EFS_1, 0x0 },
177 { WM8996_FLL_EFS_2, 0x2 },
178 { WM8996_AIF1_CONTROL, 0x0 },
179 { WM8996_AIF1_BCLK, 0x0 },
180 { WM8996_AIF1_TX_LRCLK_1, 0x80 },
181 { WM8996_AIF1_TX_LRCLK_2, 0x8 },
182 { WM8996_AIF1_RX_LRCLK_1, 0x80 },
183 { WM8996_AIF1_RX_LRCLK_2, 0x0 },
184 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
185 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
186 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
187 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
188 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
189 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
190 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
191 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
192 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
193 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
194 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
195 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
196 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
197 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
198 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
199 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
200 { WM8996_AIF1TX_TEST, 0x7 },
201 { WM8996_AIF2_CONTROL, 0x0 },
202 { WM8996_AIF2_BCLK, 0x0 },
203 { WM8996_AIF2_TX_LRCLK_1, 0x80 },
204 { WM8996_AIF2_TX_LRCLK_2, 0x8 },
205 { WM8996_AIF2_RX_LRCLK_1, 0x80 },
206 { WM8996_AIF2_RX_LRCLK_2, 0x0 },
207 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
208 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
209 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
210 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
211 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
212 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
213 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
214 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
215 { WM8996_AIF2TX_TEST, 0x1 },
216 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
217 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
218 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
219 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
220 { WM8996_DSP1_TX_FILTERS, 0x2000 },
221 { WM8996_DSP1_RX_FILTERS_1, 0x200 },
222 { WM8996_DSP1_RX_FILTERS_2, 0x10 },
223 { WM8996_DSP1_DRC_1, 0x98 },
224 { WM8996_DSP1_DRC_2, 0x845 },
225 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
226 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
227 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
228 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
229 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
230 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
231 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
232 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
233 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
234 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
235 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
236 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
237 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
238 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
239 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
240 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
241 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
242 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
243 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
244 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
245 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
246 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
247 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
248 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
249 { WM8996_DSP2_TX_FILTERS, 0x2000 },
250 { WM8996_DSP2_RX_FILTERS_1, 0x200 },
251 { WM8996_DSP2_RX_FILTERS_2, 0x10 },
252 { WM8996_DSP2_DRC_1, 0x98 },
253 { WM8996_DSP2_DRC_2, 0x845 },
254 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
255 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
256 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
257 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
258 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
259 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
260 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
261 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
262 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
263 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
264 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
265 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
266 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
267 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
268 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
269 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
270 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
271 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
272 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
273 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
274 { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
275 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
276 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
277 { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
278 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
279 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
280 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
281 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
282 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
283 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
284 { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
285 { WM8996_DAC_SOFTMUTE, 0x0 },
286 { WM8996_OVERSAMPLING, 0xd },
287 { WM8996_SIDETONE, 0x1040 },
288 { WM8996_GPIO_1, 0xa101 },
289 { WM8996_GPIO_2, 0xa101 },
290 { WM8996_GPIO_3, 0xa101 },
291 { WM8996_GPIO_4, 0xa101 },
292 { WM8996_GPIO_5, 0xa101 },
293 { WM8996_PULL_CONTROL_1, 0x0 },
294 { WM8996_PULL_CONTROL_2, 0x140 },
295 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
296 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
297 { WM8996_LEFT_PDM_SPEAKER, 0x0 },
298 { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
299 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
300 { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
301 { WM8996_WRITE_SEQUENCER_0, 0x1 },
302 { WM8996_WRITE_SEQUENCER_1, 0x1 },
303 { WM8996_WRITE_SEQUENCER_3, 0x6 },
304 { WM8996_WRITE_SEQUENCER_4, 0x40 },
305 { WM8996_WRITE_SEQUENCER_5, 0x1 },
306 { WM8996_WRITE_SEQUENCER_6, 0xf },
307 { WM8996_WRITE_SEQUENCER_7, 0x6 },
308 { WM8996_WRITE_SEQUENCER_8, 0x1 },
309 { WM8996_WRITE_SEQUENCER_9, 0x3 },
310 { WM8996_WRITE_SEQUENCER_10, 0x104 },
311 { WM8996_WRITE_SEQUENCER_12, 0x60 },
312 { WM8996_WRITE_SEQUENCER_13, 0x11 },
313 { WM8996_WRITE_SEQUENCER_14, 0x401 },
314 { WM8996_WRITE_SEQUENCER_16, 0x50 },
315 { WM8996_WRITE_SEQUENCER_17, 0x3 },
316 { WM8996_WRITE_SEQUENCER_18, 0x100 },
317 { WM8996_WRITE_SEQUENCER_20, 0x51 },
318 { WM8996_WRITE_SEQUENCER_21, 0x3 },
319 { WM8996_WRITE_SEQUENCER_22, 0x104 },
320 { WM8996_WRITE_SEQUENCER_23, 0xa },
321 { WM8996_WRITE_SEQUENCER_24, 0x60 },
322 { WM8996_WRITE_SEQUENCER_25, 0x3b },
323 { WM8996_WRITE_SEQUENCER_26, 0x502 },
324 { WM8996_WRITE_SEQUENCER_27, 0x100 },
325 { WM8996_WRITE_SEQUENCER_28, 0x2fff },
326 { WM8996_WRITE_SEQUENCER_32, 0x2fff },
327 { WM8996_WRITE_SEQUENCER_36, 0x2fff },
328 { WM8996_WRITE_SEQUENCER_40, 0x2fff },
329 { WM8996_WRITE_SEQUENCER_44, 0x2fff },
330 { WM8996_WRITE_SEQUENCER_48, 0x2fff },
331 { WM8996_WRITE_SEQUENCER_52, 0x2fff },
332 { WM8996_WRITE_SEQUENCER_56, 0x2fff },
333 { WM8996_WRITE_SEQUENCER_60, 0x2fff },
334 { WM8996_WRITE_SEQUENCER_64, 0x1 },
335 { WM8996_WRITE_SEQUENCER_65, 0x1 },
336 { WM8996_WRITE_SEQUENCER_67, 0x6 },
337 { WM8996_WRITE_SEQUENCER_68, 0x40 },
338 { WM8996_WRITE_SEQUENCER_69, 0x1 },
339 { WM8996_WRITE_SEQUENCER_70, 0xf },
340 { WM8996_WRITE_SEQUENCER_71, 0x6 },
341 { WM8996_WRITE_SEQUENCER_72, 0x1 },
342 { WM8996_WRITE_SEQUENCER_73, 0x3 },
343 { WM8996_WRITE_SEQUENCER_74, 0x104 },
344 { WM8996_WRITE_SEQUENCER_76, 0x60 },
345 { WM8996_WRITE_SEQUENCER_77, 0x11 },
346 { WM8996_WRITE_SEQUENCER_78, 0x401 },
347 { WM8996_WRITE_SEQUENCER_80, 0x50 },
348 { WM8996_WRITE_SEQUENCER_81, 0x3 },
349 { WM8996_WRITE_SEQUENCER_82, 0x100 },
350 { WM8996_WRITE_SEQUENCER_84, 0x60 },
351 { WM8996_WRITE_SEQUENCER_85, 0x3b },
352 { WM8996_WRITE_SEQUENCER_86, 0x502 },
353 { WM8996_WRITE_SEQUENCER_87, 0x100 },
354 { WM8996_WRITE_SEQUENCER_88, 0x2fff },
355 { WM8996_WRITE_SEQUENCER_92, 0x2fff },
356 { WM8996_WRITE_SEQUENCER_96, 0x2fff },
357 { WM8996_WRITE_SEQUENCER_100, 0x2fff },
358 { WM8996_WRITE_SEQUENCER_104, 0x2fff },
359 { WM8996_WRITE_SEQUENCER_108, 0x2fff },
360 { WM8996_WRITE_SEQUENCER_112, 0x2fff },
361 { WM8996_WRITE_SEQUENCER_116, 0x2fff },
362 { WM8996_WRITE_SEQUENCER_120, 0x2fff },
363 { WM8996_WRITE_SEQUENCER_124, 0x2fff },
364 { WM8996_WRITE_SEQUENCER_128, 0x1 },
365 { WM8996_WRITE_SEQUENCER_129, 0x1 },
366 { WM8996_WRITE_SEQUENCER_131, 0x6 },
367 { WM8996_WRITE_SEQUENCER_132, 0x40 },
368 { WM8996_WRITE_SEQUENCER_133, 0x1 },
369 { WM8996_WRITE_SEQUENCER_134, 0xf },
370 { WM8996_WRITE_SEQUENCER_135, 0x6 },
371 { WM8996_WRITE_SEQUENCER_136, 0x1 },
372 { WM8996_WRITE_SEQUENCER_137, 0x3 },
373 { WM8996_WRITE_SEQUENCER_138, 0x106 },
374 { WM8996_WRITE_SEQUENCER_140, 0x61 },
375 { WM8996_WRITE_SEQUENCER_141, 0x11 },
376 { WM8996_WRITE_SEQUENCER_142, 0x401 },
377 { WM8996_WRITE_SEQUENCER_144, 0x50 },
378 { WM8996_WRITE_SEQUENCER_145, 0x3 },
379 { WM8996_WRITE_SEQUENCER_146, 0x102 },
380 { WM8996_WRITE_SEQUENCER_148, 0x51 },
381 { WM8996_WRITE_SEQUENCER_149, 0x3 },
382 { WM8996_WRITE_SEQUENCER_150, 0x106 },
383 { WM8996_WRITE_SEQUENCER_151, 0xa },
384 { WM8996_WRITE_SEQUENCER_152, 0x61 },
385 { WM8996_WRITE_SEQUENCER_153, 0x3b },
386 { WM8996_WRITE_SEQUENCER_154, 0x502 },
387 { WM8996_WRITE_SEQUENCER_155, 0x100 },
388 { WM8996_WRITE_SEQUENCER_156, 0x2fff },
389 { WM8996_WRITE_SEQUENCER_160, 0x2fff },
390 { WM8996_WRITE_SEQUENCER_164, 0x2fff },
391 { WM8996_WRITE_SEQUENCER_168, 0x2fff },
392 { WM8996_WRITE_SEQUENCER_172, 0x2fff },
393 { WM8996_WRITE_SEQUENCER_176, 0x2fff },
394 { WM8996_WRITE_SEQUENCER_180, 0x2fff },
395 { WM8996_WRITE_SEQUENCER_184, 0x2fff },
396 { WM8996_WRITE_SEQUENCER_188, 0x2fff },
397 { WM8996_WRITE_SEQUENCER_192, 0x1 },
398 { WM8996_WRITE_SEQUENCER_193, 0x1 },
399 { WM8996_WRITE_SEQUENCER_195, 0x6 },
400 { WM8996_WRITE_SEQUENCER_196, 0x40 },
401 { WM8996_WRITE_SEQUENCER_197, 0x1 },
402 { WM8996_WRITE_SEQUENCER_198, 0xf },
403 { WM8996_WRITE_SEQUENCER_199, 0x6 },
404 { WM8996_WRITE_SEQUENCER_200, 0x1 },
405 { WM8996_WRITE_SEQUENCER_201, 0x3 },
406 { WM8996_WRITE_SEQUENCER_202, 0x106 },
407 { WM8996_WRITE_SEQUENCER_204, 0x61 },
408 { WM8996_WRITE_SEQUENCER_205, 0x11 },
409 { WM8996_WRITE_SEQUENCER_206, 0x401 },
410 { WM8996_WRITE_SEQUENCER_208, 0x50 },
411 { WM8996_WRITE_SEQUENCER_209, 0x3 },
412 { WM8996_WRITE_SEQUENCER_210, 0x102 },
413 { WM8996_WRITE_SEQUENCER_212, 0x61 },
414 { WM8996_WRITE_SEQUENCER_213, 0x3b },
415 { WM8996_WRITE_SEQUENCER_214, 0x502 },
416 { WM8996_WRITE_SEQUENCER_215, 0x100 },
417 { WM8996_WRITE_SEQUENCER_216, 0x2fff },
418 { WM8996_WRITE_SEQUENCER_220, 0x2fff },
419 { WM8996_WRITE_SEQUENCER_224, 0x2fff },
420 { WM8996_WRITE_SEQUENCER_228, 0x2fff },
421 { WM8996_WRITE_SEQUENCER_232, 0x2fff },
422 { WM8996_WRITE_SEQUENCER_236, 0x2fff },
423 { WM8996_WRITE_SEQUENCER_240, 0x2fff },
424 { WM8996_WRITE_SEQUENCER_244, 0x2fff },
425 { WM8996_WRITE_SEQUENCER_248, 0x2fff },
426 { WM8996_WRITE_SEQUENCER_252, 0x2fff },
427 { WM8996_WRITE_SEQUENCER_256, 0x60 },
428 { WM8996_WRITE_SEQUENCER_258, 0x601 },
429 { WM8996_WRITE_SEQUENCER_260, 0x50 },
430 { WM8996_WRITE_SEQUENCER_262, 0x100 },
431 { WM8996_WRITE_SEQUENCER_264, 0x1 },
432 { WM8996_WRITE_SEQUENCER_266, 0x104 },
433 { WM8996_WRITE_SEQUENCER_267, 0x100 },
434 { WM8996_WRITE_SEQUENCER_268, 0x2fff },
435 { WM8996_WRITE_SEQUENCER_272, 0x2fff },
436 { WM8996_WRITE_SEQUENCER_276, 0x2fff },
437 { WM8996_WRITE_SEQUENCER_280, 0x2fff },
438 { WM8996_WRITE_SEQUENCER_284, 0x2fff },
439 { WM8996_WRITE_SEQUENCER_288, 0x2fff },
440 { WM8996_WRITE_SEQUENCER_292, 0x2fff },
441 { WM8996_WRITE_SEQUENCER_296, 0x2fff },
442 { WM8996_WRITE_SEQUENCER_300, 0x2fff },
443 { WM8996_WRITE_SEQUENCER_304, 0x2fff },
444 { WM8996_WRITE_SEQUENCER_308, 0x2fff },
445 { WM8996_WRITE_SEQUENCER_312, 0x2fff },
446 { WM8996_WRITE_SEQUENCER_316, 0x2fff },
447 { WM8996_WRITE_SEQUENCER_320, 0x61 },
448 { WM8996_WRITE_SEQUENCER_322, 0x601 },
449 { WM8996_WRITE_SEQUENCER_324, 0x50 },
450 { WM8996_WRITE_SEQUENCER_326, 0x102 },
451 { WM8996_WRITE_SEQUENCER_328, 0x1 },
452 { WM8996_WRITE_SEQUENCER_330, 0x106 },
453 { WM8996_WRITE_SEQUENCER_331, 0x100 },
454 { WM8996_WRITE_SEQUENCER_332, 0x2fff },
455 { WM8996_WRITE_SEQUENCER_336, 0x2fff },
456 { WM8996_WRITE_SEQUENCER_340, 0x2fff },
457 { WM8996_WRITE_SEQUENCER_344, 0x2fff },
458 { WM8996_WRITE_SEQUENCER_348, 0x2fff },
459 { WM8996_WRITE_SEQUENCER_352, 0x2fff },
460 { WM8996_WRITE_SEQUENCER_356, 0x2fff },
461 { WM8996_WRITE_SEQUENCER_360, 0x2fff },
462 { WM8996_WRITE_SEQUENCER_364, 0x2fff },
463 { WM8996_WRITE_SEQUENCER_368, 0x2fff },
464 { WM8996_WRITE_SEQUENCER_372, 0x2fff },
465 { WM8996_WRITE_SEQUENCER_376, 0x2fff },
466 { WM8996_WRITE_SEQUENCER_380, 0x2fff },
467 { WM8996_WRITE_SEQUENCER_384, 0x60 },
468 { WM8996_WRITE_SEQUENCER_386, 0x601 },
469 { WM8996_WRITE_SEQUENCER_388, 0x61 },
470 { WM8996_WRITE_SEQUENCER_390, 0x601 },
471 { WM8996_WRITE_SEQUENCER_392, 0x50 },
472 { WM8996_WRITE_SEQUENCER_394, 0x300 },
473 { WM8996_WRITE_SEQUENCER_396, 0x1 },
474 { WM8996_WRITE_SEQUENCER_398, 0x304 },
475 { WM8996_WRITE_SEQUENCER_400, 0x40 },
476 { WM8996_WRITE_SEQUENCER_402, 0xf },
477 { WM8996_WRITE_SEQUENCER_404, 0x1 },
478 { WM8996_WRITE_SEQUENCER_407, 0x100 },
a9ba6151
MB		 479};
480
481static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
482static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
483static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
484static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
485static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
486static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
487static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
18a4eef3 488static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
a9ba6151
MB		 489
490static const char *sidetone_hpf_text[] = {
491 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
492};
493
494static const struct soc_enum sidetone_hpf =
18036b58 495 SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text);
a9ba6151
MB		 496
497static const char *hpf_mode_text[] = {
498 "HiFi", "Custom", "Voice"
499};
500
501static const struct soc_enum dsp1tx_hpf_mode =
502 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
503
504static const struct soc_enum dsp2tx_hpf_mode =
505 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
506
507static const char *hpf_cutoff_text[] = {
508 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
509};
510
511static const struct soc_enum dsp1tx_hpf_cutoff =
512 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
513
514static const struct soc_enum dsp2tx_hpf_cutoff =
515 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
516
517static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
518{
519 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
520 struct wm8996_pdata *pdata = &wm8996->pdata;
521 int base, best, best_val, save, i, cfg, iface;
522
523 if (!wm8996->num_retune_mobile_texts)
524 return;
525
526 switch (block) {
527 case 0:
528 base = WM8996_DSP1_RX_EQ_GAINS_1;
529 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
530 WM8996_DSP1RX_SRC)
531 iface = 1;
532 else
533 iface = 0;
534 break;
535 case 1:
536 base = WM8996_DSP1_RX_EQ_GAINS_2;
537 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
538 WM8996_DSP2RX_SRC)
539 iface = 1;
540 else
541 iface = 0;
542 break;
543 default:
544 return;
545 }
546
547 /* Find the version of the currently selected configuration
548 * with the nearest sample rate. */
549 cfg = wm8996->retune_mobile_cfg[block];
550 best = 0;
551 best_val = INT_MAX;
552 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
553 if (strcmp(pdata->retune_mobile_cfgs[i].name,
554 wm8996->retune_mobile_texts[cfg]) == 0 &&
555 abs(pdata->retune_mobile_cfgs[i].rate
556 - wm8996->rx_rate[iface]) < best_val) {
557 best = i;
558 best_val = abs(pdata->retune_mobile_cfgs[i].rate
559 - wm8996->rx_rate[iface]);
560 }
561 }
562
563 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
564 block,
565 pdata->retune_mobile_cfgs[best].name,
566 pdata->retune_mobile_cfgs[best].rate,
567 wm8996->rx_rate[iface]);
568
569 /* The EQ will be disabled while reconfiguring it, remember the
570 * current configuration.
571 */
572 save = snd_soc_read(codec, base);
573 save &= WM8996_DSP1RX_EQ_ENA;
574
575 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
576 snd_soc_update_bits(codec, base + i, 0xffff,
577 pdata->retune_mobile_cfgs[best].regs[i]);
578
579 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
580}
581
582/* Icky as hell but saves code duplication */
583static int wm8996_get_retune_mobile_block(const char *name)
584{
585 if (strcmp(name, "DSP1 EQ Mode") == 0)
586 return 0;
587 if (strcmp(name, "DSP2 EQ Mode") == 0)
588 return 1;
589 return -EINVAL;
590}
591
592static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
593 struct snd_ctl_elem_value *ucontrol)
594{
595 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
596 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
597 struct wm8996_pdata *pdata = &wm8996->pdata;
598 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
599 int value = ucontrol->value.integer.value[0];
600
601 if (block < 0)
602 return block;
603
604 if (value >= pdata->num_retune_mobile_cfgs)
605 return -EINVAL;
606
607 wm8996->retune_mobile_cfg[block] = value;
608
609 wm8996_set_retune_mobile(codec, block);
610
611 return 0;
612}
613
614static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
615 struct snd_ctl_elem_value *ucontrol)
616{
617 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
618 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
619 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
620
621 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
622
623 return 0;
624}
625
626static const struct snd_kcontrol_new wm8996_snd_controls[] = {
627SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
628 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
629SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
630 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
631
632SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
633 0, 5, 24, 0, sidetone_tlv),
634SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
635 0, 5, 24, 0, sidetone_tlv),
636SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
637SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
638SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
639
640SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
641 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
642SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
643 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
644
645SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
646 13, 1, 0),
647SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
648SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
649SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
650
651SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
652 13, 1, 0),
653SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
654SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
655SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
656
657SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
658 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
659SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
660
661SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
662 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
663SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
664
665SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
666 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
667SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
668 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
669
670SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
671 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
672SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
673 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
674
675SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
676SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
677SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
678SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
679
680SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
681SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
682
18a4eef3 683SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
684SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
685
686SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
687 0, threedstereo_tlv),
688SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
689 0, threedstereo_tlv),
690
a9ba6151
MB		 691SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
692 8, 0, out_digital_tlv),
693SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
694 8, 0, out_digital_tlv),
695
696SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
697 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
698SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
699 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
700
701SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
702 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
703SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
704 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
705
706SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
707 spk_tlv),
708SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
709 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
710SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
711 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
712
713SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
714SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
bcec267a
KT		 715
716SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
717SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
718SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
719
720SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
721SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
722SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
a9ba6151
MB		 723};
724
725static const struct snd_kcontrol_new wm8996_eq_controls[] = {
726SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
727 eq_tlv),
728SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
729 eq_tlv),
730SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
731 eq_tlv),
732SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
733 eq_tlv),
734SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
735 eq_tlv),
736
737SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
738 eq_tlv),
739SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
740 eq_tlv),
741SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
742 eq_tlv),
743SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
744 eq_tlv),
745SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
746 eq_tlv),
747};
748
ded71dcb
MB		 749static void wm8996_bg_enable(struct snd_soc_codec *codec)
750{
751 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
752
753 wm8996->bg_ena++;
754 if (wm8996->bg_ena == 1) {
755 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
756 WM8996_BG_ENA, WM8996_BG_ENA);
757 msleep(2);
758 }
759}
760
761static void wm8996_bg_disable(struct snd_soc_codec *codec)
762{
763 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
764
765 wm8996->bg_ena--;
766 if (!wm8996->bg_ena)
767 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
768 WM8996_BG_ENA, 0);
769}
770
8259df12
MB		 771static int bg_event(struct snd_soc_dapm_widget *w,
772 struct snd_kcontrol *kcontrol, int event)
773{
ded71dcb 774 struct snd_soc_codec *codec = w->codec;
8259df12
MB		 775 int ret = 0;
776
777 switch (event) {
ded71dcb
MB		 778 case SND_SOC_DAPM_PRE_PMU:
779 wm8996_bg_enable(codec);
780 break;
781 case SND_SOC_DAPM_POST_PMD:
782 wm8996_bg_disable(codec);
8259df12
MB		 783 break;
784 default:
785 BUG();
786 ret = -EINVAL;
787 }
788
789 return ret;
790}
791
a9ba6151
MB		 792static int cp_event(struct snd_soc_dapm_widget *w,
793 struct snd_kcontrol *kcontrol, int event)
794{
c83495af
MB		 795 int ret = 0;
796
a9ba6151
MB		 797 switch (event) {
798 case SND_SOC_DAPM_POST_PMU:
799 msleep(5);
800 break;
801 default:
802 BUG();
c83495af 803 ret = -EINVAL;
a9ba6151
MB		 804 }
805
4a086e4c 806 return 0;
a9ba6151
MB		 807}
808
809static int rmv_short_event(struct snd_soc_dapm_widget *w,
810 struct snd_kcontrol *kcontrol, int event)
811{
812 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
813
814 /* Record which outputs we enabled */
815 switch (event) {
816 case SND_SOC_DAPM_PRE_PMD:
817 wm8996->hpout_pending &= ~w->shift;
818 break;
819 case SND_SOC_DAPM_PRE_PMU:
820 wm8996->hpout_pending |= w->shift;
821 break;
822 default:
823 BUG();
824 return -EINVAL;
825 }
826
827 return 0;
828}
829
830static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
831{
832 struct i2c_client *i2c = to_i2c_client(codec->dev);
833 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
f998f257 834 int ret;
a9ba6151
MB		 835 unsigned long timeout = 200;
836
837 snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
838
839 /* Use the interrupt if possible */
840 do {
841 if (i2c->irq) {
842 timeout = wait_for_completion_timeout(&wm8996->dcs_done,
843 msecs_to_jiffies(200));
844 if (timeout == 0)
845 dev_err(codec->dev, "DC servo timed out\n");
846
847 } else {
848 msleep(1);
f998f257 849 timeout--;
a9ba6151
MB		 850 }
851
852 ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
853 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
f998f257 854 } while (timeout && ret & mask);
a9ba6151
MB		 855
856 if (timeout == 0)
857 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
858 else
859 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
860}
861
862static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
863 enum snd_soc_dapm_type event, int subseq)
864{
865 struct snd_soc_codec *codec = container_of(dapm,
866 struct snd_soc_codec, dapm);
867 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
868 u16 val, mask;
869
870 /* Complete any pending DC servo starts */
871 if (wm8996->dcs_pending) {
872 dev_dbg(codec->dev, "Starting DC servo for %x\n",
873 wm8996->dcs_pending);
874
875 /* Trigger a startup sequence */
876 wait_for_dc_servo(codec, wm8996->dcs_pending
877 << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
878
879 wm8996->dcs_pending = 0;
880 }
881
882 if (wm8996->hpout_pending != wm8996->hpout_ena) {
883 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
884 wm8996->hpout_ena, wm8996->hpout_pending);
885
886 val = 0;
887 mask = 0;
888 if (wm8996->hpout_pending & HPOUT1L) {
889 val |= WM8996_HPOUT1L_RMV_SHORT;
890 mask |= WM8996_HPOUT1L_RMV_SHORT;
891 } else {
892 mask |= WM8996_HPOUT1L_RMV_SHORT |
893 WM8996_HPOUT1L_OUTP |
894 WM8996_HPOUT1L_DLY;
895 }
896
897 if (wm8996->hpout_pending & HPOUT1R) {
898 val |= WM8996_HPOUT1R_RMV_SHORT;
899 mask |= WM8996_HPOUT1R_RMV_SHORT;
900 } else {
901 mask |= WM8996_HPOUT1R_RMV_SHORT |
902 WM8996_HPOUT1R_OUTP |
903 WM8996_HPOUT1R_DLY;
904 }
905
906 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
907
908 val = 0;
909 mask = 0;
910 if (wm8996->hpout_pending & HPOUT2L) {
911 val |= WM8996_HPOUT2L_RMV_SHORT;
912 mask |= WM8996_HPOUT2L_RMV_SHORT;
913 } else {
914 mask |= WM8996_HPOUT2L_RMV_SHORT |
915 WM8996_HPOUT2L_OUTP |
916 WM8996_HPOUT2L_DLY;
917 }
918
919 if (wm8996->hpout_pending & HPOUT2R) {
920 val |= WM8996_HPOUT2R_RMV_SHORT;
921 mask |= WM8996_HPOUT2R_RMV_SHORT;
922 } else {
923 mask |= WM8996_HPOUT2R_RMV_SHORT |
924 WM8996_HPOUT2R_OUTP |
925 WM8996_HPOUT2R_DLY;
926 }
927
928 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
929
930 wm8996->hpout_ena = wm8996->hpout_pending;
931 }
932}
933
934static int dcs_start(struct snd_soc_dapm_widget *w,
935 struct snd_kcontrol *kcontrol, int event)
936{
937 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
938
939 switch (event) {
940 case SND_SOC_DAPM_POST_PMU:
941 wm8996->dcs_pending |= 1 << w->shift;
942 break;
943 default:
944 BUG();
945 return -EINVAL;
946 }
947
948 return 0;
949}
950
951static const char *sidetone_text[] = {
952 "IN1", "IN2",
953};
954
955static const struct soc_enum left_sidetone_enum =
956 SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text);
957
958static const struct snd_kcontrol_new left_sidetone =
959 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
960
961static const struct soc_enum right_sidetone_enum =
962 SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text);
963
964static const struct snd_kcontrol_new right_sidetone =
965 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
966
967static const char *spk_text[] = {
968 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
969};
970
971static const struct soc_enum spkl_enum =
972 SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text);
973
974static const struct snd_kcontrol_new spkl_mux =
975 SOC_DAPM_ENUM("SPKL", spkl_enum);
976
977static const struct soc_enum spkr_enum =
978 SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
979
980static const struct snd_kcontrol_new spkr_mux =
981 SOC_DAPM_ENUM("SPKR", spkr_enum);
982
983static const char *dsp1rx_text[] = {
984 "AIF1", "AIF2"
985};
986
987static const struct soc_enum dsp1rx_enum =
988 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
989
990static const struct snd_kcontrol_new dsp1rx =
991 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
992
993static const char *dsp2rx_text[] = {
994 "AIF2", "AIF1"
995};
996
997static const struct soc_enum dsp2rx_enum =
998 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
999
1000static const struct snd_kcontrol_new dsp2rx =
1001 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
1002
1003static const char *aif2tx_text[] = {
1004 "DSP2", "DSP1", "AIF1"
1005};
1006
1007static const struct soc_enum aif2tx_enum =
1008 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
1009
1010static const struct snd_kcontrol_new aif2tx =
1011 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
1012
1013static const char *inmux_text[] = {
1014 "ADC", "DMIC1", "DMIC2"
1015};
1016
1017static const struct soc_enum in1_enum =
1018 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text);
1019
1020static const struct snd_kcontrol_new in1_mux =
1021 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
1022
1023static const struct soc_enum in2_enum =
1024 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text);
1025
1026static const struct snd_kcontrol_new in2_mux =
1027 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
1028
1029static const struct snd_kcontrol_new dac2r_mix[] = {
1030SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
1031 5, 1, 0),
1032SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
1033 4, 1, 0),
1034SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
1035SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
1036};
1037
1038static const struct snd_kcontrol_new dac2l_mix[] = {
1039SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
1040 5, 1, 0),
1041SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
1042 4, 1, 0),
1043SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
1044SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
1045};
1046
1047static const struct snd_kcontrol_new dac1r_mix[] = {
1048SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
1049 5, 1, 0),
1050SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
1051 4, 1, 0),
1052SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
1053SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
1054};
1055
1056static const struct snd_kcontrol_new dac1l_mix[] = {
1057SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
1058 5, 1, 0),
1059SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
1060 4, 1, 0),
1061SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
1062SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
1063};
1064
1065static const struct snd_kcontrol_new dsp1txl[] = {
1066SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1067 1, 1, 0),
1068SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1069 0, 1, 0),
1070};
1071
1072static const struct snd_kcontrol_new dsp1txr[] = {
1073SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1074 1, 1, 0),
1075SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1076 0, 1, 0),
1077};
1078
1079static const struct snd_kcontrol_new dsp2txl[] = {
1080SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1081 1, 1, 0),
1082SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1083 0, 1, 0),
1084};
1085
1086static const struct snd_kcontrol_new dsp2txr[] = {
1087SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1088 1, 1, 0),
1089SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1090 0, 1, 0),
1091};
1092
1093
1094static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
1095SND_SOC_DAPM_INPUT("IN1LN"),
1096SND_SOC_DAPM_INPUT("IN1LP"),
1097SND_SOC_DAPM_INPUT("IN1RN"),
1098SND_SOC_DAPM_INPUT("IN1RP"),
1099
1100SND_SOC_DAPM_INPUT("IN2LN"),
1101SND_SOC_DAPM_INPUT("IN2LP"),
1102SND_SOC_DAPM_INPUT("IN2RN"),
1103SND_SOC_DAPM_INPUT("IN2RP"),
1104
1105SND_SOC_DAPM_INPUT("DMIC1DAT"),
1106SND_SOC_DAPM_INPUT("DMIC2DAT"),
1107
4a086e4c 1108SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20),
a9ba6151
MB		 1109SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
1110SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
1111SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
1112SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
4a086e4c 1113 SND_SOC_DAPM_POST_PMU),
ded71dcb
MB		 1114SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
1115 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
a9ba6151 1116SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
889c85c5
MB		 1117SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
1118SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
a9ba6151
MB		 1119SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
1120SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
1121
1122SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
1123SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
1124
7691cd74
MB		 1125SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
1126SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
1127SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
1128SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
a9ba6151
MB		 1129
1130SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1131SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1132
1133SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
1134SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
1135SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
1136SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
1137
1138SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
1139SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
1140
1141SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1142SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1143
1144SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
1145SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
1146SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
1147SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
1148
1149SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
1150 dsp2txl, ARRAY_SIZE(dsp2txl)),
1151SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
1152 dsp2txr, ARRAY_SIZE(dsp2txr)),
1153SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
1154 dsp1txl, ARRAY_SIZE(dsp1txl)),
1155SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
1156 dsp1txr, ARRAY_SIZE(dsp1txr)),
1157
1158SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1159 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1160SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1161 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1162SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1163 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1164SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1165 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1166
1167SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
1168SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
1169SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
1170SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
1171
32d2a0c1 1172SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
a9ba6151 1173 WM8996_POWER_MANAGEMENT_4, 9, 0),
32d2a0c1 1174SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 1,
a9ba6151
MB		 1175 WM8996_POWER_MANAGEMENT_4, 8, 0),
1176
ff39dbe9 1177SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
a9ba6151 1178 WM8996_POWER_MANAGEMENT_6, 9, 0),
ff39dbe9 1179SND_SOC_DAPM_AIF_OUT("AIF2TX0", "AIF2 Capture", 1,
a9ba6151
MB		 1180 WM8996_POWER_MANAGEMENT_6, 8, 0),
1181
1182SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1183 WM8996_POWER_MANAGEMENT_4, 5, 0),
1184SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1185 WM8996_POWER_MANAGEMENT_4, 4, 0),
1186SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1187 WM8996_POWER_MANAGEMENT_4, 3, 0),
1188SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1189 WM8996_POWER_MANAGEMENT_4, 2, 0),
1190SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1191 WM8996_POWER_MANAGEMENT_4, 1, 0),
1192SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1193 WM8996_POWER_MANAGEMENT_4, 0, 0),
1194
1195SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1196 WM8996_POWER_MANAGEMENT_6, 5, 0),
1197SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1198 WM8996_POWER_MANAGEMENT_6, 4, 0),
1199SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1200 WM8996_POWER_MANAGEMENT_6, 3, 0),
1201SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1202 WM8996_POWER_MANAGEMENT_6, 2, 0),
1203SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1204 WM8996_POWER_MANAGEMENT_6, 1, 0),
1205SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1206 WM8996_POWER_MANAGEMENT_6, 0, 0),
1207
1208/* We route as stereo pairs so define some dummy widgets to squash
1209 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1210SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1211SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1212SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1213SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1214SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1215
1216SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1217SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1218SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1219
1220SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1221SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1222SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1223SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1224
1225SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1226SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1227SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1228 SND_SOC_DAPM_POST_PMU),
1229SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2, 6, 0, NULL, 0),
1230SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1231 rmv_short_event,
1232 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1233
1234SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1235SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1236SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1237 SND_SOC_DAPM_POST_PMU),
1238SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2, 2, 0, NULL, 0),
1239SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1240 rmv_short_event,
1241 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1242
1243SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1244SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1245SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1246 SND_SOC_DAPM_POST_PMU),
1247SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1, 6, 0, NULL, 0),
1248SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1249 rmv_short_event,
1250 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1251
1252SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1253SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1254SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1255 SND_SOC_DAPM_POST_PMU),
1256SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1, 2, 0, NULL, 0),
1257SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1258 rmv_short_event,
1259 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1260
1261SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1262SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1263SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1264SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1265SND_SOC_DAPM_OUTPUT("SPKDAT"),
1266};
1267
1268static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1269 { "AIFCLK", NULL, "SYSCLK" },
1270 { "SYSDSPCLK", NULL, "SYSCLK" },
1271 { "Charge Pump", NULL, "SYSCLK" },
4a086e4c 1272 { "Charge Pump", NULL, "CPVDD" },
a9ba6151
MB		 1273
1274 { "MICB1", NULL, "LDO2" },
889c85c5 1275 { "MICB1", NULL, "MICB1 Audio" },
8259df12 1276 { "MICB1", NULL, "Bandgap" },
a9ba6151 1277 { "MICB2", NULL, "LDO2" },
889c85c5 1278 { "MICB2", NULL, "MICB2 Audio" },
8259df12 1279 { "MICB2", NULL, "Bandgap" },
a9ba6151
MB		 1280
1281 { "IN1L PGA", NULL, "IN2LN" },
1282 { "IN1L PGA", NULL, "IN2LP" },
1283 { "IN1L PGA", NULL, "IN1LN" },
1284 { "IN1L PGA", NULL, "IN1LP" },
8259df12 1285 { "IN1L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1286
1287 { "IN1R PGA", NULL, "IN2RN" },
1288 { "IN1R PGA", NULL, "IN2RP" },
1289 { "IN1R PGA", NULL, "IN1RN" },
1290 { "IN1R PGA", NULL, "IN1RP" },
8259df12 1291 { "IN1R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1292
1293 { "ADCL", NULL, "IN1L PGA" },
1294
1295 { "ADCR", NULL, "IN1R PGA" },
1296
1297 { "DMIC1L", NULL, "DMIC1DAT" },
1298 { "DMIC1R", NULL, "DMIC1DAT" },
1299 { "DMIC2L", NULL, "DMIC2DAT" },
1300 { "DMIC2R", NULL, "DMIC2DAT" },
1301
1302 { "DMIC2L", NULL, "DMIC2" },
1303 { "DMIC2R", NULL, "DMIC2" },
1304 { "DMIC1L", NULL, "DMIC1" },
1305 { "DMIC1R", NULL, "DMIC1" },
1306
1307 { "IN1L Mux", "ADC", "ADCL" },
1308 { "IN1L Mux", "DMIC1", "DMIC1L" },
1309 { "IN1L Mux", "DMIC2", "DMIC2L" },
1310
1311 { "IN1R Mux", "ADC", "ADCR" },
1312 { "IN1R Mux", "DMIC1", "DMIC1R" },
1313 { "IN1R Mux", "DMIC2", "DMIC2R" },
1314
1315 { "IN2L Mux", "ADC", "ADCL" },
1316 { "IN2L Mux", "DMIC1", "DMIC1L" },
1317 { "IN2L Mux", "DMIC2", "DMIC2L" },
1318
1319 { "IN2R Mux", "ADC", "ADCR" },
1320 { "IN2R Mux", "DMIC1", "DMIC1R" },
1321 { "IN2R Mux", "DMIC2", "DMIC2R" },
1322
1323 { "Left Sidetone", "IN1", "IN1L Mux" },
1324 { "Left Sidetone", "IN2", "IN2L Mux" },
1325
1326 { "Right Sidetone", "IN1", "IN1R Mux" },
1327 { "Right Sidetone", "IN2", "IN2R Mux" },
1328
1329 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1330 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1331
1332 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1333 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1334
1335 { "AIF1TX0", NULL, "DSP1TXL" },
1336 { "AIF1TX1", NULL, "DSP1TXR" },
1337 { "AIF1TX2", NULL, "DSP2TXL" },
1338 { "AIF1TX3", NULL, "DSP2TXR" },
1339 { "AIF1TX4", NULL, "AIF2RX0" },
1340 { "AIF1TX5", NULL, "AIF2RX1" },
1341
1342 { "AIF1RX0", NULL, "AIFCLK" },
1343 { "AIF1RX1", NULL, "AIFCLK" },
1344 { "AIF1RX2", NULL, "AIFCLK" },
1345 { "AIF1RX3", NULL, "AIFCLK" },
1346 { "AIF1RX4", NULL, "AIFCLK" },
1347 { "AIF1RX5", NULL, "AIFCLK" },
1348
1349 { "AIF2RX0", NULL, "AIFCLK" },
1350 { "AIF2RX1", NULL, "AIFCLK" },
1351
4f41adfd
MB		 1352 { "AIF1TX0", NULL, "AIFCLK" },
1353 { "AIF1TX1", NULL, "AIFCLK" },
1354 { "AIF1TX2", NULL, "AIFCLK" },
1355 { "AIF1TX3", NULL, "AIFCLK" },
1356 { "AIF1TX4", NULL, "AIFCLK" },
1357 { "AIF1TX5", NULL, "AIFCLK" },
1358
1359 { "AIF2TX0", NULL, "AIFCLK" },
1360 { "AIF2TX1", NULL, "AIFCLK" },
1361
a9ba6151
MB		 1362 { "DSP1RXL", NULL, "SYSDSPCLK" },
1363 { "DSP1RXR", NULL, "SYSDSPCLK" },
1364 { "DSP2RXL", NULL, "SYSDSPCLK" },
1365 { "DSP2RXR", NULL, "SYSDSPCLK" },
1366 { "DSP1TXL", NULL, "SYSDSPCLK" },
1367 { "DSP1TXR", NULL, "SYSDSPCLK" },
1368 { "DSP2TXL", NULL, "SYSDSPCLK" },
1369 { "DSP2TXR", NULL, "SYSDSPCLK" },
1370
1371 { "AIF1RXA", NULL, "AIF1RX0" },
1372 { "AIF1RXA", NULL, "AIF1RX1" },
1373 { "AIF1RXB", NULL, "AIF1RX2" },
1374 { "AIF1RXB", NULL, "AIF1RX3" },
1375 { "AIF1RXC", NULL, "AIF1RX4" },
1376 { "AIF1RXC", NULL, "AIF1RX5" },
1377
1378 { "AIF2RX", NULL, "AIF2RX0" },
1379 { "AIF2RX", NULL, "AIF2RX1" },
1380
1381 { "AIF2TX", "DSP2", "DSP2TX" },
1382 { "AIF2TX", "DSP1", "DSP1RX" },
1383 { "AIF2TX", "AIF1", "AIF1RXC" },
1384
1385 { "DSP1RXL", NULL, "DSP1RX" },
1386 { "DSP1RXR", NULL, "DSP1RX" },
1387 { "DSP2RXL", NULL, "DSP2RX" },
1388 { "DSP2RXR", NULL, "DSP2RX" },
1389
1390 { "DSP2TX", NULL, "DSP2TXL" },
1391 { "DSP2TX", NULL, "DSP2TXR" },
1392
1393 { "DSP1RX", "AIF1", "AIF1RXA" },
1394 { "DSP1RX", "AIF2", "AIF2RX" },
1395
1396 { "DSP2RX", "AIF1", "AIF1RXB" },
1397 { "DSP2RX", "AIF2", "AIF2RX" },
1398
1399 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1400 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1401 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1402 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1403
1404 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1405 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1406 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1407 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1408
1409 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1410 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1411 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1412 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1413
1414 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1415 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1416 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1417 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1418
1419 { "DAC1L", NULL, "DAC1L Mixer" },
1420 { "DAC1R", NULL, "DAC1R Mixer" },
1421 { "DAC2L", NULL, "DAC2L Mixer" },
1422 { "DAC2R", NULL, "DAC2R Mixer" },
1423
1424 { "HPOUT2L PGA", NULL, "Charge Pump" },
8259df12 1425 { "HPOUT2L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1426 { "HPOUT2L PGA", NULL, "DAC2L" },
1427 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1428 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1429 { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1430 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1431
1432 { "HPOUT2R PGA", NULL, "Charge Pump" },
8259df12 1433 { "HPOUT2R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1434 { "HPOUT2R PGA", NULL, "DAC2R" },
1435 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1436 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1437 { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1438 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1439
1440 { "HPOUT1L PGA", NULL, "Charge Pump" },
8259df12 1441 { "HPOUT1L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1442 { "HPOUT1L PGA", NULL, "DAC1L" },
1443 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1444 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1445 { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1446 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1447
1448 { "HPOUT1R PGA", NULL, "Charge Pump" },
8259df12 1449 { "HPOUT1R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1450 { "HPOUT1R PGA", NULL, "DAC1R" },
1451 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1452 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1453 { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1454 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1455
1456 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1457 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1458 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1459 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1460
1461 { "SPKL", "DAC1L", "DAC1L" },
1462 { "SPKL", "DAC1R", "DAC1R" },
1463 { "SPKL", "DAC2L", "DAC2L" },
1464 { "SPKL", "DAC2R", "DAC2R" },
1465
1466 { "SPKR", "DAC1L", "DAC1L" },
1467 { "SPKR", "DAC1R", "DAC1R" },
1468 { "SPKR", "DAC2L", "DAC2L" },
1469 { "SPKR", "DAC2R", "DAC2R" },
1470
1471 { "SPKL PGA", NULL, "SPKL" },
1472 { "SPKR PGA", NULL, "SPKR" },
1473
1474 { "SPKDAT", NULL, "SPKL PGA" },
1475 { "SPKDAT", NULL, "SPKR PGA" },
1476};
1477
79172746 1478static bool wm8996_readable_register(struct device *dev, unsigned int reg)
a9ba6151
MB		 1479{
1480 /* Due to the sparseness of the register map the compiler
1481 * output from an explicit switch statement ends up being much
1482 * more efficient than a table.
1483 */
1484 switch (reg) {
1485 case WM8996_SOFTWARE_RESET:
1486 case WM8996_POWER_MANAGEMENT_1:
1487 case WM8996_POWER_MANAGEMENT_2:
1488 case WM8996_POWER_MANAGEMENT_3:
1489 case WM8996_POWER_MANAGEMENT_4:
1490 case WM8996_POWER_MANAGEMENT_5:
1491 case WM8996_POWER_MANAGEMENT_6:
1492 case WM8996_POWER_MANAGEMENT_7:
1493 case WM8996_POWER_MANAGEMENT_8:
1494 case WM8996_LEFT_LINE_INPUT_VOLUME:
1495 case WM8996_RIGHT_LINE_INPUT_VOLUME:
1496 case WM8996_LINE_INPUT_CONTROL:
1497 case WM8996_DAC1_HPOUT1_VOLUME:
1498 case WM8996_DAC2_HPOUT2_VOLUME:
1499 case WM8996_DAC1_LEFT_VOLUME:
1500 case WM8996_DAC1_RIGHT_VOLUME:
1501 case WM8996_DAC2_LEFT_VOLUME:
1502 case WM8996_DAC2_RIGHT_VOLUME:
1503 case WM8996_OUTPUT1_LEFT_VOLUME:
1504 case WM8996_OUTPUT1_RIGHT_VOLUME:
1505 case WM8996_OUTPUT2_LEFT_VOLUME:
1506 case WM8996_OUTPUT2_RIGHT_VOLUME:
1507 case WM8996_MICBIAS_1:
1508 case WM8996_MICBIAS_2:
1509 case WM8996_LDO_1:
1510 case WM8996_LDO_2:
1511 case WM8996_ACCESSORY_DETECT_MODE_1:
1512 case WM8996_ACCESSORY_DETECT_MODE_2:
1513 case WM8996_HEADPHONE_DETECT_1:
1514 case WM8996_HEADPHONE_DETECT_2:
1515 case WM8996_MIC_DETECT_1:
1516 case WM8996_MIC_DETECT_2:
1517 case WM8996_MIC_DETECT_3:
1518 case WM8996_CHARGE_PUMP_1:
1519 case WM8996_CHARGE_PUMP_2:
1520 case WM8996_DC_SERVO_1:
1521 case WM8996_DC_SERVO_2:
1522 case WM8996_DC_SERVO_3:
1523 case WM8996_DC_SERVO_5:
1524 case WM8996_DC_SERVO_6:
1525 case WM8996_DC_SERVO_7:
1526 case WM8996_DC_SERVO_READBACK_0:
1527 case WM8996_ANALOGUE_HP_1:
1528 case WM8996_ANALOGUE_HP_2:
1529 case WM8996_CHIP_REVISION:
1530 case WM8996_CONTROL_INTERFACE_1:
1531 case WM8996_WRITE_SEQUENCER_CTRL_1:
1532 case WM8996_WRITE_SEQUENCER_CTRL_2:
1533 case WM8996_AIF_CLOCKING_1:
1534 case WM8996_AIF_CLOCKING_2:
1535 case WM8996_CLOCKING_1:
1536 case WM8996_CLOCKING_2:
1537 case WM8996_AIF_RATE:
1538 case WM8996_FLL_CONTROL_1:
1539 case WM8996_FLL_CONTROL_2:
1540 case WM8996_FLL_CONTROL_3:
1541 case WM8996_FLL_CONTROL_4:
1542 case WM8996_FLL_CONTROL_5:
1543 case WM8996_FLL_CONTROL_6:
1544 case WM8996_FLL_EFS_1:
1545 case WM8996_FLL_EFS_2:
1546 case WM8996_AIF1_CONTROL:
1547 case WM8996_AIF1_BCLK:
1548 case WM8996_AIF1_TX_LRCLK_1:
1549 case WM8996_AIF1_TX_LRCLK_2:
1550 case WM8996_AIF1_RX_LRCLK_1:
1551 case WM8996_AIF1_RX_LRCLK_2:
1552 case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1553 case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1554 case WM8996_AIF1RX_DATA_CONFIGURATION:
1555 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1556 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1557 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1558 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1559 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1560 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1561 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1562 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1563 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1564 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1565 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1566 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1567 case WM8996_AIF1RX_MONO_CONFIGURATION:
1568 case WM8996_AIF1TX_TEST:
1569 case WM8996_AIF2_CONTROL:
1570 case WM8996_AIF2_BCLK:
1571 case WM8996_AIF2_TX_LRCLK_1:
1572 case WM8996_AIF2_TX_LRCLK_2:
1573 case WM8996_AIF2_RX_LRCLK_1:
1574 case WM8996_AIF2_RX_LRCLK_2:
1575 case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1576 case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1577 case WM8996_AIF2RX_DATA_CONFIGURATION:
1578 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1579 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1580 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1581 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1582 case WM8996_AIF2RX_MONO_CONFIGURATION:
1583 case WM8996_AIF2TX_TEST:
1584 case WM8996_DSP1_TX_LEFT_VOLUME:
1585 case WM8996_DSP1_TX_RIGHT_VOLUME:
1586 case WM8996_DSP1_RX_LEFT_VOLUME:
1587 case WM8996_DSP1_RX_RIGHT_VOLUME:
1588 case WM8996_DSP1_TX_FILTERS:
1589 case WM8996_DSP1_RX_FILTERS_1:
1590 case WM8996_DSP1_RX_FILTERS_2:
1591 case WM8996_DSP1_DRC_1:
1592 case WM8996_DSP1_DRC_2:
1593 case WM8996_DSP1_DRC_3:
1594 case WM8996_DSP1_DRC_4:
1595 case WM8996_DSP1_DRC_5:
1596 case WM8996_DSP1_RX_EQ_GAINS_1:
1597 case WM8996_DSP1_RX_EQ_GAINS_2:
1598 case WM8996_DSP1_RX_EQ_BAND_1_A:
1599 case WM8996_DSP1_RX_EQ_BAND_1_B:
1600 case WM8996_DSP1_RX_EQ_BAND_1_PG:
1601 case WM8996_DSP1_RX_EQ_BAND_2_A:
1602 case WM8996_DSP1_RX_EQ_BAND_2_B:
1603 case WM8996_DSP1_RX_EQ_BAND_2_C:
1604 case WM8996_DSP1_RX_EQ_BAND_2_PG:
1605 case WM8996_DSP1_RX_EQ_BAND_3_A:
1606 case WM8996_DSP1_RX_EQ_BAND_3_B:
1607 case WM8996_DSP1_RX_EQ_BAND_3_C:
1608 case WM8996_DSP1_RX_EQ_BAND_3_PG:
1609 case WM8996_DSP1_RX_EQ_BAND_4_A:
1610 case WM8996_DSP1_RX_EQ_BAND_4_B:
1611 case WM8996_DSP1_RX_EQ_BAND_4_C:
1612 case WM8996_DSP1_RX_EQ_BAND_4_PG:
1613 case WM8996_DSP1_RX_EQ_BAND_5_A:
1614 case WM8996_DSP1_RX_EQ_BAND_5_B:
1615 case WM8996_DSP1_RX_EQ_BAND_5_PG:
1616 case WM8996_DSP2_TX_LEFT_VOLUME:
1617 case WM8996_DSP2_TX_RIGHT_VOLUME:
1618 case WM8996_DSP2_RX_LEFT_VOLUME:
1619 case WM8996_DSP2_RX_RIGHT_VOLUME:
1620 case WM8996_DSP2_TX_FILTERS:
1621 case WM8996_DSP2_RX_FILTERS_1:
1622 case WM8996_DSP2_RX_FILTERS_2:
1623 case WM8996_DSP2_DRC_1:
1624 case WM8996_DSP2_DRC_2:
1625 case WM8996_DSP2_DRC_3:
1626 case WM8996_DSP2_DRC_4:
1627 case WM8996_DSP2_DRC_5:
1628 case WM8996_DSP2_RX_EQ_GAINS_1:
1629 case WM8996_DSP2_RX_EQ_GAINS_2:
1630 case WM8996_DSP2_RX_EQ_BAND_1_A:
1631 case WM8996_DSP2_RX_EQ_BAND_1_B:
1632 case WM8996_DSP2_RX_EQ_BAND_1_PG:
1633 case WM8996_DSP2_RX_EQ_BAND_2_A:
1634 case WM8996_DSP2_RX_EQ_BAND_2_B:
1635 case WM8996_DSP2_RX_EQ_BAND_2_C:
1636 case WM8996_DSP2_RX_EQ_BAND_2_PG:
1637 case WM8996_DSP2_RX_EQ_BAND_3_A:
1638 case WM8996_DSP2_RX_EQ_BAND_3_B:
1639 case WM8996_DSP2_RX_EQ_BAND_3_C:
1640 case WM8996_DSP2_RX_EQ_BAND_3_PG:
1641 case WM8996_DSP2_RX_EQ_BAND_4_A:
1642 case WM8996_DSP2_RX_EQ_BAND_4_B:
1643 case WM8996_DSP2_RX_EQ_BAND_4_C:
1644 case WM8996_DSP2_RX_EQ_BAND_4_PG:
1645 case WM8996_DSP2_RX_EQ_BAND_5_A:
1646 case WM8996_DSP2_RX_EQ_BAND_5_B:
1647 case WM8996_DSP2_RX_EQ_BAND_5_PG:
1648 case WM8996_DAC1_MIXER_VOLUMES:
1649 case WM8996_DAC1_LEFT_MIXER_ROUTING:
1650 case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1651 case WM8996_DAC2_MIXER_VOLUMES:
1652 case WM8996_DAC2_LEFT_MIXER_ROUTING:
1653 case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1654 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1655 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1656 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1657 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1658 case WM8996_DSP_TX_MIXER_SELECT:
1659 case WM8996_DAC_SOFTMUTE:
1660 case WM8996_OVERSAMPLING:
1661 case WM8996_SIDETONE:
1662 case WM8996_GPIO_1:
1663 case WM8996_GPIO_2:
1664 case WM8996_GPIO_3:
1665 case WM8996_GPIO_4:
1666 case WM8996_GPIO_5:
1667 case WM8996_PULL_CONTROL_1:
1668 case WM8996_PULL_CONTROL_2:
1669 case WM8996_INTERRUPT_STATUS_1:
1670 case WM8996_INTERRUPT_STATUS_2:
1671 case WM8996_INTERRUPT_RAW_STATUS_2:
1672 case WM8996_INTERRUPT_STATUS_1_MASK:
1673 case WM8996_INTERRUPT_STATUS_2_MASK:
1674 case WM8996_INTERRUPT_CONTROL:
1675 case WM8996_LEFT_PDM_SPEAKER:
1676 case WM8996_RIGHT_PDM_SPEAKER:
1677 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1678 case WM8996_PDM_SPEAKER_VOLUME:
1679 return 1;
1680 default:
1681 return 0;
1682 }
1683}
1684
79172746 1685static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
a9ba6151
MB		 1686{
1687 switch (reg) {
1688 case WM8996_SOFTWARE_RESET:
1689 case WM8996_CHIP_REVISION:
1690 case WM8996_LDO_1:
1691 case WM8996_LDO_2:
1692 case WM8996_INTERRUPT_STATUS_1:
1693 case WM8996_INTERRUPT_STATUS_2:
1694 case WM8996_INTERRUPT_RAW_STATUS_2:
1695 case WM8996_DC_SERVO_READBACK_0:
1696 case WM8996_DC_SERVO_2:
1697 case WM8996_DC_SERVO_6:
1698 case WM8996_DC_SERVO_7:
1699 case WM8996_FLL_CONTROL_6:
1700 case WM8996_MIC_DETECT_3:
1701 case WM8996_HEADPHONE_DETECT_1:
1702 case WM8996_HEADPHONE_DETECT_2:
1703 return 1;
1704 default:
1705 return 0;
1706 }
1707}
1708
ee5f3872 1709static int wm8996_reset(struct wm8996_priv *wm8996)
a9ba6151 1710{
ee5f3872 1711 if (wm8996->pdata.ldo_ena > 0) {
d5a7f23f 1712 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
ee5f3872
MB		 1713 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1714 return 0;
1715 } else {
1716 return regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET,
1717 0x8915);
1718 }
a9ba6151
MB		 1719}
1720
1721static const int bclk_divs[] = {
1722 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1723};
1724
1725static void wm8996_update_bclk(struct snd_soc_codec *codec)
1726{
1727 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1728 int aif, best, cur_val, bclk_rate, bclk_reg, i;
1729
1730 /* Don't bother if we're in a low frequency idle mode that
1731 * can't support audio.
1732 */
1733 if (wm8996->sysclk < 64000)
1734 return;
1735
1736 for (aif = 0; aif < WM8996_AIFS; aif++) {
1737 switch (aif) {
1738 case 0:
1739 bclk_reg = WM8996_AIF1_BCLK;
1740 break;
1741 case 1:
1742 bclk_reg = WM8996_AIF2_BCLK;
1743 break;
1744 }
1745
1746 bclk_rate = wm8996->bclk_rate[aif];
1747
1748 /* Pick a divisor for BCLK as close as we can get to ideal */
1749 best = 0;
1750 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1751 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1752 if (cur_val < 0) /* BCLK table is sorted */
1753 break;
1754 best = i;
1755 }
1756 bclk_rate = wm8996->sysclk / bclk_divs[best];
1757 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1758 bclk_divs[best], bclk_rate);
1759
1760 snd_soc_update_bits(codec, bclk_reg,
1761 WM8996_AIF1_BCLK_DIV_MASK, best);
1762 }
1763}
1764
1765static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1766 enum snd_soc_bias_level level)
1767{
1768 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1769 int ret;
1770
1771 switch (level) {
1772 case SND_SOC_BIAS_ON:
a9ba6151 1773 case SND_SOC_BIAS_PREPARE:
a9ba6151
MB		 1774 break;
1775
1776 case SND_SOC_BIAS_STANDBY:
1777 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1778 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1779 wm8996->supplies);
1780 if (ret != 0) {
1781 dev_err(codec->dev,
1782 "Failed to enable supplies: %d\n",
1783 ret);
1784 return ret;
1785 }
1786
1787 if (wm8996->pdata.ldo_ena >= 0) {
1788 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1789 1);
1790 msleep(5);
1791 }
1792
79172746
MB		 1793 regcache_cache_only(codec->control_data, false);
1794 regcache_sync(codec->control_data);
a9ba6151 1795 }
a9ba6151
MB		 1796 break;
1797
1798 case SND_SOC_BIAS_OFF:
79172746 1799 regcache_cache_only(codec->control_data, true);
a9ba6151
MB		 1800 if (wm8996->pdata.ldo_ena >= 0)
1801 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1802 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1803 wm8996->supplies);
1804 break;
1805 }
1806
1807 codec->dapm.bias_level = level;
1808
1809 return 0;
1810}
1811
1812static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1813{
1814 struct snd_soc_codec *codec = dai->codec;
1815 int aifctrl = 0;
1816 int bclk = 0;
1817 int lrclk_tx = 0;
1818 int lrclk_rx = 0;
1819 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1820
1821 switch (dai->id) {
1822 case 0:
1823 aifctrl_reg = WM8996_AIF1_CONTROL;
1824 bclk_reg = WM8996_AIF1_BCLK;
1825 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1826 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1827 break;
1828 case 1:
1829 aifctrl_reg = WM8996_AIF2_CONTROL;
1830 bclk_reg = WM8996_AIF2_BCLK;
1831 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1832 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1833 break;
1834 default:
1835 BUG();
1836 return -EINVAL;
1837 }
1838
1839 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1840 case SND_SOC_DAIFMT_NB_NF:
1841 break;
1842 case SND_SOC_DAIFMT_IB_NF:
1843 bclk |= WM8996_AIF1_BCLK_INV;
1844 break;
1845 case SND_SOC_DAIFMT_NB_IF:
1846 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1847 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1848 break;
1849 case SND_SOC_DAIFMT_IB_IF:
1850 bclk |= WM8996_AIF1_BCLK_INV;
1851 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1852 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1853 break;
1854 }
1855
1856 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1857 case SND_SOC_DAIFMT_CBS_CFS:
1858 break;
1859 case SND_SOC_DAIFMT_CBS_CFM:
1860 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1861 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1862 break;
1863 case SND_SOC_DAIFMT_CBM_CFS:
1864 bclk |= WM8996_AIF1_BCLK_MSTR;
1865 break;
1866 case SND_SOC_DAIFMT_CBM_CFM:
1867 bclk |= WM8996_AIF1_BCLK_MSTR;
1868 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1869 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1870 break;
1871 default:
1872 return -EINVAL;
1873 }
1874
1875 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1876 case SND_SOC_DAIFMT_DSP_A:
1877 break;
1878 case SND_SOC_DAIFMT_DSP_B:
1879 aifctrl |= 1;
1880 break;
1881 case SND_SOC_DAIFMT_I2S:
1882 aifctrl |= 2;
1883 break;
1884 case SND_SOC_DAIFMT_LEFT_J:
1885 aifctrl |= 3;
1886 break;
1887 default:
1888 return -EINVAL;
1889 }
1890
1891 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1892 snd_soc_update_bits(codec, bclk_reg,
1893 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1894 bclk);
1895 snd_soc_update_bits(codec, lrclk_tx_reg,
1896 WM8996_AIF1TX_LRCLK_INV |
1897 WM8996_AIF1TX_LRCLK_MSTR,
1898 lrclk_tx);
1899 snd_soc_update_bits(codec, lrclk_rx_reg,
1900 WM8996_AIF1RX_LRCLK_INV |
1901 WM8996_AIF1RX_LRCLK_MSTR,
1902 lrclk_rx);
1903
1904 return 0;
1905}
1906
1907static const int dsp_divs[] = {
1908 48000, 32000, 16000, 8000
1909};
1910
1911static int wm8996_hw_params(struct snd_pcm_substream *substream,
1912 struct snd_pcm_hw_params *params,
1913 struct snd_soc_dai *dai)
1914{
1915 struct snd_soc_codec *codec = dai->codec;
1916 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1917 int bits, i, bclk_rate;
1918 int aifdata = 0;
1919 int lrclk = 0;
1920 int dsp = 0;
1921 int aifdata_reg, lrclk_reg, dsp_shift;
1922
1923 switch (dai->id) {
1924 case 0:
1925 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1926 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1927 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1928 lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1929 } else {
1930 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1931 lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1932 }
1933 dsp_shift = 0;
1934 break;
1935 case 1:
1936 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1937 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1938 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1939 lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1940 } else {
1941 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1942 lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1943 }
1944 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1945 break;
1946 default:
1947 BUG();
1948 return -EINVAL;
1949 }
1950
1951 bclk_rate = snd_soc_params_to_bclk(params);
1952 if (bclk_rate < 0) {
1953 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1954 return bclk_rate;
1955 }
1956
1957 wm8996->bclk_rate[dai->id] = bclk_rate;
1958 wm8996->rx_rate[dai->id] = params_rate(params);
1959
1960 /* Needs looking at for TDM */
1961 bits = snd_pcm_format_width(params_format(params));
1962 if (bits < 0)
1963 return bits;
1964 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1965
1966 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1967 if (dsp_divs[i] == params_rate(params))
1968 break;
1969 }
1970 if (i == ARRAY_SIZE(dsp_divs)) {
1971 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1972 params_rate(params));
1973 return -EINVAL;
1974 }
1975 dsp |= i << dsp_shift;
1976
1977 wm8996_update_bclk(codec);
1978
1979 lrclk = bclk_rate / params_rate(params);
1980 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1981 lrclk, bclk_rate / lrclk);
1982
1983 snd_soc_update_bits(codec, aifdata_reg,
1984 WM8996_AIF1TX_WL_MASK |
1985 WM8996_AIF1TX_SLOT_LEN_MASK,
1986 aifdata);
1987 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1988 lrclk);
1989 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
3205e662 1990 WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
a9ba6151
MB		 1991
1992 return 0;
1993}
1994
1995static int wm8996_set_sysclk(struct snd_soc_dai *dai,
1996 int clk_id, unsigned int freq, int dir)
1997{
1998 struct snd_soc_codec *codec = dai->codec;
1999 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2000 int lfclk = 0;
2001 int ratediv = 0;
fed22007 2002 int sync = WM8996_REG_SYNC;
a9ba6151
MB		 2003 int src;
2004 int old;
2005
2006 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
2007 return 0;
2008
2009 /* Disable SYSCLK while we reconfigure */
2010 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
2011 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2012 WM8996_SYSCLK_ENA, 0);
2013
2014 switch (clk_id) {
2015 case WM8996_SYSCLK_MCLK1:
2016 wm8996->sysclk = freq;
2017 src = 0;
2018 break;
2019 case WM8996_SYSCLK_MCLK2:
2020 wm8996->sysclk = freq;
2021 src = 1;
2022 break;
2023 case WM8996_SYSCLK_FLL:
2024 wm8996->sysclk = freq;
2025 src = 2;
2026 break;
2027 default:
2028 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
2029 return -EINVAL;
2030 }
2031
2032 switch (wm8996->sysclk) {
2033 case 6144000:
2034 snd_soc_update_bits(codec, WM8996_AIF_RATE,
2035 WM8996_SYSCLK_RATE, 0);
2036 break;
2037 case 24576000:
2038 ratediv = WM8996_SYSCLK_DIV;
37d5993c 2039 wm8996->sysclk /= 2;
a9ba6151
MB		 2040 case 12288000:
2041 snd_soc_update_bits(codec, WM8996_AIF_RATE,
2042 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
2043 break;
2044 case 32000:
2045 case 32768:
2046 lfclk = WM8996_LFCLK_ENA;
fed22007 2047 sync = 0;
a9ba6151
MB		 2048 break;
2049 default:
2050 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
2051 wm8996->sysclk);
2052 return -EINVAL;
2053 }
2054
2055 wm8996_update_bclk(codec);
2056
2057 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2058 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
2059 src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
2060 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
fed22007
MB		 2061 snd_soc_update_bits(codec, WM8996_CONTROL_INTERFACE_1,
2062 WM8996_REG_SYNC, sync);
a9ba6151
MB		 2063 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2064 WM8996_SYSCLK_ENA, old);
2065
2066 wm8996->sysclk_src = clk_id;
2067
2068 return 0;
2069}
2070
2071struct _fll_div {
2072 u16 fll_fratio;
2073 u16 fll_outdiv;
2074 u16 fll_refclk_div;
2075 u16 fll_loop_gain;
2076 u16 fll_ref_freq;
2077 u16 n;
2078 u16 theta;
2079 u16 lambda;
2080};
2081
2082static struct {
2083 unsigned int min;
2084 unsigned int max;
2085 u16 fll_fratio;
2086 int ratio;
2087} fll_fratios[] = {
2088 { 0, 64000, 4, 16 },
2089 { 64000, 128000, 3, 8 },
2090 { 128000, 256000, 2, 4 },
2091 { 256000, 1000000, 1, 2 },
2092 { 1000000, 13500000, 0, 1 },
2093};
2094
2095static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2096 unsigned int Fout)
2097{
2098 unsigned int target;
2099 unsigned int div;
2100 unsigned int fratio, gcd_fll;
2101 int i;
2102
2103 /* Fref must be <=13.5MHz */
2104 div = 1;
2105 fll_div->fll_refclk_div = 0;
2106 while ((Fref / div) > 13500000) {
2107 div *= 2;
2108 fll_div->fll_refclk_div++;
2109
2110 if (div > 8) {
2111 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2112 Fref);
2113 return -EINVAL;
2114 }
2115 }
2116
2117 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2118
2119 /* Apply the division for our remaining calculations */
2120 Fref /= div;
2121
2122 if (Fref >= 3000000)
2123 fll_div->fll_loop_gain = 5;
2124 else
2125 fll_div->fll_loop_gain = 0;
2126
2127 if (Fref >= 48000)
2128 fll_div->fll_ref_freq = 0;
2129 else
2130 fll_div->fll_ref_freq = 1;
2131
2132 /* Fvco should be 90-100MHz; don't check the upper bound */
2133 div = 2;
2134 while (Fout * div < 90000000) {
2135 div++;
2136 if (div > 64) {
2137 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2138 Fout);
2139 return -EINVAL;
2140 }
2141 }
2142 target = Fout * div;
2143 fll_div->fll_outdiv = div - 1;
2144
2145 pr_debug("FLL Fvco=%dHz\n", target);
2146
2147 /* Find an appropraite FLL_FRATIO and factor it out of the target */
2148 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2149 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2150 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2151 fratio = fll_fratios[i].ratio;
2152 break;
2153 }
2154 }
2155 if (i == ARRAY_SIZE(fll_fratios)) {
2156 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2157 return -EINVAL;
2158 }
2159
2160 fll_div->n = target / (fratio * Fref);
2161
2162 if (target % Fref == 0) {
2163 fll_div->theta = 0;
2164 fll_div->lambda = 0;
2165 } else {
2166 gcd_fll = gcd(target, fratio * Fref);
2167
2168 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2169 / gcd_fll;
2170 fll_div->lambda = (fratio * Fref) / gcd_fll;
2171 }
2172
2173 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2174 fll_div->n, fll_div->theta, fll_div->lambda);
2175 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2176 fll_div->fll_fratio, fll_div->fll_outdiv,
2177 fll_div->fll_refclk_div);
2178
2179 return 0;
2180}
2181
2182static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2183 unsigned int Fref, unsigned int Fout)
2184{
2185 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2186 struct i2c_client *i2c = to_i2c_client(codec->dev);
2187 struct _fll_div fll_div;
2188 unsigned long timeout;
27b6d92a 2189 int ret, reg, retry;
a9ba6151
MB		 2190
2191 /* Any change? */
2192 if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2193 Fout == wm8996->fll_fout)
2194 return 0;
2195
2196 if (Fout == 0) {
2197 dev_dbg(codec->dev, "FLL disabled\n");
2198
2199 wm8996->fll_fref = 0;
2200 wm8996->fll_fout = 0;
2201
2202 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2203 WM8996_FLL_ENA, 0);
2204
ded71dcb
MB		 2205 wm8996_bg_disable(codec);
2206
a9ba6151
MB		 2207 return 0;
2208 }
2209
2210 ret = fll_factors(&fll_div, Fref, Fout);
2211 if (ret != 0)
2212 return ret;
2213
2214 switch (source) {
2215 case WM8996_FLL_MCLK1:
2216 reg = 0;
2217 break;
2218 case WM8996_FLL_MCLK2:
2219 reg = 1;
2220 break;
2221 case WM8996_FLL_DACLRCLK1:
2222 reg = 2;
2223 break;
2224 case WM8996_FLL_BCLK1:
2225 reg = 3;
2226 break;
2227 default:
2228 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2229 return -EINVAL;
2230 }
2231
2232 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2233 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2234
2235 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2236 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2237 WM8996_FLL_REFCLK_SRC_MASK, reg);
2238
2239 reg = 0;
2240 if (fll_div.theta || fll_div.lambda)
2241 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2242 else
2243 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2244 snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2245
2246 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2247 WM8996_FLL_OUTDIV_MASK |
2248 WM8996_FLL_FRATIO_MASK,
2249 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2250 (fll_div.fll_fratio));
2251
2252 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2253
2254 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2255 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2256 (fll_div.n << WM8996_FLL_N_SHIFT) |
2257 fll_div.fll_loop_gain);
2258
2259 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2260
ded71dcb
MB		 2261 /* Enable the bandgap if it's not already enabled */
2262 ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1);
2263 if (!(ret & WM8996_FLL_ENA))
2264 wm8996_bg_enable(codec);
2265
a4161945
MB		 2266 /* Clear any pending completions (eg, from failed startups) */
2267 try_wait_for_completion(&wm8996->fll_lock);
2268
a9ba6151
MB		 2269 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2270 WM8996_FLL_ENA, WM8996_FLL_ENA);
2271
2272 /* The FLL supports live reconfiguration - kick that in case we were
2273 * already enabled.
2274 */
2275 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2276
2277 /* Wait for the FLL to lock, using the interrupt if possible */
2278 if (Fref > 1000000)
2279 timeout = usecs_to_jiffies(300);
2280 else
2281 timeout = msecs_to_jiffies(2);
2282
27b6d92a
MB		 2283 /* Allow substantially longer if we've actually got the IRQ, poll
2284 * at a slightly higher rate if we don't.
2285 */
a9ba6151 2286 if (i2c->irq)
27b6d92a
MB		 2287 timeout *= 10;
2288 else
2289 timeout /= 2;
a9ba6151 2290
27b6d92a
MB		 2291 for (retry = 0; retry < 10; retry++) {
2292 ret = wait_for_completion_timeout(&wm8996->fll_lock,
2293 timeout);
2294 if (ret != 0) {
2295 WARN_ON(!i2c->irq);
2296 break;
2297 }
a9ba6151 2298
27b6d92a
MB		 2299 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2);
2300 if (ret & WM8996_FLL_LOCK_STS)
2301 break;
2302 }
2303 if (retry == 10) {
a9ba6151
MB		 2304 dev_err(codec->dev, "Timed out waiting for FLL\n");
2305 ret = -ETIMEDOUT;
a9ba6151
MB		 2306 }
2307
2308 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2309
2310 wm8996->fll_fref = Fref;
2311 wm8996->fll_fout = Fout;
2312 wm8996->fll_src = source;
2313
2314 return ret;
2315}
2316
2317#ifdef CONFIG_GPIOLIB
2318static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2319{
2320 return container_of(chip, struct wm8996_priv, gpio_chip);
2321}
2322
2323static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2324{
2325 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
a9ba6151 2326
b2d1e233
MB		 2327 regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2328 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
a9ba6151
MB		 2329}
2330
2331static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2332 unsigned offset, int value)
2333{
2334 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
a9ba6151
MB		 2335 int val;
2336
2337 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2338
b2d1e233
MB		 2339 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2340 WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2341 WM8996_GP1_LVL, val);
a9ba6151
MB		 2342}
2343
2344static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2345{
2346 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
b2d1e233 2347 unsigned int reg;
a9ba6151
MB		 2348 int ret;
2349
b2d1e233 2350 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, &reg);
a9ba6151
MB		 2351 if (ret < 0)
2352 return ret;
2353
b2d1e233 2354 return (reg & WM8996_GP1_LVL) != 0;
a9ba6151
MB		 2355}
2356
2357static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2358{
2359 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
a9ba6151 2360
b2d1e233
MB		 2361 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2362 WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2363 (1 << WM8996_GP1_FN_SHIFT) |
2364 (1 << WM8996_GP1_DIR_SHIFT));
a9ba6151
MB		 2365}
2366
2367static struct gpio_chip wm8996_template_chip = {
2368 .label = "wm8996",
2369 .owner = THIS_MODULE,
2370 .direction_output = wm8996_gpio_direction_out,
2371 .set = wm8996_gpio_set,
2372 .direction_input = wm8996_gpio_direction_in,
2373 .get = wm8996_gpio_get,
2374 .can_sleep = 1,
2375};
2376
b2d1e233 2377static void wm8996_init_gpio(struct wm8996_priv *wm8996)
a9ba6151 2378{
a9ba6151
MB		 2379 int ret;
2380
2381 wm8996->gpio_chip = wm8996_template_chip;
2382 wm8996->gpio_chip.ngpio = 5;
b2d1e233 2383 wm8996->gpio_chip.dev = wm8996->dev;
a9ba6151
MB		 2384
2385 if (wm8996->pdata.gpio_base)
2386 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2387 else
2388 wm8996->gpio_chip.base = -1;
2389
2390 ret = gpiochip_add(&wm8996->gpio_chip);
2391 if (ret != 0)
b2d1e233 2392 dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret);
a9ba6151
MB		 2393}
2394
b2d1e233 2395static void wm8996_free_gpio(struct wm8996_priv *wm8996)
a9ba6151 2396{
a9ba6151
MB		 2397 int ret;
2398
2399 ret = gpiochip_remove(&wm8996->gpio_chip);
2400 if (ret != 0)
b2d1e233 2401 dev_err(wm8996->dev, "Failed to remove GPIOs: %d\n", ret);
a9ba6151
MB		 2402}
2403#else
b2d1e233 2404static void wm8996_init_gpio(struct wm8996_priv *wm8996)
a9ba6151
MB		 2405{
2406}
2407
b2d1e233 2408static void wm8996_free_gpio(struct wm8996_priv *wm8996)
a9ba6151
MB		 2409{
2410}
2411#endif
2412
2413/**
2414 * wm8996_detect - Enable default WM8996 jack detection
2415 *
2416 * The WM8996 has advanced accessory detection support for headsets.
2417 * This function provides a default implementation which integrates
2418 * the majority of this functionality with minimal user configuration.
2419 *
2420 * This will detect headset, headphone and short circuit button and
2421 * will also detect inverted microphone ground connections and update
2422 * the polarity of the connections.
2423 */
2424int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2425 wm8996_polarity_fn polarity_cb)
2426{
2427 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2428
2429 wm8996->jack = jack;
2430 wm8996->detecting = true;
2431 wm8996->polarity_cb = polarity_cb;
d7b35570 2432 wm8996->jack_flips = 0;
a9ba6151
MB		 2433
2434 if (wm8996->polarity_cb)
2435 wm8996->polarity_cb(codec, 0);
2436
2437 /* Clear discarge to avoid noise during detection */
2438 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2439 WM8996_MICB1_DISCH, 0);
2440 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2441 WM8996_MICB2_DISCH, 0);
2442
2443 /* LDO2 powers the microphones, SYSCLK clocks detection */
2444 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2445 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2446
2447 /* We start off just enabling microphone detection - even a
2448 * plain headphone will trigger detection.
2449 */
2450 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2451 WM8996_MICD_ENA, WM8996_MICD_ENA);
2452
2453 /* Slowest detection rate, gives debounce for initial detection */
2454 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2455 WM8996_MICD_RATE_MASK,
2456 WM8996_MICD_RATE_MASK);
2457
2458 /* Enable interrupts and we're off */
2459 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
0b684cc1 2460 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
a9ba6151
MB		 2461
2462 return 0;
2463}
2464EXPORT_SYMBOL_GPL(wm8996_detect);
2465
0b684cc1
MB		 2466static void wm8996_hpdet_irq(struct snd_soc_codec *codec)
2467{
2468 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2469 int val, reg, report;
2470
2471 /* Assume headphone in error conditions; we need to report
2472 * something or we stall our state machine.
2473 */
2474 report = SND_JACK_HEADPHONE;
2475
2476 reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2);
2477 if (reg < 0) {
2478 dev_err(codec->dev, "Failed to read HPDET status\n");
2479 goto out;
2480 }
2481
2482 if (!(reg & WM8996_HP_DONE)) {
2483 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n");
2484 goto out;
2485 }
2486
2487 val = reg & WM8996_HP_LVL_MASK;
2488
2489 dev_dbg(codec->dev, "HPDET measured %d ohms\n", val);
2490
2491 /* If we've got high enough impedence then report as line,
2492 * otherwise assume headphone.
2493 */
2494 if (val >= 126)
2495 report = SND_JACK_LINEOUT;
2496 else
2497 report = SND_JACK_HEADPHONE;
2498
2499out:
2500 if (wm8996->jack_mic)
2501 report |= SND_JACK_MICROPHONE;
2502
2503 snd_soc_jack_report(wm8996->jack, report,
2504 SND_JACK_LINEOUT | SND_JACK_HEADSET);
2505
2506 wm8996->detecting = false;
2507
2508 /* If the output isn't running re-clamp it */
2509 if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) &
2510 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
2511 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2512 WM8996_HPOUT1L_RMV_SHORT |
2513 WM8996_HPOUT1R_RMV_SHORT, 0);
2514
2515 /* Go back to looking at the microphone */
2516 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2517 WM8996_JD_MODE_MASK, 0);
2518 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
2519 WM8996_MICD_ENA);
2520
2521 snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap");
2522 snd_soc_dapm_sync(&codec->dapm);
2523}
2524
2525static void wm8996_hpdet_start(struct snd_soc_codec *codec)
2526{
2527 /* Unclamp the output, we can't measure while we're shorting it */
2528 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2529 WM8996_HPOUT1L_RMV_SHORT |
2530 WM8996_HPOUT1R_RMV_SHORT,
2531 WM8996_HPOUT1L_RMV_SHORT |
2532 WM8996_HPOUT1R_RMV_SHORT);
2533
2534 /* We need bandgap for HPDET */
2535 snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap");
2536 snd_soc_dapm_sync(&codec->dapm);
2537
2538 /* Go into headphone detect left mode */
2539 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
2540 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2541 WM8996_JD_MODE_MASK, 1);
2542
2543 /* Trigger a measurement */
2544 snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1,
2545 WM8996_HP_POLL, WM8996_HP_POLL);
2546}
2547
d7b35570
MB		 2548static void wm8996_report_headphone(struct snd_soc_codec *codec)
2549{
2550 dev_dbg(codec->dev, "Headphone detected\n");
2551 wm8996_hpdet_start(codec);
2552
2553 /* Increase the detection rate a bit for responsiveness. */
2554 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2555 WM8996_MICD_RATE_MASK |
2556 WM8996_MICD_BIAS_STARTTIME_MASK,
2557 7 << WM8996_MICD_RATE_SHIFT |
2558 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2559}
2560
a9ba6151
MB		 2561static void wm8996_micd(struct snd_soc_codec *codec)
2562{
2563 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2564 int val, reg;
2565
2566 val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2567
2568 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2569
2570 if (!(val & WM8996_MICD_VALID)) {
2571 dev_warn(codec->dev, "Microphone detection state invalid\n");
2572 return;
2573 }
2574
2575 /* No accessory, reset everything and report removal */
2576 if (!(val & WM8996_MICD_STS)) {
2577 dev_dbg(codec->dev, "Jack removal detected\n");
2578 wm8996->jack_mic = false;
2579 wm8996->detecting = true;
d7b35570 2580 wm8996->jack_flips = 0;
a9ba6151 2581 snd_soc_jack_report(wm8996->jack, 0,
0b684cc1
MB		 2582 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2583 SND_JACK_BTN_0);
2584
a9ba6151 2585 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
45ba82d8
MB		 2586 WM8996_MICD_RATE_MASK |
2587 WM8996_MICD_BIAS_STARTTIME_MASK,
2588 WM8996_MICD_RATE_MASK |
2589 9 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
a9ba6151
MB		 2590 return;
2591 }
2592
0b684cc1
MB		 2593 /* If the measurement is very high we've got a microphone,
2594 * either we just detected one or if we already reported then
2595 * we've got a button release event.
a9ba6151
MB		 2596 */
2597 if (val & 0x400) {
0b684cc1
MB		 2598 if (wm8996->detecting) {
2599 dev_dbg(codec->dev, "Microphone detected\n");
2600 wm8996->jack_mic = true;
2601 wm8996_hpdet_start(codec);
2602
2603 /* Increase poll rate to give better responsiveness
2604 * for buttons */
2605 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
45ba82d8
MB		 2606 WM8996_MICD_RATE_MASK |
2607 WM8996_MICD_BIAS_STARTTIME_MASK,
2608 5 << WM8996_MICD_RATE_SHIFT |
2609 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
0b684cc1
MB		 2610 } else {
2611 dev_dbg(codec->dev, "Mic button up\n");
2612 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
2613 }
2614
2615 return;
a9ba6151
MB		 2616 }
2617
2618 /* If we detected a lower impedence during initial startup
2619 * then we probably have the wrong polarity, flip it. Don't
2620 * do this for the lowest impedences to speed up detection of
d7b35570
MB		 2621 * plain headphones. If both polarities report a low
2622 * impedence then give up and report headphones.
a9ba6151
MB		 2623 */
2624 if (wm8996->detecting && (val & 0x3f0)) {
d7b35570
MB		 2625 wm8996->jack_flips++;
2626
2627 if (wm8996->jack_flips > 1) {
2628 wm8996_report_headphone(codec);
2629 return;
2630 }
2631
a9ba6151
MB		 2632 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2633 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2634 WM8996_MICD_BIAS_SRC;
2635 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2636 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2637 WM8996_MICD_BIAS_SRC, reg);
2638
2639 if (wm8996->polarity_cb)
2640 wm8996->polarity_cb(codec,
2641 (reg & WM8996_MICD_SRC) != 0);
2642
2643 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2644 (reg & WM8996_MICD_SRC) != 0);
2645
2646 return;
2647 }
2648
2649 /* Don't distinguish between buttons, just report any low
2650 * impedence as BTN_0.
2651 */
2652 if (val & 0x3fc) {
2653 if (wm8996->jack_mic) {
2654 dev_dbg(codec->dev, "Mic button detected\n");
0b684cc1 2655 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
a9ba6151 2656 SND_JACK_BTN_0);
0b684cc1 2657 } else if (wm8996->detecting) {
d7b35570 2658 wm8996_report_headphone(codec);
a9ba6151
MB		 2659 }
2660 }
2661}
2662
2663static irqreturn_t wm8996_irq(int irq, void *data)
2664{
2665 struct snd_soc_codec *codec = data;
2666 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2667 int irq_val;
2668
2669 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2670 if (irq_val < 0) {
2671 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2672 irq_val);
2673 return IRQ_NONE;
2674 }
2675 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2676
2fde6e80
MB		 2677 if (!irq_val)
2678 return IRQ_NONE;
2679
84497091
MB		 2680 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2681
a9ba6151
MB		 2682 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2683 dev_dbg(codec->dev, "DC servo IRQ\n");
2684 complete(&wm8996->dcs_done);
2685 }
2686
2687 if (irq_val & WM8996_FIFOS_ERR_EINT)
2688 dev_err(codec->dev, "Digital core FIFO error\n");
2689
2690 if (irq_val & WM8996_FLL_LOCK_EINT) {
2691 dev_dbg(codec->dev, "FLL locked\n");
2692 complete(&wm8996->fll_lock);
2693 }
2694
2695 if (irq_val & WM8996_MICD_EINT)
2696 wm8996_micd(codec);
2697
0b684cc1
MB		 2698 if (irq_val & WM8996_HP_DONE_EINT)
2699 wm8996_hpdet_irq(codec);
2700
2fde6e80 2701 return IRQ_HANDLED;
a9ba6151
MB		 2702}
2703
2704static irqreturn_t wm8996_edge_irq(int irq, void *data)
2705{
2706 irqreturn_t ret = IRQ_NONE;
2707 irqreturn_t val;
2708
2709 do {
2710 val = wm8996_irq(irq, data);
2711 if (val != IRQ_NONE)
2712 ret = val;
2713 } while (val != IRQ_NONE);
2714
2715 return ret;
2716}
2717
2718static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2719{
2720 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2721 struct wm8996_pdata *pdata = &wm8996->pdata;
2722
2723 struct snd_kcontrol_new controls[] = {
2724 SOC_ENUM_EXT("DSP1 EQ Mode",
2725 wm8996->retune_mobile_enum,
2726 wm8996_get_retune_mobile_enum,
2727 wm8996_put_retune_mobile_enum),
2728 SOC_ENUM_EXT("DSP2 EQ Mode",
2729 wm8996->retune_mobile_enum,
2730 wm8996_get_retune_mobile_enum,
2731 wm8996_put_retune_mobile_enum),
2732 };
2733 int ret, i, j;
2734 const char **t;
2735
2736 /* We need an array of texts for the enum API but the number
2737 * of texts is likely to be less than the number of
2738 * configurations due to the sample rate dependency of the
2739 * configurations. */
2740 wm8996->num_retune_mobile_texts = 0;
2741 wm8996->retune_mobile_texts = NULL;
2742 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2743 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2744 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2745 wm8996->retune_mobile_texts[j]) == 0)
2746 break;
2747 }
2748
2749 if (j != wm8996->num_retune_mobile_texts)
2750 continue;
2751
2752 /* Expand the array... */
2753 t = krealloc(wm8996->retune_mobile_texts,
2754 sizeof(char *) *
2755 (wm8996->num_retune_mobile_texts + 1),
2756 GFP_KERNEL);
2757 if (t == NULL)
2758 continue;
2759
2760 /* ...store the new entry... */
2761 t[wm8996->num_retune_mobile_texts] =
2762 pdata->retune_mobile_cfgs[i].name;
2763
2764 /* ...and remember the new version. */
2765 wm8996->num_retune_mobile_texts++;
2766 wm8996->retune_mobile_texts = t;
2767 }
2768
2769 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2770 wm8996->num_retune_mobile_texts);
2771
2772 wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts;
2773 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2774
022658be 2775 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls));
a9ba6151
MB		 2776 if (ret != 0)
2777 dev_err(codec->dev,
2778 "Failed to add ReTune Mobile controls: %d\n", ret);
2779}
2780
79172746
MB		 2781static const struct regmap_config wm8996_regmap = {
2782 .reg_bits = 16,
2783 .val_bits = 16,
2784
2785 .max_register = WM8996_MAX_REGISTER,
2786 .reg_defaults = wm8996_reg,
2787 .num_reg_defaults = ARRAY_SIZE(wm8996_reg),
2788 .volatile_reg = wm8996_volatile_register,
2789 .readable_reg = wm8996_readable_register,
2790 .cache_type = REGCACHE_RBTREE,
2791};
2792
a9ba6151
MB		 2793static int wm8996_probe(struct snd_soc_codec *codec)
2794{
2795 int ret;
2796 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2797 struct i2c_client *i2c = to_i2c_client(codec->dev);
a9ba6151
MB		 2798 int i, irq_flags;
2799
2800 wm8996->codec = codec;
2801
2802 init_completion(&wm8996->dcs_done);
2803 init_completion(&wm8996->fll_lock);
2804
ee5f3872 2805 codec->control_data = wm8996->regmap;
79172746
MB		 2806
2807 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
a9ba6151
MB		 2808 if (ret != 0) {
2809 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
ee5f3872 2810 goto err;
a9ba6151
MB		 2811 }
2812
2813 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2814 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2815 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
c83495af 2816
a9ba6151
MB		 2817 /* This should really be moved into the regulator core */
2818 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2819 ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2820 &wm8996->disable_nb[i]);
2821 if (ret != 0) {
2822 dev_err(codec->dev,
2823 "Failed to register regulator notifier: %d\n",
2824 ret);
2825 }
2826 }
2827
79172746 2828 regcache_cache_only(codec->control_data, true);
a9ba6151
MB		 2829
2830 /* Apply platform data settings */
2831 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL,
2832 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2833 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2834 wm8996->pdata.inr_mode);
2835
2836 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2837 if (!wm8996->pdata.gpio_default[i])
2838 continue;
2839
2840 snd_soc_write(codec, WM8996_GPIO_1 + i,
2841 wm8996->pdata.gpio_default[i] & 0xffff);
2842 }
2843
2844 if (wm8996->pdata.spkmute_seq)
2845 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2846 WM8996_SPK_MUTE_ENDIAN |
2847 WM8996_SPK_MUTE_SEQ1_MASK,
2848 wm8996->pdata.spkmute_seq);
2849
2850 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2851 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2852 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2853
2854 /* Latch volume update bits */
2855 snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME,
2856 WM8996_IN1_VU, WM8996_IN1_VU);
2857 snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME,
2858 WM8996_IN1_VU, WM8996_IN1_VU);
2859
2860 snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME,
2861 WM8996_DAC1_VU, WM8996_DAC1_VU);
2862 snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME,
2863 WM8996_DAC1_VU, WM8996_DAC1_VU);
2864 snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME,
2865 WM8996_DAC2_VU, WM8996_DAC2_VU);
2866 snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME,
2867 WM8996_DAC2_VU, WM8996_DAC2_VU);
2868
2869 snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME,
2870 WM8996_DAC1_VU, WM8996_DAC1_VU);
2871 snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME,
2872 WM8996_DAC1_VU, WM8996_DAC1_VU);
2873 snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME,
2874 WM8996_DAC2_VU, WM8996_DAC2_VU);
2875 snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME,
2876 WM8996_DAC2_VU, WM8996_DAC2_VU);
2877
2878 snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME,
2879 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2880 snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME,
2881 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2882 snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME,
2883 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2884 snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME,
2885 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2886
2887 snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME,
2888 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2889 snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME,
2890 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2891 snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME,
2892 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2893 snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME,
2894 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2895
2896 /* No support currently for the underclocked TDM modes and
2897 * pick a default TDM layout with each channel pair working with
2898 * slots 0 and 1. */
2899 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2900 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2901 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2902 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2903 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2904 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2905 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2906 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2907 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2908 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2909 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2910 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2911 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2912 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2913 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2914 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2915 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2916 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2917 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2918 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2919 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2920 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2921 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2922 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2923
2924 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2925 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2926 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2927 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2928 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2929 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2930 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2931 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2932
2933 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2934 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2935 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2936 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2937 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2938 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2939 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2940 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2941 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2942 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2943 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2944 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2945 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2946 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2947 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2948 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2949 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
2950 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
2951 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2952 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2953 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
2954 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
2955 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2956 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2957
2958 snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
2959 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
2960 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
2961 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2962 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2963 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
2964 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
2965 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2966
2967 if (wm8996->pdata.num_retune_mobile_cfgs)
2968 wm8996_retune_mobile_pdata(codec);
2969 else
022658be 2970 snd_soc_add_codec_controls(codec, wm8996_eq_controls,
a9ba6151
MB		 2971 ARRAY_SIZE(wm8996_eq_controls));
2972
2973 /* If the TX LRCLK pins are not in LRCLK mode configure the
2974 * AIFs to source their clocks from the RX LRCLKs.
2975 */
2976 if ((snd_soc_read(codec, WM8996_GPIO_1)))
2977 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2,
2978 WM8996_AIF1TX_LRCLK_MODE,
2979 WM8996_AIF1TX_LRCLK_MODE);
2980
2981 if ((snd_soc_read(codec, WM8996_GPIO_2)))
2982 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2,
2983 WM8996_AIF2TX_LRCLK_MODE,
2984 WM8996_AIF2TX_LRCLK_MODE);
2985
a9ba6151
MB		 2986 if (i2c->irq) {
2987 if (wm8996->pdata.irq_flags)
2988 irq_flags = wm8996->pdata.irq_flags;
2989 else
2990 irq_flags = IRQF_TRIGGER_LOW;
2991
2992 irq_flags |= IRQF_ONESHOT;
2993
2994 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2995 ret = request_threaded_irq(i2c->irq, NULL,
2996 wm8996_edge_irq,
2997 irq_flags, "wm8996", codec);
2998 else
2999 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
3000 irq_flags, "wm8996", codec);
3001
3002 if (ret == 0) {
3003 /* Unmask the interrupt */
3004 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
3005 WM8996_IM_IRQ, 0);
3006
3007 /* Enable error reporting and DC servo status */
3008 snd_soc_update_bits(codec,
3009 WM8996_INTERRUPT_STATUS_2_MASK,
3010 WM8996_IM_DCS_DONE_23_EINT |
3011 WM8996_IM_DCS_DONE_01_EINT |
3012 WM8996_IM_FLL_LOCK_EINT |
3013 WM8996_IM_FIFOS_ERR_EINT,
3014 0);
3015 } else {
3016 dev_err(codec->dev, "Failed to request IRQ: %d\n",
3017 ret);
3018 }
3019 }
3020
3021 return 0;
3022
a9ba6151
MB		 3023err:
3024 return ret;
3025}
3026
3027static int wm8996_remove(struct snd_soc_codec *codec)
3028{
3029 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
3030 struct i2c_client *i2c = to_i2c_client(codec->dev);
3031 int i;
3032
3033 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
3034 WM8996_IM_IRQ, WM8996_IM_IRQ);
3035
3036 if (i2c->irq)
3037 free_irq(i2c->irq, codec);
3038
a9ba6151
MB		 3039 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3040 regulator_unregister_notifier(wm8996->supplies[i].consumer,
3041 &wm8996->disable_nb[i]);
3042 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3043
3044 return 0;
3045}
3046
1b39bf34
MB		 3047static int wm8996_soc_volatile_register(struct snd_soc_codec *codec,
3048 unsigned int reg)
3049{
3050 return true;
3051}
3052
a9ba6151
MB		 3053static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
3054 .probe = wm8996_probe,
3055 .remove = wm8996_remove,
3056 .set_bias_level = wm8996_set_bias_level,
eb3032f8 3057 .idle_bias_off = true,
a9ba6151 3058 .seq_notifier = wm8996_seq_notifier,
a9ba6151
MB		 3059 .controls = wm8996_snd_controls,
3060 .num_controls = ARRAY_SIZE(wm8996_snd_controls),
3061 .dapm_widgets = wm8996_dapm_widgets,
3062 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
3063 .dapm_routes = wm8996_dapm_routes,
3064 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
3065 .set_pll = wm8996_set_fll,
1b39bf34
MB		 3066 .reg_cache_size = WM8996_MAX_REGISTER,
3067 .volatile_register = wm8996_soc_volatile_register,
a9ba6151
MB		 3068};
3069
3070#define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
3071 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
3072#define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
3073 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
3074 SNDRV_PCM_FMTBIT_S32_LE)
3075
85e7652d 3076static const struct snd_soc_dai_ops wm8996_dai_ops = {
a9ba6151
MB		 3077 .set_fmt = wm8996_set_fmt,
3078 .hw_params = wm8996_hw_params,
3079 .set_sysclk = wm8996_set_sysclk,
3080};
3081
3082static struct snd_soc_dai_driver wm8996_dai[] = {
3083 {
3084 .name = "wm8996-aif1",
3085 .playback = {
3086 .stream_name = "AIF1 Playback",
3087 .channels_min = 1,
3088 .channels_max = 6,
3089 .rates = WM8996_RATES,
3090 .formats = WM8996_FORMATS,
a4b52337 3091 .sig_bits = 24,
a9ba6151
MB		 3092 },
3093 .capture = {
3094 .stream_name = "AIF1 Capture",
3095 .channels_min = 1,
3096 .channels_max = 6,
3097 .rates = WM8996_RATES,
3098 .formats = WM8996_FORMATS,
a4b52337 3099 .sig_bits = 24,
a9ba6151
MB		 3100 },
3101 .ops = &wm8996_dai_ops,
3102 },
3103 {
3104 .name = "wm8996-aif2",
3105 .playback = {
3106 .stream_name = "AIF2 Playback",
3107 .channels_min = 1,
3108 .channels_max = 2,
3109 .rates = WM8996_RATES,
3110 .formats = WM8996_FORMATS,
a4b52337 3111 .sig_bits = 24,
a9ba6151
MB		 3112 },
3113 .capture = {
3114 .stream_name = "AIF2 Capture",
3115 .channels_min = 1,
3116 .channels_max = 2,
3117 .rates = WM8996_RATES,
3118 .formats = WM8996_FORMATS,
a4b52337 3119 .sig_bits = 24,
a9ba6151
MB		 3120 },
3121 .ops = &wm8996_dai_ops,
3122 },
3123};
3124
3125static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
3126 const struct i2c_device_id *id)
3127{
3128 struct wm8996_priv *wm8996;
ee5f3872
MB		 3129 int ret, i;
3130 unsigned int reg;
a9ba6151 3131
a290986b
MB		 3132 wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv),
3133 GFP_KERNEL);
a9ba6151
MB		 3134 if (wm8996 == NULL)
3135 return -ENOMEM;
3136
3137 i2c_set_clientdata(i2c, wm8996);
b2d1e233 3138 wm8996->dev = &i2c->dev;
a9ba6151
MB		 3139
3140 if (dev_get_platdata(&i2c->dev))
3141 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
3142 sizeof(wm8996->pdata));
3143
3144 if (wm8996->pdata.ldo_ena > 0) {
3145 ret = gpio_request_one(wm8996->pdata.ldo_ena,
3146 GPIOF_OUT_INIT_LOW, "WM8996 ENA");
3147 if (ret < 0) {
3148 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
3149 wm8996->pdata.ldo_ena, ret);
3150 goto err;
3151 }
3152 }
3153
ee5f3872
MB		 3154 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3155 wm8996->supplies[i].supply = wm8996_supply_names[i];
3156
24e0c57b
MB		 3157 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies),
3158 wm8996->supplies);
ee5f3872
MB		 3159 if (ret != 0) {
3160 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3161 goto err_gpio;
3162 }
3163
ee5f3872
MB		 3164 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
3165 wm8996->supplies);
3166 if (ret != 0) {
3167 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
24e0c57b 3168 goto err_gpio;
ee5f3872
MB		 3169 }
3170
3171 if (wm8996->pdata.ldo_ena > 0) {
3172 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
3173 msleep(5);
3174 }
3175
3176 wm8996->regmap = regmap_init_i2c(i2c, &wm8996_regmap);
3177 if (IS_ERR(wm8996->regmap)) {
3178 ret = PTR_ERR(wm8996->regmap);
3179 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
3180 goto err_enable;
3181 }
3182
3183 ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, &reg);
3184 if (ret < 0) {
3185 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
3186 goto err_regmap;
3187 }
3188 if (reg != 0x8915) {
905b4195 3189 dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg);
ee5f3872
MB		 3190 ret = -EINVAL;
3191 goto err_regmap;
3192 }
3193
3194 ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, &reg);
3195 if (ret < 0) {
3196 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3197 ret);
3198 goto err_regmap;
3199 }
3200
3201 dev_info(&i2c->dev, "revision %c\n",
3202 (reg & WM8996_CHIP_REV_MASK) + 'A');
3203
3204 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3205
3206 ret = wm8996_reset(wm8996);
3207 if (ret < 0) {
3208 dev_err(&i2c->dev, "Failed to issue reset\n");
3209 goto err_regmap;
3210 }
3211
b2d1e233
MB		 3212 wm8996_init_gpio(wm8996);
3213
a9ba6151
MB		 3214 ret = snd_soc_register_codec(&i2c->dev,
3215 &soc_codec_dev_wm8996, wm8996_dai,
3216 ARRAY_SIZE(wm8996_dai));
3217 if (ret < 0)
b2d1e233 3218 goto err_gpiolib;
a9ba6151
MB		 3219
3220 return ret;
3221
b2d1e233
MB		 3222err_gpiolib:
3223 wm8996_free_gpio(wm8996);
ee5f3872
MB		 3224err_regmap:
3225 regmap_exit(wm8996->regmap);
3226err_enable:
3227 if (wm8996->pdata.ldo_ena > 0)
3228 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3229 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
a9ba6151
MB		 3230err_gpio:
3231 if (wm8996->pdata.ldo_ena > 0)
3232 gpio_free(wm8996->pdata.ldo_ena);
3233err:
a9ba6151
MB		 3234
3235 return ret;
3236}
3237
3238static __devexit int wm8996_i2c_remove(struct i2c_client *client)
3239{
3240 struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
3241
3242 snd_soc_unregister_codec(&client->dev);
b2d1e233 3243 wm8996_free_gpio(wm8996);
ee5f3872
MB		 3244 regmap_exit(wm8996->regmap);
3245 if (wm8996->pdata.ldo_ena > 0) {
3246 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
a9ba6151 3247 gpio_free(wm8996->pdata.ldo_ena);
ee5f3872 3248 }
a9ba6151
MB		 3249 return 0;
3250}
3251
3252static const struct i2c_device_id wm8996_i2c_id[] = {
3253 { "wm8996", 0 },
3254 { }
3255};
3256MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3257
3258static struct i2c_driver wm8996_i2c_driver = {
3259 .driver = {
3260 .name = "wm8996",
3261 .owner = THIS_MODULE,
3262 },
3263 .probe = wm8996_i2c_probe,
3264 .remove = __devexit_p(wm8996_i2c_remove),
3265 .id_table = wm8996_i2c_id,
3266};
3267
8005f394 3268module_i2c_driver(wm8996_i2c_driver);
a9ba6151
MB		 3269
3270MODULE_DESCRIPTION("ASoC WM8996 driver");
3271MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3272MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)