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ASoC: Convert WM8996 to direct regmap API usage
[linux-2.6-block.git] / sound / soc / codecs / wm8996.c
CommitLineData
a9ba6151
MB		 1/*
2 * wm8996.c - WM8996 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
79172746 22#include <linux/regmap.h>
a9ba6151
MB		 23#include <linux/regulator/consumer.h>
24#include <linux/slab.h>
25#include <linux/workqueue.h>
26#include <sound/core.h>
27#include <sound/jack.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <trace/events/asoc.h>
34
35#include <sound/wm8996.h>
36#include "wm8996.h"
37
38#define WM8996_AIFS 2
39
40#define HPOUT1L 1
41#define HPOUT1R 2
42#define HPOUT2L 4
43#define HPOUT2R 8
44
c83495af 45#define WM8996_NUM_SUPPLIES 3
a9ba6151
MB		 46static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
47 "DBVDD",
48 "AVDD1",
49 "AVDD2",
a9ba6151
MB		 50};
51
52struct wm8996_priv {
53 struct snd_soc_codec *codec;
54
55 int ldo1ena;
56
57 int sysclk;
58 int sysclk_src;
59
60 int fll_src;
61 int fll_fref;
62 int fll_fout;
63
64 struct completion fll_lock;
65
66 u16 dcs_pending;
67 struct completion dcs_done;
68
69 u16 hpout_ena;
70 u16 hpout_pending;
71
72 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
73 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
c83495af 74 struct regulator *cpvdd;
ded71dcb 75 int bg_ena;
a9ba6151
MB		 76
77 struct wm8996_pdata pdata;
78
79 int rx_rate[WM8996_AIFS];
80 int bclk_rate[WM8996_AIFS];
81
82 /* Platform dependant ReTune mobile configuration */
83 int num_retune_mobile_texts;
84 const char **retune_mobile_texts;
85 int retune_mobile_cfg[2];
86 struct soc_enum retune_mobile_enum;
87
88 struct snd_soc_jack *jack;
89 bool detecting;
90 bool jack_mic;
91 wm8996_polarity_fn polarity_cb;
92
93#ifdef CONFIG_GPIOLIB
94 struct gpio_chip gpio_chip;
95#endif
96};
97
98/* We can't use the same notifier block for more than one supply and
99 * there's no way I can see to get from a callback to the caller
100 * except container_of().
101 */
102#define WM8996_REGULATOR_EVENT(n) \
103static int wm8996_regulator_event_##n(struct notifier_block *nb, \
104 unsigned long event, void *data) \
105{ \
106 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
107 disable_nb[n]); \
108 if (event & REGULATOR_EVENT_DISABLE) { \
109 wm8996->codec->cache_sync = 1; \
110 } \
111 return 0; \
112}
113
114WM8996_REGULATOR_EVENT(0)
115WM8996_REGULATOR_EVENT(1)
116WM8996_REGULATOR_EVENT(2)
a9ba6151 117
79172746
MB		 118static struct reg_default wm8996_reg[] = {
119 { WM8996_SOFTWARE_RESET, 0x8996 },
120 { WM8996_POWER_MANAGEMENT_1, 0x0 },
121 { WM8996_POWER_MANAGEMENT_2, 0x0 },
122 { WM8996_POWER_MANAGEMENT_3, 0x0 },
123 { WM8996_POWER_MANAGEMENT_4, 0x0 },
124 { WM8996_POWER_MANAGEMENT_5, 0x0 },
125 { WM8996_POWER_MANAGEMENT_6, 0x0 },
126 { WM8996_POWER_MANAGEMENT_7, 0x10 },
127 { WM8996_POWER_MANAGEMENT_8, 0x0 },
128 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
129 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
130 { WM8996_LINE_INPUT_CONTROL, 0x0 },
131 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
132 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
133 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
134 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
135 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
136 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
137 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
138 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
139 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
140 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
141 { WM8996_MICBIAS_1, 0x39 },
142 { WM8996_MICBIAS_2, 0x39 },
143 { WM8996_LDO_1, 0x3 },
144 { WM8996_LDO_2, 0x13 },
145 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
146 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
147 { WM8996_HEADPHONE_DETECT_1, 0x20 },
148 { WM8996_HEADPHONE_DETECT_2, 0x0 },
149 { WM8996_MIC_DETECT_1, 0x7600 },
150 { WM8996_MIC_DETECT_2, 0xbf },
151 { WM8996_CHARGE_PUMP_1, 0x1f25 },
152 { WM8996_CHARGE_PUMP_2, 0xab19 },
153 { WM8996_DC_SERVO_1, 0x0 },
154 { WM8996_DC_SERVO_2, 0x0 },
155 { WM8996_DC_SERVO_3, 0x0 },
156 { WM8996_DC_SERVO_5, 0x2a2a },
157 { WM8996_DC_SERVO_6, 0x0 },
158 { WM8996_DC_SERVO_7, 0x0 },
159 { WM8996_ANALOGUE_HP_1, 0x0 },
160 { WM8996_ANALOGUE_HP_2, 0x0 },
161 { WM8996_CONTROL_INTERFACE_1, 0x8004 },
162 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
163 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
164 { WM8996_AIF_CLOCKING_1, 0x0 },
165 { WM8996_AIF_CLOCKING_2, 0x0 },
166 { WM8996_CLOCKING_1, 0x10 },
167 { WM8996_CLOCKING_2, 0x0 },
168 { WM8996_AIF_RATE, 0x83 },
169 { WM8996_FLL_CONTROL_1, 0x0 },
170 { WM8996_FLL_CONTROL_2, 0x0 },
171 { WM8996_FLL_CONTROL_3, 0x0 },
172 { WM8996_FLL_CONTROL_4, 0x5dc0 },
173 { WM8996_FLL_CONTROL_5, 0xc84 },
174 { WM8996_FLL_EFS_1, 0x0 },
175 { WM8996_FLL_EFS_2, 0x2 },
176 { WM8996_AIF1_CONTROL, 0x0 },
177 { WM8996_AIF1_BCLK, 0x0 },
178 { WM8996_AIF1_TX_LRCLK_1, 0x80 },
179 { WM8996_AIF1_TX_LRCLK_2, 0x8 },
180 { WM8996_AIF1_RX_LRCLK_1, 0x80 },
181 { WM8996_AIF1_RX_LRCLK_2, 0x0 },
182 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
183 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
184 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
185 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
186 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
187 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
188 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
189 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
190 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
191 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
192 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
193 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
194 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
195 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
196 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
197 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
198 { WM8996_AIF1TX_TEST, 0x7 },
199 { WM8996_AIF2_CONTROL, 0x0 },
200 { WM8996_AIF2_BCLK, 0x0 },
201 { WM8996_AIF2_TX_LRCLK_1, 0x80 },
202 { WM8996_AIF2_TX_LRCLK_2, 0x8 },
203 { WM8996_AIF2_RX_LRCLK_1, 0x80 },
204 { WM8996_AIF2_RX_LRCLK_2, 0x0 },
205 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
206 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
207 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
208 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
209 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
210 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
211 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
212 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
213 { WM8996_AIF2TX_TEST, 0x1 },
214 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
215 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
216 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
217 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
218 { WM8996_DSP1_TX_FILTERS, 0x2000 },
219 { WM8996_DSP1_RX_FILTERS_1, 0x200 },
220 { WM8996_DSP1_RX_FILTERS_2, 0x10 },
221 { WM8996_DSP1_DRC_1, 0x98 },
222 { WM8996_DSP1_DRC_2, 0x845 },
223 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
224 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
225 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
226 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
227 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
228 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
229 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
230 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
231 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
232 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
233 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
234 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
235 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
236 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
237 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
238 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
239 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
240 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
241 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
242 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
243 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
244 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
245 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
246 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
247 { WM8996_DSP2_TX_FILTERS, 0x2000 },
248 { WM8996_DSP2_RX_FILTERS_1, 0x200 },
249 { WM8996_DSP2_RX_FILTERS_2, 0x10 },
250 { WM8996_DSP2_DRC_1, 0x98 },
251 { WM8996_DSP2_DRC_2, 0x845 },
252 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
253 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
254 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
255 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
256 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
257 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
258 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
259 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
260 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
261 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
262 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
263 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
264 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
265 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
266 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
267 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
268 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
269 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
270 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
271 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
272 { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
273 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
274 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
275 { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
276 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
277 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
278 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
279 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
280 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
281 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
282 { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
283 { WM8996_DAC_SOFTMUTE, 0x0 },
284 { WM8996_OVERSAMPLING, 0xd },
285 { WM8996_SIDETONE, 0x1040 },
286 { WM8996_GPIO_1, 0xa101 },
287 { WM8996_GPIO_2, 0xa101 },
288 { WM8996_GPIO_3, 0xa101 },
289 { WM8996_GPIO_4, 0xa101 },
290 { WM8996_GPIO_5, 0xa101 },
291 { WM8996_PULL_CONTROL_1, 0x0 },
292 { WM8996_PULL_CONTROL_2, 0x140 },
293 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
294 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
295 { WM8996_LEFT_PDM_SPEAKER, 0x0 },
296 { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
297 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
298 { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
299 { WM8996_WRITE_SEQUENCER_0, 0x1 },
300 { WM8996_WRITE_SEQUENCER_1, 0x1 },
301 { WM8996_WRITE_SEQUENCER_3, 0x6 },
302 { WM8996_WRITE_SEQUENCER_4, 0x40 },
303 { WM8996_WRITE_SEQUENCER_5, 0x1 },
304 { WM8996_WRITE_SEQUENCER_6, 0xf },
305 { WM8996_WRITE_SEQUENCER_7, 0x6 },
306 { WM8996_WRITE_SEQUENCER_8, 0x1 },
307 { WM8996_WRITE_SEQUENCER_9, 0x3 },
308 { WM8996_WRITE_SEQUENCER_10, 0x104 },
309 { WM8996_WRITE_SEQUENCER_12, 0x60 },
310 { WM8996_WRITE_SEQUENCER_13, 0x11 },
311 { WM8996_WRITE_SEQUENCER_14, 0x401 },
312 { WM8996_WRITE_SEQUENCER_16, 0x50 },
313 { WM8996_WRITE_SEQUENCER_17, 0x3 },
314 { WM8996_WRITE_SEQUENCER_18, 0x100 },
315 { WM8996_WRITE_SEQUENCER_20, 0x51 },
316 { WM8996_WRITE_SEQUENCER_21, 0x3 },
317 { WM8996_WRITE_SEQUENCER_22, 0x104 },
318 { WM8996_WRITE_SEQUENCER_23, 0xa },
319 { WM8996_WRITE_SEQUENCER_24, 0x60 },
320 { WM8996_WRITE_SEQUENCER_25, 0x3b },
321 { WM8996_WRITE_SEQUENCER_26, 0x502 },
322 { WM8996_WRITE_SEQUENCER_27, 0x100 },
323 { WM8996_WRITE_SEQUENCER_28, 0x2fff },
324 { WM8996_WRITE_SEQUENCER_32, 0x2fff },
325 { WM8996_WRITE_SEQUENCER_36, 0x2fff },
326 { WM8996_WRITE_SEQUENCER_40, 0x2fff },
327 { WM8996_WRITE_SEQUENCER_44, 0x2fff },
328 { WM8996_WRITE_SEQUENCER_48, 0x2fff },
329 { WM8996_WRITE_SEQUENCER_52, 0x2fff },
330 { WM8996_WRITE_SEQUENCER_56, 0x2fff },
331 { WM8996_WRITE_SEQUENCER_60, 0x2fff },
332 { WM8996_WRITE_SEQUENCER_64, 0x1 },
333 { WM8996_WRITE_SEQUENCER_65, 0x1 },
334 { WM8996_WRITE_SEQUENCER_67, 0x6 },
335 { WM8996_WRITE_SEQUENCER_68, 0x40 },
336 { WM8996_WRITE_SEQUENCER_69, 0x1 },
337 { WM8996_WRITE_SEQUENCER_70, 0xf },
338 { WM8996_WRITE_SEQUENCER_71, 0x6 },
339 { WM8996_WRITE_SEQUENCER_72, 0x1 },
340 { WM8996_WRITE_SEQUENCER_73, 0x3 },
341 { WM8996_WRITE_SEQUENCER_74, 0x104 },
342 { WM8996_WRITE_SEQUENCER_76, 0x60 },
343 { WM8996_WRITE_SEQUENCER_77, 0x11 },
344 { WM8996_WRITE_SEQUENCER_78, 0x401 },
345 { WM8996_WRITE_SEQUENCER_80, 0x50 },
346 { WM8996_WRITE_SEQUENCER_81, 0x3 },
347 { WM8996_WRITE_SEQUENCER_82, 0x100 },
348 { WM8996_WRITE_SEQUENCER_84, 0x60 },
349 { WM8996_WRITE_SEQUENCER_85, 0x3b },
350 { WM8996_WRITE_SEQUENCER_86, 0x502 },
351 { WM8996_WRITE_SEQUENCER_87, 0x100 },
352 { WM8996_WRITE_SEQUENCER_88, 0x2fff },
353 { WM8996_WRITE_SEQUENCER_92, 0x2fff },
354 { WM8996_WRITE_SEQUENCER_96, 0x2fff },
355 { WM8996_WRITE_SEQUENCER_100, 0x2fff },
356 { WM8996_WRITE_SEQUENCER_104, 0x2fff },
357 { WM8996_WRITE_SEQUENCER_108, 0x2fff },
358 { WM8996_WRITE_SEQUENCER_112, 0x2fff },
359 { WM8996_WRITE_SEQUENCER_116, 0x2fff },
360 { WM8996_WRITE_SEQUENCER_120, 0x2fff },
361 { WM8996_WRITE_SEQUENCER_124, 0x2fff },
362 { WM8996_WRITE_SEQUENCER_128, 0x1 },
363 { WM8996_WRITE_SEQUENCER_129, 0x1 },
364 { WM8996_WRITE_SEQUENCER_131, 0x6 },
365 { WM8996_WRITE_SEQUENCER_132, 0x40 },
366 { WM8996_WRITE_SEQUENCER_133, 0x1 },
367 { WM8996_WRITE_SEQUENCER_134, 0xf },
368 { WM8996_WRITE_SEQUENCER_135, 0x6 },
369 { WM8996_WRITE_SEQUENCER_136, 0x1 },
370 { WM8996_WRITE_SEQUENCER_137, 0x3 },
371 { WM8996_WRITE_SEQUENCER_138, 0x106 },
372 { WM8996_WRITE_SEQUENCER_140, 0x61 },
373 { WM8996_WRITE_SEQUENCER_141, 0x11 },
374 { WM8996_WRITE_SEQUENCER_142, 0x401 },
375 { WM8996_WRITE_SEQUENCER_144, 0x50 },
376 { WM8996_WRITE_SEQUENCER_145, 0x3 },
377 { WM8996_WRITE_SEQUENCER_146, 0x102 },
378 { WM8996_WRITE_SEQUENCER_148, 0x51 },
379 { WM8996_WRITE_SEQUENCER_149, 0x3 },
380 { WM8996_WRITE_SEQUENCER_150, 0x106 },
381 { WM8996_WRITE_SEQUENCER_151, 0xa },
382 { WM8996_WRITE_SEQUENCER_152, 0x61 },
383 { WM8996_WRITE_SEQUENCER_153, 0x3b },
384 { WM8996_WRITE_SEQUENCER_154, 0x502 },
385 { WM8996_WRITE_SEQUENCER_155, 0x100 },
386 { WM8996_WRITE_SEQUENCER_156, 0x2fff },
387 { WM8996_WRITE_SEQUENCER_160, 0x2fff },
388 { WM8996_WRITE_SEQUENCER_164, 0x2fff },
389 { WM8996_WRITE_SEQUENCER_168, 0x2fff },
390 { WM8996_WRITE_SEQUENCER_172, 0x2fff },
391 { WM8996_WRITE_SEQUENCER_176, 0x2fff },
392 { WM8996_WRITE_SEQUENCER_180, 0x2fff },
393 { WM8996_WRITE_SEQUENCER_184, 0x2fff },
394 { WM8996_WRITE_SEQUENCER_188, 0x2fff },
395 { WM8996_WRITE_SEQUENCER_192, 0x1 },
396 { WM8996_WRITE_SEQUENCER_193, 0x1 },
397 { WM8996_WRITE_SEQUENCER_195, 0x6 },
398 { WM8996_WRITE_SEQUENCER_196, 0x40 },
399 { WM8996_WRITE_SEQUENCER_197, 0x1 },
400 { WM8996_WRITE_SEQUENCER_198, 0xf },
401 { WM8996_WRITE_SEQUENCER_199, 0x6 },
402 { WM8996_WRITE_SEQUENCER_200, 0x1 },
403 { WM8996_WRITE_SEQUENCER_201, 0x3 },
404 { WM8996_WRITE_SEQUENCER_202, 0x106 },
405 { WM8996_WRITE_SEQUENCER_204, 0x61 },
406 { WM8996_WRITE_SEQUENCER_205, 0x11 },
407 { WM8996_WRITE_SEQUENCER_206, 0x401 },
408 { WM8996_WRITE_SEQUENCER_208, 0x50 },
409 { WM8996_WRITE_SEQUENCER_209, 0x3 },
410 { WM8996_WRITE_SEQUENCER_210, 0x102 },
411 { WM8996_WRITE_SEQUENCER_212, 0x61 },
412 { WM8996_WRITE_SEQUENCER_213, 0x3b },
413 { WM8996_WRITE_SEQUENCER_214, 0x502 },
414 { WM8996_WRITE_SEQUENCER_215, 0x100 },
415 { WM8996_WRITE_SEQUENCER_216, 0x2fff },
416 { WM8996_WRITE_SEQUENCER_220, 0x2fff },
417 { WM8996_WRITE_SEQUENCER_224, 0x2fff },
418 { WM8996_WRITE_SEQUENCER_228, 0x2fff },
419 { WM8996_WRITE_SEQUENCER_232, 0x2fff },
420 { WM8996_WRITE_SEQUENCER_236, 0x2fff },
421 { WM8996_WRITE_SEQUENCER_240, 0x2fff },
422 { WM8996_WRITE_SEQUENCER_244, 0x2fff },
423 { WM8996_WRITE_SEQUENCER_248, 0x2fff },
424 { WM8996_WRITE_SEQUENCER_252, 0x2fff },
425 { WM8996_WRITE_SEQUENCER_256, 0x60 },
426 { WM8996_WRITE_SEQUENCER_258, 0x601 },
427 { WM8996_WRITE_SEQUENCER_260, 0x50 },
428 { WM8996_WRITE_SEQUENCER_262, 0x100 },
429 { WM8996_WRITE_SEQUENCER_264, 0x1 },
430 { WM8996_WRITE_SEQUENCER_266, 0x104 },
431 { WM8996_WRITE_SEQUENCER_267, 0x100 },
432 { WM8996_WRITE_SEQUENCER_268, 0x2fff },
433 { WM8996_WRITE_SEQUENCER_272, 0x2fff },
434 { WM8996_WRITE_SEQUENCER_276, 0x2fff },
435 { WM8996_WRITE_SEQUENCER_280, 0x2fff },
436 { WM8996_WRITE_SEQUENCER_284, 0x2fff },
437 { WM8996_WRITE_SEQUENCER_288, 0x2fff },
438 { WM8996_WRITE_SEQUENCER_292, 0x2fff },
439 { WM8996_WRITE_SEQUENCER_296, 0x2fff },
440 { WM8996_WRITE_SEQUENCER_300, 0x2fff },
441 { WM8996_WRITE_SEQUENCER_304, 0x2fff },
442 { WM8996_WRITE_SEQUENCER_308, 0x2fff },
443 { WM8996_WRITE_SEQUENCER_312, 0x2fff },
444 { WM8996_WRITE_SEQUENCER_316, 0x2fff },
445 { WM8996_WRITE_SEQUENCER_320, 0x61 },
446 { WM8996_WRITE_SEQUENCER_322, 0x601 },
447 { WM8996_WRITE_SEQUENCER_324, 0x50 },
448 { WM8996_WRITE_SEQUENCER_326, 0x102 },
449 { WM8996_WRITE_SEQUENCER_328, 0x1 },
450 { WM8996_WRITE_SEQUENCER_330, 0x106 },
451 { WM8996_WRITE_SEQUENCER_331, 0x100 },
452 { WM8996_WRITE_SEQUENCER_332, 0x2fff },
453 { WM8996_WRITE_SEQUENCER_336, 0x2fff },
454 { WM8996_WRITE_SEQUENCER_340, 0x2fff },
455 { WM8996_WRITE_SEQUENCER_344, 0x2fff },
456 { WM8996_WRITE_SEQUENCER_348, 0x2fff },
457 { WM8996_WRITE_SEQUENCER_352, 0x2fff },
458 { WM8996_WRITE_SEQUENCER_356, 0x2fff },
459 { WM8996_WRITE_SEQUENCER_360, 0x2fff },
460 { WM8996_WRITE_SEQUENCER_364, 0x2fff },
461 { WM8996_WRITE_SEQUENCER_368, 0x2fff },
462 { WM8996_WRITE_SEQUENCER_372, 0x2fff },
463 { WM8996_WRITE_SEQUENCER_376, 0x2fff },
464 { WM8996_WRITE_SEQUENCER_380, 0x2fff },
465 { WM8996_WRITE_SEQUENCER_384, 0x60 },
466 { WM8996_WRITE_SEQUENCER_386, 0x601 },
467 { WM8996_WRITE_SEQUENCER_388, 0x61 },
468 { WM8996_WRITE_SEQUENCER_390, 0x601 },
469 { WM8996_WRITE_SEQUENCER_392, 0x50 },
470 { WM8996_WRITE_SEQUENCER_394, 0x300 },
471 { WM8996_WRITE_SEQUENCER_396, 0x1 },
472 { WM8996_WRITE_SEQUENCER_398, 0x304 },
473 { WM8996_WRITE_SEQUENCER_400, 0x40 },
474 { WM8996_WRITE_SEQUENCER_402, 0xf },
475 { WM8996_WRITE_SEQUENCER_404, 0x1 },
476 { WM8996_WRITE_SEQUENCER_407, 0x100 },
a9ba6151
MB		 477};
478
479static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
480static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
481static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
482static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
483static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
484static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
485static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
18a4eef3 486static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
a9ba6151
MB		 487
488static const char *sidetone_hpf_text[] = {
489 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
490};
491
492static const struct soc_enum sidetone_hpf =
18036b58 493 SOC_ENUM_SINGLE(WM8996_SIDETONE, 7, 7, sidetone_hpf_text);
a9ba6151
MB		 494
495static const char *hpf_mode_text[] = {
496 "HiFi", "Custom", "Voice"
497};
498
499static const struct soc_enum dsp1tx_hpf_mode =
500 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
501
502static const struct soc_enum dsp2tx_hpf_mode =
503 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
504
505static const char *hpf_cutoff_text[] = {
506 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
507};
508
509static const struct soc_enum dsp1tx_hpf_cutoff =
510 SOC_ENUM_SINGLE(WM8996_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
511
512static const struct soc_enum dsp2tx_hpf_cutoff =
513 SOC_ENUM_SINGLE(WM8996_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
514
515static void wm8996_set_retune_mobile(struct snd_soc_codec *codec, int block)
516{
517 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
518 struct wm8996_pdata *pdata = &wm8996->pdata;
519 int base, best, best_val, save, i, cfg, iface;
520
521 if (!wm8996->num_retune_mobile_texts)
522 return;
523
524 switch (block) {
525 case 0:
526 base = WM8996_DSP1_RX_EQ_GAINS_1;
527 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
528 WM8996_DSP1RX_SRC)
529 iface = 1;
530 else
531 iface = 0;
532 break;
533 case 1:
534 base = WM8996_DSP1_RX_EQ_GAINS_2;
535 if (snd_soc_read(codec, WM8996_POWER_MANAGEMENT_8) &
536 WM8996_DSP2RX_SRC)
537 iface = 1;
538 else
539 iface = 0;
540 break;
541 default:
542 return;
543 }
544
545 /* Find the version of the currently selected configuration
546 * with the nearest sample rate. */
547 cfg = wm8996->retune_mobile_cfg[block];
548 best = 0;
549 best_val = INT_MAX;
550 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
551 if (strcmp(pdata->retune_mobile_cfgs[i].name,
552 wm8996->retune_mobile_texts[cfg]) == 0 &&
553 abs(pdata->retune_mobile_cfgs[i].rate
554 - wm8996->rx_rate[iface]) < best_val) {
555 best = i;
556 best_val = abs(pdata->retune_mobile_cfgs[i].rate
557 - wm8996->rx_rate[iface]);
558 }
559 }
560
561 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
562 block,
563 pdata->retune_mobile_cfgs[best].name,
564 pdata->retune_mobile_cfgs[best].rate,
565 wm8996->rx_rate[iface]);
566
567 /* The EQ will be disabled while reconfiguring it, remember the
568 * current configuration.
569 */
570 save = snd_soc_read(codec, base);
571 save &= WM8996_DSP1RX_EQ_ENA;
572
573 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
574 snd_soc_update_bits(codec, base + i, 0xffff,
575 pdata->retune_mobile_cfgs[best].regs[i]);
576
577 snd_soc_update_bits(codec, base, WM8996_DSP1RX_EQ_ENA, save);
578}
579
580/* Icky as hell but saves code duplication */
581static int wm8996_get_retune_mobile_block(const char *name)
582{
583 if (strcmp(name, "DSP1 EQ Mode") == 0)
584 return 0;
585 if (strcmp(name, "DSP2 EQ Mode") == 0)
586 return 1;
587 return -EINVAL;
588}
589
590static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
591 struct snd_ctl_elem_value *ucontrol)
592{
593 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
594 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
595 struct wm8996_pdata *pdata = &wm8996->pdata;
596 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
597 int value = ucontrol->value.integer.value[0];
598
599 if (block < 0)
600 return block;
601
602 if (value >= pdata->num_retune_mobile_cfgs)
603 return -EINVAL;
604
605 wm8996->retune_mobile_cfg[block] = value;
606
607 wm8996_set_retune_mobile(codec, block);
608
609 return 0;
610}
611
612static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
613 struct snd_ctl_elem_value *ucontrol)
614{
615 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
616 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
617 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
618
619 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
620
621 return 0;
622}
623
624static const struct snd_kcontrol_new wm8996_snd_controls[] = {
625SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
626 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
627SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
628 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
629
630SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
631 0, 5, 24, 0, sidetone_tlv),
632SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
633 0, 5, 24, 0, sidetone_tlv),
634SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
635SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
636SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
637
638SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
639 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
640SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
641 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
642
643SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
644 13, 1, 0),
645SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
646SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
647SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
648
649SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
650 13, 1, 0),
651SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
652SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
653SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
654
655SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
656 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
657SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
658
659SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
660 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
661SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
662
663SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
664 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
665SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
666 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
667
668SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
669 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
670SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
671 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
672
673SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
674SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
675SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
676SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
677
678SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
679SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
680
18a4eef3 681SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
682SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
683
684SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
685 0, threedstereo_tlv),
686SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
687 0, threedstereo_tlv),
688
a9ba6151
MB		 689SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
690 8, 0, out_digital_tlv),
691SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
692 8, 0, out_digital_tlv),
693
694SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
695 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
696SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
697 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
698
699SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
700 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
701SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
702 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
703
704SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
705 spk_tlv),
706SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
707 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
708SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
709 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
710
711SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
712SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
bcec267a
KT		 713
714SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
715SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
716SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
717
718SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
719SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
720SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
a9ba6151
MB		 721};
722
723static const struct snd_kcontrol_new wm8996_eq_controls[] = {
724SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
725 eq_tlv),
726SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
727 eq_tlv),
728SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
729 eq_tlv),
730SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
731 eq_tlv),
732SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
733 eq_tlv),
734
735SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
736 eq_tlv),
737SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
738 eq_tlv),
739SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
740 eq_tlv),
741SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
742 eq_tlv),
743SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
744 eq_tlv),
745};
746
ded71dcb
MB		 747static void wm8996_bg_enable(struct snd_soc_codec *codec)
748{
749 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
750
751 wm8996->bg_ena++;
752 if (wm8996->bg_ena == 1) {
753 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
754 WM8996_BG_ENA, WM8996_BG_ENA);
755 msleep(2);
756 }
757}
758
759static void wm8996_bg_disable(struct snd_soc_codec *codec)
760{
761 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
762
763 wm8996->bg_ena--;
764 if (!wm8996->bg_ena)
765 snd_soc_update_bits(codec, WM8996_POWER_MANAGEMENT_1,
766 WM8996_BG_ENA, 0);
767}
768
8259df12
MB		 769static int bg_event(struct snd_soc_dapm_widget *w,
770 struct snd_kcontrol *kcontrol, int event)
771{
ded71dcb 772 struct snd_soc_codec *codec = w->codec;
8259df12
MB		 773 int ret = 0;
774
775 switch (event) {
ded71dcb
MB		 776 case SND_SOC_DAPM_PRE_PMU:
777 wm8996_bg_enable(codec);
778 break;
779 case SND_SOC_DAPM_POST_PMD:
780 wm8996_bg_disable(codec);
8259df12
MB		 781 break;
782 default:
783 BUG();
784 ret = -EINVAL;
785 }
786
787 return ret;
788}
789
a9ba6151
MB		 790static int cp_event(struct snd_soc_dapm_widget *w,
791 struct snd_kcontrol *kcontrol, int event)
792{
c83495af
MB		 793 struct snd_soc_codec *codec = w->codec;
794 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
795 int ret = 0;
796
a9ba6151 797 switch (event) {
c83495af
MB		 798 case SND_SOC_DAPM_PRE_PMU:
799 ret = regulator_enable(wm8996->cpvdd);
800 if (ret != 0)
801 dev_err(codec->dev, "Failed to enable CPVDD: %d\n",
802 ret);
803 break;
a9ba6151
MB		 804 case SND_SOC_DAPM_POST_PMU:
805 msleep(5);
806 break;
c83495af
MB		 807 case SND_SOC_DAPM_POST_PMD:
808 regulator_disable_deferred(wm8996->cpvdd, 20);
809 break;
a9ba6151
MB		 810 default:
811 BUG();
c83495af 812 ret = -EINVAL;
a9ba6151
MB		 813 }
814
c83495af 815 return ret;
a9ba6151
MB		 816}
817
818static int rmv_short_event(struct snd_soc_dapm_widget *w,
819 struct snd_kcontrol *kcontrol, int event)
820{
821 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
822
823 /* Record which outputs we enabled */
824 switch (event) {
825 case SND_SOC_DAPM_PRE_PMD:
826 wm8996->hpout_pending &= ~w->shift;
827 break;
828 case SND_SOC_DAPM_PRE_PMU:
829 wm8996->hpout_pending |= w->shift;
830 break;
831 default:
832 BUG();
833 return -EINVAL;
834 }
835
836 return 0;
837}
838
839static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
840{
841 struct i2c_client *i2c = to_i2c_client(codec->dev);
842 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
f998f257 843 int ret;
a9ba6151
MB		 844 unsigned long timeout = 200;
845
846 snd_soc_write(codec, WM8996_DC_SERVO_2, mask);
847
848 /* Use the interrupt if possible */
849 do {
850 if (i2c->irq) {
851 timeout = wait_for_completion_timeout(&wm8996->dcs_done,
852 msecs_to_jiffies(200));
853 if (timeout == 0)
854 dev_err(codec->dev, "DC servo timed out\n");
855
856 } else {
857 msleep(1);
f998f257 858 timeout--;
a9ba6151
MB		 859 }
860
861 ret = snd_soc_read(codec, WM8996_DC_SERVO_2);
862 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
f998f257 863 } while (timeout && ret & mask);
a9ba6151
MB		 864
865 if (timeout == 0)
866 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
867 else
868 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
869}
870
871static void wm8996_seq_notifier(struct snd_soc_dapm_context *dapm,
872 enum snd_soc_dapm_type event, int subseq)
873{
874 struct snd_soc_codec *codec = container_of(dapm,
875 struct snd_soc_codec, dapm);
876 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
877 u16 val, mask;
878
879 /* Complete any pending DC servo starts */
880 if (wm8996->dcs_pending) {
881 dev_dbg(codec->dev, "Starting DC servo for %x\n",
882 wm8996->dcs_pending);
883
884 /* Trigger a startup sequence */
885 wait_for_dc_servo(codec, wm8996->dcs_pending
886 << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
887
888 wm8996->dcs_pending = 0;
889 }
890
891 if (wm8996->hpout_pending != wm8996->hpout_ena) {
892 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
893 wm8996->hpout_ena, wm8996->hpout_pending);
894
895 val = 0;
896 mask = 0;
897 if (wm8996->hpout_pending & HPOUT1L) {
898 val |= WM8996_HPOUT1L_RMV_SHORT;
899 mask |= WM8996_HPOUT1L_RMV_SHORT;
900 } else {
901 mask |= WM8996_HPOUT1L_RMV_SHORT |
902 WM8996_HPOUT1L_OUTP |
903 WM8996_HPOUT1L_DLY;
904 }
905
906 if (wm8996->hpout_pending & HPOUT1R) {
907 val |= WM8996_HPOUT1R_RMV_SHORT;
908 mask |= WM8996_HPOUT1R_RMV_SHORT;
909 } else {
910 mask |= WM8996_HPOUT1R_RMV_SHORT |
911 WM8996_HPOUT1R_OUTP |
912 WM8996_HPOUT1R_DLY;
913 }
914
915 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1, mask, val);
916
917 val = 0;
918 mask = 0;
919 if (wm8996->hpout_pending & HPOUT2L) {
920 val |= WM8996_HPOUT2L_RMV_SHORT;
921 mask |= WM8996_HPOUT2L_RMV_SHORT;
922 } else {
923 mask |= WM8996_HPOUT2L_RMV_SHORT |
924 WM8996_HPOUT2L_OUTP |
925 WM8996_HPOUT2L_DLY;
926 }
927
928 if (wm8996->hpout_pending & HPOUT2R) {
929 val |= WM8996_HPOUT2R_RMV_SHORT;
930 mask |= WM8996_HPOUT2R_RMV_SHORT;
931 } else {
932 mask |= WM8996_HPOUT2R_RMV_SHORT |
933 WM8996_HPOUT2R_OUTP |
934 WM8996_HPOUT2R_DLY;
935 }
936
937 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_2, mask, val);
938
939 wm8996->hpout_ena = wm8996->hpout_pending;
940 }
941}
942
943static int dcs_start(struct snd_soc_dapm_widget *w,
944 struct snd_kcontrol *kcontrol, int event)
945{
946 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(w->codec);
947
948 switch (event) {
949 case SND_SOC_DAPM_POST_PMU:
950 wm8996->dcs_pending |= 1 << w->shift;
951 break;
952 default:
953 BUG();
954 return -EINVAL;
955 }
956
957 return 0;
958}
959
960static const char *sidetone_text[] = {
961 "IN1", "IN2",
962};
963
964static const struct soc_enum left_sidetone_enum =
965 SOC_ENUM_SINGLE(WM8996_SIDETONE, 0, 2, sidetone_text);
966
967static const struct snd_kcontrol_new left_sidetone =
968 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
969
970static const struct soc_enum right_sidetone_enum =
971 SOC_ENUM_SINGLE(WM8996_SIDETONE, 1, 2, sidetone_text);
972
973static const struct snd_kcontrol_new right_sidetone =
974 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
975
976static const char *spk_text[] = {
977 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
978};
979
980static const struct soc_enum spkl_enum =
981 SOC_ENUM_SINGLE(WM8996_LEFT_PDM_SPEAKER, 0, 4, spk_text);
982
983static const struct snd_kcontrol_new spkl_mux =
984 SOC_DAPM_ENUM("SPKL", spkl_enum);
985
986static const struct soc_enum spkr_enum =
987 SOC_ENUM_SINGLE(WM8996_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
988
989static const struct snd_kcontrol_new spkr_mux =
990 SOC_DAPM_ENUM("SPKR", spkr_enum);
991
992static const char *dsp1rx_text[] = {
993 "AIF1", "AIF2"
994};
995
996static const struct soc_enum dsp1rx_enum =
997 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
998
999static const struct snd_kcontrol_new dsp1rx =
1000 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
1001
1002static const char *dsp2rx_text[] = {
1003 "AIF2", "AIF1"
1004};
1005
1006static const struct soc_enum dsp2rx_enum =
1007 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
1008
1009static const struct snd_kcontrol_new dsp2rx =
1010 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
1011
1012static const char *aif2tx_text[] = {
1013 "DSP2", "DSP1", "AIF1"
1014};
1015
1016static const struct soc_enum aif2tx_enum =
1017 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
1018
1019static const struct snd_kcontrol_new aif2tx =
1020 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
1021
1022static const char *inmux_text[] = {
1023 "ADC", "DMIC1", "DMIC2"
1024};
1025
1026static const struct soc_enum in1_enum =
1027 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 0, 3, inmux_text);
1028
1029static const struct snd_kcontrol_new in1_mux =
1030 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
1031
1032static const struct soc_enum in2_enum =
1033 SOC_ENUM_SINGLE(WM8996_POWER_MANAGEMENT_7, 4, 3, inmux_text);
1034
1035static const struct snd_kcontrol_new in2_mux =
1036 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
1037
1038static const struct snd_kcontrol_new dac2r_mix[] = {
1039SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
1040 5, 1, 0),
1041SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
1042 4, 1, 0),
1043SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
1044SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
1045};
1046
1047static const struct snd_kcontrol_new dac2l_mix[] = {
1048SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
1049 5, 1, 0),
1050SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
1051 4, 1, 0),
1052SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
1053SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
1054};
1055
1056static const struct snd_kcontrol_new dac1r_mix[] = {
1057SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
1058 5, 1, 0),
1059SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
1060 4, 1, 0),
1061SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
1062SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
1063};
1064
1065static const struct snd_kcontrol_new dac1l_mix[] = {
1066SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
1067 5, 1, 0),
1068SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
1069 4, 1, 0),
1070SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
1071SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
1072};
1073
1074static const struct snd_kcontrol_new dsp1txl[] = {
1075SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1076 1, 1, 0),
1077SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
1078 0, 1, 0),
1079};
1080
1081static const struct snd_kcontrol_new dsp1txr[] = {
1082SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1083 1, 1, 0),
1084SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
1085 0, 1, 0),
1086};
1087
1088static const struct snd_kcontrol_new dsp2txl[] = {
1089SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1090 1, 1, 0),
1091SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
1092 0, 1, 0),
1093};
1094
1095static const struct snd_kcontrol_new dsp2txr[] = {
1096SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1097 1, 1, 0),
1098SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
1099 0, 1, 0),
1100};
1101
1102
1103static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
1104SND_SOC_DAPM_INPUT("IN1LN"),
1105SND_SOC_DAPM_INPUT("IN1LP"),
1106SND_SOC_DAPM_INPUT("IN1RN"),
1107SND_SOC_DAPM_INPUT("IN1RP"),
1108
1109SND_SOC_DAPM_INPUT("IN2LN"),
1110SND_SOC_DAPM_INPUT("IN2LP"),
1111SND_SOC_DAPM_INPUT("IN2RN"),
1112SND_SOC_DAPM_INPUT("IN2RP"),
1113
1114SND_SOC_DAPM_INPUT("DMIC1DAT"),
1115SND_SOC_DAPM_INPUT("DMIC2DAT"),
1116
1117SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
1118SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
1119SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
1120SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
ded71dcb
MB		 1121 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1122SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
1123 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
a9ba6151 1124SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
889c85c5
MB		 1125SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
1126SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
a9ba6151
MB		 1127SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
1128SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
1129
1130SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
1131SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
1132
7691cd74
MB		 1133SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
1134SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
1135SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
1136SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
a9ba6151
MB		 1137
1138SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1139SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1140
1141SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
1142SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
1143SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
1144SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
1145
1146SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
1147SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
1148
1149SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1150SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1151
1152SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
1153SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
1154SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
1155SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
1156
1157SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
1158 dsp2txl, ARRAY_SIZE(dsp2txl)),
1159SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
1160 dsp2txr, ARRAY_SIZE(dsp2txr)),
1161SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
1162 dsp1txl, ARRAY_SIZE(dsp1txl)),
1163SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
1164 dsp1txr, ARRAY_SIZE(dsp1txr)),
1165
1166SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1167 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1168SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1169 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1170SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1171 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1172SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1173 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1174
1175SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
1176SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
1177SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
1178SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
1179
32d2a0c1 1180SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
a9ba6151 1181 WM8996_POWER_MANAGEMENT_4, 9, 0),
32d2a0c1 1182SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 1,
a9ba6151
MB		 1183 WM8996_POWER_MANAGEMENT_4, 8, 0),
1184
ff39dbe9 1185SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
a9ba6151 1186 WM8996_POWER_MANAGEMENT_6, 9, 0),
ff39dbe9 1187SND_SOC_DAPM_AIF_OUT("AIF2TX0", "AIF2 Capture", 1,
a9ba6151
MB		 1188 WM8996_POWER_MANAGEMENT_6, 8, 0),
1189
1190SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1191 WM8996_POWER_MANAGEMENT_4, 5, 0),
1192SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1193 WM8996_POWER_MANAGEMENT_4, 4, 0),
1194SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1195 WM8996_POWER_MANAGEMENT_4, 3, 0),
1196SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1197 WM8996_POWER_MANAGEMENT_4, 2, 0),
1198SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1199 WM8996_POWER_MANAGEMENT_4, 1, 0),
1200SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1201 WM8996_POWER_MANAGEMENT_4, 0, 0),
1202
1203SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1204 WM8996_POWER_MANAGEMENT_6, 5, 0),
1205SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1206 WM8996_POWER_MANAGEMENT_6, 4, 0),
1207SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1208 WM8996_POWER_MANAGEMENT_6, 3, 0),
1209SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1210 WM8996_POWER_MANAGEMENT_6, 2, 0),
1211SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1212 WM8996_POWER_MANAGEMENT_6, 1, 0),
1213SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1214 WM8996_POWER_MANAGEMENT_6, 0, 0),
1215
1216/* We route as stereo pairs so define some dummy widgets to squash
1217 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1218SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1219SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1220SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1221SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1222SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1223
1224SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1225SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1226SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1227
1228SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1229SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1230SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1231SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1232
1233SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1234SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1235SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1236 SND_SOC_DAPM_POST_PMU),
1237SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8996_ANALOGUE_HP_2, 6, 0, NULL, 0),
1238SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1239 rmv_short_event,
1240 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1241
1242SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1243SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1244SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1245 SND_SOC_DAPM_POST_PMU),
1246SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8996_ANALOGUE_HP_2, 2, 0, NULL, 0),
1247SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1248 rmv_short_event,
1249 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1250
1251SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1252SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1253SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1254 SND_SOC_DAPM_POST_PMU),
1255SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8996_ANALOGUE_HP_1, 6, 0, NULL, 0),
1256SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1257 rmv_short_event,
1258 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1259
1260SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1261SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1262SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1263 SND_SOC_DAPM_POST_PMU),
1264SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8996_ANALOGUE_HP_1, 2, 0, NULL, 0),
1265SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1266 rmv_short_event,
1267 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1268
1269SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1270SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1271SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1272SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1273SND_SOC_DAPM_OUTPUT("SPKDAT"),
1274};
1275
1276static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1277 { "AIFCLK", NULL, "SYSCLK" },
1278 { "SYSDSPCLK", NULL, "SYSCLK" },
1279 { "Charge Pump", NULL, "SYSCLK" },
1280
1281 { "MICB1", NULL, "LDO2" },
889c85c5 1282 { "MICB1", NULL, "MICB1 Audio" },
8259df12 1283 { "MICB1", NULL, "Bandgap" },
a9ba6151 1284 { "MICB2", NULL, "LDO2" },
889c85c5 1285 { "MICB2", NULL, "MICB2 Audio" },
8259df12 1286 { "MICB2", NULL, "Bandgap" },
a9ba6151
MB		 1287
1288 { "IN1L PGA", NULL, "IN2LN" },
1289 { "IN1L PGA", NULL, "IN2LP" },
1290 { "IN1L PGA", NULL, "IN1LN" },
1291 { "IN1L PGA", NULL, "IN1LP" },
8259df12 1292 { "IN1L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1293
1294 { "IN1R PGA", NULL, "IN2RN" },
1295 { "IN1R PGA", NULL, "IN2RP" },
1296 { "IN1R PGA", NULL, "IN1RN" },
1297 { "IN1R PGA", NULL, "IN1RP" },
8259df12 1298 { "IN1R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1299
1300 { "ADCL", NULL, "IN1L PGA" },
1301
1302 { "ADCR", NULL, "IN1R PGA" },
1303
1304 { "DMIC1L", NULL, "DMIC1DAT" },
1305 { "DMIC1R", NULL, "DMIC1DAT" },
1306 { "DMIC2L", NULL, "DMIC2DAT" },
1307 { "DMIC2R", NULL, "DMIC2DAT" },
1308
1309 { "DMIC2L", NULL, "DMIC2" },
1310 { "DMIC2R", NULL, "DMIC2" },
1311 { "DMIC1L", NULL, "DMIC1" },
1312 { "DMIC1R", NULL, "DMIC1" },
1313
1314 { "IN1L Mux", "ADC", "ADCL" },
1315 { "IN1L Mux", "DMIC1", "DMIC1L" },
1316 { "IN1L Mux", "DMIC2", "DMIC2L" },
1317
1318 { "IN1R Mux", "ADC", "ADCR" },
1319 { "IN1R Mux", "DMIC1", "DMIC1R" },
1320 { "IN1R Mux", "DMIC2", "DMIC2R" },
1321
1322 { "IN2L Mux", "ADC", "ADCL" },
1323 { "IN2L Mux", "DMIC1", "DMIC1L" },
1324 { "IN2L Mux", "DMIC2", "DMIC2L" },
1325
1326 { "IN2R Mux", "ADC", "ADCR" },
1327 { "IN2R Mux", "DMIC1", "DMIC1R" },
1328 { "IN2R Mux", "DMIC2", "DMIC2R" },
1329
1330 { "Left Sidetone", "IN1", "IN1L Mux" },
1331 { "Left Sidetone", "IN2", "IN2L Mux" },
1332
1333 { "Right Sidetone", "IN1", "IN1R Mux" },
1334 { "Right Sidetone", "IN2", "IN2R Mux" },
1335
1336 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1337 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1338
1339 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1340 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1341
1342 { "AIF1TX0", NULL, "DSP1TXL" },
1343 { "AIF1TX1", NULL, "DSP1TXR" },
1344 { "AIF1TX2", NULL, "DSP2TXL" },
1345 { "AIF1TX3", NULL, "DSP2TXR" },
1346 { "AIF1TX4", NULL, "AIF2RX0" },
1347 { "AIF1TX5", NULL, "AIF2RX1" },
1348
1349 { "AIF1RX0", NULL, "AIFCLK" },
1350 { "AIF1RX1", NULL, "AIFCLK" },
1351 { "AIF1RX2", NULL, "AIFCLK" },
1352 { "AIF1RX3", NULL, "AIFCLK" },
1353 { "AIF1RX4", NULL, "AIFCLK" },
1354 { "AIF1RX5", NULL, "AIFCLK" },
1355
1356 { "AIF2RX0", NULL, "AIFCLK" },
1357 { "AIF2RX1", NULL, "AIFCLK" },
1358
4f41adfd
MB		 1359 { "AIF1TX0", NULL, "AIFCLK" },
1360 { "AIF1TX1", NULL, "AIFCLK" },
1361 { "AIF1TX2", NULL, "AIFCLK" },
1362 { "AIF1TX3", NULL, "AIFCLK" },
1363 { "AIF1TX4", NULL, "AIFCLK" },
1364 { "AIF1TX5", NULL, "AIFCLK" },
1365
1366 { "AIF2TX0", NULL, "AIFCLK" },
1367 { "AIF2TX1", NULL, "AIFCLK" },
1368
a9ba6151
MB		 1369 { "DSP1RXL", NULL, "SYSDSPCLK" },
1370 { "DSP1RXR", NULL, "SYSDSPCLK" },
1371 { "DSP2RXL", NULL, "SYSDSPCLK" },
1372 { "DSP2RXR", NULL, "SYSDSPCLK" },
1373 { "DSP1TXL", NULL, "SYSDSPCLK" },
1374 { "DSP1TXR", NULL, "SYSDSPCLK" },
1375 { "DSP2TXL", NULL, "SYSDSPCLK" },
1376 { "DSP2TXR", NULL, "SYSDSPCLK" },
1377
1378 { "AIF1RXA", NULL, "AIF1RX0" },
1379 { "AIF1RXA", NULL, "AIF1RX1" },
1380 { "AIF1RXB", NULL, "AIF1RX2" },
1381 { "AIF1RXB", NULL, "AIF1RX3" },
1382 { "AIF1RXC", NULL, "AIF1RX4" },
1383 { "AIF1RXC", NULL, "AIF1RX5" },
1384
1385 { "AIF2RX", NULL, "AIF2RX0" },
1386 { "AIF2RX", NULL, "AIF2RX1" },
1387
1388 { "AIF2TX", "DSP2", "DSP2TX" },
1389 { "AIF2TX", "DSP1", "DSP1RX" },
1390 { "AIF2TX", "AIF1", "AIF1RXC" },
1391
1392 { "DSP1RXL", NULL, "DSP1RX" },
1393 { "DSP1RXR", NULL, "DSP1RX" },
1394 { "DSP2RXL", NULL, "DSP2RX" },
1395 { "DSP2RXR", NULL, "DSP2RX" },
1396
1397 { "DSP2TX", NULL, "DSP2TXL" },
1398 { "DSP2TX", NULL, "DSP2TXR" },
1399
1400 { "DSP1RX", "AIF1", "AIF1RXA" },
1401 { "DSP1RX", "AIF2", "AIF2RX" },
1402
1403 { "DSP2RX", "AIF1", "AIF1RXB" },
1404 { "DSP2RX", "AIF2", "AIF2RX" },
1405
1406 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1407 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1408 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1409 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1410
1411 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1412 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1413 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1414 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1415
1416 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1417 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1418 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1419 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1420
1421 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1422 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1423 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1424 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1425
1426 { "DAC1L", NULL, "DAC1L Mixer" },
1427 { "DAC1R", NULL, "DAC1R Mixer" },
1428 { "DAC2L", NULL, "DAC2L Mixer" },
1429 { "DAC2R", NULL, "DAC2R Mixer" },
1430
1431 { "HPOUT2L PGA", NULL, "Charge Pump" },
8259df12 1432 { "HPOUT2L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1433 { "HPOUT2L PGA", NULL, "DAC2L" },
1434 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1435 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1436 { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1437 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1438
1439 { "HPOUT2R PGA", NULL, "Charge Pump" },
8259df12 1440 { "HPOUT2R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1441 { "HPOUT2R PGA", NULL, "DAC2R" },
1442 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1443 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1444 { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1445 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1446
1447 { "HPOUT1L PGA", NULL, "Charge Pump" },
8259df12 1448 { "HPOUT1L PGA", NULL, "Bandgap" },
a9ba6151
MB		 1449 { "HPOUT1L PGA", NULL, "DAC1L" },
1450 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1451 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1452 { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1453 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1454
1455 { "HPOUT1R PGA", NULL, "Charge Pump" },
8259df12 1456 { "HPOUT1R PGA", NULL, "Bandgap" },
a9ba6151
MB		 1457 { "HPOUT1R PGA", NULL, "DAC1R" },
1458 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1459 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1460 { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1461 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1462
1463 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1464 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1465 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1466 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1467
1468 { "SPKL", "DAC1L", "DAC1L" },
1469 { "SPKL", "DAC1R", "DAC1R" },
1470 { "SPKL", "DAC2L", "DAC2L" },
1471 { "SPKL", "DAC2R", "DAC2R" },
1472
1473 { "SPKR", "DAC1L", "DAC1L" },
1474 { "SPKR", "DAC1R", "DAC1R" },
1475 { "SPKR", "DAC2L", "DAC2L" },
1476 { "SPKR", "DAC2R", "DAC2R" },
1477
1478 { "SPKL PGA", NULL, "SPKL" },
1479 { "SPKR PGA", NULL, "SPKR" },
1480
1481 { "SPKDAT", NULL, "SPKL PGA" },
1482 { "SPKDAT", NULL, "SPKR PGA" },
1483};
1484
79172746 1485static bool wm8996_readable_register(struct device *dev, unsigned int reg)
a9ba6151
MB		 1486{
1487 /* Due to the sparseness of the register map the compiler
1488 * output from an explicit switch statement ends up being much
1489 * more efficient than a table.
1490 */
1491 switch (reg) {
1492 case WM8996_SOFTWARE_RESET:
1493 case WM8996_POWER_MANAGEMENT_1:
1494 case WM8996_POWER_MANAGEMENT_2:
1495 case WM8996_POWER_MANAGEMENT_3:
1496 case WM8996_POWER_MANAGEMENT_4:
1497 case WM8996_POWER_MANAGEMENT_5:
1498 case WM8996_POWER_MANAGEMENT_6:
1499 case WM8996_POWER_MANAGEMENT_7:
1500 case WM8996_POWER_MANAGEMENT_8:
1501 case WM8996_LEFT_LINE_INPUT_VOLUME:
1502 case WM8996_RIGHT_LINE_INPUT_VOLUME:
1503 case WM8996_LINE_INPUT_CONTROL:
1504 case WM8996_DAC1_HPOUT1_VOLUME:
1505 case WM8996_DAC2_HPOUT2_VOLUME:
1506 case WM8996_DAC1_LEFT_VOLUME:
1507 case WM8996_DAC1_RIGHT_VOLUME:
1508 case WM8996_DAC2_LEFT_VOLUME:
1509 case WM8996_DAC2_RIGHT_VOLUME:
1510 case WM8996_OUTPUT1_LEFT_VOLUME:
1511 case WM8996_OUTPUT1_RIGHT_VOLUME:
1512 case WM8996_OUTPUT2_LEFT_VOLUME:
1513 case WM8996_OUTPUT2_RIGHT_VOLUME:
1514 case WM8996_MICBIAS_1:
1515 case WM8996_MICBIAS_2:
1516 case WM8996_LDO_1:
1517 case WM8996_LDO_2:
1518 case WM8996_ACCESSORY_DETECT_MODE_1:
1519 case WM8996_ACCESSORY_DETECT_MODE_2:
1520 case WM8996_HEADPHONE_DETECT_1:
1521 case WM8996_HEADPHONE_DETECT_2:
1522 case WM8996_MIC_DETECT_1:
1523 case WM8996_MIC_DETECT_2:
1524 case WM8996_MIC_DETECT_3:
1525 case WM8996_CHARGE_PUMP_1:
1526 case WM8996_CHARGE_PUMP_2:
1527 case WM8996_DC_SERVO_1:
1528 case WM8996_DC_SERVO_2:
1529 case WM8996_DC_SERVO_3:
1530 case WM8996_DC_SERVO_5:
1531 case WM8996_DC_SERVO_6:
1532 case WM8996_DC_SERVO_7:
1533 case WM8996_DC_SERVO_READBACK_0:
1534 case WM8996_ANALOGUE_HP_1:
1535 case WM8996_ANALOGUE_HP_2:
1536 case WM8996_CHIP_REVISION:
1537 case WM8996_CONTROL_INTERFACE_1:
1538 case WM8996_WRITE_SEQUENCER_CTRL_1:
1539 case WM8996_WRITE_SEQUENCER_CTRL_2:
1540 case WM8996_AIF_CLOCKING_1:
1541 case WM8996_AIF_CLOCKING_2:
1542 case WM8996_CLOCKING_1:
1543 case WM8996_CLOCKING_2:
1544 case WM8996_AIF_RATE:
1545 case WM8996_FLL_CONTROL_1:
1546 case WM8996_FLL_CONTROL_2:
1547 case WM8996_FLL_CONTROL_3:
1548 case WM8996_FLL_CONTROL_4:
1549 case WM8996_FLL_CONTROL_5:
1550 case WM8996_FLL_CONTROL_6:
1551 case WM8996_FLL_EFS_1:
1552 case WM8996_FLL_EFS_2:
1553 case WM8996_AIF1_CONTROL:
1554 case WM8996_AIF1_BCLK:
1555 case WM8996_AIF1_TX_LRCLK_1:
1556 case WM8996_AIF1_TX_LRCLK_2:
1557 case WM8996_AIF1_RX_LRCLK_1:
1558 case WM8996_AIF1_RX_LRCLK_2:
1559 case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1560 case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1561 case WM8996_AIF1RX_DATA_CONFIGURATION:
1562 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1563 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1564 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1565 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1566 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1567 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1568 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1569 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1570 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1571 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1572 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1573 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1574 case WM8996_AIF1RX_MONO_CONFIGURATION:
1575 case WM8996_AIF1TX_TEST:
1576 case WM8996_AIF2_CONTROL:
1577 case WM8996_AIF2_BCLK:
1578 case WM8996_AIF2_TX_LRCLK_1:
1579 case WM8996_AIF2_TX_LRCLK_2:
1580 case WM8996_AIF2_RX_LRCLK_1:
1581 case WM8996_AIF2_RX_LRCLK_2:
1582 case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1583 case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1584 case WM8996_AIF2RX_DATA_CONFIGURATION:
1585 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1586 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1587 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1588 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1589 case WM8996_AIF2RX_MONO_CONFIGURATION:
1590 case WM8996_AIF2TX_TEST:
1591 case WM8996_DSP1_TX_LEFT_VOLUME:
1592 case WM8996_DSP1_TX_RIGHT_VOLUME:
1593 case WM8996_DSP1_RX_LEFT_VOLUME:
1594 case WM8996_DSP1_RX_RIGHT_VOLUME:
1595 case WM8996_DSP1_TX_FILTERS:
1596 case WM8996_DSP1_RX_FILTERS_1:
1597 case WM8996_DSP1_RX_FILTERS_2:
1598 case WM8996_DSP1_DRC_1:
1599 case WM8996_DSP1_DRC_2:
1600 case WM8996_DSP1_DRC_3:
1601 case WM8996_DSP1_DRC_4:
1602 case WM8996_DSP1_DRC_5:
1603 case WM8996_DSP1_RX_EQ_GAINS_1:
1604 case WM8996_DSP1_RX_EQ_GAINS_2:
1605 case WM8996_DSP1_RX_EQ_BAND_1_A:
1606 case WM8996_DSP1_RX_EQ_BAND_1_B:
1607 case WM8996_DSP1_RX_EQ_BAND_1_PG:
1608 case WM8996_DSP1_RX_EQ_BAND_2_A:
1609 case WM8996_DSP1_RX_EQ_BAND_2_B:
1610 case WM8996_DSP1_RX_EQ_BAND_2_C:
1611 case WM8996_DSP1_RX_EQ_BAND_2_PG:
1612 case WM8996_DSP1_RX_EQ_BAND_3_A:
1613 case WM8996_DSP1_RX_EQ_BAND_3_B:
1614 case WM8996_DSP1_RX_EQ_BAND_3_C:
1615 case WM8996_DSP1_RX_EQ_BAND_3_PG:
1616 case WM8996_DSP1_RX_EQ_BAND_4_A:
1617 case WM8996_DSP1_RX_EQ_BAND_4_B:
1618 case WM8996_DSP1_RX_EQ_BAND_4_C:
1619 case WM8996_DSP1_RX_EQ_BAND_4_PG:
1620 case WM8996_DSP1_RX_EQ_BAND_5_A:
1621 case WM8996_DSP1_RX_EQ_BAND_5_B:
1622 case WM8996_DSP1_RX_EQ_BAND_5_PG:
1623 case WM8996_DSP2_TX_LEFT_VOLUME:
1624 case WM8996_DSP2_TX_RIGHT_VOLUME:
1625 case WM8996_DSP2_RX_LEFT_VOLUME:
1626 case WM8996_DSP2_RX_RIGHT_VOLUME:
1627 case WM8996_DSP2_TX_FILTERS:
1628 case WM8996_DSP2_RX_FILTERS_1:
1629 case WM8996_DSP2_RX_FILTERS_2:
1630 case WM8996_DSP2_DRC_1:
1631 case WM8996_DSP2_DRC_2:
1632 case WM8996_DSP2_DRC_3:
1633 case WM8996_DSP2_DRC_4:
1634 case WM8996_DSP2_DRC_5:
1635 case WM8996_DSP2_RX_EQ_GAINS_1:
1636 case WM8996_DSP2_RX_EQ_GAINS_2:
1637 case WM8996_DSP2_RX_EQ_BAND_1_A:
1638 case WM8996_DSP2_RX_EQ_BAND_1_B:
1639 case WM8996_DSP2_RX_EQ_BAND_1_PG:
1640 case WM8996_DSP2_RX_EQ_BAND_2_A:
1641 case WM8996_DSP2_RX_EQ_BAND_2_B:
1642 case WM8996_DSP2_RX_EQ_BAND_2_C:
1643 case WM8996_DSP2_RX_EQ_BAND_2_PG:
1644 case WM8996_DSP2_RX_EQ_BAND_3_A:
1645 case WM8996_DSP2_RX_EQ_BAND_3_B:
1646 case WM8996_DSP2_RX_EQ_BAND_3_C:
1647 case WM8996_DSP2_RX_EQ_BAND_3_PG:
1648 case WM8996_DSP2_RX_EQ_BAND_4_A:
1649 case WM8996_DSP2_RX_EQ_BAND_4_B:
1650 case WM8996_DSP2_RX_EQ_BAND_4_C:
1651 case WM8996_DSP2_RX_EQ_BAND_4_PG:
1652 case WM8996_DSP2_RX_EQ_BAND_5_A:
1653 case WM8996_DSP2_RX_EQ_BAND_5_B:
1654 case WM8996_DSP2_RX_EQ_BAND_5_PG:
1655 case WM8996_DAC1_MIXER_VOLUMES:
1656 case WM8996_DAC1_LEFT_MIXER_ROUTING:
1657 case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1658 case WM8996_DAC2_MIXER_VOLUMES:
1659 case WM8996_DAC2_LEFT_MIXER_ROUTING:
1660 case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1661 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1662 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1663 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1664 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1665 case WM8996_DSP_TX_MIXER_SELECT:
1666 case WM8996_DAC_SOFTMUTE:
1667 case WM8996_OVERSAMPLING:
1668 case WM8996_SIDETONE:
1669 case WM8996_GPIO_1:
1670 case WM8996_GPIO_2:
1671 case WM8996_GPIO_3:
1672 case WM8996_GPIO_4:
1673 case WM8996_GPIO_5:
1674 case WM8996_PULL_CONTROL_1:
1675 case WM8996_PULL_CONTROL_2:
1676 case WM8996_INTERRUPT_STATUS_1:
1677 case WM8996_INTERRUPT_STATUS_2:
1678 case WM8996_INTERRUPT_RAW_STATUS_2:
1679 case WM8996_INTERRUPT_STATUS_1_MASK:
1680 case WM8996_INTERRUPT_STATUS_2_MASK:
1681 case WM8996_INTERRUPT_CONTROL:
1682 case WM8996_LEFT_PDM_SPEAKER:
1683 case WM8996_RIGHT_PDM_SPEAKER:
1684 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1685 case WM8996_PDM_SPEAKER_VOLUME:
1686 return 1;
1687 default:
1688 return 0;
1689 }
1690}
1691
79172746 1692static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
a9ba6151
MB		 1693{
1694 switch (reg) {
1695 case WM8996_SOFTWARE_RESET:
1696 case WM8996_CHIP_REVISION:
1697 case WM8996_LDO_1:
1698 case WM8996_LDO_2:
1699 case WM8996_INTERRUPT_STATUS_1:
1700 case WM8996_INTERRUPT_STATUS_2:
1701 case WM8996_INTERRUPT_RAW_STATUS_2:
1702 case WM8996_DC_SERVO_READBACK_0:
1703 case WM8996_DC_SERVO_2:
1704 case WM8996_DC_SERVO_6:
1705 case WM8996_DC_SERVO_7:
1706 case WM8996_FLL_CONTROL_6:
1707 case WM8996_MIC_DETECT_3:
1708 case WM8996_HEADPHONE_DETECT_1:
1709 case WM8996_HEADPHONE_DETECT_2:
1710 return 1;
1711 default:
1712 return 0;
1713 }
1714}
1715
1716static int wm8996_reset(struct snd_soc_codec *codec)
1717{
1718 return snd_soc_write(codec, WM8996_SOFTWARE_RESET, 0x8915);
1719}
1720
1721static const int bclk_divs[] = {
1722 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1723};
1724
1725static void wm8996_update_bclk(struct snd_soc_codec *codec)
1726{
1727 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1728 int aif, best, cur_val, bclk_rate, bclk_reg, i;
1729
1730 /* Don't bother if we're in a low frequency idle mode that
1731 * can't support audio.
1732 */
1733 if (wm8996->sysclk < 64000)
1734 return;
1735
1736 for (aif = 0; aif < WM8996_AIFS; aif++) {
1737 switch (aif) {
1738 case 0:
1739 bclk_reg = WM8996_AIF1_BCLK;
1740 break;
1741 case 1:
1742 bclk_reg = WM8996_AIF2_BCLK;
1743 break;
1744 }
1745
1746 bclk_rate = wm8996->bclk_rate[aif];
1747
1748 /* Pick a divisor for BCLK as close as we can get to ideal */
1749 best = 0;
1750 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1751 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1752 if (cur_val < 0) /* BCLK table is sorted */
1753 break;
1754 best = i;
1755 }
1756 bclk_rate = wm8996->sysclk / bclk_divs[best];
1757 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1758 bclk_divs[best], bclk_rate);
1759
1760 snd_soc_update_bits(codec, bclk_reg,
1761 WM8996_AIF1_BCLK_DIV_MASK, best);
1762 }
1763}
1764
1765static int wm8996_set_bias_level(struct snd_soc_codec *codec,
1766 enum snd_soc_bias_level level)
1767{
1768 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1769 int ret;
1770
1771 switch (level) {
1772 case SND_SOC_BIAS_ON:
a9ba6151 1773 case SND_SOC_BIAS_PREPARE:
a9ba6151
MB		 1774 break;
1775
1776 case SND_SOC_BIAS_STANDBY:
1777 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1778 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1779 wm8996->supplies);
1780 if (ret != 0) {
1781 dev_err(codec->dev,
1782 "Failed to enable supplies: %d\n",
1783 ret);
1784 return ret;
1785 }
1786
1787 if (wm8996->pdata.ldo_ena >= 0) {
1788 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1789 1);
1790 msleep(5);
1791 }
1792
79172746
MB		 1793 regcache_cache_only(codec->control_data, false);
1794 regcache_sync(codec->control_data);
a9ba6151 1795 }
a9ba6151
MB		 1796 break;
1797
1798 case SND_SOC_BIAS_OFF:
79172746 1799 regcache_cache_only(codec->control_data, true);
a9ba6151
MB		 1800 if (wm8996->pdata.ldo_ena >= 0)
1801 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1802 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1803 wm8996->supplies);
1804 break;
1805 }
1806
1807 codec->dapm.bias_level = level;
1808
1809 return 0;
1810}
1811
1812static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1813{
1814 struct snd_soc_codec *codec = dai->codec;
1815 int aifctrl = 0;
1816 int bclk = 0;
1817 int lrclk_tx = 0;
1818 int lrclk_rx = 0;
1819 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1820
1821 switch (dai->id) {
1822 case 0:
1823 aifctrl_reg = WM8996_AIF1_CONTROL;
1824 bclk_reg = WM8996_AIF1_BCLK;
1825 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1826 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1827 break;
1828 case 1:
1829 aifctrl_reg = WM8996_AIF2_CONTROL;
1830 bclk_reg = WM8996_AIF2_BCLK;
1831 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1832 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1833 break;
1834 default:
1835 BUG();
1836 return -EINVAL;
1837 }
1838
1839 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1840 case SND_SOC_DAIFMT_NB_NF:
1841 break;
1842 case SND_SOC_DAIFMT_IB_NF:
1843 bclk |= WM8996_AIF1_BCLK_INV;
1844 break;
1845 case SND_SOC_DAIFMT_NB_IF:
1846 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1847 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1848 break;
1849 case SND_SOC_DAIFMT_IB_IF:
1850 bclk |= WM8996_AIF1_BCLK_INV;
1851 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1852 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1853 break;
1854 }
1855
1856 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1857 case SND_SOC_DAIFMT_CBS_CFS:
1858 break;
1859 case SND_SOC_DAIFMT_CBS_CFM:
1860 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1861 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1862 break;
1863 case SND_SOC_DAIFMT_CBM_CFS:
1864 bclk |= WM8996_AIF1_BCLK_MSTR;
1865 break;
1866 case SND_SOC_DAIFMT_CBM_CFM:
1867 bclk |= WM8996_AIF1_BCLK_MSTR;
1868 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1869 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1870 break;
1871 default:
1872 return -EINVAL;
1873 }
1874
1875 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1876 case SND_SOC_DAIFMT_DSP_A:
1877 break;
1878 case SND_SOC_DAIFMT_DSP_B:
1879 aifctrl |= 1;
1880 break;
1881 case SND_SOC_DAIFMT_I2S:
1882 aifctrl |= 2;
1883 break;
1884 case SND_SOC_DAIFMT_LEFT_J:
1885 aifctrl |= 3;
1886 break;
1887 default:
1888 return -EINVAL;
1889 }
1890
1891 snd_soc_update_bits(codec, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1892 snd_soc_update_bits(codec, bclk_reg,
1893 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1894 bclk);
1895 snd_soc_update_bits(codec, lrclk_tx_reg,
1896 WM8996_AIF1TX_LRCLK_INV |
1897 WM8996_AIF1TX_LRCLK_MSTR,
1898 lrclk_tx);
1899 snd_soc_update_bits(codec, lrclk_rx_reg,
1900 WM8996_AIF1RX_LRCLK_INV |
1901 WM8996_AIF1RX_LRCLK_MSTR,
1902 lrclk_rx);
1903
1904 return 0;
1905}
1906
1907static const int dsp_divs[] = {
1908 48000, 32000, 16000, 8000
1909};
1910
1911static int wm8996_hw_params(struct snd_pcm_substream *substream,
1912 struct snd_pcm_hw_params *params,
1913 struct snd_soc_dai *dai)
1914{
1915 struct snd_soc_codec *codec = dai->codec;
1916 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
1917 int bits, i, bclk_rate;
1918 int aifdata = 0;
1919 int lrclk = 0;
1920 int dsp = 0;
1921 int aifdata_reg, lrclk_reg, dsp_shift;
1922
1923 switch (dai->id) {
1924 case 0:
1925 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1926 (snd_soc_read(codec, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1927 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1928 lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1929 } else {
1930 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1931 lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1932 }
1933 dsp_shift = 0;
1934 break;
1935 case 1:
1936 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1937 (snd_soc_read(codec, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1938 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1939 lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1940 } else {
1941 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1942 lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1943 }
1944 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1945 break;
1946 default:
1947 BUG();
1948 return -EINVAL;
1949 }
1950
1951 bclk_rate = snd_soc_params_to_bclk(params);
1952 if (bclk_rate < 0) {
1953 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1954 return bclk_rate;
1955 }
1956
1957 wm8996->bclk_rate[dai->id] = bclk_rate;
1958 wm8996->rx_rate[dai->id] = params_rate(params);
1959
1960 /* Needs looking at for TDM */
1961 bits = snd_pcm_format_width(params_format(params));
1962 if (bits < 0)
1963 return bits;
1964 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1965
1966 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1967 if (dsp_divs[i] == params_rate(params))
1968 break;
1969 }
1970 if (i == ARRAY_SIZE(dsp_divs)) {
1971 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1972 params_rate(params));
1973 return -EINVAL;
1974 }
1975 dsp |= i << dsp_shift;
1976
1977 wm8996_update_bclk(codec);
1978
1979 lrclk = bclk_rate / params_rate(params);
1980 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1981 lrclk, bclk_rate / lrclk);
1982
1983 snd_soc_update_bits(codec, aifdata_reg,
1984 WM8996_AIF1TX_WL_MASK |
1985 WM8996_AIF1TX_SLOT_LEN_MASK,
1986 aifdata);
1987 snd_soc_update_bits(codec, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1988 lrclk);
1989 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_2,
3205e662 1990 WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
a9ba6151
MB		 1991
1992 return 0;
1993}
1994
1995static int wm8996_set_sysclk(struct snd_soc_dai *dai,
1996 int clk_id, unsigned int freq, int dir)
1997{
1998 struct snd_soc_codec *codec = dai->codec;
1999 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2000 int lfclk = 0;
2001 int ratediv = 0;
2002 int src;
2003 int old;
2004
2005 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
2006 return 0;
2007
2008 /* Disable SYSCLK while we reconfigure */
2009 old = snd_soc_read(codec, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
2010 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2011 WM8996_SYSCLK_ENA, 0);
2012
2013 switch (clk_id) {
2014 case WM8996_SYSCLK_MCLK1:
2015 wm8996->sysclk = freq;
2016 src = 0;
2017 break;
2018 case WM8996_SYSCLK_MCLK2:
2019 wm8996->sysclk = freq;
2020 src = 1;
2021 break;
2022 case WM8996_SYSCLK_FLL:
2023 wm8996->sysclk = freq;
2024 src = 2;
2025 break;
2026 default:
2027 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
2028 return -EINVAL;
2029 }
2030
2031 switch (wm8996->sysclk) {
2032 case 6144000:
2033 snd_soc_update_bits(codec, WM8996_AIF_RATE,
2034 WM8996_SYSCLK_RATE, 0);
2035 break;
2036 case 24576000:
2037 ratediv = WM8996_SYSCLK_DIV;
2038 case 12288000:
2039 snd_soc_update_bits(codec, WM8996_AIF_RATE,
2040 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
2041 break;
2042 case 32000:
2043 case 32768:
2044 lfclk = WM8996_LFCLK_ENA;
2045 break;
2046 default:
2047 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
2048 wm8996->sysclk);
2049 return -EINVAL;
2050 }
2051
2052 wm8996_update_bclk(codec);
2053
2054 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2055 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
2056 src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
2057 snd_soc_update_bits(codec, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
2058 snd_soc_update_bits(codec, WM8996_AIF_CLOCKING_1,
2059 WM8996_SYSCLK_ENA, old);
2060
2061 wm8996->sysclk_src = clk_id;
2062
2063 return 0;
2064}
2065
2066struct _fll_div {
2067 u16 fll_fratio;
2068 u16 fll_outdiv;
2069 u16 fll_refclk_div;
2070 u16 fll_loop_gain;
2071 u16 fll_ref_freq;
2072 u16 n;
2073 u16 theta;
2074 u16 lambda;
2075};
2076
2077static struct {
2078 unsigned int min;
2079 unsigned int max;
2080 u16 fll_fratio;
2081 int ratio;
2082} fll_fratios[] = {
2083 { 0, 64000, 4, 16 },
2084 { 64000, 128000, 3, 8 },
2085 { 128000, 256000, 2, 4 },
2086 { 256000, 1000000, 1, 2 },
2087 { 1000000, 13500000, 0, 1 },
2088};
2089
2090static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2091 unsigned int Fout)
2092{
2093 unsigned int target;
2094 unsigned int div;
2095 unsigned int fratio, gcd_fll;
2096 int i;
2097
2098 /* Fref must be <=13.5MHz */
2099 div = 1;
2100 fll_div->fll_refclk_div = 0;
2101 while ((Fref / div) > 13500000) {
2102 div *= 2;
2103 fll_div->fll_refclk_div++;
2104
2105 if (div > 8) {
2106 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2107 Fref);
2108 return -EINVAL;
2109 }
2110 }
2111
2112 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2113
2114 /* Apply the division for our remaining calculations */
2115 Fref /= div;
2116
2117 if (Fref >= 3000000)
2118 fll_div->fll_loop_gain = 5;
2119 else
2120 fll_div->fll_loop_gain = 0;
2121
2122 if (Fref >= 48000)
2123 fll_div->fll_ref_freq = 0;
2124 else
2125 fll_div->fll_ref_freq = 1;
2126
2127 /* Fvco should be 90-100MHz; don't check the upper bound */
2128 div = 2;
2129 while (Fout * div < 90000000) {
2130 div++;
2131 if (div > 64) {
2132 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2133 Fout);
2134 return -EINVAL;
2135 }
2136 }
2137 target = Fout * div;
2138 fll_div->fll_outdiv = div - 1;
2139
2140 pr_debug("FLL Fvco=%dHz\n", target);
2141
2142 /* Find an appropraite FLL_FRATIO and factor it out of the target */
2143 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2144 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2145 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2146 fratio = fll_fratios[i].ratio;
2147 break;
2148 }
2149 }
2150 if (i == ARRAY_SIZE(fll_fratios)) {
2151 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2152 return -EINVAL;
2153 }
2154
2155 fll_div->n = target / (fratio * Fref);
2156
2157 if (target % Fref == 0) {
2158 fll_div->theta = 0;
2159 fll_div->lambda = 0;
2160 } else {
2161 gcd_fll = gcd(target, fratio * Fref);
2162
2163 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2164 / gcd_fll;
2165 fll_div->lambda = (fratio * Fref) / gcd_fll;
2166 }
2167
2168 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2169 fll_div->n, fll_div->theta, fll_div->lambda);
2170 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2171 fll_div->fll_fratio, fll_div->fll_outdiv,
2172 fll_div->fll_refclk_div);
2173
2174 return 0;
2175}
2176
2177static int wm8996_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2178 unsigned int Fref, unsigned int Fout)
2179{
2180 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2181 struct i2c_client *i2c = to_i2c_client(codec->dev);
2182 struct _fll_div fll_div;
2183 unsigned long timeout;
27b6d92a 2184 int ret, reg, retry;
a9ba6151
MB		 2185
2186 /* Any change? */
2187 if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2188 Fout == wm8996->fll_fout)
2189 return 0;
2190
2191 if (Fout == 0) {
2192 dev_dbg(codec->dev, "FLL disabled\n");
2193
2194 wm8996->fll_fref = 0;
2195 wm8996->fll_fout = 0;
2196
2197 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2198 WM8996_FLL_ENA, 0);
2199
ded71dcb
MB		 2200 wm8996_bg_disable(codec);
2201
a9ba6151
MB		 2202 return 0;
2203 }
2204
2205 ret = fll_factors(&fll_div, Fref, Fout);
2206 if (ret != 0)
2207 return ret;
2208
2209 switch (source) {
2210 case WM8996_FLL_MCLK1:
2211 reg = 0;
2212 break;
2213 case WM8996_FLL_MCLK2:
2214 reg = 1;
2215 break;
2216 case WM8996_FLL_DACLRCLK1:
2217 reg = 2;
2218 break;
2219 case WM8996_FLL_BCLK1:
2220 reg = 3;
2221 break;
2222 default:
2223 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2224 return -EINVAL;
2225 }
2226
2227 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2228 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2229
2230 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_5,
2231 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2232 WM8996_FLL_REFCLK_SRC_MASK, reg);
2233
2234 reg = 0;
2235 if (fll_div.theta || fll_div.lambda)
2236 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2237 else
2238 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2239 snd_soc_write(codec, WM8996_FLL_EFS_2, reg);
2240
2241 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_2,
2242 WM8996_FLL_OUTDIV_MASK |
2243 WM8996_FLL_FRATIO_MASK,
2244 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2245 (fll_div.fll_fratio));
2246
2247 snd_soc_write(codec, WM8996_FLL_CONTROL_3, fll_div.theta);
2248
2249 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_4,
2250 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2251 (fll_div.n << WM8996_FLL_N_SHIFT) |
2252 fll_div.fll_loop_gain);
2253
2254 snd_soc_write(codec, WM8996_FLL_EFS_1, fll_div.lambda);
2255
ded71dcb
MB		 2256 /* Enable the bandgap if it's not already enabled */
2257 ret = snd_soc_read(codec, WM8996_FLL_CONTROL_1);
2258 if (!(ret & WM8996_FLL_ENA))
2259 wm8996_bg_enable(codec);
2260
a4161945
MB		 2261 /* Clear any pending completions (eg, from failed startups) */
2262 try_wait_for_completion(&wm8996->fll_lock);
2263
a9ba6151
MB		 2264 snd_soc_update_bits(codec, WM8996_FLL_CONTROL_1,
2265 WM8996_FLL_ENA, WM8996_FLL_ENA);
2266
2267 /* The FLL supports live reconfiguration - kick that in case we were
2268 * already enabled.
2269 */
2270 snd_soc_write(codec, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2271
2272 /* Wait for the FLL to lock, using the interrupt if possible */
2273 if (Fref > 1000000)
2274 timeout = usecs_to_jiffies(300);
2275 else
2276 timeout = msecs_to_jiffies(2);
2277
27b6d92a
MB		 2278 /* Allow substantially longer if we've actually got the IRQ, poll
2279 * at a slightly higher rate if we don't.
2280 */
a9ba6151 2281 if (i2c->irq)
27b6d92a
MB		 2282 timeout *= 10;
2283 else
2284 timeout /= 2;
a9ba6151 2285
27b6d92a
MB		 2286 for (retry = 0; retry < 10; retry++) {
2287 ret = wait_for_completion_timeout(&wm8996->fll_lock,
2288 timeout);
2289 if (ret != 0) {
2290 WARN_ON(!i2c->irq);
2291 break;
2292 }
a9ba6151 2293
27b6d92a
MB		 2294 ret = snd_soc_read(codec, WM8996_INTERRUPT_RAW_STATUS_2);
2295 if (ret & WM8996_FLL_LOCK_STS)
2296 break;
2297 }
2298 if (retry == 10) {
a9ba6151
MB		 2299 dev_err(codec->dev, "Timed out waiting for FLL\n");
2300 ret = -ETIMEDOUT;
a9ba6151
MB		 2301 }
2302
2303 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2304
2305 wm8996->fll_fref = Fref;
2306 wm8996->fll_fout = Fout;
2307 wm8996->fll_src = source;
2308
2309 return ret;
2310}
2311
2312#ifdef CONFIG_GPIOLIB
2313static inline struct wm8996_priv *gpio_to_wm8996(struct gpio_chip *chip)
2314{
2315 return container_of(chip, struct wm8996_priv, gpio_chip);
2316}
2317
2318static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2319{
2320 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2321 struct snd_soc_codec *codec = wm8996->codec;
2322
2323 snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2324 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
2325}
2326
2327static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2328 unsigned offset, int value)
2329{
2330 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2331 struct snd_soc_codec *codec = wm8996->codec;
2332 int val;
2333
2334 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2335
2336 return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2337 WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2338 WM8996_GP1_LVL, val);
2339}
2340
2341static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2342{
2343 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2344 struct snd_soc_codec *codec = wm8996->codec;
2345 int ret;
2346
2347 ret = snd_soc_read(codec, WM8996_GPIO_1 + offset);
2348 if (ret < 0)
2349 return ret;
2350
2351 return (ret & WM8996_GP1_LVL) != 0;
2352}
2353
2354static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2355{
2356 struct wm8996_priv *wm8996 = gpio_to_wm8996(chip);
2357 struct snd_soc_codec *codec = wm8996->codec;
2358
2359 return snd_soc_update_bits(codec, WM8996_GPIO_1 + offset,
2360 WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2361 (1 << WM8996_GP1_FN_SHIFT) |
2362 (1 << WM8996_GP1_DIR_SHIFT));
2363}
2364
2365static struct gpio_chip wm8996_template_chip = {
2366 .label = "wm8996",
2367 .owner = THIS_MODULE,
2368 .direction_output = wm8996_gpio_direction_out,
2369 .set = wm8996_gpio_set,
2370 .direction_input = wm8996_gpio_direction_in,
2371 .get = wm8996_gpio_get,
2372 .can_sleep = 1,
2373};
2374
2375static void wm8996_init_gpio(struct snd_soc_codec *codec)
2376{
2377 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2378 int ret;
2379
2380 wm8996->gpio_chip = wm8996_template_chip;
2381 wm8996->gpio_chip.ngpio = 5;
2382 wm8996->gpio_chip.dev = codec->dev;
2383
2384 if (wm8996->pdata.gpio_base)
2385 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2386 else
2387 wm8996->gpio_chip.base = -1;
2388
2389 ret = gpiochip_add(&wm8996->gpio_chip);
2390 if (ret != 0)
2391 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2392}
2393
2394static void wm8996_free_gpio(struct snd_soc_codec *codec)
2395{
2396 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2397 int ret;
2398
2399 ret = gpiochip_remove(&wm8996->gpio_chip);
2400 if (ret != 0)
2401 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2402}
2403#else
2404static void wm8996_init_gpio(struct snd_soc_codec *codec)
2405{
2406}
2407
2408static void wm8996_free_gpio(struct snd_soc_codec *codec)
2409{
2410}
2411#endif
2412
2413/**
2414 * wm8996_detect - Enable default WM8996 jack detection
2415 *
2416 * The WM8996 has advanced accessory detection support for headsets.
2417 * This function provides a default implementation which integrates
2418 * the majority of this functionality with minimal user configuration.
2419 *
2420 * This will detect headset, headphone and short circuit button and
2421 * will also detect inverted microphone ground connections and update
2422 * the polarity of the connections.
2423 */
2424int wm8996_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2425 wm8996_polarity_fn polarity_cb)
2426{
2427 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2428
2429 wm8996->jack = jack;
2430 wm8996->detecting = true;
2431 wm8996->polarity_cb = polarity_cb;
2432
2433 if (wm8996->polarity_cb)
2434 wm8996->polarity_cb(codec, 0);
2435
2436 /* Clear discarge to avoid noise during detection */
2437 snd_soc_update_bits(codec, WM8996_MICBIAS_1,
2438 WM8996_MICB1_DISCH, 0);
2439 snd_soc_update_bits(codec, WM8996_MICBIAS_2,
2440 WM8996_MICB2_DISCH, 0);
2441
2442 /* LDO2 powers the microphones, SYSCLK clocks detection */
2443 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2444 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2445
2446 /* We start off just enabling microphone detection - even a
2447 * plain headphone will trigger detection.
2448 */
2449 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2450 WM8996_MICD_ENA, WM8996_MICD_ENA);
2451
2452 /* Slowest detection rate, gives debounce for initial detection */
2453 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2454 WM8996_MICD_RATE_MASK,
2455 WM8996_MICD_RATE_MASK);
2456
2457 /* Enable interrupts and we're off */
2458 snd_soc_update_bits(codec, WM8996_INTERRUPT_STATUS_2_MASK,
0b684cc1 2459 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
a9ba6151
MB		 2460
2461 return 0;
2462}
2463EXPORT_SYMBOL_GPL(wm8996_detect);
2464
0b684cc1
MB		 2465static void wm8996_hpdet_irq(struct snd_soc_codec *codec)
2466{
2467 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2468 int val, reg, report;
2469
2470 /* Assume headphone in error conditions; we need to report
2471 * something or we stall our state machine.
2472 */
2473 report = SND_JACK_HEADPHONE;
2474
2475 reg = snd_soc_read(codec, WM8996_HEADPHONE_DETECT_2);
2476 if (reg < 0) {
2477 dev_err(codec->dev, "Failed to read HPDET status\n");
2478 goto out;
2479 }
2480
2481 if (!(reg & WM8996_HP_DONE)) {
2482 dev_err(codec->dev, "Got HPDET IRQ but HPDET is busy\n");
2483 goto out;
2484 }
2485
2486 val = reg & WM8996_HP_LVL_MASK;
2487
2488 dev_dbg(codec->dev, "HPDET measured %d ohms\n", val);
2489
2490 /* If we've got high enough impedence then report as line,
2491 * otherwise assume headphone.
2492 */
2493 if (val >= 126)
2494 report = SND_JACK_LINEOUT;
2495 else
2496 report = SND_JACK_HEADPHONE;
2497
2498out:
2499 if (wm8996->jack_mic)
2500 report |= SND_JACK_MICROPHONE;
2501
2502 snd_soc_jack_report(wm8996->jack, report,
2503 SND_JACK_LINEOUT | SND_JACK_HEADSET);
2504
2505 wm8996->detecting = false;
2506
2507 /* If the output isn't running re-clamp it */
2508 if (!(snd_soc_read(codec, WM8996_POWER_MANAGEMENT_1) &
2509 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
2510 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2511 WM8996_HPOUT1L_RMV_SHORT |
2512 WM8996_HPOUT1R_RMV_SHORT, 0);
2513
2514 /* Go back to looking at the microphone */
2515 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2516 WM8996_JD_MODE_MASK, 0);
2517 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
2518 WM8996_MICD_ENA);
2519
2520 snd_soc_dapm_disable_pin(&codec->dapm, "Bandgap");
2521 snd_soc_dapm_sync(&codec->dapm);
2522}
2523
2524static void wm8996_hpdet_start(struct snd_soc_codec *codec)
2525{
2526 /* Unclamp the output, we can't measure while we're shorting it */
2527 snd_soc_update_bits(codec, WM8996_ANALOGUE_HP_1,
2528 WM8996_HPOUT1L_RMV_SHORT |
2529 WM8996_HPOUT1R_RMV_SHORT,
2530 WM8996_HPOUT1L_RMV_SHORT |
2531 WM8996_HPOUT1R_RMV_SHORT);
2532
2533 /* We need bandgap for HPDET */
2534 snd_soc_dapm_force_enable_pin(&codec->dapm, "Bandgap");
2535 snd_soc_dapm_sync(&codec->dapm);
2536
2537 /* Go into headphone detect left mode */
2538 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
2539 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_1,
2540 WM8996_JD_MODE_MASK, 1);
2541
2542 /* Trigger a measurement */
2543 snd_soc_update_bits(codec, WM8996_HEADPHONE_DETECT_1,
2544 WM8996_HP_POLL, WM8996_HP_POLL);
2545}
2546
a9ba6151
MB		 2547static void wm8996_micd(struct snd_soc_codec *codec)
2548{
2549 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2550 int val, reg;
2551
2552 val = snd_soc_read(codec, WM8996_MIC_DETECT_3);
2553
2554 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2555
2556 if (!(val & WM8996_MICD_VALID)) {
2557 dev_warn(codec->dev, "Microphone detection state invalid\n");
2558 return;
2559 }
2560
2561 /* No accessory, reset everything and report removal */
2562 if (!(val & WM8996_MICD_STS)) {
2563 dev_dbg(codec->dev, "Jack removal detected\n");
2564 wm8996->jack_mic = false;
2565 wm8996->detecting = true;
2566 snd_soc_jack_report(wm8996->jack, 0,
0b684cc1
MB		 2567 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2568 SND_JACK_BTN_0);
2569
a9ba6151
MB		 2570 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2571 WM8996_MICD_RATE_MASK,
2572 WM8996_MICD_RATE_MASK);
2573 return;
2574 }
2575
0b684cc1
MB		 2576 /* If the measurement is very high we've got a microphone,
2577 * either we just detected one or if we already reported then
2578 * we've got a button release event.
a9ba6151
MB		 2579 */
2580 if (val & 0x400) {
0b684cc1
MB		 2581 if (wm8996->detecting) {
2582 dev_dbg(codec->dev, "Microphone detected\n");
2583 wm8996->jack_mic = true;
2584 wm8996_hpdet_start(codec);
2585
2586 /* Increase poll rate to give better responsiveness
2587 * for buttons */
2588 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2589 WM8996_MICD_RATE_MASK,
2590 5 << WM8996_MICD_RATE_SHIFT);
2591 } else {
2592 dev_dbg(codec->dev, "Mic button up\n");
2593 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
2594 }
2595
2596 return;
a9ba6151
MB		 2597 }
2598
2599 /* If we detected a lower impedence during initial startup
2600 * then we probably have the wrong polarity, flip it. Don't
2601 * do this for the lowest impedences to speed up detection of
2602 * plain headphones.
2603 */
2604 if (wm8996->detecting && (val & 0x3f0)) {
2605 reg = snd_soc_read(codec, WM8996_ACCESSORY_DETECT_MODE_2);
2606 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2607 WM8996_MICD_BIAS_SRC;
2608 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2609 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2610 WM8996_MICD_BIAS_SRC, reg);
2611
2612 if (wm8996->polarity_cb)
2613 wm8996->polarity_cb(codec,
2614 (reg & WM8996_MICD_SRC) != 0);
2615
2616 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2617 (reg & WM8996_MICD_SRC) != 0);
2618
2619 return;
2620 }
2621
2622 /* Don't distinguish between buttons, just report any low
2623 * impedence as BTN_0.
2624 */
2625 if (val & 0x3fc) {
2626 if (wm8996->jack_mic) {
2627 dev_dbg(codec->dev, "Mic button detected\n");
0b684cc1 2628 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
a9ba6151 2629 SND_JACK_BTN_0);
0b684cc1
MB		 2630 } else if (wm8996->detecting) {
2631 dev_dbg(codec->dev, "Headphone detected\n");
2632 wm8996_hpdet_start(codec);
a9ba6151
MB		 2633
2634 /* Increase the detection rate a bit for
2635 * responsiveness.
2636 */
2637 snd_soc_update_bits(codec, WM8996_MIC_DETECT_1,
2638 WM8996_MICD_RATE_MASK,
2639 7 << WM8996_MICD_RATE_SHIFT);
a9ba6151
MB		 2640 }
2641 }
2642}
2643
2644static irqreturn_t wm8996_irq(int irq, void *data)
2645{
2646 struct snd_soc_codec *codec = data;
2647 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2648 int irq_val;
2649
2650 irq_val = snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2);
2651 if (irq_val < 0) {
2652 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2653 irq_val);
2654 return IRQ_NONE;
2655 }
2656 irq_val &= ~snd_soc_read(codec, WM8996_INTERRUPT_STATUS_2_MASK);
2657
2fde6e80
MB		 2658 if (!irq_val)
2659 return IRQ_NONE;
2660
84497091
MB		 2661 snd_soc_write(codec, WM8996_INTERRUPT_STATUS_2, irq_val);
2662
a9ba6151
MB		 2663 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2664 dev_dbg(codec->dev, "DC servo IRQ\n");
2665 complete(&wm8996->dcs_done);
2666 }
2667
2668 if (irq_val & WM8996_FIFOS_ERR_EINT)
2669 dev_err(codec->dev, "Digital core FIFO error\n");
2670
2671 if (irq_val & WM8996_FLL_LOCK_EINT) {
2672 dev_dbg(codec->dev, "FLL locked\n");
2673 complete(&wm8996->fll_lock);
2674 }
2675
2676 if (irq_val & WM8996_MICD_EINT)
2677 wm8996_micd(codec);
2678
0b684cc1
MB		 2679 if (irq_val & WM8996_HP_DONE_EINT)
2680 wm8996_hpdet_irq(codec);
2681
2fde6e80 2682 return IRQ_HANDLED;
a9ba6151
MB		 2683}
2684
2685static irqreturn_t wm8996_edge_irq(int irq, void *data)
2686{
2687 irqreturn_t ret = IRQ_NONE;
2688 irqreturn_t val;
2689
2690 do {
2691 val = wm8996_irq(irq, data);
2692 if (val != IRQ_NONE)
2693 ret = val;
2694 } while (val != IRQ_NONE);
2695
2696 return ret;
2697}
2698
2699static void wm8996_retune_mobile_pdata(struct snd_soc_codec *codec)
2700{
2701 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2702 struct wm8996_pdata *pdata = &wm8996->pdata;
2703
2704 struct snd_kcontrol_new controls[] = {
2705 SOC_ENUM_EXT("DSP1 EQ Mode",
2706 wm8996->retune_mobile_enum,
2707 wm8996_get_retune_mobile_enum,
2708 wm8996_put_retune_mobile_enum),
2709 SOC_ENUM_EXT("DSP2 EQ Mode",
2710 wm8996->retune_mobile_enum,
2711 wm8996_get_retune_mobile_enum,
2712 wm8996_put_retune_mobile_enum),
2713 };
2714 int ret, i, j;
2715 const char **t;
2716
2717 /* We need an array of texts for the enum API but the number
2718 * of texts is likely to be less than the number of
2719 * configurations due to the sample rate dependency of the
2720 * configurations. */
2721 wm8996->num_retune_mobile_texts = 0;
2722 wm8996->retune_mobile_texts = NULL;
2723 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2724 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2725 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2726 wm8996->retune_mobile_texts[j]) == 0)
2727 break;
2728 }
2729
2730 if (j != wm8996->num_retune_mobile_texts)
2731 continue;
2732
2733 /* Expand the array... */
2734 t = krealloc(wm8996->retune_mobile_texts,
2735 sizeof(char *) *
2736 (wm8996->num_retune_mobile_texts + 1),
2737 GFP_KERNEL);
2738 if (t == NULL)
2739 continue;
2740
2741 /* ...store the new entry... */
2742 t[wm8996->num_retune_mobile_texts] =
2743 pdata->retune_mobile_cfgs[i].name;
2744
2745 /* ...and remember the new version. */
2746 wm8996->num_retune_mobile_texts++;
2747 wm8996->retune_mobile_texts = t;
2748 }
2749
2750 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2751 wm8996->num_retune_mobile_texts);
2752
2753 wm8996->retune_mobile_enum.max = wm8996->num_retune_mobile_texts;
2754 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2755
2756 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2757 if (ret != 0)
2758 dev_err(codec->dev,
2759 "Failed to add ReTune Mobile controls: %d\n", ret);
2760}
2761
79172746
MB		 2762static const struct regmap_config wm8996_regmap = {
2763 .reg_bits = 16,
2764 .val_bits = 16,
2765
2766 .max_register = WM8996_MAX_REGISTER,
2767 .reg_defaults = wm8996_reg,
2768 .num_reg_defaults = ARRAY_SIZE(wm8996_reg),
2769 .volatile_reg = wm8996_volatile_register,
2770 .readable_reg = wm8996_readable_register,
2771 .cache_type = REGCACHE_RBTREE,
2772};
2773
a9ba6151
MB		 2774static int wm8996_probe(struct snd_soc_codec *codec)
2775{
2776 int ret;
2777 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
2778 struct i2c_client *i2c = to_i2c_client(codec->dev);
2779 struct snd_soc_dapm_context *dapm = &codec->dapm;
2780 int i, irq_flags;
2781
2782 wm8996->codec = codec;
2783
2784 init_completion(&wm8996->dcs_done);
2785 init_completion(&wm8996->fll_lock);
2786
2787 dapm->idle_bias_off = true;
a9ba6151 2788
79172746
MB		 2789 codec->control_data = regmap_init_i2c(i2c, &wm8996_regmap);
2790 if (IS_ERR(codec->control_data)) {
2791 ret = PTR_ERR(codec->control_data);
2792 dev_err(codec->dev, "regmap_init() failed: %d\n", ret);
2793 goto err;
2794 }
2795
2796 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
a9ba6151
MB		 2797 if (ret != 0) {
2798 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
79172746 2799 goto err_regmap;
a9ba6151
MB		 2800 }
2801
2802 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2803 wm8996->supplies[i].supply = wm8996_supply_names[i];
2804
2805 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8996->supplies),
2806 wm8996->supplies);
2807 if (ret != 0) {
2808 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
79172746 2809 goto err_regmap;
a9ba6151
MB		 2810 }
2811
2812 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2813 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2814 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
c83495af
MB		 2815
2816 wm8996->cpvdd = regulator_get(&i2c->dev, "CPVDD");
2817 if (IS_ERR(wm8996->cpvdd)) {
2818 ret = PTR_ERR(wm8996->cpvdd);
2819 dev_err(&i2c->dev, "Failed to get CPVDD: %d\n", ret);
2820 goto err_get;
2821 }
a9ba6151
MB		 2822
2823 /* This should really be moved into the regulator core */
2824 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2825 ret = regulator_register_notifier(wm8996->supplies[i].consumer,
2826 &wm8996->disable_nb[i]);
2827 if (ret != 0) {
2828 dev_err(codec->dev,
2829 "Failed to register regulator notifier: %d\n",
2830 ret);
2831 }
2832 }
2833
2834 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
2835 wm8996->supplies);
2836 if (ret != 0) {
2837 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
c83495af 2838 goto err_cpvdd;
a9ba6151
MB		 2839 }
2840
2841 if (wm8996->pdata.ldo_ena >= 0) {
2842 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
2843 msleep(5);
2844 }
2845
2846 ret = snd_soc_read(codec, WM8996_SOFTWARE_RESET);
2847 if (ret < 0) {
2848 dev_err(codec->dev, "Failed to read ID register: %d\n", ret);
2849 goto err_enable;
2850 }
2851 if (ret != 0x8915) {
2852 dev_err(codec->dev, "Device is not a WM8996, ID %x\n", ret);
2853 ret = -EINVAL;
2854 goto err_enable;
2855 }
2856
2857 ret = snd_soc_read(codec, WM8996_CHIP_REVISION);
2858 if (ret < 0) {
2859 dev_err(codec->dev, "Failed to read device revision: %d\n",
2860 ret);
2861 goto err_enable;
2862 }
2863
2864 dev_info(codec->dev, "revision %c\n",
2865 (ret & WM8996_CHIP_REV_MASK) + 'A');
2866
2867 if (wm8996->pdata.ldo_ena >= 0) {
2868 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2869 } else {
2870 ret = wm8996_reset(codec);
2871 if (ret < 0) {
2872 dev_err(codec->dev, "Failed to issue reset\n");
2873 goto err_enable;
2874 }
2875 }
2876
79172746 2877 regcache_cache_only(codec->control_data, true);
a9ba6151
MB		 2878
2879 /* Apply platform data settings */
2880 snd_soc_update_bits(codec, WM8996_LINE_INPUT_CONTROL,
2881 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2882 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2883 wm8996->pdata.inr_mode);
2884
2885 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2886 if (!wm8996->pdata.gpio_default[i])
2887 continue;
2888
2889 snd_soc_write(codec, WM8996_GPIO_1 + i,
2890 wm8996->pdata.gpio_default[i] & 0xffff);
2891 }
2892
2893 if (wm8996->pdata.spkmute_seq)
2894 snd_soc_update_bits(codec, WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2895 WM8996_SPK_MUTE_ENDIAN |
2896 WM8996_SPK_MUTE_SEQ1_MASK,
2897 wm8996->pdata.spkmute_seq);
2898
2899 snd_soc_update_bits(codec, WM8996_ACCESSORY_DETECT_MODE_2,
2900 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2901 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2902
2903 /* Latch volume update bits */
2904 snd_soc_update_bits(codec, WM8996_LEFT_LINE_INPUT_VOLUME,
2905 WM8996_IN1_VU, WM8996_IN1_VU);
2906 snd_soc_update_bits(codec, WM8996_RIGHT_LINE_INPUT_VOLUME,
2907 WM8996_IN1_VU, WM8996_IN1_VU);
2908
2909 snd_soc_update_bits(codec, WM8996_DAC1_LEFT_VOLUME,
2910 WM8996_DAC1_VU, WM8996_DAC1_VU);
2911 snd_soc_update_bits(codec, WM8996_DAC1_RIGHT_VOLUME,
2912 WM8996_DAC1_VU, WM8996_DAC1_VU);
2913 snd_soc_update_bits(codec, WM8996_DAC2_LEFT_VOLUME,
2914 WM8996_DAC2_VU, WM8996_DAC2_VU);
2915 snd_soc_update_bits(codec, WM8996_DAC2_RIGHT_VOLUME,
2916 WM8996_DAC2_VU, WM8996_DAC2_VU);
2917
2918 snd_soc_update_bits(codec, WM8996_OUTPUT1_LEFT_VOLUME,
2919 WM8996_DAC1_VU, WM8996_DAC1_VU);
2920 snd_soc_update_bits(codec, WM8996_OUTPUT1_RIGHT_VOLUME,
2921 WM8996_DAC1_VU, WM8996_DAC1_VU);
2922 snd_soc_update_bits(codec, WM8996_OUTPUT2_LEFT_VOLUME,
2923 WM8996_DAC2_VU, WM8996_DAC2_VU);
2924 snd_soc_update_bits(codec, WM8996_OUTPUT2_RIGHT_VOLUME,
2925 WM8996_DAC2_VU, WM8996_DAC2_VU);
2926
2927 snd_soc_update_bits(codec, WM8996_DSP1_TX_LEFT_VOLUME,
2928 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2929 snd_soc_update_bits(codec, WM8996_DSP1_TX_RIGHT_VOLUME,
2930 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2931 snd_soc_update_bits(codec, WM8996_DSP2_TX_LEFT_VOLUME,
2932 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2933 snd_soc_update_bits(codec, WM8996_DSP2_TX_RIGHT_VOLUME,
2934 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2935
2936 snd_soc_update_bits(codec, WM8996_DSP1_RX_LEFT_VOLUME,
2937 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2938 snd_soc_update_bits(codec, WM8996_DSP1_RX_RIGHT_VOLUME,
2939 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2940 snd_soc_update_bits(codec, WM8996_DSP2_RX_LEFT_VOLUME,
2941 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2942 snd_soc_update_bits(codec, WM8996_DSP2_RX_RIGHT_VOLUME,
2943 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2944
2945 /* No support currently for the underclocked TDM modes and
2946 * pick a default TDM layout with each channel pair working with
2947 * slots 0 and 1. */
2948 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2949 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2950 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2951 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2952 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2953 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2954 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2955 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2956 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2957 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2958 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2959 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2960 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2961 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2962 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2963 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2964 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2965 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2966 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2967 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2968 snd_soc_update_bits(codec, WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2969 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2970 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2971 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2972
2973 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2974 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2975 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2976 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2977 snd_soc_update_bits(codec, WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2978 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2979 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2980 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2981
2982 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2983 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2984 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2985 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2986 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2987 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2988 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2989 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2990 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2991 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2992 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2993 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2994 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2995 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2996 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2997 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2998 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
2999 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
3000 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3001 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
3002 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
3003 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
3004 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3005 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
3006
3007 snd_soc_update_bits(codec, WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
3008 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
3009 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
3010 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
3011 snd_soc_update_bits(codec, WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
3012 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
3013 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
3014 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
3015
3016 if (wm8996->pdata.num_retune_mobile_cfgs)
3017 wm8996_retune_mobile_pdata(codec);
3018 else
3019 snd_soc_add_controls(codec, wm8996_eq_controls,
3020 ARRAY_SIZE(wm8996_eq_controls));
3021
3022 /* If the TX LRCLK pins are not in LRCLK mode configure the
3023 * AIFs to source their clocks from the RX LRCLKs.
3024 */
3025 if ((snd_soc_read(codec, WM8996_GPIO_1)))
3026 snd_soc_update_bits(codec, WM8996_AIF1_TX_LRCLK_2,
3027 WM8996_AIF1TX_LRCLK_MODE,
3028 WM8996_AIF1TX_LRCLK_MODE);
3029
3030 if ((snd_soc_read(codec, WM8996_GPIO_2)))
3031 snd_soc_update_bits(codec, WM8996_AIF2_TX_LRCLK_2,
3032 WM8996_AIF2TX_LRCLK_MODE,
3033 WM8996_AIF2TX_LRCLK_MODE);
3034
3035 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3036
3037 wm8996_init_gpio(codec);
3038
3039 if (i2c->irq) {
3040 if (wm8996->pdata.irq_flags)
3041 irq_flags = wm8996->pdata.irq_flags;
3042 else
3043 irq_flags = IRQF_TRIGGER_LOW;
3044
3045 irq_flags |= IRQF_ONESHOT;
3046
3047 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
3048 ret = request_threaded_irq(i2c->irq, NULL,
3049 wm8996_edge_irq,
3050 irq_flags, "wm8996", codec);
3051 else
3052 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
3053 irq_flags, "wm8996", codec);
3054
3055 if (ret == 0) {
3056 /* Unmask the interrupt */
3057 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
3058 WM8996_IM_IRQ, 0);
3059
3060 /* Enable error reporting and DC servo status */
3061 snd_soc_update_bits(codec,
3062 WM8996_INTERRUPT_STATUS_2_MASK,
3063 WM8996_IM_DCS_DONE_23_EINT |
3064 WM8996_IM_DCS_DONE_01_EINT |
3065 WM8996_IM_FLL_LOCK_EINT |
3066 WM8996_IM_FIFOS_ERR_EINT,
3067 0);
3068 } else {
3069 dev_err(codec->dev, "Failed to request IRQ: %d\n",
3070 ret);
3071 }
3072 }
3073
3074 return 0;
3075
3076err_enable:
3077 if (wm8996->pdata.ldo_ena >= 0)
3078 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3079
3080 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
c83495af
MB		 3081err_cpvdd:
3082 regulator_put(wm8996->cpvdd);
a9ba6151
MB		 3083err_get:
3084 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
79172746
MB		 3085err_regmap:
3086 regmap_exit(codec->control_data);
a9ba6151
MB		 3087err:
3088 return ret;
3089}
3090
3091static int wm8996_remove(struct snd_soc_codec *codec)
3092{
3093 struct wm8996_priv *wm8996 = snd_soc_codec_get_drvdata(codec);
3094 struct i2c_client *i2c = to_i2c_client(codec->dev);
3095 int i;
3096
3097 snd_soc_update_bits(codec, WM8996_INTERRUPT_CONTROL,
3098 WM8996_IM_IRQ, WM8996_IM_IRQ);
3099
3100 if (i2c->irq)
3101 free_irq(i2c->irq, codec);
3102
3103 wm8996_free_gpio(codec);
3104
3105 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
3106 regulator_unregister_notifier(wm8996->supplies[i].consumer,
3107 &wm8996->disable_nb[i]);
c83495af 3108 regulator_put(wm8996->cpvdd);
a9ba6151 3109 regulator_bulk_free(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
79172746 3110 regmap_exit(codec->control_data);
a9ba6151
MB		 3111
3112 return 0;
3113}
3114
3115static struct snd_soc_codec_driver soc_codec_dev_wm8996 = {
3116 .probe = wm8996_probe,
3117 .remove = wm8996_remove,
3118 .set_bias_level = wm8996_set_bias_level,
3119 .seq_notifier = wm8996_seq_notifier,
a9ba6151
MB		 3120 .controls = wm8996_snd_controls,
3121 .num_controls = ARRAY_SIZE(wm8996_snd_controls),
3122 .dapm_widgets = wm8996_dapm_widgets,
3123 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
3124 .dapm_routes = wm8996_dapm_routes,
3125 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
3126 .set_pll = wm8996_set_fll,
3127};
3128
3129#define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
3130 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
3131#define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
3132 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
3133 SNDRV_PCM_FMTBIT_S32_LE)
3134
3135static struct snd_soc_dai_ops wm8996_dai_ops = {
3136 .set_fmt = wm8996_set_fmt,
3137 .hw_params = wm8996_hw_params,
3138 .set_sysclk = wm8996_set_sysclk,
3139};
3140
3141static struct snd_soc_dai_driver wm8996_dai[] = {
3142 {
3143 .name = "wm8996-aif1",
3144 .playback = {
3145 .stream_name = "AIF1 Playback",
3146 .channels_min = 1,
3147 .channels_max = 6,
3148 .rates = WM8996_RATES,
3149 .formats = WM8996_FORMATS,
3150 },
3151 .capture = {
3152 .stream_name = "AIF1 Capture",
3153 .channels_min = 1,
3154 .channels_max = 6,
3155 .rates = WM8996_RATES,
3156 .formats = WM8996_FORMATS,
3157 },
3158 .ops = &wm8996_dai_ops,
3159 },
3160 {
3161 .name = "wm8996-aif2",
3162 .playback = {
3163 .stream_name = "AIF2 Playback",
3164 .channels_min = 1,
3165 .channels_max = 2,
3166 .rates = WM8996_RATES,
3167 .formats = WM8996_FORMATS,
3168 },
3169 .capture = {
3170 .stream_name = "AIF2 Capture",
3171 .channels_min = 1,
3172 .channels_max = 2,
3173 .rates = WM8996_RATES,
3174 .formats = WM8996_FORMATS,
3175 },
3176 .ops = &wm8996_dai_ops,
3177 },
3178};
3179
3180static __devinit int wm8996_i2c_probe(struct i2c_client *i2c,
3181 const struct i2c_device_id *id)
3182{
3183 struct wm8996_priv *wm8996;
3184 int ret;
3185
3186 wm8996 = kzalloc(sizeof(struct wm8996_priv), GFP_KERNEL);
3187 if (wm8996 == NULL)
3188 return -ENOMEM;
3189
3190 i2c_set_clientdata(i2c, wm8996);
3191
3192 if (dev_get_platdata(&i2c->dev))
3193 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
3194 sizeof(wm8996->pdata));
3195
3196 if (wm8996->pdata.ldo_ena > 0) {
3197 ret = gpio_request_one(wm8996->pdata.ldo_ena,
3198 GPIOF_OUT_INIT_LOW, "WM8996 ENA");
3199 if (ret < 0) {
3200 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
3201 wm8996->pdata.ldo_ena, ret);
3202 goto err;
3203 }
3204 }
3205
3206 ret = snd_soc_register_codec(&i2c->dev,
3207 &soc_codec_dev_wm8996, wm8996_dai,
3208 ARRAY_SIZE(wm8996_dai));
3209 if (ret < 0)
3210 goto err_gpio;
3211
3212 return ret;
3213
3214err_gpio:
3215 if (wm8996->pdata.ldo_ena > 0)
3216 gpio_free(wm8996->pdata.ldo_ena);
3217err:
3218 kfree(wm8996);
3219
3220 return ret;
3221}
3222
3223static __devexit int wm8996_i2c_remove(struct i2c_client *client)
3224{
3225 struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
3226
3227 snd_soc_unregister_codec(&client->dev);
3228 if (wm8996->pdata.ldo_ena > 0)
3229 gpio_free(wm8996->pdata.ldo_ena);
753ddf52 3230 kfree(wm8996);
a9ba6151
MB		 3231 return 0;
3232}
3233
3234static const struct i2c_device_id wm8996_i2c_id[] = {
3235 { "wm8996", 0 },
3236 { }
3237};
3238MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3239
3240static struct i2c_driver wm8996_i2c_driver = {
3241 .driver = {
3242 .name = "wm8996",
3243 .owner = THIS_MODULE,
3244 },
3245 .probe = wm8996_i2c_probe,
3246 .remove = __devexit_p(wm8996_i2c_remove),
3247 .id_table = wm8996_i2c_id,
3248};
3249
3250static int __init wm8996_modinit(void)
3251{
3252 int ret;
3253
3254 ret = i2c_add_driver(&wm8996_i2c_driver);
3255 if (ret != 0) {
3256 printk(KERN_ERR "Failed to register WM8996 I2C driver: %d\n",
3257 ret);
3258 }
3259
3260 return ret;
3261}
3262module_init(wm8996_modinit);
3263
3264static void __exit wm8996_exit(void)
3265{
3266 i2c_del_driver(&wm8996_i2c_driver);
3267}
3268module_exit(wm8996_exit);
3269
3270MODULE_DESCRIPTION("ASoC WM8996 driver");
3271MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3272MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)