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6a504a75 DP |
1 | /* |
2 | * wm8995.c -- WM8995 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2010 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * Based on wm8994.c and wm_hubs.c by Mark Brown | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/moduleparam.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/pm.h> | |
20 | #include <linux/i2c.h> | |
c42da642 | 21 | #include <linux/regmap.h> |
6a504a75 | 22 | #include <linux/spi/spi.h> |
219d8df8 | 23 | #include <linux/regulator/consumer.h> |
6a504a75 DP |
24 | #include <linux/slab.h> |
25 | #include <sound/core.h> | |
26 | #include <sound/pcm.h> | |
27 | #include <sound/pcm_params.h> | |
28 | #include <sound/soc.h> | |
29 | #include <sound/soc-dapm.h> | |
30 | #include <sound/initval.h> | |
31 | #include <sound/tlv.h> | |
32 | ||
33 | #include "wm8995.h" | |
34 | ||
219d8df8 DP |
35 | #define WM8995_NUM_SUPPLIES 8 |
36 | static const char *wm8995_supply_names[WM8995_NUM_SUPPLIES] = { | |
37 | "DCVDD", | |
38 | "DBVDD1", | |
39 | "DBVDD2", | |
40 | "DBVDD3", | |
41 | "AVDD1", | |
42 | "AVDD2", | |
43 | "CPVDD", | |
44 | "MICVDD" | |
45 | }; | |
46 | ||
27ad02f3 | 47 | static const struct reg_default wm8995_reg_defaults[] = { |
c42da642 MB |
48 | { 0, 0x8995 }, |
49 | { 5, 0x0100 }, | |
50 | { 16, 0x000b }, | |
51 | { 17, 0x000b }, | |
52 | { 24, 0x02c0 }, | |
53 | { 25, 0x02c0 }, | |
54 | { 26, 0x02c0 }, | |
55 | { 27, 0x02c0 }, | |
56 | { 28, 0x000f }, | |
57 | { 32, 0x0005 }, | |
58 | { 33, 0x0005 }, | |
59 | { 40, 0x0003 }, | |
60 | { 41, 0x0013 }, | |
61 | { 48, 0x0004 }, | |
62 | { 56, 0x09f8 }, | |
63 | { 64, 0x1f25 }, | |
64 | { 69, 0x0004 }, | |
65 | { 82, 0xaaaa }, | |
66 | { 84, 0x2a2a }, | |
67 | { 146, 0x0060 }, | |
68 | { 256, 0x0002 }, | |
69 | { 257, 0x8004 }, | |
70 | { 520, 0x0010 }, | |
71 | { 528, 0x0083 }, | |
72 | { 529, 0x0083 }, | |
73 | { 548, 0x0c80 }, | |
74 | { 580, 0x0c80 }, | |
75 | { 768, 0x4050 }, | |
76 | { 769, 0x4000 }, | |
77 | { 771, 0x0040 }, | |
78 | { 772, 0x0040 }, | |
79 | { 773, 0x0040 }, | |
80 | { 774, 0x0004 }, | |
81 | { 775, 0x0100 }, | |
82 | { 784, 0x4050 }, | |
83 | { 785, 0x4000 }, | |
84 | { 787, 0x0040 }, | |
85 | { 788, 0x0040 }, | |
86 | { 789, 0x0040 }, | |
87 | { 1024, 0x00c0 }, | |
88 | { 1025, 0x00c0 }, | |
89 | { 1026, 0x00c0 }, | |
90 | { 1027, 0x00c0 }, | |
91 | { 1028, 0x00c0 }, | |
92 | { 1029, 0x00c0 }, | |
93 | { 1030, 0x00c0 }, | |
94 | { 1031, 0x00c0 }, | |
95 | { 1056, 0x0200 }, | |
96 | { 1057, 0x0010 }, | |
97 | { 1058, 0x0200 }, | |
98 | { 1059, 0x0010 }, | |
99 | { 1088, 0x0098 }, | |
100 | { 1089, 0x0845 }, | |
101 | { 1104, 0x0098 }, | |
102 | { 1105, 0x0845 }, | |
103 | { 1152, 0x6318 }, | |
104 | { 1153, 0x6300 }, | |
105 | { 1154, 0x0fca }, | |
106 | { 1155, 0x0400 }, | |
107 | { 1156, 0x00d8 }, | |
108 | { 1157, 0x1eb5 }, | |
109 | { 1158, 0xf145 }, | |
110 | { 1159, 0x0b75 }, | |
111 | { 1160, 0x01c5 }, | |
112 | { 1161, 0x1c58 }, | |
113 | { 1162, 0xf373 }, | |
114 | { 1163, 0x0a54 }, | |
115 | { 1164, 0x0558 }, | |
116 | { 1165, 0x168e }, | |
117 | { 1166, 0xf829 }, | |
118 | { 1167, 0x07ad }, | |
119 | { 1168, 0x1103 }, | |
120 | { 1169, 0x0564 }, | |
121 | { 1170, 0x0559 }, | |
122 | { 1171, 0x4000 }, | |
123 | { 1184, 0x6318 }, | |
124 | { 1185, 0x6300 }, | |
125 | { 1186, 0x0fca }, | |
126 | { 1187, 0x0400 }, | |
127 | { 1188, 0x00d8 }, | |
128 | { 1189, 0x1eb5 }, | |
129 | { 1190, 0xf145 }, | |
130 | { 1191, 0x0b75 }, | |
131 | { 1192, 0x01c5 }, | |
132 | { 1193, 0x1c58 }, | |
133 | { 1194, 0xf373 }, | |
134 | { 1195, 0x0a54 }, | |
135 | { 1196, 0x0558 }, | |
136 | { 1197, 0x168e }, | |
137 | { 1198, 0xf829 }, | |
138 | { 1199, 0x07ad }, | |
139 | { 1200, 0x1103 }, | |
140 | { 1201, 0x0564 }, | |
141 | { 1202, 0x0559 }, | |
142 | { 1203, 0x4000 }, | |
143 | { 1280, 0x00c0 }, | |
144 | { 1281, 0x00c0 }, | |
145 | { 1282, 0x00c0 }, | |
146 | { 1283, 0x00c0 }, | |
147 | { 1312, 0x0200 }, | |
148 | { 1313, 0x0010 }, | |
149 | { 1344, 0x0098 }, | |
150 | { 1345, 0x0845 }, | |
151 | { 1408, 0x6318 }, | |
152 | { 1409, 0x6300 }, | |
153 | { 1410, 0x0fca }, | |
154 | { 1411, 0x0400 }, | |
155 | { 1412, 0x00d8 }, | |
156 | { 1413, 0x1eb5 }, | |
157 | { 1414, 0xf145 }, | |
158 | { 1415, 0x0b75 }, | |
159 | { 1416, 0x01c5 }, | |
160 | { 1417, 0x1c58 }, | |
161 | { 1418, 0xf373 }, | |
162 | { 1419, 0x0a54 }, | |
163 | { 1420, 0x0558 }, | |
164 | { 1421, 0x168e }, | |
165 | { 1422, 0xf829 }, | |
166 | { 1423, 0x07ad }, | |
167 | { 1424, 0x1103 }, | |
168 | { 1425, 0x0564 }, | |
169 | { 1426, 0x0559 }, | |
170 | { 1427, 0x4000 }, | |
171 | { 1568, 0x0002 }, | |
172 | { 1792, 0xa100 }, | |
173 | { 1793, 0xa101 }, | |
174 | { 1794, 0xa101 }, | |
175 | { 1795, 0xa101 }, | |
176 | { 1796, 0xa101 }, | |
177 | { 1797, 0xa101 }, | |
178 | { 1798, 0xa101 }, | |
179 | { 1799, 0xa101 }, | |
180 | { 1800, 0xa101 }, | |
181 | { 1801, 0xa101 }, | |
182 | { 1802, 0xa101 }, | |
183 | { 1803, 0xa101 }, | |
184 | { 1804, 0xa101 }, | |
185 | { 1805, 0xa101 }, | |
186 | { 1825, 0x0055 }, | |
187 | { 1848, 0x3fff }, | |
188 | { 1849, 0x1fff }, | |
189 | { 2049, 0x0001 }, | |
190 | { 2050, 0x0069 }, | |
191 | { 2056, 0x0002 }, | |
192 | { 2057, 0x0003 }, | |
193 | { 2058, 0x0069 }, | |
194 | { 12288, 0x0001 }, | |
195 | { 12289, 0x0001 }, | |
196 | { 12291, 0x0006 }, | |
197 | { 12292, 0x0040 }, | |
198 | { 12293, 0x0001 }, | |
199 | { 12294, 0x000f }, | |
200 | { 12295, 0x0006 }, | |
201 | { 12296, 0x0001 }, | |
202 | { 12297, 0x0003 }, | |
203 | { 12298, 0x0104 }, | |
204 | { 12300, 0x0060 }, | |
205 | { 12301, 0x0011 }, | |
206 | { 12302, 0x0401 }, | |
207 | { 12304, 0x0050 }, | |
208 | { 12305, 0x0003 }, | |
209 | { 12306, 0x0100 }, | |
210 | { 12308, 0x0051 }, | |
211 | { 12309, 0x0003 }, | |
212 | { 12310, 0x0104 }, | |
213 | { 12311, 0x000a }, | |
214 | { 12312, 0x0060 }, | |
215 | { 12313, 0x003b }, | |
216 | { 12314, 0x0502 }, | |
217 | { 12315, 0x0100 }, | |
218 | { 12316, 0x2fff }, | |
219 | { 12320, 0x2fff }, | |
220 | { 12324, 0x2fff }, | |
221 | { 12328, 0x2fff }, | |
222 | { 12332, 0x2fff }, | |
223 | { 12336, 0x2fff }, | |
224 | { 12340, 0x2fff }, | |
225 | { 12344, 0x2fff }, | |
226 | { 12348, 0x2fff }, | |
227 | { 12352, 0x0001 }, | |
228 | { 12353, 0x0001 }, | |
229 | { 12355, 0x0006 }, | |
230 | { 12356, 0x0040 }, | |
231 | { 12357, 0x0001 }, | |
232 | { 12358, 0x000f }, | |
233 | { 12359, 0x0006 }, | |
234 | { 12360, 0x0001 }, | |
235 | { 12361, 0x0003 }, | |
236 | { 12362, 0x0104 }, | |
237 | { 12364, 0x0060 }, | |
238 | { 12365, 0x0011 }, | |
239 | { 12366, 0x0401 }, | |
240 | { 12368, 0x0050 }, | |
241 | { 12369, 0x0003 }, | |
242 | { 12370, 0x0100 }, | |
243 | { 12372, 0x0060 }, | |
244 | { 12373, 0x003b }, | |
245 | { 12374, 0x0502 }, | |
246 | { 12375, 0x0100 }, | |
247 | { 12376, 0x2fff }, | |
248 | { 12380, 0x2fff }, | |
249 | { 12384, 0x2fff }, | |
250 | { 12388, 0x2fff }, | |
251 | { 12392, 0x2fff }, | |
252 | { 12396, 0x2fff }, | |
253 | { 12400, 0x2fff }, | |
254 | { 12404, 0x2fff }, | |
255 | { 12408, 0x2fff }, | |
256 | { 12412, 0x2fff }, | |
257 | { 12416, 0x0001 }, | |
258 | { 12417, 0x0001 }, | |
259 | { 12419, 0x0006 }, | |
260 | { 12420, 0x0040 }, | |
261 | { 12421, 0x0001 }, | |
262 | { 12422, 0x000f }, | |
263 | { 12423, 0x0006 }, | |
264 | { 12424, 0x0001 }, | |
265 | { 12425, 0x0003 }, | |
266 | { 12426, 0x0106 }, | |
267 | { 12428, 0x0061 }, | |
268 | { 12429, 0x0011 }, | |
269 | { 12430, 0x0401 }, | |
270 | { 12432, 0x0050 }, | |
271 | { 12433, 0x0003 }, | |
272 | { 12434, 0x0102 }, | |
273 | { 12436, 0x0051 }, | |
274 | { 12437, 0x0003 }, | |
275 | { 12438, 0x0106 }, | |
276 | { 12439, 0x000a }, | |
277 | { 12440, 0x0061 }, | |
278 | { 12441, 0x003b }, | |
279 | { 12442, 0x0502 }, | |
280 | { 12443, 0x0100 }, | |
281 | { 12444, 0x2fff }, | |
282 | { 12448, 0x2fff }, | |
283 | { 12452, 0x2fff }, | |
284 | { 12456, 0x2fff }, | |
285 | { 12460, 0x2fff }, | |
286 | { 12464, 0x2fff }, | |
287 | { 12468, 0x2fff }, | |
288 | { 12472, 0x2fff }, | |
289 | { 12476, 0x2fff }, | |
290 | { 12480, 0x0001 }, | |
291 | { 12481, 0x0001 }, | |
292 | { 12483, 0x0006 }, | |
293 | { 12484, 0x0040 }, | |
294 | { 12485, 0x0001 }, | |
295 | { 12486, 0x000f }, | |
296 | { 12487, 0x0006 }, | |
297 | { 12488, 0x0001 }, | |
298 | { 12489, 0x0003 }, | |
299 | { 12490, 0x0106 }, | |
300 | { 12492, 0x0061 }, | |
301 | { 12493, 0x0011 }, | |
302 | { 12494, 0x0401 }, | |
303 | { 12496, 0x0050 }, | |
304 | { 12497, 0x0003 }, | |
305 | { 12498, 0x0102 }, | |
306 | { 12500, 0x0061 }, | |
307 | { 12501, 0x003b }, | |
308 | { 12502, 0x0502 }, | |
309 | { 12503, 0x0100 }, | |
310 | { 12504, 0x2fff }, | |
311 | { 12508, 0x2fff }, | |
312 | { 12512, 0x2fff }, | |
313 | { 12516, 0x2fff }, | |
314 | { 12520, 0x2fff }, | |
315 | { 12524, 0x2fff }, | |
316 | { 12528, 0x2fff }, | |
317 | { 12532, 0x2fff }, | |
318 | { 12536, 0x2fff }, | |
319 | { 12540, 0x2fff }, | |
320 | { 12544, 0x0060 }, | |
321 | { 12546, 0x0601 }, | |
322 | { 12548, 0x0050 }, | |
323 | { 12550, 0x0100 }, | |
324 | { 12552, 0x0001 }, | |
325 | { 12554, 0x0104 }, | |
326 | { 12555, 0x0100 }, | |
327 | { 12556, 0x2fff }, | |
328 | { 12560, 0x2fff }, | |
329 | { 12564, 0x2fff }, | |
330 | { 12568, 0x2fff }, | |
331 | { 12572, 0x2fff }, | |
332 | { 12576, 0x2fff }, | |
333 | { 12580, 0x2fff }, | |
334 | { 12584, 0x2fff }, | |
335 | { 12588, 0x2fff }, | |
336 | { 12592, 0x2fff }, | |
337 | { 12596, 0x2fff }, | |
338 | { 12600, 0x2fff }, | |
339 | { 12604, 0x2fff }, | |
340 | { 12608, 0x0061 }, | |
341 | { 12610, 0x0601 }, | |
342 | { 12612, 0x0050 }, | |
343 | { 12614, 0x0102 }, | |
344 | { 12616, 0x0001 }, | |
345 | { 12618, 0x0106 }, | |
346 | { 12619, 0x0100 }, | |
347 | { 12620, 0x2fff }, | |
348 | { 12624, 0x2fff }, | |
349 | { 12628, 0x2fff }, | |
350 | { 12632, 0x2fff }, | |
351 | { 12636, 0x2fff }, | |
352 | { 12640, 0x2fff }, | |
353 | { 12644, 0x2fff }, | |
354 | { 12648, 0x2fff }, | |
355 | { 12652, 0x2fff }, | |
356 | { 12656, 0x2fff }, | |
357 | { 12660, 0x2fff }, | |
358 | { 12664, 0x2fff }, | |
359 | { 12668, 0x2fff }, | |
360 | { 12672, 0x0060 }, | |
361 | { 12674, 0x0601 }, | |
362 | { 12676, 0x0061 }, | |
363 | { 12678, 0x0601 }, | |
364 | { 12680, 0x0050 }, | |
365 | { 12682, 0x0300 }, | |
366 | { 12684, 0x0001 }, | |
367 | { 12686, 0x0304 }, | |
368 | { 12688, 0x0040 }, | |
369 | { 12690, 0x000f }, | |
370 | { 12692, 0x0001 }, | |
371 | { 12695, 0x0100 }, | |
6a504a75 DP |
372 | }; |
373 | ||
374 | struct fll_config { | |
375 | int src; | |
376 | int in; | |
377 | int out; | |
378 | }; | |
379 | ||
380 | struct wm8995_priv { | |
c42da642 | 381 | struct regmap *regmap; |
6a504a75 DP |
382 | int sysclk[2]; |
383 | int mclk[2]; | |
384 | int aifclk[2]; | |
385 | struct fll_config fll[2], fll_suspend[2]; | |
219d8df8 DP |
386 | struct regulator_bulk_data supplies[WM8995_NUM_SUPPLIES]; |
387 | struct notifier_block disable_nb[WM8995_NUM_SUPPLIES]; | |
708ebb3b | 388 | struct snd_soc_component *component; |
6a504a75 DP |
389 | }; |
390 | ||
219d8df8 DP |
391 | /* |
392 | * We can't use the same notifier block for more than one supply and | |
393 | * there's no way I can see to get from a callback to the caller | |
394 | * except container_of(). | |
395 | */ | |
396 | #define WM8995_REGULATOR_EVENT(n) \ | |
397 | static int wm8995_regulator_event_##n(struct notifier_block *nb, \ | |
398 | unsigned long event, void *data) \ | |
399 | { \ | |
400 | struct wm8995_priv *wm8995 = container_of(nb, struct wm8995_priv, \ | |
401 | disable_nb[n]); \ | |
402 | if (event & REGULATOR_EVENT_DISABLE) { \ | |
c42da642 | 403 | regcache_mark_dirty(wm8995->regmap); \ |
219d8df8 DP |
404 | } \ |
405 | return 0; \ | |
406 | } | |
407 | ||
408 | WM8995_REGULATOR_EVENT(0) | |
409 | WM8995_REGULATOR_EVENT(1) | |
410 | WM8995_REGULATOR_EVENT(2) | |
411 | WM8995_REGULATOR_EVENT(3) | |
412 | WM8995_REGULATOR_EVENT(4) | |
413 | WM8995_REGULATOR_EVENT(5) | |
414 | WM8995_REGULATOR_EVENT(6) | |
415 | WM8995_REGULATOR_EVENT(7) | |
416 | ||
6a504a75 DP |
417 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); |
418 | static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0); | |
419 | static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0); | |
420 | static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); | |
421 | ||
422 | static const char *in1l_text[] = { | |
423 | "Differential", "Single-ended IN1LN", "Single-ended IN1LP" | |
424 | }; | |
425 | ||
48e50ce3 TI |
426 | static SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL, |
427 | 2, in1l_text); | |
6a504a75 DP |
428 | |
429 | static const char *in1r_text[] = { | |
430 | "Differential", "Single-ended IN1RN", "Single-ended IN1RP" | |
431 | }; | |
432 | ||
48e50ce3 TI |
433 | static SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL, |
434 | 0, in1r_text); | |
6a504a75 DP |
435 | |
436 | static const char *dmic_src_text[] = { | |
437 | "DMICDAT1", "DMICDAT2", "DMICDAT3" | |
438 | }; | |
439 | ||
48e50ce3 TI |
440 | static SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5, |
441 | 8, dmic_src_text); | |
442 | static SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5, | |
443 | 6, dmic_src_text); | |
6a504a75 DP |
444 | |
445 | static const struct snd_kcontrol_new wm8995_snd_controls[] = { | |
446 | SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME, | |
447 | WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
448 | SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME, | |
449 | WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1), | |
450 | ||
451 | SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME, | |
452 | WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
453 | SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME, | |
454 | WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1), | |
455 | ||
456 | SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME, | |
457 | WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
458 | SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME, | |
459 | WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
460 | SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME, | |
461 | WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
462 | ||
463 | SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME, | |
464 | WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv), | |
465 | ||
466 | SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL, | |
467 | 4, 3, 0, in1l_boost_tlv), | |
468 | ||
469 | SOC_ENUM("IN1L Mode", in1l_enum), | |
470 | SOC_ENUM("IN1R Mode", in1r_enum), | |
471 | ||
472 | SOC_ENUM("DMIC1 SRC", dmic_src1_enum), | |
473 | SOC_ENUM("DMIC2 SRC", dmic_src2_enum), | |
474 | ||
475 | SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5, | |
476 | 24, 0, sidetone_tlv), | |
477 | SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5, | |
478 | 24, 0, sidetone_tlv), | |
479 | ||
480 | SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME, | |
481 | WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
482 | SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME, | |
483 | WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
484 | SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME, | |
485 | WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv) | |
486 | }; | |
487 | ||
708ebb3b | 488 | static void wm8995_update_class_w(struct snd_soc_component *component) |
6a504a75 DP |
489 | { |
490 | int enable = 1; | |
491 | int source = 0; /* GCC flow analysis can't track enable */ | |
492 | int reg, reg_r; | |
493 | ||
494 | /* We also need the same setting for L/R and only one path */ | |
708ebb3b | 495 | reg = snd_soc_component_read32(component, WM8995_DAC1_LEFT_MIXER_ROUTING); |
6a504a75 DP |
496 | switch (reg) { |
497 | case WM8995_AIF2DACL_TO_DAC1L: | |
708ebb3b | 498 | dev_dbg(component->dev, "Class W source AIF2DAC\n"); |
6a504a75 DP |
499 | source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT; |
500 | break; | |
501 | case WM8995_AIF1DAC2L_TO_DAC1L: | |
708ebb3b | 502 | dev_dbg(component->dev, "Class W source AIF1DAC2\n"); |
6a504a75 DP |
503 | source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT; |
504 | break; | |
505 | case WM8995_AIF1DAC1L_TO_DAC1L: | |
708ebb3b | 506 | dev_dbg(component->dev, "Class W source AIF1DAC1\n"); |
6a504a75 DP |
507 | source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT; |
508 | break; | |
509 | default: | |
708ebb3b | 510 | dev_dbg(component->dev, "DAC mixer setting: %x\n", reg); |
6a504a75 DP |
511 | enable = 0; |
512 | break; | |
513 | } | |
514 | ||
708ebb3b | 515 | reg_r = snd_soc_component_read32(component, WM8995_DAC1_RIGHT_MIXER_ROUTING); |
6a504a75 | 516 | if (reg_r != reg) { |
708ebb3b | 517 | dev_dbg(component->dev, "Left and right DAC mixers different\n"); |
6a504a75 DP |
518 | enable = 0; |
519 | } | |
520 | ||
521 | if (enable) { | |
708ebb3b KM |
522 | dev_dbg(component->dev, "Class W enabled\n"); |
523 | snd_soc_component_update_bits(component, WM8995_CLASS_W_1, | |
6a504a75 DP |
524 | WM8995_CP_DYN_PWR_MASK | |
525 | WM8995_CP_DYN_SRC_SEL_MASK, | |
526 | source | WM8995_CP_DYN_PWR); | |
527 | } else { | |
708ebb3b KM |
528 | dev_dbg(component->dev, "Class W disabled\n"); |
529 | snd_soc_component_update_bits(component, WM8995_CLASS_W_1, | |
6a504a75 DP |
530 | WM8995_CP_DYN_PWR_MASK, 0); |
531 | } | |
532 | } | |
533 | ||
534 | static int check_clk_sys(struct snd_soc_dapm_widget *source, | |
535 | struct snd_soc_dapm_widget *sink) | |
536 | { | |
708ebb3b | 537 | struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm); |
6a504a75 DP |
538 | unsigned int reg; |
539 | const char *clk; | |
540 | ||
708ebb3b | 541 | reg = snd_soc_component_read32(component, WM8995_CLOCKING_1); |
6a504a75 DP |
542 | /* Check what we're currently using for CLK_SYS */ |
543 | if (reg & WM8995_SYSCLK_SRC) | |
544 | clk = "AIF2CLK"; | |
545 | else | |
546 | clk = "AIF1CLK"; | |
547 | return !strcmp(source->name, clk); | |
548 | } | |
549 | ||
550 | static int wm8995_put_class_w(struct snd_kcontrol *kcontrol, | |
551 | struct snd_ctl_elem_value *ucontrol) | |
552 | { | |
708ebb3b | 553 | struct snd_soc_component *component = snd_soc_dapm_kcontrol_component(kcontrol); |
6a504a75 DP |
554 | int ret; |
555 | ||
6a504a75 | 556 | ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); |
708ebb3b | 557 | wm8995_update_class_w(component); |
6a504a75 DP |
558 | return ret; |
559 | } | |
560 | ||
561 | static int hp_supply_event(struct snd_soc_dapm_widget *w, | |
562 | struct snd_kcontrol *kcontrol, int event) | |
563 | { | |
708ebb3b | 564 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
6a504a75 DP |
565 | |
566 | switch (event) { | |
567 | case SND_SOC_DAPM_PRE_PMU: | |
568 | /* Enable the headphone amp */ | |
708ebb3b | 569 | snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1, |
6a504a75 DP |
570 | WM8995_HPOUT1L_ENA_MASK | |
571 | WM8995_HPOUT1R_ENA_MASK, | |
572 | WM8995_HPOUT1L_ENA | | |
573 | WM8995_HPOUT1R_ENA); | |
574 | ||
575 | /* Enable the second stage */ | |
708ebb3b | 576 | snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1, |
6a504a75 DP |
577 | WM8995_HPOUT1L_DLY_MASK | |
578 | WM8995_HPOUT1R_DLY_MASK, | |
579 | WM8995_HPOUT1L_DLY | | |
580 | WM8995_HPOUT1R_DLY); | |
581 | break; | |
582 | case SND_SOC_DAPM_PRE_PMD: | |
708ebb3b | 583 | snd_soc_component_update_bits(component, WM8995_CHARGE_PUMP_1, |
6a504a75 DP |
584 | WM8995_CP_ENA_MASK, 0); |
585 | break; | |
586 | } | |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
708ebb3b | 591 | static void dc_servo_cmd(struct snd_soc_component *component, |
6a504a75 DP |
592 | unsigned int reg, unsigned int val, unsigned int mask) |
593 | { | |
594 | int timeout = 10; | |
595 | ||
708ebb3b | 596 | dev_dbg(component->dev, "%s: reg = %#x, val = %#x, mask = %#x\n", |
6a504a75 DP |
597 | __func__, reg, val, mask); |
598 | ||
708ebb3b | 599 | snd_soc_component_write(component, reg, val); |
6a504a75 DP |
600 | while (timeout--) { |
601 | msleep(10); | |
708ebb3b | 602 | val = snd_soc_component_read32(component, WM8995_DC_SERVO_READBACK_0); |
6a504a75 DP |
603 | if ((val & mask) == mask) |
604 | return; | |
605 | } | |
606 | ||
708ebb3b | 607 | dev_err(component->dev, "Timed out waiting for DC Servo\n"); |
6a504a75 DP |
608 | } |
609 | ||
610 | static int hp_event(struct snd_soc_dapm_widget *w, | |
611 | struct snd_kcontrol *kcontrol, int event) | |
612 | { | |
708ebb3b | 613 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
6a504a75 DP |
614 | unsigned int reg; |
615 | ||
708ebb3b | 616 | reg = snd_soc_component_read32(component, WM8995_ANALOGUE_HP_1); |
6a504a75 DP |
617 | |
618 | switch (event) { | |
619 | case SND_SOC_DAPM_POST_PMU: | |
708ebb3b | 620 | snd_soc_component_update_bits(component, WM8995_CHARGE_PUMP_1, |
6a504a75 DP |
621 | WM8995_CP_ENA_MASK, WM8995_CP_ENA); |
622 | ||
623 | msleep(5); | |
624 | ||
708ebb3b | 625 | snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1, |
6a504a75 DP |
626 | WM8995_HPOUT1L_ENA_MASK | |
627 | WM8995_HPOUT1R_ENA_MASK, | |
628 | WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA); | |
629 | ||
630 | udelay(20); | |
631 | ||
632 | reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY; | |
708ebb3b | 633 | snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg); |
6a504a75 | 634 | |
708ebb3b | 635 | snd_soc_component_write(component, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 | |
6a504a75 DP |
636 | WM8995_DCS_ENA_CHAN_1); |
637 | ||
708ebb3b | 638 | dc_servo_cmd(component, WM8995_DC_SERVO_2, |
6a504a75 DP |
639 | WM8995_DCS_TRIG_STARTUP_0 | |
640 | WM8995_DCS_TRIG_STARTUP_1, | |
641 | WM8995_DCS_TRIG_DAC_WR_0 | | |
642 | WM8995_DCS_TRIG_DAC_WR_1); | |
643 | ||
644 | reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT | | |
645 | WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT; | |
708ebb3b | 646 | snd_soc_component_write(component, WM8995_ANALOGUE_HP_1, reg); |
6a504a75 DP |
647 | |
648 | break; | |
649 | case SND_SOC_DAPM_PRE_PMD: | |
708ebb3b | 650 | snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1, |
6a504a75 DP |
651 | WM8995_HPOUT1L_OUTP_MASK | |
652 | WM8995_HPOUT1R_OUTP_MASK | | |
653 | WM8995_HPOUT1L_RMV_SHORT_MASK | | |
654 | WM8995_HPOUT1R_RMV_SHORT_MASK, 0); | |
655 | ||
708ebb3b | 656 | snd_soc_component_update_bits(component, WM8995_ANALOGUE_HP_1, |
6a504a75 DP |
657 | WM8995_HPOUT1L_DLY_MASK | |
658 | WM8995_HPOUT1R_DLY_MASK, 0); | |
659 | ||
708ebb3b | 660 | snd_soc_component_write(component, WM8995_DC_SERVO_1, 0); |
6a504a75 | 661 | |
708ebb3b | 662 | snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1, |
6a504a75 DP |
663 | WM8995_HPOUT1L_ENA_MASK | |
664 | WM8995_HPOUT1R_ENA_MASK, | |
665 | 0); | |
666 | break; | |
667 | } | |
668 | ||
669 | return 0; | |
670 | } | |
671 | ||
708ebb3b | 672 | static int configure_aif_clock(struct snd_soc_component *component, int aif) |
6a504a75 DP |
673 | { |
674 | struct wm8995_priv *wm8995; | |
675 | int rate; | |
676 | int reg1 = 0; | |
677 | int offset; | |
678 | ||
708ebb3b | 679 | wm8995 = snd_soc_component_get_drvdata(component); |
6a504a75 DP |
680 | |
681 | if (aif) | |
682 | offset = 4; | |
683 | else | |
684 | offset = 0; | |
685 | ||
686 | switch (wm8995->sysclk[aif]) { | |
687 | case WM8995_SYSCLK_MCLK1: | |
688 | rate = wm8995->mclk[0]; | |
689 | break; | |
690 | case WM8995_SYSCLK_MCLK2: | |
691 | reg1 |= 0x8; | |
692 | rate = wm8995->mclk[1]; | |
693 | break; | |
694 | case WM8995_SYSCLK_FLL1: | |
695 | reg1 |= 0x10; | |
696 | rate = wm8995->fll[0].out; | |
697 | break; | |
698 | case WM8995_SYSCLK_FLL2: | |
699 | reg1 |= 0x18; | |
700 | rate = wm8995->fll[1].out; | |
701 | break; | |
702 | default: | |
703 | return -EINVAL; | |
704 | } | |
705 | ||
706 | if (rate >= 13500000) { | |
707 | rate /= 2; | |
708 | reg1 |= WM8995_AIF1CLK_DIV; | |
709 | ||
708ebb3b | 710 | dev_dbg(component->dev, "Dividing AIF%d clock to %dHz\n", |
6a504a75 DP |
711 | aif + 1, rate); |
712 | } | |
713 | ||
714 | wm8995->aifclk[aif] = rate; | |
715 | ||
708ebb3b | 716 | snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1 + offset, |
6a504a75 DP |
717 | WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK, |
718 | reg1); | |
719 | return 0; | |
720 | } | |
721 | ||
708ebb3b | 722 | static int configure_clock(struct snd_soc_component *component) |
6a504a75 | 723 | { |
708ebb3b | 724 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
6a504a75 | 725 | struct wm8995_priv *wm8995; |
73478755 | 726 | int change, new; |
6a504a75 | 727 | |
708ebb3b | 728 | wm8995 = snd_soc_component_get_drvdata(component); |
6a504a75 DP |
729 | |
730 | /* Bring up the AIF clocks first */ | |
708ebb3b KM |
731 | configure_aif_clock(component, 0); |
732 | configure_aif_clock(component, 1); | |
6a504a75 DP |
733 | |
734 | /* | |
735 | * Then switch CLK_SYS over to the higher of them; a change | |
736 | * can only happen as a result of a clocking change which can | |
737 | * only be made outside of DAPM so we can safely redo the | |
738 | * clocking. | |
739 | */ | |
740 | ||
741 | /* If they're equal it doesn't matter which is used */ | |
742 | if (wm8995->aifclk[0] == wm8995->aifclk[1]) | |
743 | return 0; | |
744 | ||
745 | if (wm8995->aifclk[0] < wm8995->aifclk[1]) | |
746 | new = WM8995_SYSCLK_SRC; | |
747 | else | |
748 | new = 0; | |
749 | ||
708ebb3b | 750 | change = snd_soc_component_update_bits(component, WM8995_CLOCKING_1, |
73478755 AL |
751 | WM8995_SYSCLK_SRC_MASK, new); |
752 | if (!change) | |
6a504a75 DP |
753 | return 0; |
754 | ||
a01ddd38 | 755 | snd_soc_dapm_sync(dapm); |
6a504a75 DP |
756 | |
757 | return 0; | |
758 | } | |
759 | ||
760 | static int clk_sys_event(struct snd_soc_dapm_widget *w, | |
761 | struct snd_kcontrol *kcontrol, int event) | |
762 | { | |
708ebb3b | 763 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
6a504a75 DP |
764 | |
765 | switch (event) { | |
766 | case SND_SOC_DAPM_PRE_PMU: | |
708ebb3b | 767 | return configure_clock(component); |
6a504a75 DP |
768 | |
769 | case SND_SOC_DAPM_POST_PMD: | |
708ebb3b | 770 | configure_clock(component); |
6a504a75 DP |
771 | break; |
772 | } | |
773 | ||
774 | return 0; | |
775 | } | |
776 | ||
777 | static const char *sidetone_text[] = { | |
778 | "ADC/DMIC1", "DMIC2", | |
779 | }; | |
780 | ||
15b49e73 | 781 | static SOC_ENUM_SINGLE_DECL(sidetone1_enum, WM8995_SIDETONE, 0, sidetone_text); |
6a504a75 DP |
782 | |
783 | static const struct snd_kcontrol_new sidetone1_mux = | |
784 | SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); | |
785 | ||
15b49e73 | 786 | static SOC_ENUM_SINGLE_DECL(sidetone2_enum, WM8995_SIDETONE, 1, sidetone_text); |
6a504a75 DP |
787 | |
788 | static const struct snd_kcontrol_new sidetone2_mux = | |
789 | SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); | |
790 | ||
791 | static const struct snd_kcontrol_new aif1adc1l_mix[] = { | |
792 | SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, | |
793 | 1, 1, 0), | |
794 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, | |
795 | 0, 1, 0), | |
796 | }; | |
797 | ||
798 | static const struct snd_kcontrol_new aif1adc1r_mix[] = { | |
799 | SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, | |
800 | 1, 1, 0), | |
801 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, | |
802 | 0, 1, 0), | |
803 | }; | |
804 | ||
805 | static const struct snd_kcontrol_new aif1adc2l_mix[] = { | |
806 | SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, | |
807 | 1, 1, 0), | |
808 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, | |
809 | 0, 1, 0), | |
810 | }; | |
811 | ||
812 | static const struct snd_kcontrol_new aif1adc2r_mix[] = { | |
813 | SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, | |
814 | 1, 1, 0), | |
815 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, | |
816 | 0, 1, 0), | |
817 | }; | |
818 | ||
819 | static const struct snd_kcontrol_new dac1l_mix[] = { | |
820 | WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
821 | 5, 1, 0), | |
822 | WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
823 | 4, 1, 0), | |
824 | WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
825 | 2, 1, 0), | |
826 | WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
827 | 1, 1, 0), | |
828 | WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
829 | 0, 1, 0), | |
830 | }; | |
831 | ||
832 | static const struct snd_kcontrol_new dac1r_mix[] = { | |
833 | WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
834 | 5, 1, 0), | |
835 | WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
836 | 4, 1, 0), | |
837 | WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
838 | 2, 1, 0), | |
839 | WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
840 | 1, 1, 0), | |
841 | WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
842 | 0, 1, 0), | |
843 | }; | |
844 | ||
845 | static const struct snd_kcontrol_new aif2dac2l_mix[] = { | |
846 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
847 | 5, 1, 0), | |
848 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
849 | 4, 1, 0), | |
850 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
851 | 2, 1, 0), | |
852 | SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
853 | 1, 1, 0), | |
854 | SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
855 | 0, 1, 0), | |
856 | }; | |
857 | ||
858 | static const struct snd_kcontrol_new aif2dac2r_mix[] = { | |
859 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
860 | 5, 1, 0), | |
861 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
862 | 4, 1, 0), | |
863 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
864 | 2, 1, 0), | |
865 | SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
866 | 1, 1, 0), | |
867 | SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
868 | 0, 1, 0), | |
869 | }; | |
870 | ||
871 | static const struct snd_kcontrol_new in1l_pga = | |
872 | SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0); | |
873 | ||
874 | static const struct snd_kcontrol_new in1r_pga = | |
875 | SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0); | |
876 | ||
877 | static const char *adc_mux_text[] = { | |
878 | "ADC", | |
879 | "DMIC", | |
880 | }; | |
881 | ||
f6b45c28 | 882 | static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text); |
6a504a75 DP |
883 | |
884 | static const struct snd_kcontrol_new adcl_mux = | |
b8eecc19 | 885 | SOC_DAPM_ENUM("ADCL Mux", adc_enum); |
6a504a75 DP |
886 | |
887 | static const struct snd_kcontrol_new adcr_mux = | |
b8eecc19 | 888 | SOC_DAPM_ENUM("ADCR Mux", adc_enum); |
6a504a75 DP |
889 | |
890 | static const char *spk_src_text[] = { | |
891 | "DAC1L", "DAC1R", "DAC2L", "DAC2R" | |
892 | }; | |
893 | ||
48e50ce3 TI |
894 | static SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1, |
895 | 0, spk_src_text); | |
896 | static SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1, | |
897 | 0, spk_src_text); | |
898 | static SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2, | |
899 | 0, spk_src_text); | |
900 | static SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2, | |
901 | 0, spk_src_text); | |
6a504a75 DP |
902 | |
903 | static const struct snd_kcontrol_new spk1l_mux = | |
904 | SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum); | |
905 | static const struct snd_kcontrol_new spk1r_mux = | |
906 | SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum); | |
907 | static const struct snd_kcontrol_new spk2l_mux = | |
908 | SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum); | |
909 | static const struct snd_kcontrol_new spk2r_mux = | |
910 | SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum); | |
911 | ||
912 | static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = { | |
913 | SND_SOC_DAPM_INPUT("DMIC1DAT"), | |
914 | SND_SOC_DAPM_INPUT("DMIC2DAT"), | |
915 | ||
916 | SND_SOC_DAPM_INPUT("IN1L"), | |
917 | SND_SOC_DAPM_INPUT("IN1R"), | |
918 | ||
919 | SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0, | |
920 | &in1l_pga, 1), | |
921 | SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0, | |
922 | &in1r_pga, 1), | |
923 | ||
9ce31623 MB |
924 | SND_SOC_DAPM_SUPPLY("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0, |
925 | NULL, 0), | |
926 | SND_SOC_DAPM_SUPPLY("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0, | |
927 | NULL, 0), | |
6a504a75 DP |
928 | |
929 | SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0), | |
930 | SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0), | |
931 | SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0), | |
932 | SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0), | |
933 | SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0), | |
934 | SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, | |
935 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
936 | ||
937 | SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0, | |
938 | WM8995_POWER_MANAGEMENT_3, 9, 0), | |
939 | SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0, | |
940 | WM8995_POWER_MANAGEMENT_3, 8, 0), | |
941 | SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, | |
942 | SND_SOC_NOPM, 0, 0), | |
943 | SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", | |
944 | 0, WM8995_POWER_MANAGEMENT_3, 11, 0), | |
945 | SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", | |
946 | 0, WM8995_POWER_MANAGEMENT_3, 10, 0), | |
947 | ||
b8eecc19 LPC |
948 | SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, &adcl_mux), |
949 | SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, &adcr_mux), | |
6a504a75 DP |
950 | |
951 | SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0), | |
952 | SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0), | |
953 | SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0), | |
954 | SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0), | |
955 | ||
956 | SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0), | |
957 | SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0), | |
958 | ||
959 | SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, | |
960 | aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), | |
961 | SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, | |
962 | aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), | |
963 | SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, | |
964 | aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), | |
965 | SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, | |
966 | aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), | |
967 | ||
968 | SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4, | |
969 | 9, 0), | |
970 | SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4, | |
971 | 8, 0), | |
972 | SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, | |
973 | 0, 0), | |
974 | ||
975 | SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4, | |
976 | 11, 0), | |
977 | SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4, | |
978 | 10, 0), | |
979 | ||
980 | SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, | |
981 | aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), | |
982 | SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, | |
983 | aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), | |
984 | ||
985 | SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0), | |
986 | SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0), | |
987 | SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0), | |
988 | SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0), | |
989 | ||
990 | SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix, | |
991 | ARRAY_SIZE(dac1l_mix)), | |
992 | SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix, | |
993 | ARRAY_SIZE(dac1r_mix)), | |
994 | ||
995 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), | |
996 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), | |
997 | ||
998 | SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0, | |
999 | hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
1000 | ||
1001 | SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, | |
1002 | hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
1003 | ||
1004 | SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1, | |
1005 | 4, 0, &spk1l_mux), | |
1006 | SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1, | |
1007 | 4, 0, &spk1r_mux), | |
1008 | SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2, | |
1009 | 4, 0, &spk2l_mux), | |
1010 | SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2, | |
1011 | 4, 0, &spk2r_mux), | |
1012 | ||
1013 | SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0), | |
1014 | ||
1015 | SND_SOC_DAPM_OUTPUT("HP1L"), | |
1016 | SND_SOC_DAPM_OUTPUT("HP1R"), | |
1017 | SND_SOC_DAPM_OUTPUT("SPK1L"), | |
1018 | SND_SOC_DAPM_OUTPUT("SPK1R"), | |
1019 | SND_SOC_DAPM_OUTPUT("SPK2L"), | |
1020 | SND_SOC_DAPM_OUTPUT("SPK2R") | |
1021 | }; | |
1022 | ||
1023 | static const struct snd_soc_dapm_route wm8995_intercon[] = { | |
1024 | { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, | |
1025 | { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, | |
1026 | ||
1027 | { "DSP1CLK", NULL, "CLK_SYS" }, | |
1028 | { "DSP2CLK", NULL, "CLK_SYS" }, | |
1029 | { "SYSDSPCLK", NULL, "CLK_SYS" }, | |
1030 | ||
1031 | { "AIF1ADC1L", NULL, "AIF1CLK" }, | |
1032 | { "AIF1ADC1L", NULL, "DSP1CLK" }, | |
1033 | { "AIF1ADC1R", NULL, "AIF1CLK" }, | |
1034 | { "AIF1ADC1R", NULL, "DSP1CLK" }, | |
1035 | { "AIF1ADC1R", NULL, "SYSDSPCLK" }, | |
1036 | ||
1037 | { "AIF1ADC2L", NULL, "AIF1CLK" }, | |
1038 | { "AIF1ADC2L", NULL, "DSP1CLK" }, | |
1039 | { "AIF1ADC2R", NULL, "AIF1CLK" }, | |
1040 | { "AIF1ADC2R", NULL, "DSP1CLK" }, | |
1041 | { "AIF1ADC2R", NULL, "SYSDSPCLK" }, | |
1042 | ||
1043 | { "DMIC1L", NULL, "DMIC1DAT" }, | |
1044 | { "DMIC1L", NULL, "CLK_SYS" }, | |
1045 | { "DMIC1R", NULL, "DMIC1DAT" }, | |
1046 | { "DMIC1R", NULL, "CLK_SYS" }, | |
1047 | { "DMIC2L", NULL, "DMIC2DAT" }, | |
1048 | { "DMIC2L", NULL, "CLK_SYS" }, | |
1049 | { "DMIC2R", NULL, "DMIC2DAT" }, | |
1050 | { "DMIC2R", NULL, "CLK_SYS" }, | |
1051 | ||
1052 | { "ADCL", NULL, "AIF1CLK" }, | |
1053 | { "ADCL", NULL, "DSP1CLK" }, | |
1054 | { "ADCL", NULL, "SYSDSPCLK" }, | |
1055 | ||
1056 | { "ADCR", NULL, "AIF1CLK" }, | |
1057 | { "ADCR", NULL, "DSP1CLK" }, | |
1058 | { "ADCR", NULL, "SYSDSPCLK" }, | |
1059 | ||
1060 | { "IN1L PGA", "IN1L Switch", "IN1L" }, | |
1061 | { "IN1R PGA", "IN1R Switch", "IN1R" }, | |
1062 | { "IN1L PGA", NULL, "LDO2" }, | |
1063 | { "IN1R PGA", NULL, "LDO2" }, | |
1064 | ||
1065 | { "ADCL", NULL, "IN1L PGA" }, | |
1066 | { "ADCR", NULL, "IN1R PGA" }, | |
1067 | ||
1068 | { "ADCL Mux", "ADC", "ADCL" }, | |
1069 | { "ADCL Mux", "DMIC", "DMIC1L" }, | |
1070 | { "ADCR Mux", "ADC", "ADCR" }, | |
1071 | { "ADCR Mux", "DMIC", "DMIC1R" }, | |
1072 | ||
1073 | /* AIF1 outputs */ | |
1074 | { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, | |
1075 | { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, | |
1076 | ||
1077 | { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, | |
1078 | { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, | |
1079 | ||
1080 | { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, | |
1081 | { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, | |
1082 | ||
1083 | { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, | |
1084 | { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, | |
1085 | ||
1086 | /* Sidetone */ | |
1087 | { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" }, | |
1088 | { "Left Sidetone", "DMIC2", "AIF1ADC2L" }, | |
1089 | { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" }, | |
1090 | { "Right Sidetone", "DMIC2", "AIF1ADC2R" }, | |
1091 | ||
1092 | { "AIF1DAC1L", NULL, "AIF1CLK" }, | |
1093 | { "AIF1DAC1L", NULL, "DSP1CLK" }, | |
1094 | { "AIF1DAC1R", NULL, "AIF1CLK" }, | |
1095 | { "AIF1DAC1R", NULL, "DSP1CLK" }, | |
1096 | { "AIF1DAC1R", NULL, "SYSDSPCLK" }, | |
1097 | ||
1098 | { "AIF1DAC2L", NULL, "AIF1CLK" }, | |
1099 | { "AIF1DAC2L", NULL, "DSP1CLK" }, | |
1100 | { "AIF1DAC2R", NULL, "AIF1CLK" }, | |
1101 | { "AIF1DAC2R", NULL, "DSP1CLK" }, | |
1102 | { "AIF1DAC2R", NULL, "SYSDSPCLK" }, | |
1103 | ||
1104 | { "DAC1L", NULL, "AIF1CLK" }, | |
1105 | { "DAC1L", NULL, "DSP1CLK" }, | |
1106 | { "DAC1L", NULL, "SYSDSPCLK" }, | |
1107 | ||
1108 | { "DAC1R", NULL, "AIF1CLK" }, | |
1109 | { "DAC1R", NULL, "DSP1CLK" }, | |
1110 | { "DAC1R", NULL, "SYSDSPCLK" }, | |
1111 | ||
1112 | { "AIF1DAC1L", NULL, "AIF1DACDAT" }, | |
1113 | { "AIF1DAC1R", NULL, "AIF1DACDAT" }, | |
1114 | { "AIF1DAC2L", NULL, "AIF1DACDAT" }, | |
1115 | { "AIF1DAC2R", NULL, "AIF1DACDAT" }, | |
1116 | ||
1117 | /* DAC1 inputs */ | |
1118 | { "DAC1L", NULL, "DAC1L Mixer" }, | |
1119 | { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, | |
1120 | { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, | |
1121 | { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1122 | { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1123 | ||
1124 | { "DAC1R", NULL, "DAC1R Mixer" }, | |
1125 | { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, | |
1126 | { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, | |
1127 | { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1128 | { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1129 | ||
1130 | /* DAC2/AIF2 outputs */ | |
1131 | { "DAC2L", NULL, "AIF2DAC2L Mixer" }, | |
1132 | { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, | |
1133 | { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, | |
1134 | ||
1135 | { "DAC2R", NULL, "AIF2DAC2R Mixer" }, | |
1136 | { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, | |
1137 | { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, | |
1138 | ||
1139 | /* Output stages */ | |
1140 | { "Headphone PGA", NULL, "DAC1L" }, | |
1141 | { "Headphone PGA", NULL, "DAC1R" }, | |
1142 | ||
1143 | { "Headphone PGA", NULL, "DAC2L" }, | |
1144 | { "Headphone PGA", NULL, "DAC2R" }, | |
1145 | ||
1146 | { "Headphone PGA", NULL, "Headphone Supply" }, | |
1147 | { "Headphone PGA", NULL, "CLK_SYS" }, | |
1148 | { "Headphone PGA", NULL, "LDO2" }, | |
1149 | ||
1150 | { "HP1L", NULL, "Headphone PGA" }, | |
1151 | { "HP1R", NULL, "Headphone PGA" }, | |
1152 | ||
1153 | { "SPK1L Driver", "DAC1L", "DAC1L" }, | |
1154 | { "SPK1L Driver", "DAC1R", "DAC1R" }, | |
1155 | { "SPK1L Driver", "DAC2L", "DAC2L" }, | |
1156 | { "SPK1L Driver", "DAC2R", "DAC2R" }, | |
1157 | { "SPK1L Driver", NULL, "CLK_SYS" }, | |
1158 | ||
1159 | { "SPK1R Driver", "DAC1L", "DAC1L" }, | |
1160 | { "SPK1R Driver", "DAC1R", "DAC1R" }, | |
1161 | { "SPK1R Driver", "DAC2L", "DAC2L" }, | |
1162 | { "SPK1R Driver", "DAC2R", "DAC2R" }, | |
1163 | { "SPK1R Driver", NULL, "CLK_SYS" }, | |
1164 | ||
1165 | { "SPK2L Driver", "DAC1L", "DAC1L" }, | |
1166 | { "SPK2L Driver", "DAC1R", "DAC1R" }, | |
1167 | { "SPK2L Driver", "DAC2L", "DAC2L" }, | |
1168 | { "SPK2L Driver", "DAC2R", "DAC2R" }, | |
1169 | { "SPK2L Driver", NULL, "CLK_SYS" }, | |
1170 | ||
1171 | { "SPK2R Driver", "DAC1L", "DAC1L" }, | |
1172 | { "SPK2R Driver", "DAC1R", "DAC1R" }, | |
1173 | { "SPK2R Driver", "DAC2L", "DAC2L" }, | |
1174 | { "SPK2R Driver", "DAC2R", "DAC2R" }, | |
1175 | { "SPK2R Driver", NULL, "CLK_SYS" }, | |
1176 | ||
1177 | { "SPK1L", NULL, "SPK1L Driver" }, | |
1178 | { "SPK1R", NULL, "SPK1R Driver" }, | |
1179 | { "SPK2L", NULL, "SPK2L Driver" }, | |
1180 | { "SPK2R", NULL, "SPK2R Driver" } | |
1181 | }; | |
1182 | ||
c42da642 | 1183 | static bool wm8995_readable(struct device *dev, unsigned int reg) |
6a504a75 | 1184 | { |
6a504a75 DP |
1185 | switch (reg) { |
1186 | case WM8995_SOFTWARE_RESET: | |
c42da642 MB |
1187 | case WM8995_POWER_MANAGEMENT_1: |
1188 | case WM8995_POWER_MANAGEMENT_2: | |
1189 | case WM8995_POWER_MANAGEMENT_3: | |
1190 | case WM8995_POWER_MANAGEMENT_4: | |
1191 | case WM8995_POWER_MANAGEMENT_5: | |
1192 | case WM8995_LEFT_LINE_INPUT_1_VOLUME: | |
1193 | case WM8995_RIGHT_LINE_INPUT_1_VOLUME: | |
1194 | case WM8995_LEFT_LINE_INPUT_CONTROL: | |
1195 | case WM8995_DAC1_LEFT_VOLUME: | |
1196 | case WM8995_DAC1_RIGHT_VOLUME: | |
1197 | case WM8995_DAC2_LEFT_VOLUME: | |
1198 | case WM8995_DAC2_RIGHT_VOLUME: | |
1199 | case WM8995_OUTPUT_VOLUME_ZC_1: | |
1200 | case WM8995_MICBIAS_1: | |
1201 | case WM8995_MICBIAS_2: | |
1202 | case WM8995_LDO_1: | |
1203 | case WM8995_LDO_2: | |
1204 | case WM8995_ACCESSORY_DETECT_MODE1: | |
1205 | case WM8995_ACCESSORY_DETECT_MODE2: | |
1206 | case WM8995_HEADPHONE_DETECT1: | |
1207 | case WM8995_HEADPHONE_DETECT2: | |
1208 | case WM8995_MIC_DETECT_1: | |
1209 | case WM8995_MIC_DETECT_2: | |
1210 | case WM8995_CHARGE_PUMP_1: | |
1211 | case WM8995_CLASS_W_1: | |
1212 | case WM8995_DC_SERVO_1: | |
1213 | case WM8995_DC_SERVO_2: | |
1214 | case WM8995_DC_SERVO_3: | |
1215 | case WM8995_DC_SERVO_5: | |
1216 | case WM8995_DC_SERVO_6: | |
1217 | case WM8995_DC_SERVO_7: | |
6a504a75 | 1218 | case WM8995_DC_SERVO_READBACK_0: |
c42da642 MB |
1219 | case WM8995_ANALOGUE_HP_1: |
1220 | case WM8995_ANALOGUE_HP_2: | |
1221 | case WM8995_CHIP_REVISION: | |
1222 | case WM8995_CONTROL_INTERFACE_1: | |
1223 | case WM8995_CONTROL_INTERFACE_2: | |
1224 | case WM8995_WRITE_SEQUENCER_CTRL_1: | |
1225 | case WM8995_WRITE_SEQUENCER_CTRL_2: | |
1226 | case WM8995_AIF1_CLOCKING_1: | |
1227 | case WM8995_AIF1_CLOCKING_2: | |
1228 | case WM8995_AIF2_CLOCKING_1: | |
1229 | case WM8995_AIF2_CLOCKING_2: | |
1230 | case WM8995_CLOCKING_1: | |
1231 | case WM8995_CLOCKING_2: | |
1232 | case WM8995_AIF1_RATE: | |
1233 | case WM8995_AIF2_RATE: | |
1234 | case WM8995_RATE_STATUS: | |
1235 | case WM8995_FLL1_CONTROL_1: | |
1236 | case WM8995_FLL1_CONTROL_2: | |
1237 | case WM8995_FLL1_CONTROL_3: | |
1238 | case WM8995_FLL1_CONTROL_4: | |
1239 | case WM8995_FLL1_CONTROL_5: | |
1240 | case WM8995_FLL2_CONTROL_1: | |
1241 | case WM8995_FLL2_CONTROL_2: | |
1242 | case WM8995_FLL2_CONTROL_3: | |
1243 | case WM8995_FLL2_CONTROL_4: | |
1244 | case WM8995_FLL2_CONTROL_5: | |
1245 | case WM8995_AIF1_CONTROL_1: | |
1246 | case WM8995_AIF1_CONTROL_2: | |
1247 | case WM8995_AIF1_MASTER_SLAVE: | |
1248 | case WM8995_AIF1_BCLK: | |
1249 | case WM8995_AIF1ADC_LRCLK: | |
1250 | case WM8995_AIF1DAC_LRCLK: | |
1251 | case WM8995_AIF1DAC_DATA: | |
1252 | case WM8995_AIF1ADC_DATA: | |
1253 | case WM8995_AIF2_CONTROL_1: | |
1254 | case WM8995_AIF2_CONTROL_2: | |
1255 | case WM8995_AIF2_MASTER_SLAVE: | |
1256 | case WM8995_AIF2_BCLK: | |
1257 | case WM8995_AIF2ADC_LRCLK: | |
1258 | case WM8995_AIF2DAC_LRCLK: | |
1259 | case WM8995_AIF2DAC_DATA: | |
1260 | case WM8995_AIF2ADC_DATA: | |
1261 | case WM8995_AIF1_ADC1_LEFT_VOLUME: | |
1262 | case WM8995_AIF1_ADC1_RIGHT_VOLUME: | |
1263 | case WM8995_AIF1_DAC1_LEFT_VOLUME: | |
1264 | case WM8995_AIF1_DAC1_RIGHT_VOLUME: | |
1265 | case WM8995_AIF1_ADC2_LEFT_VOLUME: | |
1266 | case WM8995_AIF1_ADC2_RIGHT_VOLUME: | |
1267 | case WM8995_AIF1_DAC2_LEFT_VOLUME: | |
1268 | case WM8995_AIF1_DAC2_RIGHT_VOLUME: | |
1269 | case WM8995_AIF1_ADC1_FILTERS: | |
1270 | case WM8995_AIF1_ADC2_FILTERS: | |
1271 | case WM8995_AIF1_DAC1_FILTERS_1: | |
1272 | case WM8995_AIF1_DAC1_FILTERS_2: | |
1273 | case WM8995_AIF1_DAC2_FILTERS_1: | |
1274 | case WM8995_AIF1_DAC2_FILTERS_2: | |
1275 | case WM8995_AIF1_DRC1_1: | |
1276 | case WM8995_AIF1_DRC1_2: | |
1277 | case WM8995_AIF1_DRC1_3: | |
1278 | case WM8995_AIF1_DRC1_4: | |
1279 | case WM8995_AIF1_DRC1_5: | |
1280 | case WM8995_AIF1_DRC2_1: | |
1281 | case WM8995_AIF1_DRC2_2: | |
1282 | case WM8995_AIF1_DRC2_3: | |
1283 | case WM8995_AIF1_DRC2_4: | |
1284 | case WM8995_AIF1_DRC2_5: | |
1285 | case WM8995_AIF1_DAC1_EQ_GAINS_1: | |
1286 | case WM8995_AIF1_DAC1_EQ_GAINS_2: | |
1287 | case WM8995_AIF1_DAC1_EQ_BAND_1_A: | |
1288 | case WM8995_AIF1_DAC1_EQ_BAND_1_B: | |
1289 | case WM8995_AIF1_DAC1_EQ_BAND_1_PG: | |
1290 | case WM8995_AIF1_DAC1_EQ_BAND_2_A: | |
1291 | case WM8995_AIF1_DAC1_EQ_BAND_2_B: | |
1292 | case WM8995_AIF1_DAC1_EQ_BAND_2_C: | |
1293 | case WM8995_AIF1_DAC1_EQ_BAND_2_PG: | |
1294 | case WM8995_AIF1_DAC1_EQ_BAND_3_A: | |
1295 | case WM8995_AIF1_DAC1_EQ_BAND_3_B: | |
1296 | case WM8995_AIF1_DAC1_EQ_BAND_3_C: | |
1297 | case WM8995_AIF1_DAC1_EQ_BAND_3_PG: | |
1298 | case WM8995_AIF1_DAC1_EQ_BAND_4_A: | |
1299 | case WM8995_AIF1_DAC1_EQ_BAND_4_B: | |
1300 | case WM8995_AIF1_DAC1_EQ_BAND_4_C: | |
1301 | case WM8995_AIF1_DAC1_EQ_BAND_4_PG: | |
1302 | case WM8995_AIF1_DAC1_EQ_BAND_5_A: | |
1303 | case WM8995_AIF1_DAC1_EQ_BAND_5_B: | |
1304 | case WM8995_AIF1_DAC1_EQ_BAND_5_PG: | |
1305 | case WM8995_AIF1_DAC2_EQ_GAINS_1: | |
1306 | case WM8995_AIF1_DAC2_EQ_GAINS_2: | |
1307 | case WM8995_AIF1_DAC2_EQ_BAND_1_A: | |
1308 | case WM8995_AIF1_DAC2_EQ_BAND_1_B: | |
1309 | case WM8995_AIF1_DAC2_EQ_BAND_1_PG: | |
1310 | case WM8995_AIF1_DAC2_EQ_BAND_2_A: | |
1311 | case WM8995_AIF1_DAC2_EQ_BAND_2_B: | |
1312 | case WM8995_AIF1_DAC2_EQ_BAND_2_C: | |
1313 | case WM8995_AIF1_DAC2_EQ_BAND_2_PG: | |
1314 | case WM8995_AIF1_DAC2_EQ_BAND_3_A: | |
1315 | case WM8995_AIF1_DAC2_EQ_BAND_3_B: | |
1316 | case WM8995_AIF1_DAC2_EQ_BAND_3_C: | |
1317 | case WM8995_AIF1_DAC2_EQ_BAND_3_PG: | |
1318 | case WM8995_AIF1_DAC2_EQ_BAND_4_A: | |
1319 | case WM8995_AIF1_DAC2_EQ_BAND_4_B: | |
1320 | case WM8995_AIF1_DAC2_EQ_BAND_4_C: | |
1321 | case WM8995_AIF1_DAC2_EQ_BAND_4_PG: | |
1322 | case WM8995_AIF1_DAC2_EQ_BAND_5_A: | |
1323 | case WM8995_AIF1_DAC2_EQ_BAND_5_B: | |
1324 | case WM8995_AIF1_DAC2_EQ_BAND_5_PG: | |
1325 | case WM8995_AIF2_ADC_LEFT_VOLUME: | |
1326 | case WM8995_AIF2_ADC_RIGHT_VOLUME: | |
1327 | case WM8995_AIF2_DAC_LEFT_VOLUME: | |
1328 | case WM8995_AIF2_DAC_RIGHT_VOLUME: | |
1329 | case WM8995_AIF2_ADC_FILTERS: | |
1330 | case WM8995_AIF2_DAC_FILTERS_1: | |
1331 | case WM8995_AIF2_DAC_FILTERS_2: | |
1332 | case WM8995_AIF2_DRC_1: | |
1333 | case WM8995_AIF2_DRC_2: | |
1334 | case WM8995_AIF2_DRC_3: | |
1335 | case WM8995_AIF2_DRC_4: | |
1336 | case WM8995_AIF2_DRC_5: | |
1337 | case WM8995_AIF2_EQ_GAINS_1: | |
1338 | case WM8995_AIF2_EQ_GAINS_2: | |
1339 | case WM8995_AIF2_EQ_BAND_1_A: | |
1340 | case WM8995_AIF2_EQ_BAND_1_B: | |
1341 | case WM8995_AIF2_EQ_BAND_1_PG: | |
1342 | case WM8995_AIF2_EQ_BAND_2_A: | |
1343 | case WM8995_AIF2_EQ_BAND_2_B: | |
1344 | case WM8995_AIF2_EQ_BAND_2_C: | |
1345 | case WM8995_AIF2_EQ_BAND_2_PG: | |
1346 | case WM8995_AIF2_EQ_BAND_3_A: | |
1347 | case WM8995_AIF2_EQ_BAND_3_B: | |
1348 | case WM8995_AIF2_EQ_BAND_3_C: | |
1349 | case WM8995_AIF2_EQ_BAND_3_PG: | |
1350 | case WM8995_AIF2_EQ_BAND_4_A: | |
1351 | case WM8995_AIF2_EQ_BAND_4_B: | |
1352 | case WM8995_AIF2_EQ_BAND_4_C: | |
1353 | case WM8995_AIF2_EQ_BAND_4_PG: | |
1354 | case WM8995_AIF2_EQ_BAND_5_A: | |
1355 | case WM8995_AIF2_EQ_BAND_5_B: | |
1356 | case WM8995_AIF2_EQ_BAND_5_PG: | |
1357 | case WM8995_DAC1_MIXER_VOLUMES: | |
1358 | case WM8995_DAC1_LEFT_MIXER_ROUTING: | |
1359 | case WM8995_DAC1_RIGHT_MIXER_ROUTING: | |
1360 | case WM8995_DAC2_MIXER_VOLUMES: | |
1361 | case WM8995_DAC2_LEFT_MIXER_ROUTING: | |
1362 | case WM8995_DAC2_RIGHT_MIXER_ROUTING: | |
1363 | case WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING: | |
1364 | case WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING: | |
1365 | case WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING: | |
1366 | case WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING: | |
1367 | case WM8995_DAC_SOFTMUTE: | |
1368 | case WM8995_OVERSAMPLING: | |
1369 | case WM8995_SIDETONE: | |
1370 | case WM8995_GPIO_1: | |
1371 | case WM8995_GPIO_2: | |
1372 | case WM8995_GPIO_3: | |
1373 | case WM8995_GPIO_4: | |
1374 | case WM8995_GPIO_5: | |
1375 | case WM8995_GPIO_6: | |
1376 | case WM8995_GPIO_7: | |
1377 | case WM8995_GPIO_8: | |
1378 | case WM8995_GPIO_9: | |
1379 | case WM8995_GPIO_10: | |
1380 | case WM8995_GPIO_11: | |
1381 | case WM8995_GPIO_12: | |
1382 | case WM8995_GPIO_13: | |
1383 | case WM8995_GPIO_14: | |
1384 | case WM8995_PULL_CONTROL_1: | |
1385 | case WM8995_PULL_CONTROL_2: | |
6a504a75 DP |
1386 | case WM8995_INTERRUPT_STATUS_1: |
1387 | case WM8995_INTERRUPT_STATUS_2: | |
c42da642 | 1388 | case WM8995_INTERRUPT_RAW_STATUS_2: |
6a504a75 DP |
1389 | case WM8995_INTERRUPT_STATUS_1_MASK: |
1390 | case WM8995_INTERRUPT_STATUS_2_MASK: | |
1391 | case WM8995_INTERRUPT_CONTROL: | |
c42da642 MB |
1392 | case WM8995_LEFT_PDM_SPEAKER_1: |
1393 | case WM8995_RIGHT_PDM_SPEAKER_1: | |
1394 | case WM8995_PDM_SPEAKER_1_MUTE_SEQUENCE: | |
1395 | case WM8995_LEFT_PDM_SPEAKER_2: | |
1396 | case WM8995_RIGHT_PDM_SPEAKER_2: | |
1397 | case WM8995_PDM_SPEAKER_2_MUTE_SEQUENCE: | |
1398 | return true; | |
1399 | default: | |
1400 | return false; | |
1401 | } | |
1402 | } | |
1403 | ||
1404 | static bool wm8995_volatile(struct device *dev, unsigned int reg) | |
1405 | { | |
1406 | switch (reg) { | |
1407 | case WM8995_SOFTWARE_RESET: | |
1408 | case WM8995_DC_SERVO_READBACK_0: | |
1409 | case WM8995_INTERRUPT_STATUS_1: | |
1410 | case WM8995_INTERRUPT_STATUS_2: | |
1411 | case WM8995_INTERRUPT_CONTROL: | |
6a504a75 DP |
1412 | case WM8995_ACCESSORY_DETECT_MODE1: |
1413 | case WM8995_ACCESSORY_DETECT_MODE2: | |
1414 | case WM8995_HEADPHONE_DETECT1: | |
1415 | case WM8995_HEADPHONE_DETECT2: | |
c42da642 MB |
1416 | case WM8995_RATE_STATUS: |
1417 | return true; | |
1418 | default: | |
1419 | return false; | |
6a504a75 | 1420 | } |
6a504a75 DP |
1421 | } |
1422 | ||
1423 | static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute) | |
1424 | { | |
708ebb3b | 1425 | struct snd_soc_component *component = dai->component; |
6a504a75 DP |
1426 | int mute_reg; |
1427 | ||
1428 | switch (dai->id) { | |
1429 | case 0: | |
1430 | mute_reg = WM8995_AIF1_DAC1_FILTERS_1; | |
1431 | break; | |
1432 | case 1: | |
1433 | mute_reg = WM8995_AIF2_DAC_FILTERS_1; | |
1434 | break; | |
1435 | default: | |
1436 | return -EINVAL; | |
1437 | } | |
1438 | ||
708ebb3b | 1439 | snd_soc_component_update_bits(component, mute_reg, WM8995_AIF1DAC1_MUTE_MASK, |
6a504a75 DP |
1440 | !!mute << WM8995_AIF1DAC1_MUTE_SHIFT); |
1441 | return 0; | |
1442 | } | |
1443 | ||
1444 | static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
1445 | { | |
708ebb3b | 1446 | struct snd_soc_component *component; |
6a504a75 DP |
1447 | int master; |
1448 | int aif; | |
1449 | ||
708ebb3b | 1450 | component = dai->component; |
6a504a75 DP |
1451 | |
1452 | master = 0; | |
1453 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1454 | case SND_SOC_DAIFMT_CBS_CFS: | |
1455 | break; | |
1456 | case SND_SOC_DAIFMT_CBM_CFM: | |
1457 | master = WM8995_AIF1_MSTR; | |
1458 | break; | |
1459 | default: | |
1460 | dev_err(dai->dev, "Unknown master/slave configuration\n"); | |
1461 | return -EINVAL; | |
1462 | } | |
1463 | ||
1464 | aif = 0; | |
1465 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1466 | case SND_SOC_DAIFMT_DSP_B: | |
1467 | aif |= WM8995_AIF1_LRCLK_INV; | |
af5d1d5d | 1468 | /* fall through */ |
6a504a75 DP |
1469 | case SND_SOC_DAIFMT_DSP_A: |
1470 | aif |= (0x3 << WM8995_AIF1_FMT_SHIFT); | |
1471 | break; | |
1472 | case SND_SOC_DAIFMT_I2S: | |
1473 | aif |= (0x2 << WM8995_AIF1_FMT_SHIFT); | |
1474 | break; | |
1475 | case SND_SOC_DAIFMT_RIGHT_J: | |
1476 | break; | |
1477 | case SND_SOC_DAIFMT_LEFT_J: | |
1478 | aif |= (0x1 << WM8995_AIF1_FMT_SHIFT); | |
1479 | break; | |
1480 | default: | |
1481 | dev_err(dai->dev, "Unknown dai format\n"); | |
1482 | return -EINVAL; | |
1483 | } | |
1484 | ||
1485 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1486 | case SND_SOC_DAIFMT_DSP_A: | |
1487 | case SND_SOC_DAIFMT_DSP_B: | |
1488 | /* frame inversion not valid for DSP modes */ | |
1489 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1490 | case SND_SOC_DAIFMT_NB_NF: | |
1491 | break; | |
1492 | case SND_SOC_DAIFMT_IB_NF: | |
1493 | aif |= WM8995_AIF1_BCLK_INV; | |
1494 | break; | |
1495 | default: | |
1496 | return -EINVAL; | |
1497 | } | |
1498 | break; | |
1499 | ||
1500 | case SND_SOC_DAIFMT_I2S: | |
1501 | case SND_SOC_DAIFMT_RIGHT_J: | |
1502 | case SND_SOC_DAIFMT_LEFT_J: | |
1503 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1504 | case SND_SOC_DAIFMT_NB_NF: | |
1505 | break; | |
1506 | case SND_SOC_DAIFMT_IB_IF: | |
1507 | aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV; | |
1508 | break; | |
1509 | case SND_SOC_DAIFMT_IB_NF: | |
1510 | aif |= WM8995_AIF1_BCLK_INV; | |
1511 | break; | |
1512 | case SND_SOC_DAIFMT_NB_IF: | |
1513 | aif |= WM8995_AIF1_LRCLK_INV; | |
1514 | break; | |
1515 | default: | |
1516 | return -EINVAL; | |
1517 | } | |
1518 | break; | |
1519 | default: | |
1520 | return -EINVAL; | |
1521 | } | |
1522 | ||
708ebb3b | 1523 | snd_soc_component_update_bits(component, WM8995_AIF1_CONTROL_1, |
6a504a75 DP |
1524 | WM8995_AIF1_BCLK_INV_MASK | |
1525 | WM8995_AIF1_LRCLK_INV_MASK | | |
1526 | WM8995_AIF1_FMT_MASK, aif); | |
708ebb3b | 1527 | snd_soc_component_update_bits(component, WM8995_AIF1_MASTER_SLAVE, |
6a504a75 DP |
1528 | WM8995_AIF1_MSTR_MASK, master); |
1529 | return 0; | |
1530 | } | |
1531 | ||
1532 | static const int srs[] = { | |
1533 | 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, | |
1534 | 48000, 88200, 96000 | |
1535 | }; | |
1536 | ||
1537 | static const int fs_ratios[] = { | |
1538 | -1 /* reserved */, | |
1539 | 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 | |
1540 | }; | |
1541 | ||
1542 | static const int bclk_divs[] = { | |
1543 | 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480 | |
1544 | }; | |
1545 | ||
1546 | static int wm8995_hw_params(struct snd_pcm_substream *substream, | |
1547 | struct snd_pcm_hw_params *params, | |
1548 | struct snd_soc_dai *dai) | |
1549 | { | |
708ebb3b | 1550 | struct snd_soc_component *component; |
6a504a75 DP |
1551 | struct wm8995_priv *wm8995; |
1552 | int aif1_reg; | |
1553 | int bclk_reg; | |
1554 | int lrclk_reg; | |
1555 | int rate_reg; | |
1556 | int bclk_rate; | |
1557 | int aif1; | |
1558 | int lrclk, bclk; | |
1559 | int i, rate_val, best, best_val, cur_val; | |
1560 | ||
708ebb3b KM |
1561 | component = dai->component; |
1562 | wm8995 = snd_soc_component_get_drvdata(component); | |
6a504a75 DP |
1563 | |
1564 | switch (dai->id) { | |
1565 | case 0: | |
1566 | aif1_reg = WM8995_AIF1_CONTROL_1; | |
1567 | bclk_reg = WM8995_AIF1_BCLK; | |
1568 | rate_reg = WM8995_AIF1_RATE; | |
1569 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || | |
1570 | wm8995->lrclk_shared[0] */) { | |
1571 | lrclk_reg = WM8995_AIF1DAC_LRCLK; | |
1572 | } else { | |
1573 | lrclk_reg = WM8995_AIF1ADC_LRCLK; | |
708ebb3b | 1574 | dev_dbg(component->dev, "AIF1 using split LRCLK\n"); |
6a504a75 DP |
1575 | } |
1576 | break; | |
1577 | case 1: | |
1578 | aif1_reg = WM8995_AIF2_CONTROL_1; | |
1579 | bclk_reg = WM8995_AIF2_BCLK; | |
1580 | rate_reg = WM8995_AIF2_RATE; | |
1581 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || | |
1582 | wm8995->lrclk_shared[1] */) { | |
1583 | lrclk_reg = WM8995_AIF2DAC_LRCLK; | |
1584 | } else { | |
1585 | lrclk_reg = WM8995_AIF2ADC_LRCLK; | |
708ebb3b | 1586 | dev_dbg(component->dev, "AIF2 using split LRCLK\n"); |
6a504a75 DP |
1587 | } |
1588 | break; | |
1589 | default: | |
1590 | return -EINVAL; | |
1591 | } | |
1592 | ||
1593 | bclk_rate = snd_soc_params_to_bclk(params); | |
1594 | if (bclk_rate < 0) | |
1595 | return bclk_rate; | |
1596 | ||
1597 | aif1 = 0; | |
f882728c MB |
1598 | switch (params_width(params)) { |
1599 | case 16: | |
6a504a75 | 1600 | break; |
f882728c | 1601 | case 20: |
6a504a75 DP |
1602 | aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT); |
1603 | break; | |
f882728c | 1604 | case 24: |
6a504a75 DP |
1605 | aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT); |
1606 | break; | |
f882728c | 1607 | case 32: |
6a504a75 DP |
1608 | aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT); |
1609 | break; | |
1610 | default: | |
1611 | dev_err(dai->dev, "Unsupported word length %u\n", | |
f882728c | 1612 | params_width(params)); |
6a504a75 DP |
1613 | return -EINVAL; |
1614 | } | |
1615 | ||
1616 | /* try to find a suitable sample rate */ | |
1617 | for (i = 0; i < ARRAY_SIZE(srs); ++i) | |
1618 | if (srs[i] == params_rate(params)) | |
1619 | break; | |
1620 | if (i == ARRAY_SIZE(srs)) { | |
1621 | dev_err(dai->dev, "Sample rate %d is not supported\n", | |
1622 | params_rate(params)); | |
1623 | return -EINVAL; | |
1624 | } | |
1625 | rate_val = i << WM8995_AIF1_SR_SHIFT; | |
1626 | ||
1627 | dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]); | |
1628 | dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", | |
1629 | dai->id + 1, wm8995->aifclk[dai->id], bclk_rate); | |
1630 | ||
1631 | /* AIFCLK/fs ratio; look for a close match in either direction */ | |
1632 | best = 1; | |
1633 | best_val = abs((fs_ratios[1] * params_rate(params)) | |
1634 | - wm8995->aifclk[dai->id]); | |
1635 | for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) { | |
1636 | cur_val = abs((fs_ratios[i] * params_rate(params)) | |
1637 | - wm8995->aifclk[dai->id]); | |
1638 | if (cur_val >= best_val) | |
1639 | continue; | |
1640 | best = i; | |
1641 | best_val = cur_val; | |
1642 | } | |
1643 | rate_val |= best; | |
1644 | ||
1645 | dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", | |
1646 | dai->id + 1, fs_ratios[best]); | |
1647 | ||
1648 | /* | |
1649 | * We may not get quite the right frequency if using | |
1650 | * approximate clocks so look for the closest match that is | |
1651 | * higher than the target (we need to ensure that there enough | |
1652 | * BCLKs to clock out the samples). | |
1653 | */ | |
1654 | best = 0; | |
1655 | bclk = 0; | |
1656 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
1657 | cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate; | |
1658 | if (cur_val < 0) /* BCLK table is sorted */ | |
1659 | break; | |
1660 | best = i; | |
1661 | } | |
1662 | bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT; | |
1663 | ||
1664 | bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best]; | |
1665 | dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", | |
1666 | bclk_divs[best], bclk_rate); | |
1667 | ||
1668 | lrclk = bclk_rate / params_rate(params); | |
1669 | dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", | |
1670 | lrclk, bclk_rate / lrclk); | |
1671 | ||
708ebb3b | 1672 | snd_soc_component_update_bits(component, aif1_reg, |
6a504a75 | 1673 | WM8995_AIF1_WL_MASK, aif1); |
708ebb3b | 1674 | snd_soc_component_update_bits(component, bclk_reg, |
6a504a75 | 1675 | WM8995_AIF1_BCLK_DIV_MASK, bclk); |
708ebb3b | 1676 | snd_soc_component_update_bits(component, lrclk_reg, |
6a504a75 | 1677 | WM8995_AIF1DAC_RATE_MASK, lrclk); |
708ebb3b | 1678 | snd_soc_component_update_bits(component, rate_reg, |
6a504a75 DP |
1679 | WM8995_AIF1_SR_MASK | |
1680 | WM8995_AIF1CLK_RATE_MASK, rate_val); | |
1681 | return 0; | |
1682 | } | |
1683 | ||
1684 | static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate) | |
1685 | { | |
708ebb3b | 1686 | struct snd_soc_component *component = codec_dai->component; |
6a504a75 DP |
1687 | int reg, val, mask; |
1688 | ||
1689 | switch (codec_dai->id) { | |
1690 | case 0: | |
1691 | reg = WM8995_AIF1_MASTER_SLAVE; | |
1692 | mask = WM8995_AIF1_TRI; | |
1693 | break; | |
1694 | case 1: | |
1695 | reg = WM8995_AIF2_MASTER_SLAVE; | |
1696 | mask = WM8995_AIF2_TRI; | |
1697 | break; | |
1698 | case 2: | |
1699 | reg = WM8995_POWER_MANAGEMENT_5; | |
1700 | mask = WM8995_AIF3_TRI; | |
1701 | break; | |
1702 | default: | |
1703 | return -EINVAL; | |
1704 | } | |
1705 | ||
1706 | if (tristate) | |
1707 | val = mask; | |
1708 | else | |
1709 | val = 0; | |
1710 | ||
708ebb3b | 1711 | return snd_soc_component_update_bits(component, reg, mask, val); |
6a504a75 DP |
1712 | } |
1713 | ||
1714 | /* The size in bits of the FLL divide multiplied by 10 | |
1715 | * to allow rounding later */ | |
1716 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
1717 | ||
1718 | struct fll_div { | |
1719 | u16 outdiv; | |
1720 | u16 n; | |
1721 | u16 k; | |
1722 | u16 clk_ref_div; | |
1723 | u16 fll_fratio; | |
1724 | }; | |
1725 | ||
1726 | static int wm8995_get_fll_config(struct fll_div *fll, | |
1727 | int freq_in, int freq_out) | |
1728 | { | |
1729 | u64 Kpart; | |
1730 | unsigned int K, Ndiv, Nmod; | |
1731 | ||
1732 | pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); | |
1733 | ||
1734 | /* Scale the input frequency down to <= 13.5MHz */ | |
1735 | fll->clk_ref_div = 0; | |
1736 | while (freq_in > 13500000) { | |
1737 | fll->clk_ref_div++; | |
1738 | freq_in /= 2; | |
1739 | ||
1740 | if (fll->clk_ref_div > 3) | |
1741 | return -EINVAL; | |
1742 | } | |
1743 | pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); | |
1744 | ||
1745 | /* Scale the output to give 90MHz<=Fvco<=100MHz */ | |
1746 | fll->outdiv = 3; | |
1747 | while (freq_out * (fll->outdiv + 1) < 90000000) { | |
1748 | fll->outdiv++; | |
1749 | if (fll->outdiv > 63) | |
1750 | return -EINVAL; | |
1751 | } | |
1752 | freq_out *= fll->outdiv + 1; | |
1753 | pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); | |
1754 | ||
1755 | if (freq_in > 1000000) { | |
1756 | fll->fll_fratio = 0; | |
1757 | } else if (freq_in > 256000) { | |
1758 | fll->fll_fratio = 1; | |
1759 | freq_in *= 2; | |
1760 | } else if (freq_in > 128000) { | |
1761 | fll->fll_fratio = 2; | |
1762 | freq_in *= 4; | |
1763 | } else if (freq_in > 64000) { | |
1764 | fll->fll_fratio = 3; | |
1765 | freq_in *= 8; | |
1766 | } else { | |
1767 | fll->fll_fratio = 4; | |
1768 | freq_in *= 16; | |
1769 | } | |
1770 | pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); | |
1771 | ||
1772 | /* Now, calculate N.K */ | |
1773 | Ndiv = freq_out / freq_in; | |
1774 | ||
1775 | fll->n = Ndiv; | |
1776 | Nmod = freq_out % freq_in; | |
1777 | pr_debug("Nmod=%d\n", Nmod); | |
1778 | ||
1779 | /* Calculate fractional part - scale up so we can round. */ | |
1780 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
1781 | ||
1782 | do_div(Kpart, freq_in); | |
1783 | ||
1784 | K = Kpart & 0xFFFFFFFF; | |
1785 | ||
1786 | if ((K % 10) >= 5) | |
1787 | K += 5; | |
1788 | ||
1789 | /* Move down to proper range now rounding is done */ | |
1790 | fll->k = K / 10; | |
1791 | ||
1792 | pr_debug("N=%x K=%x\n", fll->n, fll->k); | |
1793 | ||
1794 | return 0; | |
1795 | } | |
1796 | ||
1797 | static int wm8995_set_fll(struct snd_soc_dai *dai, int id, | |
1798 | int src, unsigned int freq_in, | |
1799 | unsigned int freq_out) | |
1800 | { | |
708ebb3b | 1801 | struct snd_soc_component *component; |
6a504a75 DP |
1802 | struct wm8995_priv *wm8995; |
1803 | int reg_offset, ret; | |
1804 | struct fll_div fll; | |
1805 | u16 reg, aif1, aif2; | |
1806 | ||
708ebb3b KM |
1807 | component = dai->component; |
1808 | wm8995 = snd_soc_component_get_drvdata(component); | |
6a504a75 | 1809 | |
708ebb3b | 1810 | aif1 = snd_soc_component_read32(component, WM8995_AIF1_CLOCKING_1) |
6a504a75 DP |
1811 | & WM8995_AIF1CLK_ENA; |
1812 | ||
708ebb3b | 1813 | aif2 = snd_soc_component_read32(component, WM8995_AIF2_CLOCKING_1) |
6a504a75 DP |
1814 | & WM8995_AIF2CLK_ENA; |
1815 | ||
1816 | switch (id) { | |
1817 | case WM8995_FLL1: | |
1818 | reg_offset = 0; | |
1819 | id = 0; | |
1820 | break; | |
1821 | case WM8995_FLL2: | |
1822 | reg_offset = 0x20; | |
1823 | id = 1; | |
1824 | break; | |
1825 | default: | |
1826 | return -EINVAL; | |
1827 | } | |
1828 | ||
1829 | switch (src) { | |
1830 | case 0: | |
1831 | /* Allow no source specification when stopping */ | |
1832 | if (freq_out) | |
1833 | return -EINVAL; | |
1834 | break; | |
1835 | case WM8995_FLL_SRC_MCLK1: | |
1836 | case WM8995_FLL_SRC_MCLK2: | |
1837 | case WM8995_FLL_SRC_LRCLK: | |
1838 | case WM8995_FLL_SRC_BCLK: | |
1839 | break; | |
1840 | default: | |
1841 | return -EINVAL; | |
1842 | } | |
1843 | ||
1844 | /* Are we changing anything? */ | |
1845 | if (wm8995->fll[id].src == src && | |
1846 | wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out) | |
1847 | return 0; | |
1848 | ||
1849 | /* If we're stopping the FLL redo the old config - no | |
1850 | * registers will actually be written but we avoid GCC flow | |
1851 | * analysis bugs spewing warnings. | |
1852 | */ | |
1853 | if (freq_out) | |
1854 | ret = wm8995_get_fll_config(&fll, freq_in, freq_out); | |
1855 | else | |
1856 | ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in, | |
1857 | wm8995->fll[id].out); | |
1858 | if (ret < 0) | |
1859 | return ret; | |
1860 | ||
1861 | /* Gate the AIF clocks while we reclock */ | |
708ebb3b | 1862 | snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1, |
6a504a75 | 1863 | WM8995_AIF1CLK_ENA_MASK, 0); |
708ebb3b | 1864 | snd_soc_component_update_bits(component, WM8995_AIF2_CLOCKING_1, |
6a504a75 DP |
1865 | WM8995_AIF2CLK_ENA_MASK, 0); |
1866 | ||
1867 | /* We always need to disable the FLL while reconfiguring */ | |
708ebb3b | 1868 | snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset, |
6a504a75 DP |
1869 | WM8995_FLL1_ENA_MASK, 0); |
1870 | ||
1871 | reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) | | |
1872 | (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT); | |
708ebb3b | 1873 | snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_2 + reg_offset, |
6a504a75 DP |
1874 | WM8995_FLL1_OUTDIV_MASK | |
1875 | WM8995_FLL1_FRATIO_MASK, reg); | |
1876 | ||
708ebb3b | 1877 | snd_soc_component_write(component, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); |
6a504a75 | 1878 | |
708ebb3b | 1879 | snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_4 + reg_offset, |
6a504a75 DP |
1880 | WM8995_FLL1_N_MASK, |
1881 | fll.n << WM8995_FLL1_N_SHIFT); | |
1882 | ||
708ebb3b | 1883 | snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_5 + reg_offset, |
6a504a75 DP |
1884 | WM8995_FLL1_REFCLK_DIV_MASK | |
1885 | WM8995_FLL1_REFCLK_SRC_MASK, | |
1886 | (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) | | |
1887 | (src - 1)); | |
1888 | ||
1889 | if (freq_out) | |
708ebb3b | 1890 | snd_soc_component_update_bits(component, WM8995_FLL1_CONTROL_1 + reg_offset, |
6a504a75 DP |
1891 | WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA); |
1892 | ||
1893 | wm8995->fll[id].in = freq_in; | |
1894 | wm8995->fll[id].out = freq_out; | |
1895 | wm8995->fll[id].src = src; | |
1896 | ||
1897 | /* Enable any gated AIF clocks */ | |
708ebb3b | 1898 | snd_soc_component_update_bits(component, WM8995_AIF1_CLOCKING_1, |
6a504a75 | 1899 | WM8995_AIF1CLK_ENA_MASK, aif1); |
708ebb3b | 1900 | snd_soc_component_update_bits(component, WM8995_AIF2_CLOCKING_1, |
6a504a75 DP |
1901 | WM8995_AIF2CLK_ENA_MASK, aif2); |
1902 | ||
708ebb3b | 1903 | configure_clock(component); |
6a504a75 DP |
1904 | |
1905 | return 0; | |
1906 | } | |
1907 | ||
1908 | static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai, | |
1909 | int clk_id, unsigned int freq, int dir) | |
1910 | { | |
708ebb3b | 1911 | struct snd_soc_component *component; |
6a504a75 DP |
1912 | struct wm8995_priv *wm8995; |
1913 | ||
708ebb3b KM |
1914 | component = dai->component; |
1915 | wm8995 = snd_soc_component_get_drvdata(component); | |
6a504a75 DP |
1916 | |
1917 | switch (dai->id) { | |
1918 | case 0: | |
1919 | case 1: | |
1920 | break; | |
1921 | default: | |
1922 | /* AIF3 shares clocking with AIF1/2 */ | |
1923 | return -EINVAL; | |
1924 | } | |
1925 | ||
1926 | switch (clk_id) { | |
1927 | case WM8995_SYSCLK_MCLK1: | |
1928 | wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; | |
1929 | wm8995->mclk[0] = freq; | |
1930 | dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", | |
1931 | dai->id + 1, freq); | |
1932 | break; | |
1933 | case WM8995_SYSCLK_MCLK2: | |
fcd9d310 | 1934 | wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK2; |
6a504a75 DP |
1935 | wm8995->mclk[1] = freq; |
1936 | dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", | |
1937 | dai->id + 1, freq); | |
1938 | break; | |
1939 | case WM8995_SYSCLK_FLL1: | |
1940 | wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1; | |
1941 | dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1); | |
1942 | break; | |
1943 | case WM8995_SYSCLK_FLL2: | |
1944 | wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2; | |
1945 | dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1); | |
1946 | break; | |
1947 | case WM8995_SYSCLK_OPCLK: | |
1948 | default: | |
1949 | dev_err(dai->dev, "Unknown clock source %d\n", clk_id); | |
1950 | return -EINVAL; | |
1951 | } | |
1952 | ||
708ebb3b | 1953 | configure_clock(component); |
6a504a75 DP |
1954 | |
1955 | return 0; | |
1956 | } | |
1957 | ||
708ebb3b | 1958 | static int wm8995_set_bias_level(struct snd_soc_component *component, |
6a504a75 DP |
1959 | enum snd_soc_bias_level level) |
1960 | { | |
1961 | struct wm8995_priv *wm8995; | |
1962 | int ret; | |
1963 | ||
708ebb3b | 1964 | wm8995 = snd_soc_component_get_drvdata(component); |
6a504a75 DP |
1965 | switch (level) { |
1966 | case SND_SOC_BIAS_ON: | |
1967 | case SND_SOC_BIAS_PREPARE: | |
1968 | break; | |
1969 | case SND_SOC_BIAS_STANDBY: | |
708ebb3b | 1970 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
219d8df8 DP |
1971 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies), |
1972 | wm8995->supplies); | |
1973 | if (ret) | |
1974 | return ret; | |
1975 | ||
c42da642 | 1976 | ret = regcache_sync(wm8995->regmap); |
6a504a75 | 1977 | if (ret) { |
708ebb3b | 1978 | dev_err(component->dev, |
6a504a75 DP |
1979 | "Failed to sync cache: %d\n", ret); |
1980 | return ret; | |
1981 | } | |
1982 | ||
708ebb3b | 1983 | snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1, |
6a504a75 | 1984 | WM8995_BG_ENA_MASK, WM8995_BG_ENA); |
6a504a75 DP |
1985 | } |
1986 | break; | |
1987 | case SND_SOC_BIAS_OFF: | |
708ebb3b | 1988 | snd_soc_component_update_bits(component, WM8995_POWER_MANAGEMENT_1, |
6a504a75 | 1989 | WM8995_BG_ENA_MASK, 0); |
219d8df8 DP |
1990 | regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), |
1991 | wm8995->supplies); | |
6a504a75 DP |
1992 | break; |
1993 | } | |
1994 | ||
6a504a75 DP |
1995 | return 0; |
1996 | } | |
1997 | ||
708ebb3b | 1998 | static int wm8995_probe(struct snd_soc_component *component) |
6a504a75 DP |
1999 | { |
2000 | struct wm8995_priv *wm8995; | |
219d8df8 | 2001 | int i; |
6a504a75 DP |
2002 | int ret; |
2003 | ||
708ebb3b KM |
2004 | wm8995 = snd_soc_component_get_drvdata(component); |
2005 | wm8995->component = component; | |
6a504a75 | 2006 | |
219d8df8 DP |
2007 | for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) |
2008 | wm8995->supplies[i].supply = wm8995_supply_names[i]; | |
2009 | ||
0bb423f2 GL |
2010 | ret = devm_regulator_bulk_get(component->dev, |
2011 | ARRAY_SIZE(wm8995->supplies), | |
2012 | wm8995->supplies); | |
219d8df8 | 2013 | if (ret) { |
708ebb3b | 2014 | dev_err(component->dev, "Failed to request supplies: %d\n", ret); |
219d8df8 DP |
2015 | return ret; |
2016 | } | |
2017 | ||
2018 | wm8995->disable_nb[0].notifier_call = wm8995_regulator_event_0; | |
2019 | wm8995->disable_nb[1].notifier_call = wm8995_regulator_event_1; | |
2020 | wm8995->disable_nb[2].notifier_call = wm8995_regulator_event_2; | |
2021 | wm8995->disable_nb[3].notifier_call = wm8995_regulator_event_3; | |
2022 | wm8995->disable_nb[4].notifier_call = wm8995_regulator_event_4; | |
2023 | wm8995->disable_nb[5].notifier_call = wm8995_regulator_event_5; | |
2024 | wm8995->disable_nb[6].notifier_call = wm8995_regulator_event_6; | |
2025 | wm8995->disable_nb[7].notifier_call = wm8995_regulator_event_7; | |
2026 | ||
2027 | /* This should really be moved into the regulator core */ | |
2028 | for (i = 0; i < ARRAY_SIZE(wm8995->supplies); i++) { | |
0bb423f2 GL |
2029 | ret = devm_regulator_register_notifier( |
2030 | wm8995->supplies[i].consumer, | |
2031 | &wm8995->disable_nb[i]); | |
219d8df8 | 2032 | if (ret) { |
708ebb3b | 2033 | dev_err(component->dev, |
219d8df8 DP |
2034 | "Failed to register regulator notifier: %d\n", |
2035 | ret); | |
2036 | } | |
2037 | } | |
2038 | ||
2039 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8995->supplies), | |
2040 | wm8995->supplies); | |
2041 | if (ret) { | |
708ebb3b | 2042 | dev_err(component->dev, "Failed to enable supplies: %d\n", ret); |
0bb423f2 | 2043 | return ret; |
219d8df8 DP |
2044 | } |
2045 | ||
708ebb3b | 2046 | ret = snd_soc_component_read32(component, WM8995_SOFTWARE_RESET); |
6a504a75 | 2047 | if (ret < 0) { |
708ebb3b | 2048 | dev_err(component->dev, "Failed to read device ID: %d\n", ret); |
219d8df8 | 2049 | goto err_reg_enable; |
6a504a75 DP |
2050 | } |
2051 | ||
2052 | if (ret != 0x8995) { | |
708ebb3b | 2053 | dev_err(component->dev, "Invalid device ID: %#x\n", ret); |
6fa0c25b | 2054 | ret = -EINVAL; |
219d8df8 | 2055 | goto err_reg_enable; |
6a504a75 DP |
2056 | } |
2057 | ||
708ebb3b | 2058 | ret = snd_soc_component_write(component, WM8995_SOFTWARE_RESET, 0); |
6a504a75 | 2059 | if (ret < 0) { |
708ebb3b | 2060 | dev_err(component->dev, "Failed to issue reset: %d\n", ret); |
219d8df8 | 2061 | goto err_reg_enable; |
6a504a75 DP |
2062 | } |
2063 | ||
6a504a75 | 2064 | /* Latch volume updates (right only; we always do left then right). */ |
708ebb3b | 2065 | snd_soc_component_update_bits(component, WM8995_AIF1_DAC1_RIGHT_VOLUME, |
6a504a75 | 2066 | WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU); |
708ebb3b | 2067 | snd_soc_component_update_bits(component, WM8995_AIF1_DAC2_RIGHT_VOLUME, |
6a504a75 | 2068 | WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU); |
708ebb3b | 2069 | snd_soc_component_update_bits(component, WM8995_AIF2_DAC_RIGHT_VOLUME, |
6a504a75 | 2070 | WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU); |
708ebb3b | 2071 | snd_soc_component_update_bits(component, WM8995_AIF1_ADC1_RIGHT_VOLUME, |
6a504a75 | 2072 | WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU); |
708ebb3b | 2073 | snd_soc_component_update_bits(component, WM8995_AIF1_ADC2_RIGHT_VOLUME, |
6a504a75 | 2074 | WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU); |
708ebb3b | 2075 | snd_soc_component_update_bits(component, WM8995_AIF2_ADC_RIGHT_VOLUME, |
6a504a75 | 2076 | WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU); |
708ebb3b | 2077 | snd_soc_component_update_bits(component, WM8995_DAC1_RIGHT_VOLUME, |
6a504a75 | 2078 | WM8995_DAC1_VU_MASK, WM8995_DAC1_VU); |
708ebb3b | 2079 | snd_soc_component_update_bits(component, WM8995_DAC2_RIGHT_VOLUME, |
6a504a75 | 2080 | WM8995_DAC2_VU_MASK, WM8995_DAC2_VU); |
708ebb3b | 2081 | snd_soc_component_update_bits(component, WM8995_RIGHT_LINE_INPUT_1_VOLUME, |
6a504a75 DP |
2082 | WM8995_IN1_VU_MASK, WM8995_IN1_VU); |
2083 | ||
708ebb3b | 2084 | wm8995_update_class_w(component); |
6a504a75 | 2085 | |
6a504a75 | 2086 | return 0; |
219d8df8 DP |
2087 | |
2088 | err_reg_enable: | |
2089 | regulator_bulk_disable(ARRAY_SIZE(wm8995->supplies), wm8995->supplies); | |
219d8df8 | 2090 | return ret; |
6a504a75 DP |
2091 | } |
2092 | ||
2093 | #define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
2094 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
2095 | ||
85e7652d | 2096 | static const struct snd_soc_dai_ops wm8995_aif1_dai_ops = { |
6a504a75 DP |
2097 | .set_sysclk = wm8995_set_dai_sysclk, |
2098 | .set_fmt = wm8995_set_dai_fmt, | |
2099 | .hw_params = wm8995_hw_params, | |
2100 | .digital_mute = wm8995_aif_mute, | |
2101 | .set_pll = wm8995_set_fll, | |
2102 | .set_tristate = wm8995_set_tristate, | |
2103 | }; | |
2104 | ||
85e7652d | 2105 | static const struct snd_soc_dai_ops wm8995_aif2_dai_ops = { |
6a504a75 DP |
2106 | .set_sysclk = wm8995_set_dai_sysclk, |
2107 | .set_fmt = wm8995_set_dai_fmt, | |
2108 | .hw_params = wm8995_hw_params, | |
2109 | .digital_mute = wm8995_aif_mute, | |
2110 | .set_pll = wm8995_set_fll, | |
2111 | .set_tristate = wm8995_set_tristate, | |
2112 | }; | |
2113 | ||
85e7652d | 2114 | static const struct snd_soc_dai_ops wm8995_aif3_dai_ops = { |
6a504a75 DP |
2115 | .set_tristate = wm8995_set_tristate, |
2116 | }; | |
2117 | ||
2118 | static struct snd_soc_dai_driver wm8995_dai[] = { | |
2119 | { | |
2120 | .name = "wm8995-aif1", | |
2121 | .playback = { | |
2122 | .stream_name = "AIF1 Playback", | |
2123 | .channels_min = 2, | |
2124 | .channels_max = 2, | |
2125 | .rates = SNDRV_PCM_RATE_8000_96000, | |
2126 | .formats = WM8995_FORMATS | |
2127 | }, | |
2128 | .capture = { | |
2129 | .stream_name = "AIF1 Capture", | |
2130 | .channels_min = 2, | |
2131 | .channels_max = 2, | |
2132 | .rates = SNDRV_PCM_RATE_8000_48000, | |
2133 | .formats = WM8995_FORMATS | |
2134 | }, | |
2135 | .ops = &wm8995_aif1_dai_ops | |
2136 | }, | |
2137 | { | |
2138 | .name = "wm8995-aif2", | |
2139 | .playback = { | |
2140 | .stream_name = "AIF2 Playback", | |
2141 | .channels_min = 2, | |
2142 | .channels_max = 2, | |
2143 | .rates = SNDRV_PCM_RATE_8000_96000, | |
2144 | .formats = WM8995_FORMATS | |
2145 | }, | |
2146 | .capture = { | |
2147 | .stream_name = "AIF2 Capture", | |
2148 | .channels_min = 2, | |
2149 | .channels_max = 2, | |
2150 | .rates = SNDRV_PCM_RATE_8000_48000, | |
2151 | .formats = WM8995_FORMATS | |
2152 | }, | |
2153 | .ops = &wm8995_aif2_dai_ops | |
2154 | }, | |
2155 | { | |
2156 | .name = "wm8995-aif3", | |
2157 | .playback = { | |
2158 | .stream_name = "AIF3 Playback", | |
2159 | .channels_min = 2, | |
2160 | .channels_max = 2, | |
2161 | .rates = SNDRV_PCM_RATE_8000_96000, | |
2162 | .formats = WM8995_FORMATS | |
2163 | }, | |
2164 | .capture = { | |
2165 | .stream_name = "AIF3 Capture", | |
2166 | .channels_min = 2, | |
2167 | .channels_max = 2, | |
2168 | .rates = SNDRV_PCM_RATE_8000_48000, | |
2169 | .formats = WM8995_FORMATS | |
2170 | }, | |
2171 | .ops = &wm8995_aif3_dai_ops | |
2172 | } | |
2173 | }; | |
2174 | ||
708ebb3b KM |
2175 | static const struct snd_soc_component_driver soc_component_dev_wm8995 = { |
2176 | .probe = wm8995_probe, | |
708ebb3b KM |
2177 | .set_bias_level = wm8995_set_bias_level, |
2178 | .controls = wm8995_snd_controls, | |
2179 | .num_controls = ARRAY_SIZE(wm8995_snd_controls), | |
2180 | .dapm_widgets = wm8995_dapm_widgets, | |
2181 | .num_dapm_widgets = ARRAY_SIZE(wm8995_dapm_widgets), | |
2182 | .dapm_routes = wm8995_intercon, | |
2183 | .num_dapm_routes = ARRAY_SIZE(wm8995_intercon), | |
2184 | .use_pmdown_time = 1, | |
2185 | .endianness = 1, | |
2186 | .non_legacy_dai_naming = 1, | |
c42da642 MB |
2187 | }; |
2188 | ||
27ad02f3 | 2189 | static const struct regmap_config wm8995_regmap = { |
c42da642 MB |
2190 | .reg_bits = 16, |
2191 | .val_bits = 16, | |
2192 | ||
2193 | .max_register = WM8995_MAX_REGISTER, | |
2194 | .reg_defaults = wm8995_reg_defaults, | |
2195 | .num_reg_defaults = ARRAY_SIZE(wm8995_reg_defaults), | |
2196 | .volatile_reg = wm8995_volatile, | |
2197 | .readable_reg = wm8995_readable, | |
2198 | .cache_type = REGCACHE_RBTREE, | |
6a504a75 DP |
2199 | }; |
2200 | ||
2201 | #if defined(CONFIG_SPI_MASTER) | |
7a79e94e | 2202 | static int wm8995_spi_probe(struct spi_device *spi) |
6a504a75 DP |
2203 | { |
2204 | struct wm8995_priv *wm8995; | |
2205 | int ret; | |
2206 | ||
d5ff3c8a | 2207 | wm8995 = devm_kzalloc(&spi->dev, sizeof(*wm8995), GFP_KERNEL); |
6a504a75 DP |
2208 | if (!wm8995) |
2209 | return -ENOMEM; | |
2210 | ||
6a504a75 DP |
2211 | spi_set_drvdata(spi, wm8995); |
2212 | ||
d2d1fe90 | 2213 | wm8995->regmap = devm_regmap_init_spi(spi, &wm8995_regmap); |
c42da642 MB |
2214 | if (IS_ERR(wm8995->regmap)) { |
2215 | ret = PTR_ERR(wm8995->regmap); | |
2216 | dev_err(&spi->dev, "Failed to register regmap: %d\n", ret); | |
d5ff3c8a | 2217 | return ret; |
c42da642 MB |
2218 | } |
2219 | ||
708ebb3b KM |
2220 | ret = devm_snd_soc_register_component(&spi->dev, |
2221 | &soc_component_dev_wm8995, wm8995_dai, | |
6a504a75 | 2222 | ARRAY_SIZE(wm8995_dai)); |
6a504a75 DP |
2223 | return ret; |
2224 | } | |
2225 | ||
6a504a75 DP |
2226 | static struct spi_driver wm8995_spi_driver = { |
2227 | .driver = { | |
2228 | .name = "wm8995", | |
6a504a75 DP |
2229 | }, |
2230 | .probe = wm8995_spi_probe, | |
6a504a75 DP |
2231 | }; |
2232 | #endif | |
2233 | ||
d44008b3 | 2234 | #if IS_ENABLED(CONFIG_I2C) |
7a79e94e BP |
2235 | static int wm8995_i2c_probe(struct i2c_client *i2c, |
2236 | const struct i2c_device_id *id) | |
6a504a75 DP |
2237 | { |
2238 | struct wm8995_priv *wm8995; | |
2239 | int ret; | |
2240 | ||
d5ff3c8a | 2241 | wm8995 = devm_kzalloc(&i2c->dev, sizeof(*wm8995), GFP_KERNEL); |
6a504a75 DP |
2242 | if (!wm8995) |
2243 | return -ENOMEM; | |
2244 | ||
6a504a75 DP |
2245 | i2c_set_clientdata(i2c, wm8995); |
2246 | ||
d2d1fe90 | 2247 | wm8995->regmap = devm_regmap_init_i2c(i2c, &wm8995_regmap); |
c42da642 MB |
2248 | if (IS_ERR(wm8995->regmap)) { |
2249 | ret = PTR_ERR(wm8995->regmap); | |
2250 | dev_err(&i2c->dev, "Failed to register regmap: %d\n", ret); | |
d5ff3c8a | 2251 | return ret; |
c42da642 MB |
2252 | } |
2253 | ||
708ebb3b KM |
2254 | ret = devm_snd_soc_register_component(&i2c->dev, |
2255 | &soc_component_dev_wm8995, wm8995_dai, | |
6a504a75 | 2256 | ARRAY_SIZE(wm8995_dai)); |
d2d1fe90 | 2257 | if (ret < 0) |
c42da642 | 2258 | dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret); |
c42da642 | 2259 | |
6a504a75 DP |
2260 | return ret; |
2261 | } | |
2262 | ||
6a504a75 DP |
2263 | static const struct i2c_device_id wm8995_i2c_id[] = { |
2264 | {"wm8995", 0}, | |
2265 | {} | |
2266 | }; | |
2267 | ||
2268 | MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id); | |
2269 | ||
2270 | static struct i2c_driver wm8995_i2c_driver = { | |
2271 | .driver = { | |
2272 | .name = "wm8995", | |
6a504a75 DP |
2273 | }, |
2274 | .probe = wm8995_i2c_probe, | |
6a504a75 DP |
2275 | .id_table = wm8995_i2c_id |
2276 | }; | |
2277 | #endif | |
2278 | ||
2279 | static int __init wm8995_modinit(void) | |
2280 | { | |
2281 | int ret = 0; | |
2282 | ||
d44008b3 | 2283 | #if IS_ENABLED(CONFIG_I2C) |
6a504a75 DP |
2284 | ret = i2c_add_driver(&wm8995_i2c_driver); |
2285 | if (ret) { | |
2286 | printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n", | |
2287 | ret); | |
2288 | } | |
2289 | #endif | |
2290 | #if defined(CONFIG_SPI_MASTER) | |
2291 | ret = spi_register_driver(&wm8995_spi_driver); | |
2292 | if (ret) { | |
2293 | printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n", | |
2294 | ret); | |
2295 | } | |
2296 | #endif | |
2297 | return ret; | |
2298 | } | |
2299 | ||
2300 | module_init(wm8995_modinit); | |
2301 | ||
2302 | static void __exit wm8995_exit(void) | |
2303 | { | |
d44008b3 | 2304 | #if IS_ENABLED(CONFIG_I2C) |
6a504a75 DP |
2305 | i2c_del_driver(&wm8995_i2c_driver); |
2306 | #endif | |
2307 | #if defined(CONFIG_SPI_MASTER) | |
2308 | spi_unregister_driver(&wm8995_spi_driver); | |
2309 | #endif | |
2310 | } | |
2311 | ||
2312 | module_exit(wm8995_exit); | |
2313 | ||
2314 | MODULE_DESCRIPTION("ASoC WM8995 driver"); | |
2315 | MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>"); | |
2316 | MODULE_LICENSE("GPL"); |