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ASoC: Handle failed WM8994 FLL lock waits
[linux-2.6-block.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
9e6e96a1
MB		 41#define WM8994_NUM_DRC 3
42#define WM8994_NUM_EQ 3
43
44static int wm8994_drc_base[] = {
45 WM8994_AIF1_DRC1_1,
46 WM8994_AIF1_DRC2_1,
47 WM8994_AIF2_DRC_1,
48};
49
50static int wm8994_retune_mobile_base[] = {
51 WM8994_AIF1_DAC1_EQ_GAINS_1,
52 WM8994_AIF1_DAC2_EQ_GAINS_1,
53 WM8994_AIF2_EQ_GAINS_1,
54};
55
d4754ec9 56static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
9e6e96a1 57{
af9af866
MB		 58 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
59 struct wm8994 *control = wm8994->control_data;
60
e88ff1e6
MB		 61 switch (reg) {
62 case WM8994_GPIO_1:
63 case WM8994_GPIO_2:
64 case WM8994_GPIO_3:
65 case WM8994_GPIO_4:
66 case WM8994_GPIO_5:
67 case WM8994_GPIO_6:
68 case WM8994_GPIO_7:
69 case WM8994_GPIO_8:
70 case WM8994_GPIO_9:
71 case WM8994_GPIO_10:
72 case WM8994_GPIO_11:
73 case WM8994_INTERRUPT_STATUS_1:
74 case WM8994_INTERRUPT_STATUS_2:
75 case WM8994_INTERRUPT_RAW_STATUS_2:
76 return 1;
af9af866
MB		 77
78 case WM8958_DSP2_PROGRAM:
79 case WM8958_DSP2_CONFIG:
80 case WM8958_DSP2_EXECCONTROL:
81 if (control->type == WM8958)
82 return 1;
83 else
84 return 0;
85
e88ff1e6
MB		 86 default:
87 break;
88 }
89
7b306dae 90 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1 91 return 0;
7b306dae 92 return wm8994_access_masks[reg].readable != 0;
9e6e96a1
MB		 93}
94
d4754ec9 95static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
9e6e96a1 96{
ca9aef50 97 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1
MB		 98 return 1;
99
100 switch (reg) {
101 case WM8994_SOFTWARE_RESET:
102 case WM8994_CHIP_REVISION:
103 case WM8994_DC_SERVO_1:
104 case WM8994_DC_SERVO_READBACK:
105 case WM8994_RATE_STATUS:
106 case WM8994_LDO_1:
107 case WM8994_LDO_2:
d6addcc9 108 case WM8958_DSP2_EXECCONTROL:
821edd2f 109 case WM8958_MIC_DETECT_3:
9e6e96a1
MB		 110 return 1;
111 default:
112 return 0;
113 }
114}
115
116static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
117 unsigned int value)
118{
ca9aef50 119 int ret;
9e6e96a1
MB		 120
121 BUG_ON(reg > WM8994_MAX_REGISTER);
122
d4754ec9 123 if (!wm8994_volatile(codec, reg)) {
ca9aef50
MB		 124 ret = snd_soc_cache_write(codec, reg, value);
125 if (ret != 0)
126 dev_err(codec->dev, "Cache write to %x failed: %d\n",
127 reg, ret);
128 }
9e6e96a1
MB		 129
130 return wm8994_reg_write(codec->control_data, reg, value);
131}
132
133static unsigned int wm8994_read(struct snd_soc_codec *codec,
134 unsigned int reg)
135{
ca9aef50
MB		 136 unsigned int val;
137 int ret;
9e6e96a1
MB		 138
139 BUG_ON(reg > WM8994_MAX_REGISTER);
140
d4754ec9 141 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
ca9aef50
MB		 142 reg < codec->driver->reg_cache_size) {
143 ret = snd_soc_cache_read(codec, reg, &val);
144 if (ret >= 0)
145 return val;
146 else
147 dev_err(codec->dev, "Cache read from %x failed: %d\n",
148 reg, ret);
149 }
150
151 return wm8994_reg_read(codec->control_data, reg);
9e6e96a1
MB		 152}
153
154static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
155{
b2c812e2 156 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 157 int rate;
158 int reg1 = 0;
159 int offset;
160
161 if (aif)
162 offset = 4;
163 else
164 offset = 0;
165
166 switch (wm8994->sysclk[aif]) {
167 case WM8994_SYSCLK_MCLK1:
168 rate = wm8994->mclk[0];
169 break;
170
171 case WM8994_SYSCLK_MCLK2:
172 reg1 |= 0x8;
173 rate = wm8994->mclk[1];
174 break;
175
176 case WM8994_SYSCLK_FLL1:
177 reg1 |= 0x10;
178 rate = wm8994->fll[0].out;
179 break;
180
181 case WM8994_SYSCLK_FLL2:
182 reg1 |= 0x18;
183 rate = wm8994->fll[1].out;
184 break;
185
186 default:
187 return -EINVAL;
188 }
189
190 if (rate >= 13500000) {
191 rate /= 2;
192 reg1 |= WM8994_AIF1CLK_DIV;
193
194 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
195 aif + 1, rate);
196 }
5e5e2bef 197
9e6e96a1
MB		 198 wm8994->aifclk[aif] = rate;
199
200 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
201 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
202 reg1);
203
204 return 0;
205}
206
207static int configure_clock(struct snd_soc_codec *codec)
208{
b2c812e2 209 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 210 int old, new;
211
212 /* Bring up the AIF clocks first */
213 configure_aif_clock(codec, 0);
214 configure_aif_clock(codec, 1);
215
216 /* Then switch CLK_SYS over to the higher of them; a change
217 * can only happen as a result of a clocking change which can
218 * only be made outside of DAPM so we can safely redo the
219 * clocking.
220 */
221
222 /* If they're equal it doesn't matter which is used */
223 if (wm8994->aifclk[0] == wm8994->aifclk[1])
224 return 0;
225
226 if (wm8994->aifclk[0] < wm8994->aifclk[1])
227 new = WM8994_SYSCLK_SRC;
228 else
229 new = 0;
230
231 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
232
233 /* If there's no change then we're done. */
234 if (old == new)
235 return 0;
236
237 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
238
ce6120cc 239 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1
MB		 240
241 return 0;
242}
243
244static int check_clk_sys(struct snd_soc_dapm_widget *source,
245 struct snd_soc_dapm_widget *sink)
246{
247 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
248 const char *clk;
249
250 /* Check what we're currently using for CLK_SYS */
251 if (reg & WM8994_SYSCLK_SRC)
252 clk = "AIF2CLK";
253 else
254 clk = "AIF1CLK";
255
256 return strcmp(source->name, clk) == 0;
257}
258
259static const char *sidetone_hpf_text[] = {
260 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
261};
262
263static const struct soc_enum sidetone_hpf =
264 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
265
146fd574
UK		 266static const char *adc_hpf_text[] = {
267 "HiFi", "Voice 1", "Voice 2", "Voice 3"
268};
269
270static const struct soc_enum aif1adc1_hpf =
271 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
272
273static const struct soc_enum aif1adc2_hpf =
274 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
275
276static const struct soc_enum aif2adc_hpf =
277 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
278
9e6e96a1
MB		 279static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
280static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
281static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
282static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
283static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
284
285#define WM8994_DRC_SWITCH(xname, reg, shift) \
286{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
287 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
288 .put = wm8994_put_drc_sw, \
289 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
290
291static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
292 struct snd_ctl_elem_value *ucontrol)
293{
294 struct soc_mixer_control *mc =
295 (struct soc_mixer_control *)kcontrol->private_value;
296 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
297 int mask, ret;
298
299 /* Can't enable both ADC and DAC paths simultaneously */
300 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
301 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
302 WM8994_AIF1ADC1R_DRC_ENA_MASK;
303 else
304 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
305
306 ret = snd_soc_read(codec, mc->reg);
307 if (ret < 0)
308 return ret;
309 if (ret & mask)
310 return -EINVAL;
311
312 return snd_soc_put_volsw(kcontrol, ucontrol);
313}
314
9e6e96a1
MB		 315static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
316{
b2c812e2 317 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 318 struct wm8994_pdata *pdata = wm8994->pdata;
319 int base = wm8994_drc_base[drc];
320 int cfg = wm8994->drc_cfg[drc];
321 int save, i;
322
323 /* Save any enables; the configuration should clear them. */
324 save = snd_soc_read(codec, base);
325 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
326 WM8994_AIF1ADC1R_DRC_ENA;
327
328 for (i = 0; i < WM8994_DRC_REGS; i++)
329 snd_soc_update_bits(codec, base + i, 0xffff,
330 pdata->drc_cfgs[cfg].regs[i]);
331
332 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
333 WM8994_AIF1ADC1L_DRC_ENA |
334 WM8994_AIF1ADC1R_DRC_ENA, save);
335}
336
337/* Icky as hell but saves code duplication */
338static int wm8994_get_drc(const char *name)
339{
340 if (strcmp(name, "AIF1DRC1 Mode") == 0)
341 return 0;
342 if (strcmp(name, "AIF1DRC2 Mode") == 0)
343 return 1;
344 if (strcmp(name, "AIF2DRC Mode") == 0)
345 return 2;
346 return -EINVAL;
347}
348
349static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
350 struct snd_ctl_elem_value *ucontrol)
351{
352 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 353 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 354 struct wm8994_pdata *pdata = wm8994->pdata;
355 int drc = wm8994_get_drc(kcontrol->id.name);
356 int value = ucontrol->value.integer.value[0];
357
358 if (drc < 0)
359 return drc;
360
361 if (value >= pdata->num_drc_cfgs)
362 return -EINVAL;
363
364 wm8994->drc_cfg[drc] = value;
365
366 wm8994_set_drc(codec, drc);
367
368 return 0;
369}
370
371static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
372 struct snd_ctl_elem_value *ucontrol)
373{
374 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 375 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 376 int drc = wm8994_get_drc(kcontrol->id.name);
377
378 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
379
380 return 0;
381}
382
383static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
384{
b2c812e2 385 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 386 struct wm8994_pdata *pdata = wm8994->pdata;
387 int base = wm8994_retune_mobile_base[block];
388 int iface, best, best_val, save, i, cfg;
389
390 if (!pdata || !wm8994->num_retune_mobile_texts)
391 return;
392
393 switch (block) {
394 case 0:
395 case 1:
396 iface = 0;
397 break;
398 case 2:
399 iface = 1;
400 break;
401 default:
402 return;
403 }
404
405 /* Find the version of the currently selected configuration
406 * with the nearest sample rate. */
407 cfg = wm8994->retune_mobile_cfg[block];
408 best = 0;
409 best_val = INT_MAX;
410 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
411 if (strcmp(pdata->retune_mobile_cfgs[i].name,
412 wm8994->retune_mobile_texts[cfg]) == 0 &&
413 abs(pdata->retune_mobile_cfgs[i].rate
414 - wm8994->dac_rates[iface]) < best_val) {
415 best = i;
416 best_val = abs(pdata->retune_mobile_cfgs[i].rate
417 - wm8994->dac_rates[iface]);
418 }
419 }
420
421 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
422 block,
423 pdata->retune_mobile_cfgs[best].name,
424 pdata->retune_mobile_cfgs[best].rate,
425 wm8994->dac_rates[iface]);
426
427 /* The EQ will be disabled while reconfiguring it, remember the
428 * current configuration.
429 */
430 save = snd_soc_read(codec, base);
431 save &= WM8994_AIF1DAC1_EQ_ENA;
432
433 for (i = 0; i < WM8994_EQ_REGS; i++)
434 snd_soc_update_bits(codec, base + i, 0xffff,
435 pdata->retune_mobile_cfgs[best].regs[i]);
436
437 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
438}
439
440/* Icky as hell but saves code duplication */
441static int wm8994_get_retune_mobile_block(const char *name)
442{
443 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
444 return 0;
445 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
446 return 1;
447 if (strcmp(name, "AIF2 EQ Mode") == 0)
448 return 2;
449 return -EINVAL;
450}
451
452static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
453 struct snd_ctl_elem_value *ucontrol)
454{
455 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 456 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 457 struct wm8994_pdata *pdata = wm8994->pdata;
458 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
459 int value = ucontrol->value.integer.value[0];
460
461 if (block < 0)
462 return block;
463
464 if (value >= pdata->num_retune_mobile_cfgs)
465 return -EINVAL;
466
467 wm8994->retune_mobile_cfg[block] = value;
468
469 wm8994_set_retune_mobile(codec, block);
470
471 return 0;
472}
473
474static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
475 struct snd_ctl_elem_value *ucontrol)
476{
477 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 478 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 479 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
480
481 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
482
483 return 0;
484}
485
96b101ef 486static const char *aif_chan_src_text[] = {
f554885f
MB		 487 "Left", "Right"
488};
489
96b101ef
MB		 490static const struct soc_enum aif1adcl_src =
491 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
492
493static const struct soc_enum aif1adcr_src =
494 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
495
496static const struct soc_enum aif2adcl_src =
497 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
498
499static const struct soc_enum aif2adcr_src =
500 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
501
f554885f 502static const struct soc_enum aif1dacl_src =
96b101ef 503 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 504
505static const struct soc_enum aif1dacr_src =
96b101ef 506 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 507
508static const struct soc_enum aif2dacl_src =
96b101ef 509 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 510
511static const struct soc_enum aif2dacr_src =
96b101ef 512 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 513
154b26aa
MB		 514static const char *osr_text[] = {
515 "Low Power", "High Performance",
516};
517
518static const struct soc_enum dac_osr =
519 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
520
521static const struct soc_enum adc_osr =
522 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
523
9e6e96a1
MB		 524static const struct snd_kcontrol_new wm8994_snd_controls[] = {
525SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
526 WM8994_AIF1_ADC1_RIGHT_VOLUME,
527 1, 119, 0, digital_tlv),
528SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
529 WM8994_AIF1_ADC2_RIGHT_VOLUME,
530 1, 119, 0, digital_tlv),
531SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
532 WM8994_AIF2_ADC_RIGHT_VOLUME,
533 1, 119, 0, digital_tlv),
534
96b101ef
MB		 535SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
536SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 537SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
538SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 539
f554885f
MB		 540SOC_ENUM("AIF1DACL Source", aif1dacl_src),
541SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 542SOC_ENUM("AIF2DACL Source", aif2dacl_src),
543SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 544
9e6e96a1
MB		 545SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
546 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
547SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
548 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
549SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
550 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
551
552SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
553SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
554
555SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
556SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
557SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
558
559WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
560WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
561WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
562
563WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
564WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
565WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
566
567WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
568WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
569WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
570
571SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
572 5, 12, 0, st_tlv),
573SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
574 0, 12, 0, st_tlv),
575SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
576 5, 12, 0, st_tlv),
577SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
578 0, 12, 0, st_tlv),
579SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
580SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
581
146fd574
UK		 582SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
583SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
584
585SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
586SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
587
588SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
589SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
590
154b26aa
MB		 591SOC_ENUM("ADC OSR", adc_osr),
592SOC_ENUM("DAC OSR", dac_osr),
593
9e6e96a1
MB		 594SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
595 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
596SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
597 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
598
599SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
600 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
601SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
602 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
603
604SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
605 6, 1, 1, wm_hubs_spkmix_tlv),
606SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
607 2, 1, 1, wm_hubs_spkmix_tlv),
608
609SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
610 6, 1, 1, wm_hubs_spkmix_tlv),
611SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
612 2, 1, 1, wm_hubs_spkmix_tlv),
613
614SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
615 10, 15, 0, wm8994_3d_tlv),
458350b3 616SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 617 8, 1, 0),
618SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
619 10, 15, 0, wm8994_3d_tlv),
620SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
621 8, 1, 0),
458350b3 622SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 623 10, 15, 0, wm8994_3d_tlv),
458350b3 624SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 625 8, 1, 0),
626};
627
628static const struct snd_kcontrol_new wm8994_eq_controls[] = {
629SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
630 eq_tlv),
631SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
632 eq_tlv),
633SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
634 eq_tlv),
635SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
636 eq_tlv),
637SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
638 eq_tlv),
639
640SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
641 eq_tlv),
642SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
643 eq_tlv),
644SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
647 eq_tlv),
648SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
649 eq_tlv),
650
651SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
652 eq_tlv),
653SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
654 eq_tlv),
655SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
658 eq_tlv),
659SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
660 eq_tlv),
661};
662
c4431df0
MB		 663static const struct snd_kcontrol_new wm8958_snd_controls[] = {
664SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
665};
666
9e6e96a1
MB		 667static int clk_sys_event(struct snd_soc_dapm_widget *w,
668 struct snd_kcontrol *kcontrol, int event)
669{
670 struct snd_soc_codec *codec = w->codec;
671
672 switch (event) {
673 case SND_SOC_DAPM_PRE_PMU:
674 return configure_clock(codec);
675
676 case SND_SOC_DAPM_POST_PMD:
677 configure_clock(codec);
678 break;
679 }
680
681 return 0;
682}
683
684static void wm8994_update_class_w(struct snd_soc_codec *codec)
685{
fec6dd83 686 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 687 int enable = 1;
688 int source = 0; /* GCC flow analysis can't track enable */
689 int reg, reg_r;
690
691 /* Only support direct DAC->headphone paths */
692 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
693 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 694 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 695 enable = 0;
696 }
697
698 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
699 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 700 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 701 enable = 0;
702 }
703
704 /* We also need the same setting for L/R and only one path */
705 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
706 switch (reg) {
707 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 708 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 709 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
710 break;
711 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 712 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 713 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
714 break;
715 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 716 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 717 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
718 break;
719 default:
ee839a21 720 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 721 enable = 0;
722 break;
723 }
724
725 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
726 if (reg_r != reg) {
ee839a21 727 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 728 enable = 0;
729 }
730
731 if (enable) {
732 dev_dbg(codec->dev, "Class W enabled\n");
733 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
734 WM8994_CP_DYN_PWR |
735 WM8994_CP_DYN_SRC_SEL_MASK,
736 source | WM8994_CP_DYN_PWR);
fec6dd83 737 wm8994->hubs.class_w = true;
9e6e96a1
MB		 738
739 } else {
740 dev_dbg(codec->dev, "Class W disabled\n");
741 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
742 WM8994_CP_DYN_PWR, 0);
fec6dd83 743 wm8994->hubs.class_w = false;
9e6e96a1
MB		 744 }
745}
746
173efa09
DP		 747static int late_enable_ev(struct snd_soc_dapm_widget *w,
748 struct snd_kcontrol *kcontrol, int event)
749{
750 struct snd_soc_codec *codec = w->codec;
751 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
752
753 switch (event) {
754 case SND_SOC_DAPM_PRE_PMU:
a3cff81a 755 if (wm8994->aif1clk_enable) {
173efa09
DP		 756 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
757 WM8994_AIF1CLK_ENA_MASK,
758 WM8994_AIF1CLK_ENA);
a3cff81a
DP		 759 wm8994->aif1clk_enable = 0;
760 }
761 if (wm8994->aif2clk_enable) {
173efa09
DP		 762 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
763 WM8994_AIF2CLK_ENA_MASK,
764 WM8994_AIF2CLK_ENA);
a3cff81a
DP		 765 wm8994->aif2clk_enable = 0;
766 }
173efa09
DP		 767 break;
768 }
769
c6b7b570
MB		 770 /* We may also have postponed startup of DSP, handle that. */
771 wm8958_aif_ev(w, kcontrol, event);
772
173efa09
DP		 773 return 0;
774}
775
776static int late_disable_ev(struct snd_soc_dapm_widget *w,
777 struct snd_kcontrol *kcontrol, int event)
778{
779 struct snd_soc_codec *codec = w->codec;
780 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
781
782 switch (event) {
783 case SND_SOC_DAPM_POST_PMD:
a3cff81a 784 if (wm8994->aif1clk_disable) {
173efa09
DP		 785 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
786 WM8994_AIF1CLK_ENA_MASK, 0);
a3cff81a 787 wm8994->aif1clk_disable = 0;
173efa09 788 }
a3cff81a 789 if (wm8994->aif2clk_disable) {
173efa09
DP		 790 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
791 WM8994_AIF2CLK_ENA_MASK, 0);
a3cff81a 792 wm8994->aif2clk_disable = 0;
173efa09
DP		 793 }
794 break;
795 }
796
797 return 0;
798}
799
800static int aif1clk_ev(struct snd_soc_dapm_widget *w,
801 struct snd_kcontrol *kcontrol, int event)
802{
803 struct snd_soc_codec *codec = w->codec;
804 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
805
806 switch (event) {
807 case SND_SOC_DAPM_PRE_PMU:
808 wm8994->aif1clk_enable = 1;
809 break;
a3cff81a
DP		 810 case SND_SOC_DAPM_POST_PMD:
811 wm8994->aif1clk_disable = 1;
812 break;
173efa09
DP		 813 }
814
815 return 0;
816}
817
818static int aif2clk_ev(struct snd_soc_dapm_widget *w,
819 struct snd_kcontrol *kcontrol, int event)
820{
821 struct snd_soc_codec *codec = w->codec;
822 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
823
824 switch (event) {
825 case SND_SOC_DAPM_PRE_PMU:
826 wm8994->aif2clk_enable = 1;
827 break;
a3cff81a
DP		 828 case SND_SOC_DAPM_POST_PMD:
829 wm8994->aif2clk_disable = 1;
830 break;
173efa09
DP		 831 }
832
833 return 0;
834}
835
04d28681
DP		 836static int adc_mux_ev(struct snd_soc_dapm_widget *w,
837 struct snd_kcontrol *kcontrol, int event)
838{
839 late_enable_ev(w, kcontrol, event);
840 return 0;
841}
842
b462c6e6
DP		 843static int micbias_ev(struct snd_soc_dapm_widget *w,
844 struct snd_kcontrol *kcontrol, int event)
845{
846 late_enable_ev(w, kcontrol, event);
847 return 0;
848}
849
c52fd021
DP		 850static int dac_ev(struct snd_soc_dapm_widget *w,
851 struct snd_kcontrol *kcontrol, int event)
852{
853 struct snd_soc_codec *codec = w->codec;
854 unsigned int mask = 1 << w->shift;
855
856 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
857 mask, mask);
858 return 0;
859}
860
9e6e96a1
MB		 861static const char *hp_mux_text[] = {
862 "Mixer",
863 "DAC",
864};
865
866#define WM8994_HP_ENUM(xname, xenum) \
867{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
868 .info = snd_soc_info_enum_double, \
869 .get = snd_soc_dapm_get_enum_double, \
870 .put = wm8994_put_hp_enum, \
871 .private_value = (unsigned long)&xenum }
872
873static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
874 struct snd_ctl_elem_value *ucontrol)
875{
9d03545d
JN		 876 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
877 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 878 struct snd_soc_codec *codec = w->codec;
879 int ret;
880
881 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
882
883 wm8994_update_class_w(codec);
884
885 return ret;
886}
887
888static const struct soc_enum hpl_enum =
889 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
890
891static const struct snd_kcontrol_new hpl_mux =
892 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
893
894static const struct soc_enum hpr_enum =
895 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
896
897static const struct snd_kcontrol_new hpr_mux =
898 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
899
900static const char *adc_mux_text[] = {
901 "ADC",
902 "DMIC",
903};
904
905static const struct soc_enum adc_enum =
906 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
907
908static const struct snd_kcontrol_new adcl_mux =
909 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
910
911static const struct snd_kcontrol_new adcr_mux =
912 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
913
914static const struct snd_kcontrol_new left_speaker_mixer[] = {
915SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
916SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
917SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
918SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
919SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
920};
921
922static const struct snd_kcontrol_new right_speaker_mixer[] = {
923SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
924SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
925SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
926SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
927SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
928};
929
930/* Debugging; dump chip status after DAPM transitions */
931static int post_ev(struct snd_soc_dapm_widget *w,
932 struct snd_kcontrol *kcontrol, int event)
933{
934 struct snd_soc_codec *codec = w->codec;
935 dev_dbg(codec->dev, "SRC status: %x\n",
936 snd_soc_read(codec,
937 WM8994_RATE_STATUS));
938 return 0;
939}
940
941static const struct snd_kcontrol_new aif1adc1l_mix[] = {
942SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
943 1, 1, 0),
944SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
945 0, 1, 0),
946};
947
948static const struct snd_kcontrol_new aif1adc1r_mix[] = {
949SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
950 1, 1, 0),
951SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
952 0, 1, 0),
953};
954
a3257ba8
MB		 955static const struct snd_kcontrol_new aif1adc2l_mix[] = {
956SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
957 1, 1, 0),
958SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
959 0, 1, 0),
960};
961
962static const struct snd_kcontrol_new aif1adc2r_mix[] = {
963SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
964 1, 1, 0),
965SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
966 0, 1, 0),
967};
968
9e6e96a1
MB		 969static const struct snd_kcontrol_new aif2dac2l_mix[] = {
970SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
971 5, 1, 0),
972SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
973 4, 1, 0),
974SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
975 2, 1, 0),
976SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
977 1, 1, 0),
978SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
979 0, 1, 0),
980};
981
982static const struct snd_kcontrol_new aif2dac2r_mix[] = {
983SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
984 5, 1, 0),
985SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
986 4, 1, 0),
987SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
988 2, 1, 0),
989SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
990 1, 1, 0),
991SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
992 0, 1, 0),
993};
994
995#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
996{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
997 .info = snd_soc_info_volsw, \
998 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
999 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1000
1001static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1002 struct snd_ctl_elem_value *ucontrol)
1003{
9d03545d
JN		 1004 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1005 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1006 struct snd_soc_codec *codec = w->codec;
1007 int ret;
1008
1009 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1010
1011 wm8994_update_class_w(codec);
1012
1013 return ret;
1014}
1015
1016static const struct snd_kcontrol_new dac1l_mix[] = {
1017WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1018 5, 1, 0),
1019WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1020 4, 1, 0),
1021WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1022 2, 1, 0),
1023WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1024 1, 1, 0),
1025WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1026 0, 1, 0),
1027};
1028
1029static const struct snd_kcontrol_new dac1r_mix[] = {
1030WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1031 5, 1, 0),
1032WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1033 4, 1, 0),
1034WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1035 2, 1, 0),
1036WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1037 1, 1, 0),
1038WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1039 0, 1, 0),
1040};
1041
1042static const char *sidetone_text[] = {
1043 "ADC/DMIC1", "DMIC2",
1044};
1045
1046static const struct soc_enum sidetone1_enum =
1047 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1048
1049static const struct snd_kcontrol_new sidetone1_mux =
1050 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1051
1052static const struct soc_enum sidetone2_enum =
1053 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1054
1055static const struct snd_kcontrol_new sidetone2_mux =
1056 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1057
1058static const char *aif1dac_text[] = {
1059 "AIF1DACDAT", "AIF3DACDAT",
1060};
1061
1062static const struct soc_enum aif1dac_enum =
1063 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1064
1065static const struct snd_kcontrol_new aif1dac_mux =
1066 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1067
1068static const char *aif2dac_text[] = {
1069 "AIF2DACDAT", "AIF3DACDAT",
1070};
1071
1072static const struct soc_enum aif2dac_enum =
1073 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1074
1075static const struct snd_kcontrol_new aif2dac_mux =
1076 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1077
1078static const char *aif2adc_text[] = {
1079 "AIF2ADCDAT", "AIF3DACDAT",
1080};
1081
1082static const struct soc_enum aif2adc_enum =
1083 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1084
1085static const struct snd_kcontrol_new aif2adc_mux =
1086 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1087
1088static const char *aif3adc_text[] = {
c4431df0 1089 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1090};
1091
c4431df0 1092static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1093 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1094
c4431df0
MB		 1095static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1096 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1097
1098static const struct soc_enum wm8958_aif3adc_enum =
1099 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1100
1101static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1102 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1103
1104static const char *mono_pcm_out_text[] = {
1105 "None", "AIF2ADCL", "AIF2ADCR",
1106};
1107
1108static const struct soc_enum mono_pcm_out_enum =
1109 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1110
1111static const struct snd_kcontrol_new mono_pcm_out_mux =
1112 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1113
1114static const char *aif2dac_src_text[] = {
1115 "AIF2", "AIF3",
1116};
1117
1118/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1119static const struct soc_enum aif2dacl_src_enum =
1120 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1121
1122static const struct snd_kcontrol_new aif2dacl_src_mux =
1123 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1124
1125static const struct soc_enum aif2dacr_src_enum =
1126 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1127
1128static const struct snd_kcontrol_new aif2dacr_src_mux =
1129 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1130
173efa09
DP		 1131static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1132SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1133 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1134SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1135 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1136
1137SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1138 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1139SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1140 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1141SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1142 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1143SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1144 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1145SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1146 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1147
1148SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1149 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1150 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1151SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1152 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1153 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1154SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1155 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1156SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1157 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1158
1159SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1160};
1161
1162static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1163SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
b70a51ba
MB		 1164SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1165SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1166SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1167 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1168SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1169 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1170SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1171SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
173efa09
DP		 1172};
1173
c52fd021
DP		 1174static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1175SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1176 dac_ev, SND_SOC_DAPM_PRE_PMU),
1177SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1178 dac_ev, SND_SOC_DAPM_PRE_PMU),
1179SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1180 dac_ev, SND_SOC_DAPM_PRE_PMU),
1181SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1182 dac_ev, SND_SOC_DAPM_PRE_PMU),
1183};
1184
1185static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1186SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1187SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1188SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1189SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1190};
1191
04d28681
DP		 1192static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1193SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1194 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1195SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1196 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1197};
1198
1199static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1200SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1201SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1202};
1203
9e6e96a1
MB		 1204static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1205SND_SOC_DAPM_INPUT("DMIC1DAT"),
1206SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1207SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1208
b462c6e6
DP		 1209SND_SOC_DAPM_MICBIAS("MICBIAS", WM8994_MICBIAS, 2, 0),
1210SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1211 SND_SOC_DAPM_PRE_PMU),
1212
9e6e96a1
MB		 1213SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1214 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1215
1216SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1217SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1218SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1219
7f94de48 1220SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1221 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1222SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1223 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1224SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1225 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1226 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1227SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1228 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1229 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1230
7f94de48 1231SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1232 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1233SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1234 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1235SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1236 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1237 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1238SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1239 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1240 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1241
1242SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1243 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1244SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1245 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1246
a3257ba8
MB		 1247SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1248 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1249SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1250 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1251
9e6e96a1
MB		 1252SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1253 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1254SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1255 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1256
1257SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1258SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1259
1260SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1261 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1262SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1263 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1264
1265SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1266 WM8994_POWER_MANAGEMENT_4, 13, 0),
1267SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1268 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1269SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1270 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1271 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1272SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1273 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1274 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1275
1276SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1277SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
7f94de48 1278SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1279SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1280
1281SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1282SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1283SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1284
1285SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1286SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1287
1288SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1289
1290SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1291SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1292SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1293SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1294
1295/* Power is done with the muxes since the ADC power also controls the
1296 * downsampling chain, the chip will automatically manage the analogue
1297 * specific portions.
1298 */
1299SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1300SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1301
9e6e96a1
MB		 1302SND_SOC_DAPM_POST("Debug log", post_ev),
1303};
1304
c4431df0
MB		 1305static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1306SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1307};
9e6e96a1 1308
c4431df0
MB		 1309static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1310SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1311SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1312SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1313SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1314};
1315
1316static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1317 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1318 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1319
1320 { "DSP1CLK", NULL, "CLK_SYS" },
1321 { "DSP2CLK", NULL, "CLK_SYS" },
1322 { "DSPINTCLK", NULL, "CLK_SYS" },
1323
1324 { "AIF1ADC1L", NULL, "AIF1CLK" },
1325 { "AIF1ADC1L", NULL, "DSP1CLK" },
1326 { "AIF1ADC1R", NULL, "AIF1CLK" },
1327 { "AIF1ADC1R", NULL, "DSP1CLK" },
1328 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1329
1330 { "AIF1DAC1L", NULL, "AIF1CLK" },
1331 { "AIF1DAC1L", NULL, "DSP1CLK" },
1332 { "AIF1DAC1R", NULL, "AIF1CLK" },
1333 { "AIF1DAC1R", NULL, "DSP1CLK" },
1334 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1335
1336 { "AIF1ADC2L", NULL, "AIF1CLK" },
1337 { "AIF1ADC2L", NULL, "DSP1CLK" },
1338 { "AIF1ADC2R", NULL, "AIF1CLK" },
1339 { "AIF1ADC2R", NULL, "DSP1CLK" },
1340 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1341
1342 { "AIF1DAC2L", NULL, "AIF1CLK" },
1343 { "AIF1DAC2L", NULL, "DSP1CLK" },
1344 { "AIF1DAC2R", NULL, "AIF1CLK" },
1345 { "AIF1DAC2R", NULL, "DSP1CLK" },
1346 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1347
1348 { "AIF2ADCL", NULL, "AIF2CLK" },
1349 { "AIF2ADCL", NULL, "DSP2CLK" },
1350 { "AIF2ADCR", NULL, "AIF2CLK" },
1351 { "AIF2ADCR", NULL, "DSP2CLK" },
1352 { "AIF2ADCR", NULL, "DSPINTCLK" },
1353
1354 { "AIF2DACL", NULL, "AIF2CLK" },
1355 { "AIF2DACL", NULL, "DSP2CLK" },
1356 { "AIF2DACR", NULL, "AIF2CLK" },
1357 { "AIF2DACR", NULL, "DSP2CLK" },
1358 { "AIF2DACR", NULL, "DSPINTCLK" },
1359
1360 { "DMIC1L", NULL, "DMIC1DAT" },
1361 { "DMIC1L", NULL, "CLK_SYS" },
1362 { "DMIC1R", NULL, "DMIC1DAT" },
1363 { "DMIC1R", NULL, "CLK_SYS" },
1364 { "DMIC2L", NULL, "DMIC2DAT" },
1365 { "DMIC2L", NULL, "CLK_SYS" },
1366 { "DMIC2R", NULL, "DMIC2DAT" },
1367 { "DMIC2R", NULL, "CLK_SYS" },
1368
1369 { "ADCL", NULL, "AIF1CLK" },
1370 { "ADCL", NULL, "DSP1CLK" },
1371 { "ADCL", NULL, "DSPINTCLK" },
1372
1373 { "ADCR", NULL, "AIF1CLK" },
1374 { "ADCR", NULL, "DSP1CLK" },
1375 { "ADCR", NULL, "DSPINTCLK" },
1376
1377 { "ADCL Mux", "ADC", "ADCL" },
1378 { "ADCL Mux", "DMIC", "DMIC1L" },
1379 { "ADCR Mux", "ADC", "ADCR" },
1380 { "ADCR Mux", "DMIC", "DMIC1R" },
1381
1382 { "DAC1L", NULL, "AIF1CLK" },
1383 { "DAC1L", NULL, "DSP1CLK" },
1384 { "DAC1L", NULL, "DSPINTCLK" },
1385
1386 { "DAC1R", NULL, "AIF1CLK" },
1387 { "DAC1R", NULL, "DSP1CLK" },
1388 { "DAC1R", NULL, "DSPINTCLK" },
1389
1390 { "DAC2L", NULL, "AIF2CLK" },
1391 { "DAC2L", NULL, "DSP2CLK" },
1392 { "DAC2L", NULL, "DSPINTCLK" },
1393
1394 { "DAC2R", NULL, "AIF2DACR" },
1395 { "DAC2R", NULL, "AIF2CLK" },
1396 { "DAC2R", NULL, "DSP2CLK" },
1397 { "DAC2R", NULL, "DSPINTCLK" },
1398
1399 { "TOCLK", NULL, "CLK_SYS" },
1400
1401 /* AIF1 outputs */
1402 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1403 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1404 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1405
1406 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1407 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1408 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1409
a3257ba8
MB		 1410 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1411 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1412 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1413
1414 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1415 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1416 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1417
9e6e96a1
MB		 1418 /* Pin level routing for AIF3 */
1419 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1420 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1421 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1422 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1423
9e6e96a1
MB		 1424 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1425 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1426 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1427 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1428 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1429 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1430 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1431
1432 /* DAC1 inputs */
9e6e96a1
MB		 1433 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1434 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1435 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1436 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1437 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1438
9e6e96a1
MB		 1439 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1440 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1441 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1442 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1443 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1444
1445 /* DAC2/AIF2 outputs */
1446 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1447 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1448 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1449 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1450 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1451 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1452
1453 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1454 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1455 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1456 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1457 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1458 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1459
7f94de48
MB		 1460 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1461 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1462 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1463 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1464
9e6e96a1
MB		 1465 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1466
1467 /* AIF3 output */
1468 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1469 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1470 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1471 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1472 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1473 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1474 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1475 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1476
1477 /* Sidetone */
1478 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1479 { "Left Sidetone", "DMIC2", "DMIC2L" },
1480 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1481 { "Right Sidetone", "DMIC2", "DMIC2R" },
1482
1483 /* Output stages */
1484 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1485 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1486
1487 { "SPKL", "DAC1 Switch", "DAC1L" },
1488 { "SPKL", "DAC2 Switch", "DAC2L" },
1489
1490 { "SPKR", "DAC1 Switch", "DAC1R" },
1491 { "SPKR", "DAC2 Switch", "DAC2R" },
1492
1493 { "Left Headphone Mux", "DAC", "DAC1L" },
1494 { "Right Headphone Mux", "DAC", "DAC1R" },
1495};
1496
173efa09
DP		 1497static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1498 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1499 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1500 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1501 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1502 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1503 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1504 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1505 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1506};
1507
1508static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1509 { "DAC1L", NULL, "DAC1L Mixer" },
1510 { "DAC1R", NULL, "DAC1R Mixer" },
1511 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1512 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1513};
1514
6ed8f148
MB		 1515static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1516 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1517 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1518 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1519 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b462c6e6
DP		 1520 { "MICBIAS", NULL, "CLK_SYS" },
1521 { "MICBIAS", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1522};
1523
c4431df0
MB		 1524static const struct snd_soc_dapm_route wm8994_intercon[] = {
1525 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1526 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1527};
1528
1529static const struct snd_soc_dapm_route wm8958_intercon[] = {
1530 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1531 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1532
1533 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1534 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1535 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1536 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1537
1538 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1539 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1540
1541 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1542};
1543
9e6e96a1
MB		 1544/* The size in bits of the FLL divide multiplied by 10
1545 * to allow rounding later */
1546#define FIXED_FLL_SIZE ((1 << 16) * 10)
1547
1548struct fll_div {
1549 u16 outdiv;
1550 u16 n;
1551 u16 k;
1552 u16 clk_ref_div;
1553 u16 fll_fratio;
1554};
1555
1556static int wm8994_get_fll_config(struct fll_div *fll,
1557 int freq_in, int freq_out)
1558{
1559 u64 Kpart;
1560 unsigned int K, Ndiv, Nmod;
1561
1562 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1563
1564 /* Scale the input frequency down to <= 13.5MHz */
1565 fll->clk_ref_div = 0;
1566 while (freq_in > 13500000) {
1567 fll->clk_ref_div++;
1568 freq_in /= 2;
1569
1570 if (fll->clk_ref_div > 3)
1571 return -EINVAL;
1572 }
1573 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1574
1575 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1576 fll->outdiv = 3;
1577 while (freq_out * (fll->outdiv + 1) < 90000000) {
1578 fll->outdiv++;
1579 if (fll->outdiv > 63)
1580 return -EINVAL;
1581 }
1582 freq_out *= fll->outdiv + 1;
1583 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1584
1585 if (freq_in > 1000000) {
1586 fll->fll_fratio = 0;
7d48a6ac
MB		 1587 } else if (freq_in > 256000) {
1588 fll->fll_fratio = 1;
1589 freq_in *= 2;
1590 } else if (freq_in > 128000) {
1591 fll->fll_fratio = 2;
1592 freq_in *= 4;
1593 } else if (freq_in > 64000) {
9e6e96a1
MB		 1594 fll->fll_fratio = 3;
1595 freq_in *= 8;
7d48a6ac
MB		 1596 } else {
1597 fll->fll_fratio = 4;
1598 freq_in *= 16;
9e6e96a1
MB		 1599 }
1600 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1601
1602 /* Now, calculate N.K */
1603 Ndiv = freq_out / freq_in;
1604
1605 fll->n = Ndiv;
1606 Nmod = freq_out % freq_in;
1607 pr_debug("Nmod=%d\n", Nmod);
1608
1609 /* Calculate fractional part - scale up so we can round. */
1610 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1611
1612 do_div(Kpart, freq_in);
1613
1614 K = Kpart & 0xFFFFFFFF;
1615
1616 if ((K % 10) >= 5)
1617 K += 5;
1618
1619 /* Move down to proper range now rounding is done */
1620 fll->k = K / 10;
1621
1622 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1623
1624 return 0;
1625}
1626
f0fba2ad 1627static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1628 unsigned int freq_in, unsigned int freq_out)
1629{
b2c812e2 1630 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 1631 int reg_offset, ret;
1632 struct fll_div fll;
1633 u16 reg, aif1, aif2;
c7ebf932 1634 unsigned long timeout;
9e6e96a1
MB		 1635
1636 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1637 & WM8994_AIF1CLK_ENA;
1638
1639 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1640 & WM8994_AIF2CLK_ENA;
1641
1642 switch (id) {
1643 case WM8994_FLL1:
1644 reg_offset = 0;
1645 id = 0;
1646 break;
1647 case WM8994_FLL2:
1648 reg_offset = 0x20;
1649 id = 1;
1650 break;
1651 default:
1652 return -EINVAL;
1653 }
1654
136ff2a2 1655 switch (src) {
7add84aa
MB		 1656 case 0:
1657 /* Allow no source specification when stopping */
1658 if (freq_out)
1659 return -EINVAL;
4514e899 1660 src = wm8994->fll[id].src;
7add84aa 1661 break;
136ff2a2
MB		 1662 case WM8994_FLL_SRC_MCLK1:
1663 case WM8994_FLL_SRC_MCLK2:
1664 case WM8994_FLL_SRC_LRCLK:
1665 case WM8994_FLL_SRC_BCLK:
1666 break;
1667 default:
1668 return -EINVAL;
1669 }
1670
9e6e96a1
MB		 1671 /* Are we changing anything? */
1672 if (wm8994->fll[id].src == src &&
1673 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1674 return 0;
1675
1676 /* If we're stopping the FLL redo the old config - no
1677 * registers will actually be written but we avoid GCC flow
1678 * analysis bugs spewing warnings.
1679 */
1680 if (freq_out)
1681 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1682 else
1683 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1684 wm8994->fll[id].out);
1685 if (ret < 0)
1686 return ret;
1687
1688 /* Gate the AIF clocks while we reclock */
1689 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1690 WM8994_AIF1CLK_ENA, 0);
1691 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1692 WM8994_AIF2CLK_ENA, 0);
1693
1694 /* We always need to disable the FLL while reconfiguring */
1695 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1696 WM8994_FLL1_ENA, 0);
1697
1698 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1699 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1700 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1701 WM8994_FLL1_OUTDIV_MASK |
1702 WM8994_FLL1_FRATIO_MASK, reg);
1703
1704 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1705
1706 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1707 WM8994_FLL1_N_MASK,
1708 fll.n << WM8994_FLL1_N_SHIFT);
1709
1710 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1711 WM8994_FLL1_REFCLK_DIV_MASK |
1712 WM8994_FLL1_REFCLK_SRC_MASK,
1713 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1714 (src - 1));
9e6e96a1 1715
f0f5039c
MB		 1716 /* Clear any pending completion from a previous failure */
1717 try_wait_for_completion(&wm8994->fll_locked[id]);
1718
9e6e96a1
MB		 1719 /* Enable (with fractional mode if required) */
1720 if (freq_out) {
1721 if (fll.k)
1722 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1723 else
1724 reg = WM8994_FLL1_ENA;
1725 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1726 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1727 reg);
8e9ddf81 1728
c7ebf932
MB		 1729 if (wm8994->fll_locked_irq) {
1730 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1731 msecs_to_jiffies(10));
1732 if (timeout == 0)
1733 dev_warn(codec->dev,
1734 "Timed out waiting for FLL lock\n");
1735 } else {
1736 msleep(5);
1737 }
9e6e96a1
MB		 1738 }
1739
1740 wm8994->fll[id].in = freq_in;
1741 wm8994->fll[id].out = freq_out;
136ff2a2 1742 wm8994->fll[id].src = src;
9e6e96a1
MB		 1743
1744 /* Enable any gated AIF clocks */
1745 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1746 WM8994_AIF1CLK_ENA, aif1);
1747 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1748 WM8994_AIF2CLK_ENA, aif2);
1749
1750 configure_clock(codec);
1751
1752 return 0;
1753}
1754
c7ebf932
MB		 1755static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1756{
1757 struct completion *completion = data;
1758
1759 complete(completion);
1760
1761 return IRQ_HANDLED;
1762}
f0fba2ad 1763
66b47fdb
MB		 1764static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1765
f0fba2ad
LG		 1766static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1767 unsigned int freq_in, unsigned int freq_out)
1768{
1769 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1770}
1771
9e6e96a1
MB		 1772static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1773 int clk_id, unsigned int freq, int dir)
1774{
1775 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1776 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 1777 int i;
9e6e96a1
MB		 1778
1779 switch (dai->id) {
1780 case 1:
1781 case 2:
1782 break;
1783
1784 default:
1785 /* AIF3 shares clocking with AIF1/2 */
1786 return -EINVAL;
1787 }
1788
1789 switch (clk_id) {
1790 case WM8994_SYSCLK_MCLK1:
1791 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1792 wm8994->mclk[0] = freq;
1793 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1794 dai->id, freq);
1795 break;
1796
1797 case WM8994_SYSCLK_MCLK2:
1798 /* TODO: Set GPIO AF */
1799 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1800 wm8994->mclk[1] = freq;
1801 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1802 dai->id, freq);
1803 break;
1804
1805 case WM8994_SYSCLK_FLL1:
1806 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1807 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1808 break;
1809
1810 case WM8994_SYSCLK_FLL2:
1811 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1812 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1813 break;
1814
66b47fdb
MB		 1815 case WM8994_SYSCLK_OPCLK:
1816 /* Special case - a division (times 10) is given and
1817 * no effect on main clocking.
1818 */
1819 if (freq) {
1820 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1821 if (opclk_divs[i] == freq)
1822 break;
1823 if (i == ARRAY_SIZE(opclk_divs))
1824 return -EINVAL;
1825 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1826 WM8994_OPCLK_DIV_MASK, i);
1827 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1828 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1829 } else {
1830 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1831 WM8994_OPCLK_ENA, 0);
1832 }
1833
9e6e96a1
MB		 1834 default:
1835 return -EINVAL;
1836 }
1837
1838 configure_clock(codec);
1839
1840 return 0;
1841}
1842
1843static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1844 enum snd_soc_bias_level level)
1845{
3a423157 1846 struct wm8994 *control = codec->control_data;
b6b05691
MB		 1847 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1848
9e6e96a1
MB		 1849 switch (level) {
1850 case SND_SOC_BIAS_ON:
1851 break;
1852
1853 case SND_SOC_BIAS_PREPARE:
1854 /* VMID=2x40k */
1855 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1856 WM8994_VMID_SEL_MASK, 0x2);
1857 break;
1858
1859 case SND_SOC_BIAS_STANDBY:
ce6120cc 1860 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
39fb51a1
MB		 1861 pm_runtime_get_sync(codec->dev);
1862
8bc3c2c2
MB		 1863 switch (control->type) {
1864 case WM8994:
1865 if (wm8994->revision < 4) {
1866 /* Tweak DC servo and DSP
1867 * configuration for improved
1868 * performance. */
1869 snd_soc_write(codec, 0x102, 0x3);
1870 snd_soc_write(codec, 0x56, 0x3);
1871 snd_soc_write(codec, 0x817, 0);
1872 snd_soc_write(codec, 0x102, 0);
1873 }
1874 break;
1875
1876 case WM8958:
1877 if (wm8994->revision == 0) {
1878 /* Optimise performance for rev A */
1879 snd_soc_write(codec, 0x102, 0x3);
1880 snd_soc_write(codec, 0xcb, 0x81);
1881 snd_soc_write(codec, 0x817, 0);
1882 snd_soc_write(codec, 0x102, 0);
1883
1884 snd_soc_update_bits(codec,
1885 WM8958_CHARGE_PUMP_2,
1886 WM8958_CP_DISCH,
1887 WM8958_CP_DISCH);
1888 }
1889 break;
b6b05691 1890 }
9e6e96a1
MB		 1891
1892 /* Discharge LINEOUT1 & 2 */
1893 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1894 WM8994_LINEOUT1_DISCH |
1895 WM8994_LINEOUT2_DISCH,
1896 WM8994_LINEOUT1_DISCH |
1897 WM8994_LINEOUT2_DISCH);
1898
1899 /* Startup bias, VMID ramp & buffer */
1900 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1901 WM8994_STARTUP_BIAS_ENA |
1902 WM8994_VMID_BUF_ENA |
1903 WM8994_VMID_RAMP_MASK,
1904 WM8994_STARTUP_BIAS_ENA |
1905 WM8994_VMID_BUF_ENA |
1906 (0x11 << WM8994_VMID_RAMP_SHIFT));
1907
1908 /* Main bias enable, VMID=2x40k */
1909 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1910 WM8994_BIAS_ENA |
1911 WM8994_VMID_SEL_MASK,
1912 WM8994_BIAS_ENA | 0x2);
1913
1914 msleep(20);
1915 }
1916
1917 /* VMID=2x500k */
1918 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1919 WM8994_VMID_SEL_MASK, 0x4);
1920
1921 break;
1922
1923 case SND_SOC_BIAS_OFF:
ce6120cc 1924 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
d522ffbf
MB		 1925 /* Switch over to startup biases */
1926 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1927 WM8994_BIAS_SRC |
1928 WM8994_STARTUP_BIAS_ENA |
1929 WM8994_VMID_BUF_ENA |
1930 WM8994_VMID_RAMP_MASK,
1931 WM8994_BIAS_SRC |
1932 WM8994_STARTUP_BIAS_ENA |
1933 WM8994_VMID_BUF_ENA |
1934 (1 << WM8994_VMID_RAMP_SHIFT));
9e6e96a1 1935
d522ffbf
MB		 1936 /* Disable main biases */
1937 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1938 WM8994_BIAS_ENA |
1939 WM8994_VMID_SEL_MASK, 0);
9e6e96a1 1940
d522ffbf
MB		 1941 /* Discharge line */
1942 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1943 WM8994_LINEOUT1_DISCH |
1944 WM8994_LINEOUT2_DISCH,
1945 WM8994_LINEOUT1_DISCH |
1946 WM8994_LINEOUT2_DISCH);
9e6e96a1 1947
d522ffbf 1948 msleep(5);
9e6e96a1 1949
d522ffbf
MB		 1950 /* Switch off startup biases */
1951 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1952 WM8994_BIAS_SRC |
1953 WM8994_STARTUP_BIAS_ENA |
1954 WM8994_VMID_BUF_ENA |
1955 WM8994_VMID_RAMP_MASK, 0);
39fb51a1 1956
fbbf5920
MB		 1957 wm8994->cur_fw = NULL;
1958
39fb51a1 1959 pm_runtime_put(codec->dev);
d522ffbf 1960 }
9e6e96a1
MB		 1961 break;
1962 }
ce6120cc 1963 codec->dapm.bias_level = level;
9e6e96a1
MB		 1964 return 0;
1965}
1966
1967static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1968{
1969 struct snd_soc_codec *codec = dai->codec;
c4431df0 1970 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 1971 int ms_reg;
1972 int aif1_reg;
1973 int ms = 0;
1974 int aif1 = 0;
1975
1976 switch (dai->id) {
1977 case 1:
1978 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1979 aif1_reg = WM8994_AIF1_CONTROL_1;
1980 break;
1981 case 2:
1982 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1983 aif1_reg = WM8994_AIF2_CONTROL_1;
1984 break;
1985 default:
1986 return -EINVAL;
1987 }
1988
1989 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1990 case SND_SOC_DAIFMT_CBS_CFS:
1991 break;
1992 case SND_SOC_DAIFMT_CBM_CFM:
1993 ms = WM8994_AIF1_MSTR;
1994 break;
1995 default:
1996 return -EINVAL;
1997 }
1998
1999 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2000 case SND_SOC_DAIFMT_DSP_B:
2001 aif1 |= WM8994_AIF1_LRCLK_INV;
2002 case SND_SOC_DAIFMT_DSP_A:
2003 aif1 |= 0x18;
2004 break;
2005 case SND_SOC_DAIFMT_I2S:
2006 aif1 |= 0x10;
2007 break;
2008 case SND_SOC_DAIFMT_RIGHT_J:
2009 break;
2010 case SND_SOC_DAIFMT_LEFT_J:
2011 aif1 |= 0x8;
2012 break;
2013 default:
2014 return -EINVAL;
2015 }
2016
2017 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2018 case SND_SOC_DAIFMT_DSP_A:
2019 case SND_SOC_DAIFMT_DSP_B:
2020 /* frame inversion not valid for DSP modes */
2021 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2022 case SND_SOC_DAIFMT_NB_NF:
2023 break;
2024 case SND_SOC_DAIFMT_IB_NF:
2025 aif1 |= WM8994_AIF1_BCLK_INV;
2026 break;
2027 default:
2028 return -EINVAL;
2029 }
2030 break;
2031
2032 case SND_SOC_DAIFMT_I2S:
2033 case SND_SOC_DAIFMT_RIGHT_J:
2034 case SND_SOC_DAIFMT_LEFT_J:
2035 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2036 case SND_SOC_DAIFMT_NB_NF:
2037 break;
2038 case SND_SOC_DAIFMT_IB_IF:
2039 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2040 break;
2041 case SND_SOC_DAIFMT_IB_NF:
2042 aif1 |= WM8994_AIF1_BCLK_INV;
2043 break;
2044 case SND_SOC_DAIFMT_NB_IF:
2045 aif1 |= WM8994_AIF1_LRCLK_INV;
2046 break;
2047 default:
2048 return -EINVAL;
2049 }
2050 break;
2051 default:
2052 return -EINVAL;
2053 }
2054
c4431df0
MB		 2055 /* The AIF2 format configuration needs to be mirrored to AIF3
2056 * on WM8958 if it's in use so just do it all the time. */
2057 if (control->type == WM8958 && dai->id == 2)
2058 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2059 WM8994_AIF1_LRCLK_INV |
2060 WM8958_AIF3_FMT_MASK, aif1);
2061
9e6e96a1
MB		 2062 snd_soc_update_bits(codec, aif1_reg,
2063 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2064 WM8994_AIF1_FMT_MASK,
2065 aif1);
2066 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2067 ms);
2068
2069 return 0;
2070}
2071
2072static struct {
2073 int val, rate;
2074} srs[] = {
2075 { 0, 8000 },
2076 { 1, 11025 },
2077 { 2, 12000 },
2078 { 3, 16000 },
2079 { 4, 22050 },
2080 { 5, 24000 },
2081 { 6, 32000 },
2082 { 7, 44100 },
2083 { 8, 48000 },
2084 { 9, 88200 },
2085 { 10, 96000 },
2086};
2087
2088static int fs_ratios[] = {
2089 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2090};
2091
2092static int bclk_divs[] = {
2093 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2094 640, 880, 960, 1280, 1760, 1920
2095};
2096
2097static int wm8994_hw_params(struct snd_pcm_substream *substream,
2098 struct snd_pcm_hw_params *params,
2099 struct snd_soc_dai *dai)
2100{
2101 struct snd_soc_codec *codec = dai->codec;
c4431df0 2102 struct wm8994 *control = codec->control_data;
b2c812e2 2103 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2104 int aif1_reg;
b1e43d93 2105 int aif2_reg;
9e6e96a1
MB		 2106 int bclk_reg;
2107 int lrclk_reg;
2108 int rate_reg;
2109 int aif1 = 0;
b1e43d93 2110 int aif2 = 0;
9e6e96a1
MB		 2111 int bclk = 0;
2112 int lrclk = 0;
2113 int rate_val = 0;
2114 int id = dai->id - 1;
2115
2116 int i, cur_val, best_val, bclk_rate, best;
2117
2118 switch (dai->id) {
2119 case 1:
2120 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2121 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2122 bclk_reg = WM8994_AIF1_BCLK;
2123 rate_reg = WM8994_AIF1_RATE;
2124 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2125 wm8994->lrclk_shared[0]) {
9e6e96a1 2126 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2127 } else {
9e6e96a1 2128 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2129 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2130 }
9e6e96a1
MB		 2131 break;
2132 case 2:
2133 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2134 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2135 bclk_reg = WM8994_AIF2_BCLK;
2136 rate_reg = WM8994_AIF2_RATE;
2137 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2138 wm8994->lrclk_shared[1]) {
9e6e96a1 2139 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2140 } else {
9e6e96a1 2141 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2142 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2143 }
9e6e96a1 2144 break;
c4431df0
MB		 2145 case 3:
2146 switch (control->type) {
2147 case WM8958:
2148 aif1_reg = WM8958_AIF3_CONTROL_1;
2149 break;
2150 default:
2151 return 0;
2152 }
9e6e96a1
MB		 2153 default:
2154 return -EINVAL;
2155 }
2156
2157 bclk_rate = params_rate(params) * 2;
2158 switch (params_format(params)) {
2159 case SNDRV_PCM_FORMAT_S16_LE:
2160 bclk_rate *= 16;
2161 break;
2162 case SNDRV_PCM_FORMAT_S20_3LE:
2163 bclk_rate *= 20;
2164 aif1 |= 0x20;
2165 break;
2166 case SNDRV_PCM_FORMAT_S24_LE:
2167 bclk_rate *= 24;
2168 aif1 |= 0x40;
2169 break;
2170 case SNDRV_PCM_FORMAT_S32_LE:
2171 bclk_rate *= 32;
2172 aif1 |= 0x60;
2173 break;
2174 default:
2175 return -EINVAL;
2176 }
2177
2178 /* Try to find an appropriate sample rate; look for an exact match. */
2179 for (i = 0; i < ARRAY_SIZE(srs); i++)
2180 if (srs[i].rate == params_rate(params))
2181 break;
2182 if (i == ARRAY_SIZE(srs))
2183 return -EINVAL;
2184 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2185
2186 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2187 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2188 dai->id, wm8994->aifclk[id], bclk_rate);
2189
b1e43d93
MB		 2190 if (params_channels(params) == 1 &&
2191 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2192 aif2 |= WM8994_AIF1_MONO;
2193
9e6e96a1
MB		 2194 if (wm8994->aifclk[id] == 0) {
2195 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2196 return -EINVAL;
2197 }
2198
2199 /* AIFCLK/fs ratio; look for a close match in either direction */
2200 best = 0;
2201 best_val = abs((fs_ratios[0] * params_rate(params))
2202 - wm8994->aifclk[id]);
2203 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2204 cur_val = abs((fs_ratios[i] * params_rate(params))
2205 - wm8994->aifclk[id]);
2206 if (cur_val >= best_val)
2207 continue;
2208 best = i;
2209 best_val = cur_val;
2210 }
2211 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2212 dai->id, fs_ratios[best]);
2213 rate_val |= best;
2214
2215 /* We may not get quite the right frequency if using
2216 * approximate clocks so look for the closest match that is
2217 * higher than the target (we need to ensure that there enough
2218 * BCLKs to clock out the samples).
2219 */
2220 best = 0;
2221 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2222 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2223 if (cur_val < 0) /* BCLK table is sorted */
2224 break;
2225 best = i;
2226 }
07cd8ada 2227 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2228 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2229 bclk_divs[best], bclk_rate);
2230 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2231
2232 lrclk = bclk_rate / params_rate(params);
2233 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2234 lrclk, bclk_rate / lrclk);
2235
2236 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2237 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2238 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2239 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2240 lrclk);
2241 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2242 WM8994_AIF1CLK_RATE_MASK, rate_val);
2243
2244 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2245 switch (dai->id) {
2246 case 1:
2247 wm8994->dac_rates[0] = params_rate(params);
2248 wm8994_set_retune_mobile(codec, 0);
2249 wm8994_set_retune_mobile(codec, 1);
2250 break;
2251 case 2:
2252 wm8994->dac_rates[1] = params_rate(params);
2253 wm8994_set_retune_mobile(codec, 2);
2254 break;
2255 }
2256 }
2257
2258 return 0;
2259}
2260
c4431df0
MB		 2261static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2262 struct snd_pcm_hw_params *params,
2263 struct snd_soc_dai *dai)
2264{
2265 struct snd_soc_codec *codec = dai->codec;
2266 struct wm8994 *control = codec->control_data;
2267 int aif1_reg;
2268 int aif1 = 0;
2269
2270 switch (dai->id) {
2271 case 3:
2272 switch (control->type) {
2273 case WM8958:
2274 aif1_reg = WM8958_AIF3_CONTROL_1;
2275 break;
2276 default:
2277 return 0;
2278 }
2279 default:
2280 return 0;
2281 }
2282
2283 switch (params_format(params)) {
2284 case SNDRV_PCM_FORMAT_S16_LE:
2285 break;
2286 case SNDRV_PCM_FORMAT_S20_3LE:
2287 aif1 |= 0x20;
2288 break;
2289 case SNDRV_PCM_FORMAT_S24_LE:
2290 aif1 |= 0x40;
2291 break;
2292 case SNDRV_PCM_FORMAT_S32_LE:
2293 aif1 |= 0x60;
2294 break;
2295 default:
2296 return -EINVAL;
2297 }
2298
2299 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2300}
2301
9e6e96a1
MB		 2302static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2303{
2304 struct snd_soc_codec *codec = codec_dai->codec;
2305 int mute_reg;
2306 int reg;
2307
2308 switch (codec_dai->id) {
2309 case 1:
2310 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2311 break;
2312 case 2:
2313 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2314 break;
2315 default:
2316 return -EINVAL;
2317 }
2318
2319 if (mute)
2320 reg = WM8994_AIF1DAC1_MUTE;
2321 else
2322 reg = 0;
2323
2324 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2325
2326 return 0;
2327}
2328
778a76e2
MB		 2329static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2330{
2331 struct snd_soc_codec *codec = codec_dai->codec;
2332 int reg, val, mask;
2333
2334 switch (codec_dai->id) {
2335 case 1:
2336 reg = WM8994_AIF1_MASTER_SLAVE;
2337 mask = WM8994_AIF1_TRI;
2338 break;
2339 case 2:
2340 reg = WM8994_AIF2_MASTER_SLAVE;
2341 mask = WM8994_AIF2_TRI;
2342 break;
2343 case 3:
2344 reg = WM8994_POWER_MANAGEMENT_6;
2345 mask = WM8994_AIF3_TRI;
2346 break;
2347 default:
2348 return -EINVAL;
2349 }
2350
2351 if (tristate)
2352 val = mask;
2353 else
2354 val = 0;
2355
78b3fb46 2356 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2357}
2358
9e6e96a1
MB		 2359#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2360
2361#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2362 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1
MB		 2363
2364static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2365 .set_sysclk = wm8994_set_dai_sysclk,
2366 .set_fmt = wm8994_set_dai_fmt,
2367 .hw_params = wm8994_hw_params,
2368 .digital_mute = wm8994_aif_mute,
2369 .set_pll = wm8994_set_fll,
778a76e2 2370 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2371};
2372
2373static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2374 .set_sysclk = wm8994_set_dai_sysclk,
2375 .set_fmt = wm8994_set_dai_fmt,
2376 .hw_params = wm8994_hw_params,
2377 .digital_mute = wm8994_aif_mute,
2378 .set_pll = wm8994_set_fll,
778a76e2
MB		 2379 .set_tristate = wm8994_set_tristate,
2380};
2381
2382static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2383 .hw_params = wm8994_aif3_hw_params,
778a76e2 2384 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2385};
2386
f0fba2ad 2387static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2388 {
f0fba2ad 2389 .name = "wm8994-aif1",
8c7f78b3 2390 .id = 1,
9e6e96a1
MB		 2391 .playback = {
2392 .stream_name = "AIF1 Playback",
b1e43d93 2393 .channels_min = 1,
9e6e96a1
MB		 2394 .channels_max = 2,
2395 .rates = WM8994_RATES,
2396 .formats = WM8994_FORMATS,
2397 },
2398 .capture = {
2399 .stream_name = "AIF1 Capture",
b1e43d93 2400 .channels_min = 1,
9e6e96a1
MB		 2401 .channels_max = 2,
2402 .rates = WM8994_RATES,
2403 .formats = WM8994_FORMATS,
2404 },
2405 .ops = &wm8994_aif1_dai_ops,
2406 },
2407 {
f0fba2ad 2408 .name = "wm8994-aif2",
8c7f78b3 2409 .id = 2,
9e6e96a1
MB		 2410 .playback = {
2411 .stream_name = "AIF2 Playback",
b1e43d93 2412 .channels_min = 1,
9e6e96a1
MB		 2413 .channels_max = 2,
2414 .rates = WM8994_RATES,
2415 .formats = WM8994_FORMATS,
2416 },
2417 .capture = {
2418 .stream_name = "AIF2 Capture",
b1e43d93 2419 .channels_min = 1,
9e6e96a1
MB		 2420 .channels_max = 2,
2421 .rates = WM8994_RATES,
2422 .formats = WM8994_FORMATS,
2423 },
2424 .ops = &wm8994_aif2_dai_ops,
2425 },
2426 {
f0fba2ad 2427 .name = "wm8994-aif3",
8c7f78b3 2428 .id = 3,
9e6e96a1
MB		 2429 .playback = {
2430 .stream_name = "AIF3 Playback",
b1e43d93 2431 .channels_min = 1,
9e6e96a1
MB		 2432 .channels_max = 2,
2433 .rates = WM8994_RATES,
2434 .formats = WM8994_FORMATS,
2435 },
a8462bde 2436 .capture = {
9e6e96a1 2437 .stream_name = "AIF3 Capture",
b1e43d93 2438 .channels_min = 1,
9e6e96a1
MB		 2439 .channels_max = 2,
2440 .rates = WM8994_RATES,
2441 .formats = WM8994_FORMATS,
2442 },
778a76e2 2443 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2444 }
2445};
9e6e96a1
MB		 2446
2447#ifdef CONFIG_PM
f0fba2ad 2448static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
9e6e96a1 2449{
b2c812e2 2450 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ca629928 2451 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 2452 int i, ret;
2453
ca629928
MB		 2454 switch (control->type) {
2455 case WM8994:
2456 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2457 break;
2458 case WM8958:
2459 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2460 WM8958_MICD_ENA, 0);
2461 break;
2462 }
2463
9e6e96a1
MB		 2464 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2465 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2466 sizeof(struct wm8994_fll_config));
f0fba2ad 2467 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2468 if (ret < 0)
2469 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2470 i + 1, ret);
2471 }
2472
2473 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2474
2475 return 0;
2476}
2477
f0fba2ad 2478static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2479{
b2c812e2 2480 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ca629928 2481 struct wm8994 *control = codec->control_data;
9e6e96a1 2482 int i, ret;
c52fd021
DP		 2483 unsigned int val, mask;
2484
2485 if (wm8994->revision < 4) {
2486 /* force a HW read */
2487 val = wm8994_reg_read(codec->control_data,
2488 WM8994_POWER_MANAGEMENT_5);
2489
2490 /* modify the cache only */
2491 codec->cache_only = 1;
2492 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2493 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2494 val &= mask;
2495 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2496 mask, val);
2497 codec->cache_only = 0;
2498 }
9e6e96a1
MB		 2499
2500 /* Restore the registers */
ca9aef50
MB		 2501 ret = snd_soc_cache_sync(codec);
2502 if (ret != 0)
2503 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
9e6e96a1
MB		 2504
2505 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2506
2507 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2508 if (!wm8994->fll_suspend[i].out)
2509 continue;
2510
f0fba2ad 2511 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2512 wm8994->fll_suspend[i].src,
2513 wm8994->fll_suspend[i].in,
2514 wm8994->fll_suspend[i].out);
2515 if (ret < 0)
2516 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2517 i + 1, ret);
2518 }
2519
ca629928
MB		 2520 switch (control->type) {
2521 case WM8994:
2522 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2523 snd_soc_update_bits(codec, WM8994_MICBIAS,
2524 WM8994_MICD_ENA, WM8994_MICD_ENA);
2525 break;
2526 case WM8958:
2527 if (wm8994->jack_cb)
2528 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2529 WM8958_MICD_ENA, WM8958_MICD_ENA);
2530 break;
2531 }
2532
9e6e96a1
MB		 2533 return 0;
2534}
2535#else
2536#define wm8994_suspend NULL
2537#define wm8994_resume NULL
2538#endif
2539
2540static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2541{
f0fba2ad 2542 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2543 struct wm8994_pdata *pdata = wm8994->pdata;
2544 struct snd_kcontrol_new controls[] = {
2545 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2546 wm8994->retune_mobile_enum,
2547 wm8994_get_retune_mobile_enum,
2548 wm8994_put_retune_mobile_enum),
2549 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2550 wm8994->retune_mobile_enum,
2551 wm8994_get_retune_mobile_enum,
2552 wm8994_put_retune_mobile_enum),
2553 SOC_ENUM_EXT("AIF2 EQ Mode",
2554 wm8994->retune_mobile_enum,
2555 wm8994_get_retune_mobile_enum,
2556 wm8994_put_retune_mobile_enum),
2557 };
2558 int ret, i, j;
2559 const char **t;
2560
2561 /* We need an array of texts for the enum API but the number
2562 * of texts is likely to be less than the number of
2563 * configurations due to the sample rate dependency of the
2564 * configurations. */
2565 wm8994->num_retune_mobile_texts = 0;
2566 wm8994->retune_mobile_texts = NULL;
2567 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2568 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2569 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2570 wm8994->retune_mobile_texts[j]) == 0)
2571 break;
2572 }
2573
2574 if (j != wm8994->num_retune_mobile_texts)
2575 continue;
2576
2577 /* Expand the array... */
2578 t = krealloc(wm8994->retune_mobile_texts,
2579 sizeof(char *) *
2580 (wm8994->num_retune_mobile_texts + 1),
2581 GFP_KERNEL);
2582 if (t == NULL)
2583 continue;
2584
2585 /* ...store the new entry... */
2586 t[wm8994->num_retune_mobile_texts] =
2587 pdata->retune_mobile_cfgs[i].name;
2588
2589 /* ...and remember the new version. */
2590 wm8994->num_retune_mobile_texts++;
2591 wm8994->retune_mobile_texts = t;
2592 }
2593
2594 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2595 wm8994->num_retune_mobile_texts);
2596
2597 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2598 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2599
f0fba2ad 2600 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2601 ARRAY_SIZE(controls));
2602 if (ret != 0)
f0fba2ad 2603 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2604 "Failed to add ReTune Mobile controls: %d\n", ret);
2605}
2606
2607static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2608{
f0fba2ad 2609 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2610 struct wm8994_pdata *pdata = wm8994->pdata;
2611 int ret, i;
2612
2613 if (!pdata)
2614 return;
2615
2616 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2617 pdata->lineout2_diff,
2618 pdata->lineout1fb,
2619 pdata->lineout2fb,
2620 pdata->jd_scthr,
2621 pdata->jd_thr,
2622 pdata->micbias1_lvl,
2623 pdata->micbias2_lvl);
2624
2625 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2626
2627 if (pdata->num_drc_cfgs) {
2628 struct snd_kcontrol_new controls[] = {
2629 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2630 wm8994_get_drc_enum, wm8994_put_drc_enum),
2631 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2632 wm8994_get_drc_enum, wm8994_put_drc_enum),
2633 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2634 wm8994_get_drc_enum, wm8994_put_drc_enum),
2635 };
2636
2637 /* We need an array of texts for the enum API */
2638 wm8994->drc_texts = kmalloc(sizeof(char *)
2639 * pdata->num_drc_cfgs, GFP_KERNEL);
2640 if (!wm8994->drc_texts) {
f0fba2ad 2641 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2642 "Failed to allocate %d DRC config texts\n",
2643 pdata->num_drc_cfgs);
2644 return;
2645 }
2646
2647 for (i = 0; i < pdata->num_drc_cfgs; i++)
2648 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2649
2650 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2651 wm8994->drc_enum.texts = wm8994->drc_texts;
2652
f0fba2ad 2653 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2654 ARRAY_SIZE(controls));
2655 if (ret != 0)
f0fba2ad 2656 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2657 "Failed to add DRC mode controls: %d\n", ret);
2658
2659 for (i = 0; i < WM8994_NUM_DRC; i++)
2660 wm8994_set_drc(codec, i);
2661 }
2662
2663 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2664 pdata->num_retune_mobile_cfgs);
2665
2666 if (pdata->num_retune_mobile_cfgs)
2667 wm8994_handle_retune_mobile_pdata(wm8994);
2668 else
f0fba2ad 2669 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 2670 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 2671
2672 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2673 if (pdata->micbias[i]) {
2674 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2675 pdata->micbias[i] & 0xffff);
2676 }
2677 }
9e6e96a1
MB		 2678}
2679
88766984
MB		 2680/**
2681 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2682 *
2683 * @codec: WM8994 codec
2684 * @jack: jack to report detection events on
2685 * @micbias: microphone bias to detect on
2686 * @det: value to report for presence detection
2687 * @shrt: value to report for short detection
2688 *
2689 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2690 * being used to bring out signals to the processor then only platform
5ab230a7 2691 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2692 * be configured using snd_soc_jack_add_gpios() instead.
2693 *
2694 * Configuration of detection levels is available via the micbias1_lvl
2695 * and micbias2_lvl platform data members.
2696 */
2697int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2698 int micbias, int det, int shrt)
2699{
b2c812e2 2700 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2701 struct wm8994_micdet *micdet;
3a423157 2702 struct wm8994 *control = codec->control_data;
88766984
MB		 2703 int reg;
2704
3a423157
MB		 2705 if (control->type != WM8994)
2706 return -EINVAL;
2707
88766984
MB		 2708 switch (micbias) {
2709 case 1:
2710 micdet = &wm8994->micdet[0];
2711 break;
2712 case 2:
2713 micdet = &wm8994->micdet[1];
2714 break;
2715 default:
2716 return -EINVAL;
2717 }
2718
2719 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2720 micbias, det, shrt);
2721
2722 /* Store the configuration */
2723 micdet->jack = jack;
2724 micdet->det = det;
2725 micdet->shrt = shrt;
2726
2727 /* If either of the jacks is set up then enable detection */
2728 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2729 reg = WM8994_MICD_ENA;
2730 else
2731 reg = 0;
2732
2733 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2734
2735 return 0;
2736}
2737EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2738
2739static irqreturn_t wm8994_mic_irq(int irq, void *data)
2740{
2741 struct wm8994_priv *priv = data;
f0fba2ad 2742 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 2743 int reg;
2744 int report;
2745
7116f452 2746#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 2747 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 2748#endif
2bbb5d66 2749
88766984
MB		 2750 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2751 if (reg < 0) {
2752 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2753 reg);
2754 return IRQ_HANDLED;
2755 }
2756
2757 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2758
2759 report = 0;
2760 if (reg & WM8994_MIC1_DET_STS)
2761 report |= priv->micdet[0].det;
2762 if (reg & WM8994_MIC1_SHRT_STS)
2763 report |= priv->micdet[0].shrt;
2764 snd_soc_jack_report(priv->micdet[0].jack, report,
2765 priv->micdet[0].det | priv->micdet[0].shrt);
2766
2767 report = 0;
2768 if (reg & WM8994_MIC2_DET_STS)
2769 report |= priv->micdet[1].det;
2770 if (reg & WM8994_MIC2_SHRT_STS)
2771 report |= priv->micdet[1].shrt;
2772 snd_soc_jack_report(priv->micdet[1].jack, report,
2773 priv->micdet[1].det | priv->micdet[1].shrt);
2774
2775 return IRQ_HANDLED;
2776}
2777
821edd2f
MB		 2778/* Default microphone detection handler for WM8958 - the user can
2779 * override this if they wish.
2780 */
2781static void wm8958_default_micdet(u16 status, void *data)
2782{
2783 struct snd_soc_codec *codec = data;
2784 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2785 int report = 0;
2786
2787 /* If nothing present then clear our statuses */
864c4bd2 2788 if (!(status & WM8958_MICD_STS))
821edd2f 2789 goto done;
821edd2f 2790
864c4bd2 2791 report = SND_JACK_MICROPHONE;
821edd2f
MB		 2792
2793 /* Everything else is buttons; just assign slots */
b35e160a 2794 if (status & 0x1c)
821edd2f 2795 report |= SND_JACK_BTN_0;
821edd2f
MB		 2796
2797done:
406e56c9 2798 snd_soc_jack_report(wm8994->micdet[0].jack, report,
864c4bd2 2799 SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
821edd2f
MB		 2800}
2801
2802/**
2803 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2804 *
2805 * @codec: WM8958 codec
2806 * @jack: jack to report detection events on
2807 *
2808 * Enable microphone detection functionality for the WM8958. By
2809 * default simple detection which supports the detection of up to 6
2810 * buttons plus video and microphone functionality is supported.
2811 *
2812 * The WM8958 has an advanced jack detection facility which is able to
2813 * support complex accessory detection, especially when used in
2814 * conjunction with external circuitry. In order to provide maximum
2815 * flexiblity a callback is provided which allows a completely custom
2816 * detection algorithm.
2817 */
2818int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2819 wm8958_micdet_cb cb, void *cb_data)
2820{
2821 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2822 struct wm8994 *control = codec->control_data;
2823
2824 if (control->type != WM8958)
2825 return -EINVAL;
2826
2827 if (jack) {
2828 if (!cb) {
2829 dev_dbg(codec->dev, "Using default micdet callback\n");
2830 cb = wm8958_default_micdet;
2831 cb_data = codec;
2832 }
2833
2834 wm8994->micdet[0].jack = jack;
2835 wm8994->jack_cb = cb;
2836 wm8994->jack_cb_data = cb_data;
2837
2838 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2839 WM8958_MICD_ENA, WM8958_MICD_ENA);
2840 } else {
2841 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2842 WM8958_MICD_ENA, 0);
2843 }
2844
2845 return 0;
2846}
2847EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2848
2849static irqreturn_t wm8958_mic_irq(int irq, void *data)
2850{
2851 struct wm8994_priv *wm8994 = data;
2852 struct snd_soc_codec *codec = wm8994->codec;
2853 int reg;
2854
2855 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2856 if (reg < 0) {
2857 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2858 reg);
2859 return IRQ_NONE;
2860 }
2861
2862 if (!(reg & WM8958_MICD_VALID)) {
2863 dev_dbg(codec->dev, "Mic detect data not valid\n");
2864 goto out;
2865 }
2866
7116f452 2867#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 2868 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 2869#endif
2bbb5d66 2870
821edd2f
MB		 2871 if (wm8994->jack_cb)
2872 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2873 else
2874 dev_warn(codec->dev, "Accessory detection with no callback\n");
2875
2876out:
2877 return IRQ_HANDLED;
2878}
2879
3b1af3f8
MB		 2880static irqreturn_t wm8994_fifo_error(int irq, void *data)
2881{
2882 struct snd_soc_codec *codec = data;
2883
2884 dev_err(codec->dev, "FIFO error\n");
2885
2886 return IRQ_HANDLED;
2887}
2888
f0fba2ad 2889static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 2890{
3a423157 2891 struct wm8994 *control;
9e6e96a1 2892 struct wm8994_priv *wm8994;
ce6120cc 2893 struct snd_soc_dapm_context *dapm = &codec->dapm;
ec62dbd7 2894 int ret, i;
9e6e96a1 2895
f0fba2ad 2896 codec->control_data = dev_get_drvdata(codec->dev->parent);
3a423157 2897 control = codec->control_data;
9e6e96a1
MB		 2898
2899 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
f0fba2ad 2900 if (wm8994 == NULL)
9e6e96a1 2901 return -ENOMEM;
b2c812e2 2902 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad
LG		 2903
2904 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2905 wm8994->codec = codec;
9e6e96a1 2906
c7ebf932
MB		 2907 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2908 init_completion(&wm8994->fll_locked[i]);
2909
9b7c525d
MB		 2910 if (wm8994->pdata && wm8994->pdata->micdet_irq)
2911 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
2912 else if (wm8994->pdata && wm8994->pdata->irq_base)
2913 wm8994->micdet_irq = wm8994->pdata->irq_base +
2914 WM8994_IRQ_MIC1_DET;
2915
39fb51a1
MB		 2916 pm_runtime_enable(codec->dev);
2917 pm_runtime_resume(codec->dev);
2918
ca9aef50
MB		 2919 /* Read our current status back from the chip - we don't want to
2920 * reset as this may interfere with the GPIO or LDO operation. */
2921 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
d4754ec9 2922 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
ca9aef50 2923 continue;
9e6e96a1 2924
ca9aef50
MB		 2925 ret = wm8994_reg_read(codec->control_data, i);
2926 if (ret <= 0)
2927 continue;
2928
2929 ret = snd_soc_cache_write(codec, i, ret);
2930 if (ret != 0) {
2931 dev_err(codec->dev,
2932 "Failed to initialise cache for 0x%x: %d\n",
2933 i, ret);
2934 goto err;
2935 }
2936 }
9e6e96a1
MB		 2937
2938 /* Set revision-specific configuration */
b6b05691 2939 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 2940 switch (control->type) {
2941 case WM8994:
2942 switch (wm8994->revision) {
2943 case 2:
2944 case 3:
2945 wm8994->hubs.dcs_codes = -5;
2946 wm8994->hubs.hp_startup_mode = 1;
2947 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 2948 wm8994->hubs.series_startup = 1;
3a423157
MB		 2949 break;
2950 default:
2951 wm8994->hubs.dcs_readback_mode = 1;
2952 break;
2953 }
2954
2955 case WM8958:
8437f700 2956 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 2957 break;
3a423157 2958
9e6e96a1
MB		 2959 default:
2960 break;
2961 }
9e6e96a1 2962
3b1af3f8
MB		 2963 wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
2964 wm8994_fifo_error, "FIFO error", codec);
2965
b30ead5f
MB		 2966 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
2967 wm_hubs_dcs_done, "DC servo done",
2968 &wm8994->hubs);
2969 if (ret == 0)
2970 wm8994->hubs.dcs_done_irq = true;
2971
3a423157
MB		 2972 switch (control->type) {
2973 case WM8994:
9b7c525d
MB		 2974 if (wm8994->micdet_irq) {
2975 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
2976 wm8994_mic_irq,
2977 IRQF_TRIGGER_RISING,
2978 "Mic1 detect",
2979 wm8994);
2980 if (ret != 0)
2981 dev_warn(codec->dev,
2982 "Failed to request Mic1 detect IRQ: %d\n",
2983 ret);
2984 }
3a423157
MB		 2985
2986 ret = wm8994_request_irq(codec->control_data,
2987 WM8994_IRQ_MIC1_SHRT,
2988 wm8994_mic_irq, "Mic 1 short",
2989 wm8994);
2990 if (ret != 0)
2991 dev_warn(codec->dev,
2992 "Failed to request Mic1 short IRQ: %d\n",
2993 ret);
2994
2995 ret = wm8994_request_irq(codec->control_data,
2996 WM8994_IRQ_MIC2_DET,
2997 wm8994_mic_irq, "Mic 2 detect",
2998 wm8994);
2999 if (ret != 0)
3000 dev_warn(codec->dev,
3001 "Failed to request Mic2 detect IRQ: %d\n",
3002 ret);
3003
3004 ret = wm8994_request_irq(codec->control_data,
3005 WM8994_IRQ_MIC2_SHRT,
3006 wm8994_mic_irq, "Mic 2 short",
3007 wm8994);
3008 if (ret != 0)
3009 dev_warn(codec->dev,
3010 "Failed to request Mic2 short IRQ: %d\n",
3011 ret);
3012 break;
821edd2f
MB		 3013
3014 case WM8958:
9b7c525d
MB		 3015 if (wm8994->micdet_irq) {
3016 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3017 wm8958_mic_irq,
3018 IRQF_TRIGGER_RISING,
3019 "Mic detect",
3020 wm8994);
3021 if (ret != 0)
3022 dev_warn(codec->dev,
3023 "Failed to request Mic detect IRQ: %d\n",
3024 ret);
3025 }
3a423157 3026 }
88766984 3027
c7ebf932
MB		 3028 wm8994->fll_locked_irq = true;
3029 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3030 ret = wm8994_request_irq(codec->control_data,
3031 WM8994_IRQ_FLL1_LOCK + i,
3032 wm8994_fll_locked_irq, "FLL lock",
3033 &wm8994->fll_locked[i]);
3034 if (ret != 0)
3035 wm8994->fll_locked_irq = false;
3036 }
3037
9e6e96a1
MB		 3038 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3039 * configured on init - if a system wants to do this dynamically
3040 * at runtime we can deal with that then.
3041 */
3042 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3043 if (ret < 0) {
3044 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3045 goto err_irq;
9e6e96a1
MB		 3046 }
3047 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3048 wm8994->lrclk_shared[0] = 1;
3049 wm8994_dai[0].symmetric_rates = 1;
3050 } else {
3051 wm8994->lrclk_shared[0] = 0;
3052 }
3053
3054 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3055 if (ret < 0) {
3056 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3057 goto err_irq;
9e6e96a1
MB		 3058 }
3059 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3060 wm8994->lrclk_shared[1] = 1;
3061 wm8994_dai[1].symmetric_rates = 1;
3062 } else {
3063 wm8994->lrclk_shared[1] = 0;
3064 }
3065
9e6e96a1
MB		 3066 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3067
9e6e96a1 3068 /* Latch volume updates (right only; we always do left then right). */
baa81603
MB		 3069 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3070 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
9e6e96a1
MB		 3071 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3072 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
baa81603
MB		 3073 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3074 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
9e6e96a1
MB		 3075 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3076 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
baa81603
MB		 3077 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3078 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
9e6e96a1
MB		 3079 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3080 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
baa81603
MB		 3081 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3082 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
9e6e96a1
MB		 3083 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3084 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
baa81603
MB		 3085 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3086 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3087 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3088 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3089 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3090 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3091 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3092 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3093 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3094 WM8994_DAC1_VU, WM8994_DAC1_VU);
9e6e96a1
MB		 3095 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3096 WM8994_DAC1_VU, WM8994_DAC1_VU);
baa81603
MB		 3097 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3098 WM8994_DAC2_VU, WM8994_DAC2_VU);
9e6e96a1
MB		 3099 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3100 WM8994_DAC2_VU, WM8994_DAC2_VU);
3101
3102 /* Set the low bit of the 3D stereo depth so TLV matches */
3103 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3104 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3105 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3106 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3107 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3108 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3109 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3110 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3111 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3112
5b739670
MB		 3113 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3114 * use this; it only affects behaviour on idle TDM clock
3115 * cycles. */
3116 switch (control->type) {
3117 case WM8994:
3118 case WM8958:
3119 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3120 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3121 break;
3122 default:
3123 break;
3124 }
d1ce6b20 3125
9e6e96a1
MB		 3126 wm8994_update_class_w(codec);
3127
f0fba2ad 3128 wm8994_handle_pdata(wm8994);
9e6e96a1 3129
f0fba2ad
LG		 3130 wm_hubs_add_analogue_controls(codec);
3131 snd_soc_add_controls(codec, wm8994_snd_controls,
3132 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3133 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3134 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3135
3136 switch (control->type) {
3137 case WM8994:
3138 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3139 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3140 if (wm8994->revision < 4) {
173efa09
DP		 3141 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3142 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3143 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3144 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3145 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3146 ARRAY_SIZE(wm8994_dac_revd_widgets));
3147 } else {
173efa09
DP		 3148 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3149 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 3150 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3151 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 3152 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3153 ARRAY_SIZE(wm8994_dac_widgets));
3154 }
c4431df0
MB		 3155 break;
3156 case WM8958:
3157 snd_soc_add_controls(codec, wm8958_snd_controls,
3158 ARRAY_SIZE(wm8958_snd_controls));
3159 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3160 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 3161 if (wm8994->revision < 1) {
3162 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3163 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3164 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3165 ARRAY_SIZE(wm8994_adc_revd_widgets));
3166 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3167 ARRAY_SIZE(wm8994_dac_revd_widgets));
3168 } else {
3169 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3170 ARRAY_SIZE(wm8994_lateclk_widgets));
3171 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3172 ARRAY_SIZE(wm8994_adc_widgets));
3173 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3174 ARRAY_SIZE(wm8994_dac_widgets));
3175 }
c4431df0
MB		 3176 break;
3177 }
3178
3179
f0fba2ad 3180 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3181 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3182
c4431df0
MB		 3183 switch (control->type) {
3184 case WM8994:
3185 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3186 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3187
173efa09 3188 if (wm8994->revision < 4) {
6ed8f148
MB		 3189 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3190 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3191 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3192 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3193 } else {
3194 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3195 ARRAY_SIZE(wm8994_lateclk_intercon));
3196 }
c4431df0
MB		 3197 break;
3198 case WM8958:
780e2806
MB		 3199 if (wm8994->revision < 1) {
3200 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3201 ARRAY_SIZE(wm8994_revd_intercon));
3202 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3203 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3204 } else {
3205 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3206 ARRAY_SIZE(wm8994_lateclk_intercon));
3207 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3208 ARRAY_SIZE(wm8958_intercon));
3209 }
f701a2e5
MB		 3210
3211 wm8958_dsp2_init(codec);
c4431df0
MB		 3212 break;
3213 }
3214
9e6e96a1
MB		 3215 return 0;
3216
88766984
MB		 3217err_irq:
3218 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3219 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3220 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3221 if (wm8994->micdet_irq)
3222 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932
MB		 3223 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3224 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3225 &wm8994->fll_locked[i]);
b30ead5f
MB		 3226 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3227 &wm8994->hubs);
3b1af3f8 3228 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
9e6e96a1
MB		 3229err:
3230 kfree(wm8994);
3231 return ret;
3232}
3233
f0fba2ad 3234static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3235{
f0fba2ad 3236 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3a423157 3237 struct wm8994 *control = codec->control_data;
c7ebf932 3238 int i;
9e6e96a1
MB		 3239
3240 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3241
39fb51a1
MB		 3242 pm_runtime_disable(codec->dev);
3243
c7ebf932
MB		 3244 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3245 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3246 &wm8994->fll_locked[i]);
3247
b30ead5f
MB		 3248 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3249 &wm8994->hubs);
3b1af3f8 3250 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
b30ead5f 3251
3a423157
MB		 3252 switch (control->type) {
3253 case WM8994:
9b7c525d
MB		 3254 if (wm8994->micdet_irq)
3255 free_irq(wm8994->micdet_irq, wm8994);
3a423157
MB		 3256 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3257 wm8994);
3258 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3259 wm8994);
3260 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3261 wm8994);
3262 break;
821edd2f
MB		 3263
3264 case WM8958:
9b7c525d
MB		 3265 if (wm8994->micdet_irq)
3266 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 3267 break;
3a423157 3268 }
fbbf5920
MB		 3269 if (wm8994->mbc)
3270 release_firmware(wm8994->mbc);
09e10d7f
MB		 3271 if (wm8994->mbc_vss)
3272 release_firmware(wm8994->mbc_vss);
31215871
MB		 3273 if (wm8994->enh_eq)
3274 release_firmware(wm8994->enh_eq);
24fb2b11
AL		 3275 kfree(wm8994->retune_mobile_texts);
3276 kfree(wm8994->drc_texts);
9e6e96a1 3277 kfree(wm8994);
9e6e96a1
MB		 3278
3279 return 0;
3280}
3281
f0fba2ad
LG		 3282static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3283 .probe = wm8994_codec_probe,
3284 .remove = wm8994_codec_remove,
3285 .suspend = wm8994_suspend,
3286 .resume = wm8994_resume,
ca9aef50
MB		 3287 .read = wm8994_read,
3288 .write = wm8994_write,
eba19fdd
MB		 3289 .readable_register = wm8994_readable,
3290 .volatile_register = wm8994_volatile,
f0fba2ad 3291 .set_bias_level = wm8994_set_bias_level,
ca9aef50
MB		 3292
3293 .reg_cache_size = WM8994_CACHE_SIZE,
3294 .reg_cache_default = wm8994_reg_defaults,
3295 .reg_word_size = 2,
2e19b0c8 3296 .compress_type = SND_SOC_RBTREE_COMPRESSION,
f0fba2ad
LG		 3297};
3298
3299static int __devinit wm8994_probe(struct platform_device *pdev)
3300{
3301 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3302 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3303}
3304
3305static int __devexit wm8994_remove(struct platform_device *pdev)
3306{
3307 snd_soc_unregister_codec(&pdev->dev);
3308 return 0;
3309}
3310
9e6e96a1
MB		 3311static struct platform_driver wm8994_codec_driver = {
3312 .driver = {
3313 .name = "wm8994-codec",
3314 .owner = THIS_MODULE,
3315 },
f0fba2ad
LG		 3316 .probe = wm8994_probe,
3317 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3318};
3319
3320static __init int wm8994_init(void)
3321{
3322 return platform_driver_register(&wm8994_codec_driver);
3323}
3324module_init(wm8994_init);
3325
3326static __exit void wm8994_exit(void)
3327{
3328 platform_driver_unregister(&wm8994_codec_driver);
3329}
3330module_exit(wm8994_exit);
3331
3332
3333MODULE_DESCRIPTION("ASoC WM8994 driver");
3334MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3335MODULE_LICENSE("GPL");
3336MODULE_ALIAS("platform:wm8994-codec");
Linux 6.x block layer and io_uring tree(s)