projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: Add VMID widget for wm_hubs devices
[linux-2.6-block.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
9e6e96a1
MB		 41#define WM8994_NUM_DRC 3
42#define WM8994_NUM_EQ 3
43
44static int wm8994_drc_base[] = {
45 WM8994_AIF1_DRC1_1,
46 WM8994_AIF1_DRC2_1,
47 WM8994_AIF2_DRC_1,
48};
49
50static int wm8994_retune_mobile_base[] = {
51 WM8994_AIF1_DAC1_EQ_GAINS_1,
52 WM8994_AIF1_DAC2_EQ_GAINS_1,
53 WM8994_AIF2_EQ_GAINS_1,
54};
55
d4754ec9 56static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
9e6e96a1 57{
af9af866
MB		 58 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
59 struct wm8994 *control = wm8994->control_data;
60
e88ff1e6
MB		 61 switch (reg) {
62 case WM8994_GPIO_1:
63 case WM8994_GPIO_2:
64 case WM8994_GPIO_3:
65 case WM8994_GPIO_4:
66 case WM8994_GPIO_5:
67 case WM8994_GPIO_6:
68 case WM8994_GPIO_7:
69 case WM8994_GPIO_8:
70 case WM8994_GPIO_9:
71 case WM8994_GPIO_10:
72 case WM8994_GPIO_11:
73 case WM8994_INTERRUPT_STATUS_1:
74 case WM8994_INTERRUPT_STATUS_2:
75 case WM8994_INTERRUPT_RAW_STATUS_2:
76 return 1;
af9af866
MB		 77
78 case WM8958_DSP2_PROGRAM:
79 case WM8958_DSP2_CONFIG:
80 case WM8958_DSP2_EXECCONTROL:
81 if (control->type == WM8958)
82 return 1;
83 else
84 return 0;
85
e88ff1e6
MB		 86 default:
87 break;
88 }
89
7b306dae 90 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1 91 return 0;
7b306dae 92 return wm8994_access_masks[reg].readable != 0;
9e6e96a1
MB		 93}
94
d4754ec9 95static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
9e6e96a1 96{
ca9aef50 97 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1
MB		 98 return 1;
99
100 switch (reg) {
101 case WM8994_SOFTWARE_RESET:
102 case WM8994_CHIP_REVISION:
103 case WM8994_DC_SERVO_1:
104 case WM8994_DC_SERVO_READBACK:
105 case WM8994_RATE_STATUS:
106 case WM8994_LDO_1:
107 case WM8994_LDO_2:
d6addcc9 108 case WM8958_DSP2_EXECCONTROL:
821edd2f 109 case WM8958_MIC_DETECT_3:
79ef0abc 110 case WM8994_DC_SERVO_4E:
9e6e96a1
MB		 111 return 1;
112 default:
113 return 0;
114 }
115}
116
117static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
118 unsigned int value)
119{
ca9aef50 120 int ret;
9e6e96a1
MB		 121
122 BUG_ON(reg > WM8994_MAX_REGISTER);
123
d4754ec9 124 if (!wm8994_volatile(codec, reg)) {
ca9aef50
MB		 125 ret = snd_soc_cache_write(codec, reg, value);
126 if (ret != 0)
127 dev_err(codec->dev, "Cache write to %x failed: %d\n",
128 reg, ret);
129 }
9e6e96a1
MB		 130
131 return wm8994_reg_write(codec->control_data, reg, value);
132}
133
134static unsigned int wm8994_read(struct snd_soc_codec *codec,
135 unsigned int reg)
136{
ca9aef50
MB		 137 unsigned int val;
138 int ret;
9e6e96a1
MB		 139
140 BUG_ON(reg > WM8994_MAX_REGISTER);
141
d4754ec9 142 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
ca9aef50
MB		 143 reg < codec->driver->reg_cache_size) {
144 ret = snd_soc_cache_read(codec, reg, &val);
145 if (ret >= 0)
146 return val;
147 else
148 dev_err(codec->dev, "Cache read from %x failed: %d\n",
149 reg, ret);
150 }
151
152 return wm8994_reg_read(codec->control_data, reg);
9e6e96a1
MB		 153}
154
155static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
156{
b2c812e2 157 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 158 int rate;
159 int reg1 = 0;
160 int offset;
161
162 if (aif)
163 offset = 4;
164 else
165 offset = 0;
166
167 switch (wm8994->sysclk[aif]) {
168 case WM8994_SYSCLK_MCLK1:
169 rate = wm8994->mclk[0];
170 break;
171
172 case WM8994_SYSCLK_MCLK2:
173 reg1 |= 0x8;
174 rate = wm8994->mclk[1];
175 break;
176
177 case WM8994_SYSCLK_FLL1:
178 reg1 |= 0x10;
179 rate = wm8994->fll[0].out;
180 break;
181
182 case WM8994_SYSCLK_FLL2:
183 reg1 |= 0x18;
184 rate = wm8994->fll[1].out;
185 break;
186
187 default:
188 return -EINVAL;
189 }
190
191 if (rate >= 13500000) {
192 rate /= 2;
193 reg1 |= WM8994_AIF1CLK_DIV;
194
195 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
196 aif + 1, rate);
197 }
5e5e2bef 198
9e6e96a1
MB		 199 wm8994->aifclk[aif] = rate;
200
201 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
202 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
203 reg1);
204
205 return 0;
206}
207
208static int configure_clock(struct snd_soc_codec *codec)
209{
b2c812e2 210 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 211 int old, new;
212
213 /* Bring up the AIF clocks first */
214 configure_aif_clock(codec, 0);
215 configure_aif_clock(codec, 1);
216
217 /* Then switch CLK_SYS over to the higher of them; a change
218 * can only happen as a result of a clocking change which can
219 * only be made outside of DAPM so we can safely redo the
220 * clocking.
221 */
222
223 /* If they're equal it doesn't matter which is used */
224 if (wm8994->aifclk[0] == wm8994->aifclk[1])
225 return 0;
226
227 if (wm8994->aifclk[0] < wm8994->aifclk[1])
228 new = WM8994_SYSCLK_SRC;
229 else
230 new = 0;
231
232 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
233
234 /* If there's no change then we're done. */
235 if (old == new)
236 return 0;
237
238 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
239
ce6120cc 240 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1
MB		 241
242 return 0;
243}
244
245static int check_clk_sys(struct snd_soc_dapm_widget *source,
246 struct snd_soc_dapm_widget *sink)
247{
248 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
249 const char *clk;
250
251 /* Check what we're currently using for CLK_SYS */
252 if (reg & WM8994_SYSCLK_SRC)
253 clk = "AIF2CLK";
254 else
255 clk = "AIF1CLK";
256
257 return strcmp(source->name, clk) == 0;
258}
259
260static const char *sidetone_hpf_text[] = {
261 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
262};
263
264static const struct soc_enum sidetone_hpf =
265 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
266
146fd574
UK		 267static const char *adc_hpf_text[] = {
268 "HiFi", "Voice 1", "Voice 2", "Voice 3"
269};
270
271static const struct soc_enum aif1adc1_hpf =
272 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
273
274static const struct soc_enum aif1adc2_hpf =
275 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
276
277static const struct soc_enum aif2adc_hpf =
278 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
279
9e6e96a1
MB		 280static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
281static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
282static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
283static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
284static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
285
286#define WM8994_DRC_SWITCH(xname, reg, shift) \
287{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
288 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
289 .put = wm8994_put_drc_sw, \
290 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
291
292static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
293 struct snd_ctl_elem_value *ucontrol)
294{
295 struct soc_mixer_control *mc =
296 (struct soc_mixer_control *)kcontrol->private_value;
297 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
298 int mask, ret;
299
300 /* Can't enable both ADC and DAC paths simultaneously */
301 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
302 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
303 WM8994_AIF1ADC1R_DRC_ENA_MASK;
304 else
305 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
306
307 ret = snd_soc_read(codec, mc->reg);
308 if (ret < 0)
309 return ret;
310 if (ret & mask)
311 return -EINVAL;
312
313 return snd_soc_put_volsw(kcontrol, ucontrol);
314}
315
9e6e96a1
MB		 316static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
317{
b2c812e2 318 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 319 struct wm8994_pdata *pdata = wm8994->pdata;
320 int base = wm8994_drc_base[drc];
321 int cfg = wm8994->drc_cfg[drc];
322 int save, i;
323
324 /* Save any enables; the configuration should clear them. */
325 save = snd_soc_read(codec, base);
326 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
327 WM8994_AIF1ADC1R_DRC_ENA;
328
329 for (i = 0; i < WM8994_DRC_REGS; i++)
330 snd_soc_update_bits(codec, base + i, 0xffff,
331 pdata->drc_cfgs[cfg].regs[i]);
332
333 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
334 WM8994_AIF1ADC1L_DRC_ENA |
335 WM8994_AIF1ADC1R_DRC_ENA, save);
336}
337
338/* Icky as hell but saves code duplication */
339static int wm8994_get_drc(const char *name)
340{
341 if (strcmp(name, "AIF1DRC1 Mode") == 0)
342 return 0;
343 if (strcmp(name, "AIF1DRC2 Mode") == 0)
344 return 1;
345 if (strcmp(name, "AIF2DRC Mode") == 0)
346 return 2;
347 return -EINVAL;
348}
349
350static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
351 struct snd_ctl_elem_value *ucontrol)
352{
353 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 354 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 355 struct wm8994_pdata *pdata = wm8994->pdata;
356 int drc = wm8994_get_drc(kcontrol->id.name);
357 int value = ucontrol->value.integer.value[0];
358
359 if (drc < 0)
360 return drc;
361
362 if (value >= pdata->num_drc_cfgs)
363 return -EINVAL;
364
365 wm8994->drc_cfg[drc] = value;
366
367 wm8994_set_drc(codec, drc);
368
369 return 0;
370}
371
372static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
373 struct snd_ctl_elem_value *ucontrol)
374{
375 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 376 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 377 int drc = wm8994_get_drc(kcontrol->id.name);
378
379 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
380
381 return 0;
382}
383
384static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
385{
b2c812e2 386 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 387 struct wm8994_pdata *pdata = wm8994->pdata;
388 int base = wm8994_retune_mobile_base[block];
389 int iface, best, best_val, save, i, cfg;
390
391 if (!pdata || !wm8994->num_retune_mobile_texts)
392 return;
393
394 switch (block) {
395 case 0:
396 case 1:
397 iface = 0;
398 break;
399 case 2:
400 iface = 1;
401 break;
402 default:
403 return;
404 }
405
406 /* Find the version of the currently selected configuration
407 * with the nearest sample rate. */
408 cfg = wm8994->retune_mobile_cfg[block];
409 best = 0;
410 best_val = INT_MAX;
411 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
412 if (strcmp(pdata->retune_mobile_cfgs[i].name,
413 wm8994->retune_mobile_texts[cfg]) == 0 &&
414 abs(pdata->retune_mobile_cfgs[i].rate
415 - wm8994->dac_rates[iface]) < best_val) {
416 best = i;
417 best_val = abs(pdata->retune_mobile_cfgs[i].rate
418 - wm8994->dac_rates[iface]);
419 }
420 }
421
422 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
423 block,
424 pdata->retune_mobile_cfgs[best].name,
425 pdata->retune_mobile_cfgs[best].rate,
426 wm8994->dac_rates[iface]);
427
428 /* The EQ will be disabled while reconfiguring it, remember the
429 * current configuration.
430 */
431 save = snd_soc_read(codec, base);
432 save &= WM8994_AIF1DAC1_EQ_ENA;
433
434 for (i = 0; i < WM8994_EQ_REGS; i++)
435 snd_soc_update_bits(codec, base + i, 0xffff,
436 pdata->retune_mobile_cfgs[best].regs[i]);
437
438 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
439}
440
441/* Icky as hell but saves code duplication */
442static int wm8994_get_retune_mobile_block(const char *name)
443{
444 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
445 return 0;
446 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
447 return 1;
448 if (strcmp(name, "AIF2 EQ Mode") == 0)
449 return 2;
450 return -EINVAL;
451}
452
453static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
454 struct snd_ctl_elem_value *ucontrol)
455{
456 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 457 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 458 struct wm8994_pdata *pdata = wm8994->pdata;
459 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
460 int value = ucontrol->value.integer.value[0];
461
462 if (block < 0)
463 return block;
464
465 if (value >= pdata->num_retune_mobile_cfgs)
466 return -EINVAL;
467
468 wm8994->retune_mobile_cfg[block] = value;
469
470 wm8994_set_retune_mobile(codec, block);
471
472 return 0;
473}
474
475static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
476 struct snd_ctl_elem_value *ucontrol)
477{
478 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 479 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 480 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
481
482 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
483
484 return 0;
485}
486
96b101ef 487static const char *aif_chan_src_text[] = {
f554885f
MB		 488 "Left", "Right"
489};
490
96b101ef
MB		 491static const struct soc_enum aif1adcl_src =
492 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
493
494static const struct soc_enum aif1adcr_src =
495 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
496
497static const struct soc_enum aif2adcl_src =
498 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
499
500static const struct soc_enum aif2adcr_src =
501 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
502
f554885f 503static const struct soc_enum aif1dacl_src =
96b101ef 504 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 505
506static const struct soc_enum aif1dacr_src =
96b101ef 507 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 508
509static const struct soc_enum aif2dacl_src =
96b101ef 510 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 511
512static const struct soc_enum aif2dacr_src =
96b101ef 513 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 514
154b26aa
MB		 515static const char *osr_text[] = {
516 "Low Power", "High Performance",
517};
518
519static const struct soc_enum dac_osr =
520 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
521
522static const struct soc_enum adc_osr =
523 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
524
9e6e96a1
MB		 525static const struct snd_kcontrol_new wm8994_snd_controls[] = {
526SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
527 WM8994_AIF1_ADC1_RIGHT_VOLUME,
528 1, 119, 0, digital_tlv),
529SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
530 WM8994_AIF1_ADC2_RIGHT_VOLUME,
531 1, 119, 0, digital_tlv),
532SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
533 WM8994_AIF2_ADC_RIGHT_VOLUME,
534 1, 119, 0, digital_tlv),
535
96b101ef
MB		 536SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
537SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 538SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
539SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 540
f554885f
MB		 541SOC_ENUM("AIF1DACL Source", aif1dacl_src),
542SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 543SOC_ENUM("AIF2DACL Source", aif2dacl_src),
544SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 545
9e6e96a1
MB		 546SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
547 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
548SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
549 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
550SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
551 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
552
553SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
554SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
555
556SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
557SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
558SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
559
560WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
561WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
562WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
563
564WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
565WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
566WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
567
568WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
569WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
570WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
571
572SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
573 5, 12, 0, st_tlv),
574SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
575 0, 12, 0, st_tlv),
576SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
577 5, 12, 0, st_tlv),
578SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
579 0, 12, 0, st_tlv),
580SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
581SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
582
146fd574
UK		 583SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
584SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
585
586SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
587SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
588
589SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
590SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
591
154b26aa
MB		 592SOC_ENUM("ADC OSR", adc_osr),
593SOC_ENUM("DAC OSR", dac_osr),
594
9e6e96a1
MB		 595SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
596 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
597SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
598 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
599
600SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
601 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
602SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
603 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
604
605SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
606 6, 1, 1, wm_hubs_spkmix_tlv),
607SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
608 2, 1, 1, wm_hubs_spkmix_tlv),
609
610SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
611 6, 1, 1, wm_hubs_spkmix_tlv),
612SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
613 2, 1, 1, wm_hubs_spkmix_tlv),
614
615SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
616 10, 15, 0, wm8994_3d_tlv),
458350b3 617SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 618 8, 1, 0),
619SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
620 10, 15, 0, wm8994_3d_tlv),
621SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
622 8, 1, 0),
458350b3 623SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 624 10, 15, 0, wm8994_3d_tlv),
458350b3 625SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 626 8, 1, 0),
627};
628
629static const struct snd_kcontrol_new wm8994_eq_controls[] = {
630SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
631 eq_tlv),
632SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
633 eq_tlv),
634SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
635 eq_tlv),
636SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
637 eq_tlv),
638SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
639 eq_tlv),
640
641SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
642 eq_tlv),
643SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
644 eq_tlv),
645SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
646 eq_tlv),
647SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
648 eq_tlv),
649SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
650 eq_tlv),
651
652SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
653 eq_tlv),
654SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
655 eq_tlv),
656SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
657 eq_tlv),
658SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
659 eq_tlv),
660SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
661 eq_tlv),
662};
663
c4431df0
MB		 664static const struct snd_kcontrol_new wm8958_snd_controls[] = {
665SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
666};
667
9e6e96a1
MB		 668static int clk_sys_event(struct snd_soc_dapm_widget *w,
669 struct snd_kcontrol *kcontrol, int event)
670{
671 struct snd_soc_codec *codec = w->codec;
672
673 switch (event) {
674 case SND_SOC_DAPM_PRE_PMU:
675 return configure_clock(codec);
676
677 case SND_SOC_DAPM_POST_PMD:
678 configure_clock(codec);
679 break;
680 }
681
682 return 0;
683}
684
685static void wm8994_update_class_w(struct snd_soc_codec *codec)
686{
fec6dd83 687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 688 int enable = 1;
689 int source = 0; /* GCC flow analysis can't track enable */
690 int reg, reg_r;
691
692 /* Only support direct DAC->headphone paths */
693 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
694 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 695 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 696 enable = 0;
697 }
698
699 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
700 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 701 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 702 enable = 0;
703 }
704
705 /* We also need the same setting for L/R and only one path */
706 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
707 switch (reg) {
708 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 709 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 710 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
711 break;
712 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 713 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 714 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
715 break;
716 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 717 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 718 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
719 break;
720 default:
ee839a21 721 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 722 enable = 0;
723 break;
724 }
725
726 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
727 if (reg_r != reg) {
ee839a21 728 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 729 enable = 0;
730 }
731
732 if (enable) {
733 dev_dbg(codec->dev, "Class W enabled\n");
734 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
735 WM8994_CP_DYN_PWR |
736 WM8994_CP_DYN_SRC_SEL_MASK,
737 source | WM8994_CP_DYN_PWR);
fec6dd83 738 wm8994->hubs.class_w = true;
9e6e96a1
MB		 739
740 } else {
741 dev_dbg(codec->dev, "Class W disabled\n");
742 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
743 WM8994_CP_DYN_PWR, 0);
fec6dd83 744 wm8994->hubs.class_w = false;
9e6e96a1
MB		 745 }
746}
747
173efa09
DP		 748static int late_enable_ev(struct snd_soc_dapm_widget *w,
749 struct snd_kcontrol *kcontrol, int event)
750{
751 struct snd_soc_codec *codec = w->codec;
752 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
753
754 switch (event) {
755 case SND_SOC_DAPM_PRE_PMU:
a3cff81a 756 if (wm8994->aif1clk_enable) {
173efa09
DP		 757 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
758 WM8994_AIF1CLK_ENA_MASK,
759 WM8994_AIF1CLK_ENA);
a3cff81a
DP		 760 wm8994->aif1clk_enable = 0;
761 }
762 if (wm8994->aif2clk_enable) {
173efa09
DP		 763 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
764 WM8994_AIF2CLK_ENA_MASK,
765 WM8994_AIF2CLK_ENA);
a3cff81a
DP		 766 wm8994->aif2clk_enable = 0;
767 }
173efa09
DP		 768 break;
769 }
770
c6b7b570
MB		 771 /* We may also have postponed startup of DSP, handle that. */
772 wm8958_aif_ev(w, kcontrol, event);
773
173efa09
DP		 774 return 0;
775}
776
777static int late_disable_ev(struct snd_soc_dapm_widget *w,
778 struct snd_kcontrol *kcontrol, int event)
779{
780 struct snd_soc_codec *codec = w->codec;
781 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
782
783 switch (event) {
784 case SND_SOC_DAPM_POST_PMD:
a3cff81a 785 if (wm8994->aif1clk_disable) {
173efa09
DP		 786 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
787 WM8994_AIF1CLK_ENA_MASK, 0);
a3cff81a 788 wm8994->aif1clk_disable = 0;
173efa09 789 }
a3cff81a 790 if (wm8994->aif2clk_disable) {
173efa09
DP		 791 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
792 WM8994_AIF2CLK_ENA_MASK, 0);
a3cff81a 793 wm8994->aif2clk_disable = 0;
173efa09
DP		 794 }
795 break;
796 }
797
798 return 0;
799}
800
801static int aif1clk_ev(struct snd_soc_dapm_widget *w,
802 struct snd_kcontrol *kcontrol, int event)
803{
804 struct snd_soc_codec *codec = w->codec;
805 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
806
807 switch (event) {
808 case SND_SOC_DAPM_PRE_PMU:
809 wm8994->aif1clk_enable = 1;
810 break;
a3cff81a
DP		 811 case SND_SOC_DAPM_POST_PMD:
812 wm8994->aif1clk_disable = 1;
813 break;
173efa09
DP		 814 }
815
816 return 0;
817}
818
819static int aif2clk_ev(struct snd_soc_dapm_widget *w,
820 struct snd_kcontrol *kcontrol, int event)
821{
822 struct snd_soc_codec *codec = w->codec;
823 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
824
825 switch (event) {
826 case SND_SOC_DAPM_PRE_PMU:
827 wm8994->aif2clk_enable = 1;
828 break;
a3cff81a
DP		 829 case SND_SOC_DAPM_POST_PMD:
830 wm8994->aif2clk_disable = 1;
831 break;
173efa09
DP		 832 }
833
834 return 0;
835}
836
04d28681
DP		 837static int adc_mux_ev(struct snd_soc_dapm_widget *w,
838 struct snd_kcontrol *kcontrol, int event)
839{
840 late_enable_ev(w, kcontrol, event);
841 return 0;
842}
843
b462c6e6
DP		 844static int micbias_ev(struct snd_soc_dapm_widget *w,
845 struct snd_kcontrol *kcontrol, int event)
846{
847 late_enable_ev(w, kcontrol, event);
848 return 0;
849}
850
c52fd021
DP		 851static int dac_ev(struct snd_soc_dapm_widget *w,
852 struct snd_kcontrol *kcontrol, int event)
853{
854 struct snd_soc_codec *codec = w->codec;
855 unsigned int mask = 1 << w->shift;
856
857 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
858 mask, mask);
859 return 0;
860}
861
9e6e96a1
MB		 862static const char *hp_mux_text[] = {
863 "Mixer",
864 "DAC",
865};
866
867#define WM8994_HP_ENUM(xname, xenum) \
868{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
869 .info = snd_soc_info_enum_double, \
870 .get = snd_soc_dapm_get_enum_double, \
871 .put = wm8994_put_hp_enum, \
872 .private_value = (unsigned long)&xenum }
873
874static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
875 struct snd_ctl_elem_value *ucontrol)
876{
9d03545d
JN		 877 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
878 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 879 struct snd_soc_codec *codec = w->codec;
880 int ret;
881
882 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
883
884 wm8994_update_class_w(codec);
885
886 return ret;
887}
888
889static const struct soc_enum hpl_enum =
890 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
891
892static const struct snd_kcontrol_new hpl_mux =
893 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
894
895static const struct soc_enum hpr_enum =
896 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
897
898static const struct snd_kcontrol_new hpr_mux =
899 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
900
901static const char *adc_mux_text[] = {
902 "ADC",
903 "DMIC",
904};
905
906static const struct soc_enum adc_enum =
907 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
908
909static const struct snd_kcontrol_new adcl_mux =
910 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
911
912static const struct snd_kcontrol_new adcr_mux =
913 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
914
915static const struct snd_kcontrol_new left_speaker_mixer[] = {
916SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
917SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
918SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
919SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
920SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
921};
922
923static const struct snd_kcontrol_new right_speaker_mixer[] = {
924SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
925SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
926SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
927SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
928SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
929};
930
931/* Debugging; dump chip status after DAPM transitions */
932static int post_ev(struct snd_soc_dapm_widget *w,
933 struct snd_kcontrol *kcontrol, int event)
934{
935 struct snd_soc_codec *codec = w->codec;
936 dev_dbg(codec->dev, "SRC status: %x\n",
937 snd_soc_read(codec,
938 WM8994_RATE_STATUS));
939 return 0;
940}
941
942static const struct snd_kcontrol_new aif1adc1l_mix[] = {
943SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
944 1, 1, 0),
945SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
946 0, 1, 0),
947};
948
949static const struct snd_kcontrol_new aif1adc1r_mix[] = {
950SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
951 1, 1, 0),
952SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
953 0, 1, 0),
954};
955
a3257ba8
MB		 956static const struct snd_kcontrol_new aif1adc2l_mix[] = {
957SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
958 1, 1, 0),
959SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
960 0, 1, 0),
961};
962
963static const struct snd_kcontrol_new aif1adc2r_mix[] = {
964SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
965 1, 1, 0),
966SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
967 0, 1, 0),
968};
969
9e6e96a1
MB		 970static const struct snd_kcontrol_new aif2dac2l_mix[] = {
971SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
972 5, 1, 0),
973SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
974 4, 1, 0),
975SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
976 2, 1, 0),
977SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
978 1, 1, 0),
979SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
980 0, 1, 0),
981};
982
983static const struct snd_kcontrol_new aif2dac2r_mix[] = {
984SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
985 5, 1, 0),
986SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
987 4, 1, 0),
988SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
989 2, 1, 0),
990SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
991 1, 1, 0),
992SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
993 0, 1, 0),
994};
995
996#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
997{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
998 .info = snd_soc_info_volsw, \
999 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1000 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1001
1002static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1003 struct snd_ctl_elem_value *ucontrol)
1004{
9d03545d
JN		 1005 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1006 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1007 struct snd_soc_codec *codec = w->codec;
1008 int ret;
1009
1010 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1011
1012 wm8994_update_class_w(codec);
1013
1014 return ret;
1015}
1016
1017static const struct snd_kcontrol_new dac1l_mix[] = {
1018WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1019 5, 1, 0),
1020WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1021 4, 1, 0),
1022WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1023 2, 1, 0),
1024WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1025 1, 1, 0),
1026WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1027 0, 1, 0),
1028};
1029
1030static const struct snd_kcontrol_new dac1r_mix[] = {
1031WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1032 5, 1, 0),
1033WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1034 4, 1, 0),
1035WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1036 2, 1, 0),
1037WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1038 1, 1, 0),
1039WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1040 0, 1, 0),
1041};
1042
1043static const char *sidetone_text[] = {
1044 "ADC/DMIC1", "DMIC2",
1045};
1046
1047static const struct soc_enum sidetone1_enum =
1048 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1049
1050static const struct snd_kcontrol_new sidetone1_mux =
1051 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1052
1053static const struct soc_enum sidetone2_enum =
1054 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1055
1056static const struct snd_kcontrol_new sidetone2_mux =
1057 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1058
1059static const char *aif1dac_text[] = {
1060 "AIF1DACDAT", "AIF3DACDAT",
1061};
1062
1063static const struct soc_enum aif1dac_enum =
1064 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1065
1066static const struct snd_kcontrol_new aif1dac_mux =
1067 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1068
1069static const char *aif2dac_text[] = {
1070 "AIF2DACDAT", "AIF3DACDAT",
1071};
1072
1073static const struct soc_enum aif2dac_enum =
1074 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1075
1076static const struct snd_kcontrol_new aif2dac_mux =
1077 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1078
1079static const char *aif2adc_text[] = {
1080 "AIF2ADCDAT", "AIF3DACDAT",
1081};
1082
1083static const struct soc_enum aif2adc_enum =
1084 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1085
1086static const struct snd_kcontrol_new aif2adc_mux =
1087 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1088
1089static const char *aif3adc_text[] = {
c4431df0 1090 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1091};
1092
c4431df0 1093static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1094 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1095
c4431df0
MB		 1096static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1097 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1098
1099static const struct soc_enum wm8958_aif3adc_enum =
1100 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1101
1102static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1103 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1104
1105static const char *mono_pcm_out_text[] = {
1106 "None", "AIF2ADCL", "AIF2ADCR",
1107};
1108
1109static const struct soc_enum mono_pcm_out_enum =
1110 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1111
1112static const struct snd_kcontrol_new mono_pcm_out_mux =
1113 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1114
1115static const char *aif2dac_src_text[] = {
1116 "AIF2", "AIF3",
1117};
1118
1119/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1120static const struct soc_enum aif2dacl_src_enum =
1121 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1122
1123static const struct snd_kcontrol_new aif2dacl_src_mux =
1124 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1125
1126static const struct soc_enum aif2dacr_src_enum =
1127 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1128
1129static const struct snd_kcontrol_new aif2dacr_src_mux =
1130 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1131
173efa09
DP		 1132static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1133SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1134 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1135SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1136 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1137
1138SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1139 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1140SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1141 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1142SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1143 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1144SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1145 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1146SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1147 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1148
1149SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1150 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1151 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1152SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1153 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1154 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1155SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1156 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1157SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1158 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1159
1160SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1161};
1162
1163static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1164SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
b70a51ba
MB		 1165SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1166SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1167SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1168 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1169SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1170 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1171SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1172SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
173efa09
DP		 1173};
1174
c52fd021
DP		 1175static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1176SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1177 dac_ev, SND_SOC_DAPM_PRE_PMU),
1178SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1179 dac_ev, SND_SOC_DAPM_PRE_PMU),
1180SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1181 dac_ev, SND_SOC_DAPM_PRE_PMU),
1182SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1183 dac_ev, SND_SOC_DAPM_PRE_PMU),
1184};
1185
1186static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1187SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1188SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1189SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1190SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1191};
1192
04d28681
DP		 1193static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1194SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1195 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1196SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1197 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1198};
1199
1200static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1201SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1202SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1203};
1204
9e6e96a1
MB		 1205static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1206SND_SOC_DAPM_INPUT("DMIC1DAT"),
1207SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1208SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1209
b462c6e6
DP		 1210SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1211 SND_SOC_DAPM_PRE_PMU),
4e04adaf 1212SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0),
b462c6e6 1213
9e6e96a1
MB		 1214SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1215 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1216
1217SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1218SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1219SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1220
7f94de48 1221SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1222 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1223SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1224 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1225SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1226 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1227 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1228SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1229 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1230 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1231
7f94de48 1232SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1233 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1234SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1235 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1236SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1237 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1238 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1239SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1240 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1241 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1242
1243SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1244 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1245SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1246 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1247
a3257ba8
MB		 1248SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1249 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1250SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1251 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1252
9e6e96a1
MB		 1253SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1254 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1255SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1256 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1257
1258SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1259SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1260
1261SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1262 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1263SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1264 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1265
1266SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1267 WM8994_POWER_MANAGEMENT_4, 13, 0),
1268SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1269 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1270SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1271 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1272 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1273SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1274 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1275 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1276
1277SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1278SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
7f94de48 1279SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1280SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1281
1282SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1283SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1284SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1285
1286SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1287SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1288
1289SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1290
1291SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1292SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1293SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1294SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1295
1296/* Power is done with the muxes since the ADC power also controls the
1297 * downsampling chain, the chip will automatically manage the analogue
1298 * specific portions.
1299 */
1300SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1301SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1302
9e6e96a1
MB		 1303SND_SOC_DAPM_POST("Debug log", post_ev),
1304};
1305
c4431df0
MB		 1306static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1307SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1308};
9e6e96a1 1309
c4431df0
MB		 1310static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1311SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1312SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1313SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1314SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1315};
1316
1317static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1318 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1319 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1320
1321 { "DSP1CLK", NULL, "CLK_SYS" },
1322 { "DSP2CLK", NULL, "CLK_SYS" },
1323 { "DSPINTCLK", NULL, "CLK_SYS" },
1324
1325 { "AIF1ADC1L", NULL, "AIF1CLK" },
1326 { "AIF1ADC1L", NULL, "DSP1CLK" },
1327 { "AIF1ADC1R", NULL, "AIF1CLK" },
1328 { "AIF1ADC1R", NULL, "DSP1CLK" },
1329 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1330
1331 { "AIF1DAC1L", NULL, "AIF1CLK" },
1332 { "AIF1DAC1L", NULL, "DSP1CLK" },
1333 { "AIF1DAC1R", NULL, "AIF1CLK" },
1334 { "AIF1DAC1R", NULL, "DSP1CLK" },
1335 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1336
1337 { "AIF1ADC2L", NULL, "AIF1CLK" },
1338 { "AIF1ADC2L", NULL, "DSP1CLK" },
1339 { "AIF1ADC2R", NULL, "AIF1CLK" },
1340 { "AIF1ADC2R", NULL, "DSP1CLK" },
1341 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1342
1343 { "AIF1DAC2L", NULL, "AIF1CLK" },
1344 { "AIF1DAC2L", NULL, "DSP1CLK" },
1345 { "AIF1DAC2R", NULL, "AIF1CLK" },
1346 { "AIF1DAC2R", NULL, "DSP1CLK" },
1347 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1348
1349 { "AIF2ADCL", NULL, "AIF2CLK" },
1350 { "AIF2ADCL", NULL, "DSP2CLK" },
1351 { "AIF2ADCR", NULL, "AIF2CLK" },
1352 { "AIF2ADCR", NULL, "DSP2CLK" },
1353 { "AIF2ADCR", NULL, "DSPINTCLK" },
1354
1355 { "AIF2DACL", NULL, "AIF2CLK" },
1356 { "AIF2DACL", NULL, "DSP2CLK" },
1357 { "AIF2DACR", NULL, "AIF2CLK" },
1358 { "AIF2DACR", NULL, "DSP2CLK" },
1359 { "AIF2DACR", NULL, "DSPINTCLK" },
1360
1361 { "DMIC1L", NULL, "DMIC1DAT" },
1362 { "DMIC1L", NULL, "CLK_SYS" },
1363 { "DMIC1R", NULL, "DMIC1DAT" },
1364 { "DMIC1R", NULL, "CLK_SYS" },
1365 { "DMIC2L", NULL, "DMIC2DAT" },
1366 { "DMIC2L", NULL, "CLK_SYS" },
1367 { "DMIC2R", NULL, "DMIC2DAT" },
1368 { "DMIC2R", NULL, "CLK_SYS" },
1369
1370 { "ADCL", NULL, "AIF1CLK" },
1371 { "ADCL", NULL, "DSP1CLK" },
1372 { "ADCL", NULL, "DSPINTCLK" },
1373
1374 { "ADCR", NULL, "AIF1CLK" },
1375 { "ADCR", NULL, "DSP1CLK" },
1376 { "ADCR", NULL, "DSPINTCLK" },
1377
1378 { "ADCL Mux", "ADC", "ADCL" },
1379 { "ADCL Mux", "DMIC", "DMIC1L" },
1380 { "ADCR Mux", "ADC", "ADCR" },
1381 { "ADCR Mux", "DMIC", "DMIC1R" },
1382
1383 { "DAC1L", NULL, "AIF1CLK" },
1384 { "DAC1L", NULL, "DSP1CLK" },
1385 { "DAC1L", NULL, "DSPINTCLK" },
1386
1387 { "DAC1R", NULL, "AIF1CLK" },
1388 { "DAC1R", NULL, "DSP1CLK" },
1389 { "DAC1R", NULL, "DSPINTCLK" },
1390
1391 { "DAC2L", NULL, "AIF2CLK" },
1392 { "DAC2L", NULL, "DSP2CLK" },
1393 { "DAC2L", NULL, "DSPINTCLK" },
1394
1395 { "DAC2R", NULL, "AIF2DACR" },
1396 { "DAC2R", NULL, "AIF2CLK" },
1397 { "DAC2R", NULL, "DSP2CLK" },
1398 { "DAC2R", NULL, "DSPINTCLK" },
1399
1400 { "TOCLK", NULL, "CLK_SYS" },
1401
1402 /* AIF1 outputs */
1403 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1404 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1405 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1406
1407 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1408 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1409 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1410
a3257ba8
MB		 1411 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1412 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1413 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1414
1415 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1416 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1417 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1418
9e6e96a1
MB		 1419 /* Pin level routing for AIF3 */
1420 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1421 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1422 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1423 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1424
9e6e96a1
MB		 1425 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1426 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1427 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1428 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1429 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1430 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1431 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1432
1433 /* DAC1 inputs */
9e6e96a1
MB		 1434 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1435 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1436 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1437 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1438 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1439
9e6e96a1
MB		 1440 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1441 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1442 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1443 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1444 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1445
1446 /* DAC2/AIF2 outputs */
1447 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1448 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1449 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1450 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1451 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1452 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1453
1454 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1455 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1456 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1457 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1458 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1459 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1460
7f94de48
MB		 1461 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1462 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1463 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1464 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1465
9e6e96a1
MB		 1466 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1467
1468 /* AIF3 output */
1469 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1470 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1471 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1472 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1473 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1474 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1475 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1476 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1477
1478 /* Sidetone */
1479 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1480 { "Left Sidetone", "DMIC2", "DMIC2L" },
1481 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1482 { "Right Sidetone", "DMIC2", "DMIC2R" },
1483
1484 /* Output stages */
1485 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1486 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1487
1488 { "SPKL", "DAC1 Switch", "DAC1L" },
1489 { "SPKL", "DAC2 Switch", "DAC2L" },
1490
1491 { "SPKR", "DAC1 Switch", "DAC1R" },
1492 { "SPKR", "DAC2 Switch", "DAC2R" },
1493
1494 { "Left Headphone Mux", "DAC", "DAC1L" },
1495 { "Right Headphone Mux", "DAC", "DAC1R" },
1496};
1497
173efa09
DP		 1498static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1499 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1500 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1501 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1502 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1503 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1504 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1505 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1506 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1507};
1508
1509static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1510 { "DAC1L", NULL, "DAC1L Mixer" },
1511 { "DAC1R", NULL, "DAC1R Mixer" },
1512 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1513 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1514};
1515
6ed8f148
MB		 1516static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1517 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1518 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1519 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1520 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1521 { "MICBIAS1", NULL, "CLK_SYS" },
1522 { "MICBIAS1", NULL, "MICBIAS Supply" },
1523 { "MICBIAS2", NULL, "CLK_SYS" },
1524 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1525};
1526
c4431df0
MB		 1527static const struct snd_soc_dapm_route wm8994_intercon[] = {
1528 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1529 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1530 { "MICBIAS1", NULL, "VMID" },
1531 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1532};
1533
1534static const struct snd_soc_dapm_route wm8958_intercon[] = {
1535 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1536 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1537
1538 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1539 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1540 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1541 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1542
1543 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1544 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1545
1546 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1547};
1548
9e6e96a1
MB		 1549/* The size in bits of the FLL divide multiplied by 10
1550 * to allow rounding later */
1551#define FIXED_FLL_SIZE ((1 << 16) * 10)
1552
1553struct fll_div {
1554 u16 outdiv;
1555 u16 n;
1556 u16 k;
1557 u16 clk_ref_div;
1558 u16 fll_fratio;
1559};
1560
1561static int wm8994_get_fll_config(struct fll_div *fll,
1562 int freq_in, int freq_out)
1563{
1564 u64 Kpart;
1565 unsigned int K, Ndiv, Nmod;
1566
1567 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1568
1569 /* Scale the input frequency down to <= 13.5MHz */
1570 fll->clk_ref_div = 0;
1571 while (freq_in > 13500000) {
1572 fll->clk_ref_div++;
1573 freq_in /= 2;
1574
1575 if (fll->clk_ref_div > 3)
1576 return -EINVAL;
1577 }
1578 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1579
1580 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1581 fll->outdiv = 3;
1582 while (freq_out * (fll->outdiv + 1) < 90000000) {
1583 fll->outdiv++;
1584 if (fll->outdiv > 63)
1585 return -EINVAL;
1586 }
1587 freq_out *= fll->outdiv + 1;
1588 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1589
1590 if (freq_in > 1000000) {
1591 fll->fll_fratio = 0;
7d48a6ac
MB		 1592 } else if (freq_in > 256000) {
1593 fll->fll_fratio = 1;
1594 freq_in *= 2;
1595 } else if (freq_in > 128000) {
1596 fll->fll_fratio = 2;
1597 freq_in *= 4;
1598 } else if (freq_in > 64000) {
9e6e96a1
MB		 1599 fll->fll_fratio = 3;
1600 freq_in *= 8;
7d48a6ac
MB		 1601 } else {
1602 fll->fll_fratio = 4;
1603 freq_in *= 16;
9e6e96a1
MB		 1604 }
1605 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1606
1607 /* Now, calculate N.K */
1608 Ndiv = freq_out / freq_in;
1609
1610 fll->n = Ndiv;
1611 Nmod = freq_out % freq_in;
1612 pr_debug("Nmod=%d\n", Nmod);
1613
1614 /* Calculate fractional part - scale up so we can round. */
1615 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1616
1617 do_div(Kpart, freq_in);
1618
1619 K = Kpart & 0xFFFFFFFF;
1620
1621 if ((K % 10) >= 5)
1622 K += 5;
1623
1624 /* Move down to proper range now rounding is done */
1625 fll->k = K / 10;
1626
1627 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1628
1629 return 0;
1630}
1631
f0fba2ad 1632static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1633 unsigned int freq_in, unsigned int freq_out)
1634{
b2c812e2 1635 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 1636 int reg_offset, ret;
1637 struct fll_div fll;
1638 u16 reg, aif1, aif2;
c7ebf932 1639 unsigned long timeout;
9e6e96a1
MB		 1640
1641 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1642 & WM8994_AIF1CLK_ENA;
1643
1644 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1645 & WM8994_AIF2CLK_ENA;
1646
1647 switch (id) {
1648 case WM8994_FLL1:
1649 reg_offset = 0;
1650 id = 0;
1651 break;
1652 case WM8994_FLL2:
1653 reg_offset = 0x20;
1654 id = 1;
1655 break;
1656 default:
1657 return -EINVAL;
1658 }
1659
136ff2a2 1660 switch (src) {
7add84aa
MB		 1661 case 0:
1662 /* Allow no source specification when stopping */
1663 if (freq_out)
1664 return -EINVAL;
4514e899 1665 src = wm8994->fll[id].src;
7add84aa 1666 break;
136ff2a2
MB		 1667 case WM8994_FLL_SRC_MCLK1:
1668 case WM8994_FLL_SRC_MCLK2:
1669 case WM8994_FLL_SRC_LRCLK:
1670 case WM8994_FLL_SRC_BCLK:
1671 break;
1672 default:
1673 return -EINVAL;
1674 }
1675
9e6e96a1
MB		 1676 /* Are we changing anything? */
1677 if (wm8994->fll[id].src == src &&
1678 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1679 return 0;
1680
1681 /* If we're stopping the FLL redo the old config - no
1682 * registers will actually be written but we avoid GCC flow
1683 * analysis bugs spewing warnings.
1684 */
1685 if (freq_out)
1686 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1687 else
1688 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1689 wm8994->fll[id].out);
1690 if (ret < 0)
1691 return ret;
1692
1693 /* Gate the AIF clocks while we reclock */
1694 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1695 WM8994_AIF1CLK_ENA, 0);
1696 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1697 WM8994_AIF2CLK_ENA, 0);
1698
1699 /* We always need to disable the FLL while reconfiguring */
1700 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1701 WM8994_FLL1_ENA, 0);
1702
1703 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1704 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1705 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1706 WM8994_FLL1_OUTDIV_MASK |
1707 WM8994_FLL1_FRATIO_MASK, reg);
1708
1709 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1710
1711 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1712 WM8994_FLL1_N_MASK,
1713 fll.n << WM8994_FLL1_N_SHIFT);
1714
1715 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1716 WM8994_FLL1_REFCLK_DIV_MASK |
1717 WM8994_FLL1_REFCLK_SRC_MASK,
1718 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1719 (src - 1));
9e6e96a1 1720
f0f5039c
MB		 1721 /* Clear any pending completion from a previous failure */
1722 try_wait_for_completion(&wm8994->fll_locked[id]);
1723
9e6e96a1
MB		 1724 /* Enable (with fractional mode if required) */
1725 if (freq_out) {
1726 if (fll.k)
1727 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1728 else
1729 reg = WM8994_FLL1_ENA;
1730 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1731 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1732 reg);
8e9ddf81 1733
c7ebf932
MB		 1734 if (wm8994->fll_locked_irq) {
1735 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1736 msecs_to_jiffies(10));
1737 if (timeout == 0)
1738 dev_warn(codec->dev,
1739 "Timed out waiting for FLL lock\n");
1740 } else {
1741 msleep(5);
1742 }
9e6e96a1
MB		 1743 }
1744
1745 wm8994->fll[id].in = freq_in;
1746 wm8994->fll[id].out = freq_out;
136ff2a2 1747 wm8994->fll[id].src = src;
9e6e96a1
MB		 1748
1749 /* Enable any gated AIF clocks */
1750 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1751 WM8994_AIF1CLK_ENA, aif1);
1752 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1753 WM8994_AIF2CLK_ENA, aif2);
1754
1755 configure_clock(codec);
1756
1757 return 0;
1758}
1759
c7ebf932
MB		 1760static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1761{
1762 struct completion *completion = data;
1763
1764 complete(completion);
1765
1766 return IRQ_HANDLED;
1767}
f0fba2ad 1768
66b47fdb
MB		 1769static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1770
f0fba2ad
LG		 1771static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1772 unsigned int freq_in, unsigned int freq_out)
1773{
1774 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1775}
1776
9e6e96a1
MB		 1777static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1778 int clk_id, unsigned int freq, int dir)
1779{
1780 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1781 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 1782 int i;
9e6e96a1
MB		 1783
1784 switch (dai->id) {
1785 case 1:
1786 case 2:
1787 break;
1788
1789 default:
1790 /* AIF3 shares clocking with AIF1/2 */
1791 return -EINVAL;
1792 }
1793
1794 switch (clk_id) {
1795 case WM8994_SYSCLK_MCLK1:
1796 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1797 wm8994->mclk[0] = freq;
1798 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1799 dai->id, freq);
1800 break;
1801
1802 case WM8994_SYSCLK_MCLK2:
1803 /* TODO: Set GPIO AF */
1804 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1805 wm8994->mclk[1] = freq;
1806 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1807 dai->id, freq);
1808 break;
1809
1810 case WM8994_SYSCLK_FLL1:
1811 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1812 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1813 break;
1814
1815 case WM8994_SYSCLK_FLL2:
1816 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1817 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1818 break;
1819
66b47fdb
MB		 1820 case WM8994_SYSCLK_OPCLK:
1821 /* Special case - a division (times 10) is given and
1822 * no effect on main clocking.
1823 */
1824 if (freq) {
1825 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1826 if (opclk_divs[i] == freq)
1827 break;
1828 if (i == ARRAY_SIZE(opclk_divs))
1829 return -EINVAL;
1830 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1831 WM8994_OPCLK_DIV_MASK, i);
1832 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1833 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1834 } else {
1835 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1836 WM8994_OPCLK_ENA, 0);
1837 }
1838
9e6e96a1
MB		 1839 default:
1840 return -EINVAL;
1841 }
1842
1843 configure_clock(codec);
1844
1845 return 0;
1846}
1847
1848static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1849 enum snd_soc_bias_level level)
1850{
3a423157 1851 struct wm8994 *control = codec->control_data;
b6b05691
MB		 1852 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1853
9e6e96a1
MB		 1854 switch (level) {
1855 case SND_SOC_BIAS_ON:
1856 break;
1857
1858 case SND_SOC_BIAS_PREPARE:
1859 /* VMID=2x40k */
1860 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1861 WM8994_VMID_SEL_MASK, 0x2);
1862 break;
1863
1864 case SND_SOC_BIAS_STANDBY:
ce6120cc 1865 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
39fb51a1
MB		 1866 pm_runtime_get_sync(codec->dev);
1867
8bc3c2c2
MB		 1868 switch (control->type) {
1869 case WM8994:
1870 if (wm8994->revision < 4) {
1871 /* Tweak DC servo and DSP
1872 * configuration for improved
1873 * performance. */
1874 snd_soc_write(codec, 0x102, 0x3);
1875 snd_soc_write(codec, 0x56, 0x3);
1876 snd_soc_write(codec, 0x817, 0);
1877 snd_soc_write(codec, 0x102, 0);
1878 }
1879 break;
1880
1881 case WM8958:
1882 if (wm8994->revision == 0) {
1883 /* Optimise performance for rev A */
1884 snd_soc_write(codec, 0x102, 0x3);
1885 snd_soc_write(codec, 0xcb, 0x81);
1886 snd_soc_write(codec, 0x817, 0);
1887 snd_soc_write(codec, 0x102, 0);
1888
1889 snd_soc_update_bits(codec,
1890 WM8958_CHARGE_PUMP_2,
1891 WM8958_CP_DISCH,
1892 WM8958_CP_DISCH);
1893 }
1894 break;
b6b05691 1895 }
9e6e96a1
MB		 1896
1897 /* Discharge LINEOUT1 & 2 */
1898 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1899 WM8994_LINEOUT1_DISCH |
1900 WM8994_LINEOUT2_DISCH,
1901 WM8994_LINEOUT1_DISCH |
1902 WM8994_LINEOUT2_DISCH);
1903
1904 /* Startup bias, VMID ramp & buffer */
1905 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1906 WM8994_STARTUP_BIAS_ENA |
1907 WM8994_VMID_BUF_ENA |
1908 WM8994_VMID_RAMP_MASK,
1909 WM8994_STARTUP_BIAS_ENA |
1910 WM8994_VMID_BUF_ENA |
1911 (0x11 << WM8994_VMID_RAMP_SHIFT));
1912
1913 /* Main bias enable, VMID=2x40k */
1914 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1915 WM8994_BIAS_ENA |
1916 WM8994_VMID_SEL_MASK,
1917 WM8994_BIAS_ENA | 0x2);
1918
1919 msleep(20);
1920 }
1921
1922 /* VMID=2x500k */
1923 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1924 WM8994_VMID_SEL_MASK, 0x4);
1925
1926 break;
1927
1928 case SND_SOC_BIAS_OFF:
ce6120cc 1929 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
d522ffbf
MB		 1930 /* Switch over to startup biases */
1931 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1932 WM8994_BIAS_SRC |
1933 WM8994_STARTUP_BIAS_ENA |
1934 WM8994_VMID_BUF_ENA |
1935 WM8994_VMID_RAMP_MASK,
1936 WM8994_BIAS_SRC |
1937 WM8994_STARTUP_BIAS_ENA |
1938 WM8994_VMID_BUF_ENA |
1939 (1 << WM8994_VMID_RAMP_SHIFT));
9e6e96a1 1940
d522ffbf
MB		 1941 /* Disable main biases */
1942 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1943 WM8994_BIAS_ENA |
1944 WM8994_VMID_SEL_MASK, 0);
9e6e96a1 1945
d522ffbf
MB		 1946 /* Discharge line */
1947 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1948 WM8994_LINEOUT1_DISCH |
1949 WM8994_LINEOUT2_DISCH,
1950 WM8994_LINEOUT1_DISCH |
1951 WM8994_LINEOUT2_DISCH);
9e6e96a1 1952
d522ffbf 1953 msleep(5);
9e6e96a1 1954
d522ffbf
MB		 1955 /* Switch off startup biases */
1956 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1957 WM8994_BIAS_SRC |
1958 WM8994_STARTUP_BIAS_ENA |
1959 WM8994_VMID_BUF_ENA |
1960 WM8994_VMID_RAMP_MASK, 0);
39fb51a1 1961
fbbf5920
MB		 1962 wm8994->cur_fw = NULL;
1963
39fb51a1 1964 pm_runtime_put(codec->dev);
d522ffbf 1965 }
9e6e96a1
MB		 1966 break;
1967 }
ce6120cc 1968 codec->dapm.bias_level = level;
9e6e96a1
MB		 1969 return 0;
1970}
1971
1972static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1973{
1974 struct snd_soc_codec *codec = dai->codec;
c4431df0 1975 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 1976 int ms_reg;
1977 int aif1_reg;
1978 int ms = 0;
1979 int aif1 = 0;
1980
1981 switch (dai->id) {
1982 case 1:
1983 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1984 aif1_reg = WM8994_AIF1_CONTROL_1;
1985 break;
1986 case 2:
1987 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1988 aif1_reg = WM8994_AIF2_CONTROL_1;
1989 break;
1990 default:
1991 return -EINVAL;
1992 }
1993
1994 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1995 case SND_SOC_DAIFMT_CBS_CFS:
1996 break;
1997 case SND_SOC_DAIFMT_CBM_CFM:
1998 ms = WM8994_AIF1_MSTR;
1999 break;
2000 default:
2001 return -EINVAL;
2002 }
2003
2004 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2005 case SND_SOC_DAIFMT_DSP_B:
2006 aif1 |= WM8994_AIF1_LRCLK_INV;
2007 case SND_SOC_DAIFMT_DSP_A:
2008 aif1 |= 0x18;
2009 break;
2010 case SND_SOC_DAIFMT_I2S:
2011 aif1 |= 0x10;
2012 break;
2013 case SND_SOC_DAIFMT_RIGHT_J:
2014 break;
2015 case SND_SOC_DAIFMT_LEFT_J:
2016 aif1 |= 0x8;
2017 break;
2018 default:
2019 return -EINVAL;
2020 }
2021
2022 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2023 case SND_SOC_DAIFMT_DSP_A:
2024 case SND_SOC_DAIFMT_DSP_B:
2025 /* frame inversion not valid for DSP modes */
2026 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2027 case SND_SOC_DAIFMT_NB_NF:
2028 break;
2029 case SND_SOC_DAIFMT_IB_NF:
2030 aif1 |= WM8994_AIF1_BCLK_INV;
2031 break;
2032 default:
2033 return -EINVAL;
2034 }
2035 break;
2036
2037 case SND_SOC_DAIFMT_I2S:
2038 case SND_SOC_DAIFMT_RIGHT_J:
2039 case SND_SOC_DAIFMT_LEFT_J:
2040 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2041 case SND_SOC_DAIFMT_NB_NF:
2042 break;
2043 case SND_SOC_DAIFMT_IB_IF:
2044 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2045 break;
2046 case SND_SOC_DAIFMT_IB_NF:
2047 aif1 |= WM8994_AIF1_BCLK_INV;
2048 break;
2049 case SND_SOC_DAIFMT_NB_IF:
2050 aif1 |= WM8994_AIF1_LRCLK_INV;
2051 break;
2052 default:
2053 return -EINVAL;
2054 }
2055 break;
2056 default:
2057 return -EINVAL;
2058 }
2059
c4431df0
MB		 2060 /* The AIF2 format configuration needs to be mirrored to AIF3
2061 * on WM8958 if it's in use so just do it all the time. */
2062 if (control->type == WM8958 && dai->id == 2)
2063 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2064 WM8994_AIF1_LRCLK_INV |
2065 WM8958_AIF3_FMT_MASK, aif1);
2066
9e6e96a1
MB		 2067 snd_soc_update_bits(codec, aif1_reg,
2068 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2069 WM8994_AIF1_FMT_MASK,
2070 aif1);
2071 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2072 ms);
2073
2074 return 0;
2075}
2076
2077static struct {
2078 int val, rate;
2079} srs[] = {
2080 { 0, 8000 },
2081 { 1, 11025 },
2082 { 2, 12000 },
2083 { 3, 16000 },
2084 { 4, 22050 },
2085 { 5, 24000 },
2086 { 6, 32000 },
2087 { 7, 44100 },
2088 { 8, 48000 },
2089 { 9, 88200 },
2090 { 10, 96000 },
2091};
2092
2093static int fs_ratios[] = {
2094 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2095};
2096
2097static int bclk_divs[] = {
2098 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2099 640, 880, 960, 1280, 1760, 1920
2100};
2101
2102static int wm8994_hw_params(struct snd_pcm_substream *substream,
2103 struct snd_pcm_hw_params *params,
2104 struct snd_soc_dai *dai)
2105{
2106 struct snd_soc_codec *codec = dai->codec;
c4431df0 2107 struct wm8994 *control = codec->control_data;
b2c812e2 2108 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2109 int aif1_reg;
b1e43d93 2110 int aif2_reg;
9e6e96a1
MB		 2111 int bclk_reg;
2112 int lrclk_reg;
2113 int rate_reg;
2114 int aif1 = 0;
b1e43d93 2115 int aif2 = 0;
9e6e96a1
MB		 2116 int bclk = 0;
2117 int lrclk = 0;
2118 int rate_val = 0;
2119 int id = dai->id - 1;
2120
2121 int i, cur_val, best_val, bclk_rate, best;
2122
2123 switch (dai->id) {
2124 case 1:
2125 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2126 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2127 bclk_reg = WM8994_AIF1_BCLK;
2128 rate_reg = WM8994_AIF1_RATE;
2129 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2130 wm8994->lrclk_shared[0]) {
9e6e96a1 2131 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2132 } else {
9e6e96a1 2133 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2134 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2135 }
9e6e96a1
MB		 2136 break;
2137 case 2:
2138 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2139 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2140 bclk_reg = WM8994_AIF2_BCLK;
2141 rate_reg = WM8994_AIF2_RATE;
2142 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2143 wm8994->lrclk_shared[1]) {
9e6e96a1 2144 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2145 } else {
9e6e96a1 2146 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2147 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2148 }
9e6e96a1 2149 break;
c4431df0
MB		 2150 case 3:
2151 switch (control->type) {
2152 case WM8958:
2153 aif1_reg = WM8958_AIF3_CONTROL_1;
2154 break;
2155 default:
2156 return 0;
2157 }
9e6e96a1
MB		 2158 default:
2159 return -EINVAL;
2160 }
2161
2162 bclk_rate = params_rate(params) * 2;
2163 switch (params_format(params)) {
2164 case SNDRV_PCM_FORMAT_S16_LE:
2165 bclk_rate *= 16;
2166 break;
2167 case SNDRV_PCM_FORMAT_S20_3LE:
2168 bclk_rate *= 20;
2169 aif1 |= 0x20;
2170 break;
2171 case SNDRV_PCM_FORMAT_S24_LE:
2172 bclk_rate *= 24;
2173 aif1 |= 0x40;
2174 break;
2175 case SNDRV_PCM_FORMAT_S32_LE:
2176 bclk_rate *= 32;
2177 aif1 |= 0x60;
2178 break;
2179 default:
2180 return -EINVAL;
2181 }
2182
2183 /* Try to find an appropriate sample rate; look for an exact match. */
2184 for (i = 0; i < ARRAY_SIZE(srs); i++)
2185 if (srs[i].rate == params_rate(params))
2186 break;
2187 if (i == ARRAY_SIZE(srs))
2188 return -EINVAL;
2189 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2190
2191 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2192 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2193 dai->id, wm8994->aifclk[id], bclk_rate);
2194
b1e43d93
MB		 2195 if (params_channels(params) == 1 &&
2196 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2197 aif2 |= WM8994_AIF1_MONO;
2198
9e6e96a1
MB		 2199 if (wm8994->aifclk[id] == 0) {
2200 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2201 return -EINVAL;
2202 }
2203
2204 /* AIFCLK/fs ratio; look for a close match in either direction */
2205 best = 0;
2206 best_val = abs((fs_ratios[0] * params_rate(params))
2207 - wm8994->aifclk[id]);
2208 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2209 cur_val = abs((fs_ratios[i] * params_rate(params))
2210 - wm8994->aifclk[id]);
2211 if (cur_val >= best_val)
2212 continue;
2213 best = i;
2214 best_val = cur_val;
2215 }
2216 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2217 dai->id, fs_ratios[best]);
2218 rate_val |= best;
2219
2220 /* We may not get quite the right frequency if using
2221 * approximate clocks so look for the closest match that is
2222 * higher than the target (we need to ensure that there enough
2223 * BCLKs to clock out the samples).
2224 */
2225 best = 0;
2226 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2227 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2228 if (cur_val < 0) /* BCLK table is sorted */
2229 break;
2230 best = i;
2231 }
07cd8ada 2232 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2233 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2234 bclk_divs[best], bclk_rate);
2235 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2236
2237 lrclk = bclk_rate / params_rate(params);
2238 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2239 lrclk, bclk_rate / lrclk);
2240
2241 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2242 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2243 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2244 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2245 lrclk);
2246 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2247 WM8994_AIF1CLK_RATE_MASK, rate_val);
2248
2249 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2250 switch (dai->id) {
2251 case 1:
2252 wm8994->dac_rates[0] = params_rate(params);
2253 wm8994_set_retune_mobile(codec, 0);
2254 wm8994_set_retune_mobile(codec, 1);
2255 break;
2256 case 2:
2257 wm8994->dac_rates[1] = params_rate(params);
2258 wm8994_set_retune_mobile(codec, 2);
2259 break;
2260 }
2261 }
2262
2263 return 0;
2264}
2265
c4431df0
MB		 2266static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2267 struct snd_pcm_hw_params *params,
2268 struct snd_soc_dai *dai)
2269{
2270 struct snd_soc_codec *codec = dai->codec;
2271 struct wm8994 *control = codec->control_data;
2272 int aif1_reg;
2273 int aif1 = 0;
2274
2275 switch (dai->id) {
2276 case 3:
2277 switch (control->type) {
2278 case WM8958:
2279 aif1_reg = WM8958_AIF3_CONTROL_1;
2280 break;
2281 default:
2282 return 0;
2283 }
2284 default:
2285 return 0;
2286 }
2287
2288 switch (params_format(params)) {
2289 case SNDRV_PCM_FORMAT_S16_LE:
2290 break;
2291 case SNDRV_PCM_FORMAT_S20_3LE:
2292 aif1 |= 0x20;
2293 break;
2294 case SNDRV_PCM_FORMAT_S24_LE:
2295 aif1 |= 0x40;
2296 break;
2297 case SNDRV_PCM_FORMAT_S32_LE:
2298 aif1 |= 0x60;
2299 break;
2300 default:
2301 return -EINVAL;
2302 }
2303
2304 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2305}
2306
7d02173c
MB		 2307static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2308 struct snd_soc_dai *dai)
2309{
2310 struct snd_soc_codec *codec = dai->codec;
2311 int rate_reg = 0;
2312
2313 switch (dai->id) {
2314 case 1:
2315 rate_reg = WM8994_AIF1_RATE;
2316 break;
2317 case 2:
2318 rate_reg = WM8994_AIF1_RATE;
2319 break;
2320 default:
2321 break;
2322 }
2323
2324 /* If the DAI is idle then configure the divider tree for the
2325 * lowest output rate to save a little power if the clock is
2326 * still active (eg, because it is system clock).
2327 */
2328 if (rate_reg && !dai->playback_active && !dai->capture_active)
2329 snd_soc_update_bits(codec, rate_reg,
2330 WM8994_AIF1_SR_MASK |
2331 WM8994_AIF1CLK_RATE_MASK, 0x9);
2332}
2333
9e6e96a1
MB		 2334static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2335{
2336 struct snd_soc_codec *codec = codec_dai->codec;
2337 int mute_reg;
2338 int reg;
2339
2340 switch (codec_dai->id) {
2341 case 1:
2342 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2343 break;
2344 case 2:
2345 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2346 break;
2347 default:
2348 return -EINVAL;
2349 }
2350
2351 if (mute)
2352 reg = WM8994_AIF1DAC1_MUTE;
2353 else
2354 reg = 0;
2355
2356 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2357
2358 return 0;
2359}
2360
778a76e2
MB		 2361static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2362{
2363 struct snd_soc_codec *codec = codec_dai->codec;
2364 int reg, val, mask;
2365
2366 switch (codec_dai->id) {
2367 case 1:
2368 reg = WM8994_AIF1_MASTER_SLAVE;
2369 mask = WM8994_AIF1_TRI;
2370 break;
2371 case 2:
2372 reg = WM8994_AIF2_MASTER_SLAVE;
2373 mask = WM8994_AIF2_TRI;
2374 break;
2375 case 3:
2376 reg = WM8994_POWER_MANAGEMENT_6;
2377 mask = WM8994_AIF3_TRI;
2378 break;
2379 default:
2380 return -EINVAL;
2381 }
2382
2383 if (tristate)
2384 val = mask;
2385 else
2386 val = 0;
2387
78b3fb46 2388 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2389}
2390
9e6e96a1
MB		 2391#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2392
2393#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2394 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1
MB		 2395
2396static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2397 .set_sysclk = wm8994_set_dai_sysclk,
2398 .set_fmt = wm8994_set_dai_fmt,
2399 .hw_params = wm8994_hw_params,
7d02173c 2400 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2401 .digital_mute = wm8994_aif_mute,
2402 .set_pll = wm8994_set_fll,
778a76e2 2403 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2404};
2405
2406static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2407 .set_sysclk = wm8994_set_dai_sysclk,
2408 .set_fmt = wm8994_set_dai_fmt,
2409 .hw_params = wm8994_hw_params,
7d02173c 2410 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2411 .digital_mute = wm8994_aif_mute,
2412 .set_pll = wm8994_set_fll,
778a76e2
MB		 2413 .set_tristate = wm8994_set_tristate,
2414};
2415
2416static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2417 .hw_params = wm8994_aif3_hw_params,
778a76e2 2418 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2419};
2420
f0fba2ad 2421static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2422 {
f0fba2ad 2423 .name = "wm8994-aif1",
8c7f78b3 2424 .id = 1,
9e6e96a1
MB		 2425 .playback = {
2426 .stream_name = "AIF1 Playback",
b1e43d93 2427 .channels_min = 1,
9e6e96a1
MB		 2428 .channels_max = 2,
2429 .rates = WM8994_RATES,
2430 .formats = WM8994_FORMATS,
2431 },
2432 .capture = {
2433 .stream_name = "AIF1 Capture",
b1e43d93 2434 .channels_min = 1,
9e6e96a1
MB		 2435 .channels_max = 2,
2436 .rates = WM8994_RATES,
2437 .formats = WM8994_FORMATS,
2438 },
2439 .ops = &wm8994_aif1_dai_ops,
2440 },
2441 {
f0fba2ad 2442 .name = "wm8994-aif2",
8c7f78b3 2443 .id = 2,
9e6e96a1
MB		 2444 .playback = {
2445 .stream_name = "AIF2 Playback",
b1e43d93 2446 .channels_min = 1,
9e6e96a1
MB		 2447 .channels_max = 2,
2448 .rates = WM8994_RATES,
2449 .formats = WM8994_FORMATS,
2450 },
2451 .capture = {
2452 .stream_name = "AIF2 Capture",
b1e43d93 2453 .channels_min = 1,
9e6e96a1
MB		 2454 .channels_max = 2,
2455 .rates = WM8994_RATES,
2456 .formats = WM8994_FORMATS,
2457 },
2458 .ops = &wm8994_aif2_dai_ops,
2459 },
2460 {
f0fba2ad 2461 .name = "wm8994-aif3",
8c7f78b3 2462 .id = 3,
9e6e96a1
MB		 2463 .playback = {
2464 .stream_name = "AIF3 Playback",
b1e43d93 2465 .channels_min = 1,
9e6e96a1
MB		 2466 .channels_max = 2,
2467 .rates = WM8994_RATES,
2468 .formats = WM8994_FORMATS,
2469 },
a8462bde 2470 .capture = {
9e6e96a1 2471 .stream_name = "AIF3 Capture",
b1e43d93 2472 .channels_min = 1,
9e6e96a1
MB		 2473 .channels_max = 2,
2474 .rates = WM8994_RATES,
2475 .formats = WM8994_FORMATS,
2476 },
778a76e2 2477 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2478 }
2479};
9e6e96a1
MB		 2480
2481#ifdef CONFIG_PM
f0fba2ad 2482static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
9e6e96a1 2483{
b2c812e2 2484 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ca629928 2485 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 2486 int i, ret;
2487
ca629928
MB		 2488 switch (control->type) {
2489 case WM8994:
2490 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2491 break;
2492 case WM8958:
2493 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2494 WM8958_MICD_ENA, 0);
2495 break;
2496 }
2497
9e6e96a1
MB		 2498 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2499 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2500 sizeof(struct wm8994_fll_config));
f0fba2ad 2501 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2502 if (ret < 0)
2503 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2504 i + 1, ret);
2505 }
2506
2507 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2508
2509 return 0;
2510}
2511
f0fba2ad 2512static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2513{
b2c812e2 2514 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ca629928 2515 struct wm8994 *control = codec->control_data;
9e6e96a1 2516 int i, ret;
c52fd021
DP		 2517 unsigned int val, mask;
2518
2519 if (wm8994->revision < 4) {
2520 /* force a HW read */
2521 val = wm8994_reg_read(codec->control_data,
2522 WM8994_POWER_MANAGEMENT_5);
2523
2524 /* modify the cache only */
2525 codec->cache_only = 1;
2526 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2527 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2528 val &= mask;
2529 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2530 mask, val);
2531 codec->cache_only = 0;
2532 }
9e6e96a1
MB		 2533
2534 /* Restore the registers */
ca9aef50
MB		 2535 ret = snd_soc_cache_sync(codec);
2536 if (ret != 0)
2537 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
9e6e96a1
MB		 2538
2539 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2540
2541 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2542 if (!wm8994->fll_suspend[i].out)
2543 continue;
2544
f0fba2ad 2545 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2546 wm8994->fll_suspend[i].src,
2547 wm8994->fll_suspend[i].in,
2548 wm8994->fll_suspend[i].out);
2549 if (ret < 0)
2550 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2551 i + 1, ret);
2552 }
2553
ca629928
MB		 2554 switch (control->type) {
2555 case WM8994:
2556 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2557 snd_soc_update_bits(codec, WM8994_MICBIAS,
2558 WM8994_MICD_ENA, WM8994_MICD_ENA);
2559 break;
2560 case WM8958:
2561 if (wm8994->jack_cb)
2562 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2563 WM8958_MICD_ENA, WM8958_MICD_ENA);
2564 break;
2565 }
2566
9e6e96a1
MB		 2567 return 0;
2568}
2569#else
2570#define wm8994_suspend NULL
2571#define wm8994_resume NULL
2572#endif
2573
2574static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2575{
f0fba2ad 2576 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2577 struct wm8994_pdata *pdata = wm8994->pdata;
2578 struct snd_kcontrol_new controls[] = {
2579 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2580 wm8994->retune_mobile_enum,
2581 wm8994_get_retune_mobile_enum,
2582 wm8994_put_retune_mobile_enum),
2583 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2584 wm8994->retune_mobile_enum,
2585 wm8994_get_retune_mobile_enum,
2586 wm8994_put_retune_mobile_enum),
2587 SOC_ENUM_EXT("AIF2 EQ Mode",
2588 wm8994->retune_mobile_enum,
2589 wm8994_get_retune_mobile_enum,
2590 wm8994_put_retune_mobile_enum),
2591 };
2592 int ret, i, j;
2593 const char **t;
2594
2595 /* We need an array of texts for the enum API but the number
2596 * of texts is likely to be less than the number of
2597 * configurations due to the sample rate dependency of the
2598 * configurations. */
2599 wm8994->num_retune_mobile_texts = 0;
2600 wm8994->retune_mobile_texts = NULL;
2601 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2602 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2603 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2604 wm8994->retune_mobile_texts[j]) == 0)
2605 break;
2606 }
2607
2608 if (j != wm8994->num_retune_mobile_texts)
2609 continue;
2610
2611 /* Expand the array... */
2612 t = krealloc(wm8994->retune_mobile_texts,
2613 sizeof(char *) *
2614 (wm8994->num_retune_mobile_texts + 1),
2615 GFP_KERNEL);
2616 if (t == NULL)
2617 continue;
2618
2619 /* ...store the new entry... */
2620 t[wm8994->num_retune_mobile_texts] =
2621 pdata->retune_mobile_cfgs[i].name;
2622
2623 /* ...and remember the new version. */
2624 wm8994->num_retune_mobile_texts++;
2625 wm8994->retune_mobile_texts = t;
2626 }
2627
2628 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2629 wm8994->num_retune_mobile_texts);
2630
2631 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2632 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2633
f0fba2ad 2634 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2635 ARRAY_SIZE(controls));
2636 if (ret != 0)
f0fba2ad 2637 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2638 "Failed to add ReTune Mobile controls: %d\n", ret);
2639}
2640
2641static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2642{
f0fba2ad 2643 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2644 struct wm8994_pdata *pdata = wm8994->pdata;
2645 int ret, i;
2646
2647 if (!pdata)
2648 return;
2649
2650 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2651 pdata->lineout2_diff,
2652 pdata->lineout1fb,
2653 pdata->lineout2fb,
2654 pdata->jd_scthr,
2655 pdata->jd_thr,
2656 pdata->micbias1_lvl,
2657 pdata->micbias2_lvl);
2658
2659 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2660
2661 if (pdata->num_drc_cfgs) {
2662 struct snd_kcontrol_new controls[] = {
2663 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2664 wm8994_get_drc_enum, wm8994_put_drc_enum),
2665 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2666 wm8994_get_drc_enum, wm8994_put_drc_enum),
2667 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2668 wm8994_get_drc_enum, wm8994_put_drc_enum),
2669 };
2670
2671 /* We need an array of texts for the enum API */
2672 wm8994->drc_texts = kmalloc(sizeof(char *)
2673 * pdata->num_drc_cfgs, GFP_KERNEL);
2674 if (!wm8994->drc_texts) {
f0fba2ad 2675 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2676 "Failed to allocate %d DRC config texts\n",
2677 pdata->num_drc_cfgs);
2678 return;
2679 }
2680
2681 for (i = 0; i < pdata->num_drc_cfgs; i++)
2682 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2683
2684 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2685 wm8994->drc_enum.texts = wm8994->drc_texts;
2686
f0fba2ad 2687 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2688 ARRAY_SIZE(controls));
2689 if (ret != 0)
f0fba2ad 2690 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2691 "Failed to add DRC mode controls: %d\n", ret);
2692
2693 for (i = 0; i < WM8994_NUM_DRC; i++)
2694 wm8994_set_drc(codec, i);
2695 }
2696
2697 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2698 pdata->num_retune_mobile_cfgs);
2699
2700 if (pdata->num_retune_mobile_cfgs)
2701 wm8994_handle_retune_mobile_pdata(wm8994);
2702 else
f0fba2ad 2703 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 2704 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 2705
2706 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2707 if (pdata->micbias[i]) {
2708 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2709 pdata->micbias[i] & 0xffff);
2710 }
2711 }
9e6e96a1
MB		 2712}
2713
88766984
MB		 2714/**
2715 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2716 *
2717 * @codec: WM8994 codec
2718 * @jack: jack to report detection events on
2719 * @micbias: microphone bias to detect on
2720 * @det: value to report for presence detection
2721 * @shrt: value to report for short detection
2722 *
2723 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2724 * being used to bring out signals to the processor then only platform
5ab230a7 2725 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2726 * be configured using snd_soc_jack_add_gpios() instead.
2727 *
2728 * Configuration of detection levels is available via the micbias1_lvl
2729 * and micbias2_lvl platform data members.
2730 */
2731int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2732 int micbias, int det, int shrt)
2733{
b2c812e2 2734 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2735 struct wm8994_micdet *micdet;
3a423157 2736 struct wm8994 *control = codec->control_data;
88766984
MB		 2737 int reg;
2738
3a423157
MB		 2739 if (control->type != WM8994)
2740 return -EINVAL;
2741
88766984
MB		 2742 switch (micbias) {
2743 case 1:
2744 micdet = &wm8994->micdet[0];
2745 break;
2746 case 2:
2747 micdet = &wm8994->micdet[1];
2748 break;
2749 default:
2750 return -EINVAL;
2751 }
2752
2753 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2754 micbias, det, shrt);
2755
2756 /* Store the configuration */
2757 micdet->jack = jack;
2758 micdet->det = det;
2759 micdet->shrt = shrt;
2760
2761 /* If either of the jacks is set up then enable detection */
2762 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2763 reg = WM8994_MICD_ENA;
2764 else
2765 reg = 0;
2766
2767 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2768
2769 return 0;
2770}
2771EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2772
2773static irqreturn_t wm8994_mic_irq(int irq, void *data)
2774{
2775 struct wm8994_priv *priv = data;
f0fba2ad 2776 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 2777 int reg;
2778 int report;
2779
7116f452 2780#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 2781 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 2782#endif
2bbb5d66 2783
88766984
MB		 2784 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2785 if (reg < 0) {
2786 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2787 reg);
2788 return IRQ_HANDLED;
2789 }
2790
2791 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2792
2793 report = 0;
2794 if (reg & WM8994_MIC1_DET_STS)
2795 report |= priv->micdet[0].det;
2796 if (reg & WM8994_MIC1_SHRT_STS)
2797 report |= priv->micdet[0].shrt;
2798 snd_soc_jack_report(priv->micdet[0].jack, report,
2799 priv->micdet[0].det | priv->micdet[0].shrt);
2800
2801 report = 0;
2802 if (reg & WM8994_MIC2_DET_STS)
2803 report |= priv->micdet[1].det;
2804 if (reg & WM8994_MIC2_SHRT_STS)
2805 report |= priv->micdet[1].shrt;
2806 snd_soc_jack_report(priv->micdet[1].jack, report,
2807 priv->micdet[1].det | priv->micdet[1].shrt);
2808
2809 return IRQ_HANDLED;
2810}
2811
821edd2f
MB		 2812/* Default microphone detection handler for WM8958 - the user can
2813 * override this if they wish.
2814 */
2815static void wm8958_default_micdet(u16 status, void *data)
2816{
2817 struct snd_soc_codec *codec = data;
2818 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2819 int report = 0;
2820
2821 /* If nothing present then clear our statuses */
864c4bd2 2822 if (!(status & WM8958_MICD_STS))
821edd2f 2823 goto done;
821edd2f 2824
864c4bd2 2825 report = SND_JACK_MICROPHONE;
821edd2f
MB		 2826
2827 /* Everything else is buttons; just assign slots */
b35e160a 2828 if (status & 0x1c)
821edd2f 2829 report |= SND_JACK_BTN_0;
821edd2f
MB		 2830
2831done:
406e56c9 2832 snd_soc_jack_report(wm8994->micdet[0].jack, report,
864c4bd2 2833 SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
821edd2f
MB		 2834}
2835
2836/**
2837 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2838 *
2839 * @codec: WM8958 codec
2840 * @jack: jack to report detection events on
2841 *
2842 * Enable microphone detection functionality for the WM8958. By
2843 * default simple detection which supports the detection of up to 6
2844 * buttons plus video and microphone functionality is supported.
2845 *
2846 * The WM8958 has an advanced jack detection facility which is able to
2847 * support complex accessory detection, especially when used in
2848 * conjunction with external circuitry. In order to provide maximum
2849 * flexiblity a callback is provided which allows a completely custom
2850 * detection algorithm.
2851 */
2852int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2853 wm8958_micdet_cb cb, void *cb_data)
2854{
2855 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2856 struct wm8994 *control = codec->control_data;
2857
2858 if (control->type != WM8958)
2859 return -EINVAL;
2860
2861 if (jack) {
2862 if (!cb) {
2863 dev_dbg(codec->dev, "Using default micdet callback\n");
2864 cb = wm8958_default_micdet;
2865 cb_data = codec;
2866 }
2867
2868 wm8994->micdet[0].jack = jack;
2869 wm8994->jack_cb = cb;
2870 wm8994->jack_cb_data = cb_data;
2871
2872 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2873 WM8958_MICD_ENA, WM8958_MICD_ENA);
2874 } else {
2875 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2876 WM8958_MICD_ENA, 0);
2877 }
2878
2879 return 0;
2880}
2881EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2882
2883static irqreturn_t wm8958_mic_irq(int irq, void *data)
2884{
2885 struct wm8994_priv *wm8994 = data;
2886 struct snd_soc_codec *codec = wm8994->codec;
2887 int reg;
2888
2889 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2890 if (reg < 0) {
2891 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2892 reg);
2893 return IRQ_NONE;
2894 }
2895
2896 if (!(reg & WM8958_MICD_VALID)) {
2897 dev_dbg(codec->dev, "Mic detect data not valid\n");
2898 goto out;
2899 }
2900
7116f452 2901#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 2902 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 2903#endif
2bbb5d66 2904
821edd2f
MB		 2905 if (wm8994->jack_cb)
2906 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2907 else
2908 dev_warn(codec->dev, "Accessory detection with no callback\n");
2909
2910out:
2911 return IRQ_HANDLED;
2912}
2913
3b1af3f8
MB		 2914static irqreturn_t wm8994_fifo_error(int irq, void *data)
2915{
2916 struct snd_soc_codec *codec = data;
2917
2918 dev_err(codec->dev, "FIFO error\n");
2919
2920 return IRQ_HANDLED;
2921}
2922
f0fba2ad 2923static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 2924{
3a423157 2925 struct wm8994 *control;
9e6e96a1 2926 struct wm8994_priv *wm8994;
ce6120cc 2927 struct snd_soc_dapm_context *dapm = &codec->dapm;
ec62dbd7 2928 int ret, i;
9e6e96a1 2929
f0fba2ad 2930 codec->control_data = dev_get_drvdata(codec->dev->parent);
3a423157 2931 control = codec->control_data;
9e6e96a1
MB		 2932
2933 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
f0fba2ad 2934 if (wm8994 == NULL)
9e6e96a1 2935 return -ENOMEM;
b2c812e2 2936 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad
LG		 2937
2938 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2939 wm8994->codec = codec;
9e6e96a1 2940
c7ebf932
MB		 2941 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2942 init_completion(&wm8994->fll_locked[i]);
2943
9b7c525d
MB		 2944 if (wm8994->pdata && wm8994->pdata->micdet_irq)
2945 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
2946 else if (wm8994->pdata && wm8994->pdata->irq_base)
2947 wm8994->micdet_irq = wm8994->pdata->irq_base +
2948 WM8994_IRQ_MIC1_DET;
2949
39fb51a1
MB		 2950 pm_runtime_enable(codec->dev);
2951 pm_runtime_resume(codec->dev);
2952
ca9aef50
MB		 2953 /* Read our current status back from the chip - we don't want to
2954 * reset as this may interfere with the GPIO or LDO operation. */
2955 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
d4754ec9 2956 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
ca9aef50 2957 continue;
9e6e96a1 2958
ca9aef50
MB		 2959 ret = wm8994_reg_read(codec->control_data, i);
2960 if (ret <= 0)
2961 continue;
2962
2963 ret = snd_soc_cache_write(codec, i, ret);
2964 if (ret != 0) {
2965 dev_err(codec->dev,
2966 "Failed to initialise cache for 0x%x: %d\n",
2967 i, ret);
2968 goto err;
2969 }
2970 }
9e6e96a1
MB		 2971
2972 /* Set revision-specific configuration */
b6b05691 2973 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 2974 switch (control->type) {
2975 case WM8994:
2976 switch (wm8994->revision) {
2977 case 2:
2978 case 3:
4537c4e7
MB		 2979 wm8994->hubs.dcs_codes_l = -5;
2980 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 2981 wm8994->hubs.hp_startup_mode = 1;
2982 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 2983 wm8994->hubs.series_startup = 1;
3a423157
MB		 2984 break;
2985 default:
79ef0abc 2986 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 2987 break;
2988 }
280ec8b7 2989 break;
3a423157
MB		 2990
2991 case WM8958:
8437f700 2992 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 2993 break;
3a423157 2994
9e6e96a1
MB		 2995 default:
2996 break;
2997 }
9e6e96a1 2998
3b1af3f8
MB		 2999 wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
3000 wm8994_fifo_error, "FIFO error", codec);
3001
b30ead5f
MB		 3002 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3003 wm_hubs_dcs_done, "DC servo done",
3004 &wm8994->hubs);
3005 if (ret == 0)
3006 wm8994->hubs.dcs_done_irq = true;
3007
3a423157
MB		 3008 switch (control->type) {
3009 case WM8994:
9b7c525d
MB		 3010 if (wm8994->micdet_irq) {
3011 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3012 wm8994_mic_irq,
3013 IRQF_TRIGGER_RISING,
3014 "Mic1 detect",
3015 wm8994);
3016 if (ret != 0)
3017 dev_warn(codec->dev,
3018 "Failed to request Mic1 detect IRQ: %d\n",
3019 ret);
3020 }
3a423157
MB		 3021
3022 ret = wm8994_request_irq(codec->control_data,
3023 WM8994_IRQ_MIC1_SHRT,
3024 wm8994_mic_irq, "Mic 1 short",
3025 wm8994);
3026 if (ret != 0)
3027 dev_warn(codec->dev,
3028 "Failed to request Mic1 short IRQ: %d\n",
3029 ret);
3030
3031 ret = wm8994_request_irq(codec->control_data,
3032 WM8994_IRQ_MIC2_DET,
3033 wm8994_mic_irq, "Mic 2 detect",
3034 wm8994);
3035 if (ret != 0)
3036 dev_warn(codec->dev,
3037 "Failed to request Mic2 detect IRQ: %d\n",
3038 ret);
3039
3040 ret = wm8994_request_irq(codec->control_data,
3041 WM8994_IRQ_MIC2_SHRT,
3042 wm8994_mic_irq, "Mic 2 short",
3043 wm8994);
3044 if (ret != 0)
3045 dev_warn(codec->dev,
3046 "Failed to request Mic2 short IRQ: %d\n",
3047 ret);
3048 break;
821edd2f
MB		 3049
3050 case WM8958:
9b7c525d
MB		 3051 if (wm8994->micdet_irq) {
3052 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3053 wm8958_mic_irq,
3054 IRQF_TRIGGER_RISING,
3055 "Mic detect",
3056 wm8994);
3057 if (ret != 0)
3058 dev_warn(codec->dev,
3059 "Failed to request Mic detect IRQ: %d\n",
3060 ret);
3061 }
3a423157 3062 }
88766984 3063
c7ebf932
MB		 3064 wm8994->fll_locked_irq = true;
3065 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3066 ret = wm8994_request_irq(codec->control_data,
3067 WM8994_IRQ_FLL1_LOCK + i,
3068 wm8994_fll_locked_irq, "FLL lock",
3069 &wm8994->fll_locked[i]);
3070 if (ret != 0)
3071 wm8994->fll_locked_irq = false;
3072 }
3073
9e6e96a1
MB		 3074 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3075 * configured on init - if a system wants to do this dynamically
3076 * at runtime we can deal with that then.
3077 */
3078 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3079 if (ret < 0) {
3080 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3081 goto err_irq;
9e6e96a1
MB		 3082 }
3083 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3084 wm8994->lrclk_shared[0] = 1;
3085 wm8994_dai[0].symmetric_rates = 1;
3086 } else {
3087 wm8994->lrclk_shared[0] = 0;
3088 }
3089
3090 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3091 if (ret < 0) {
3092 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3093 goto err_irq;
9e6e96a1
MB		 3094 }
3095 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3096 wm8994->lrclk_shared[1] = 1;
3097 wm8994_dai[1].symmetric_rates = 1;
3098 } else {
3099 wm8994->lrclk_shared[1] = 0;
3100 }
3101
9e6e96a1
MB		 3102 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3103
9e6e96a1 3104 /* Latch volume updates (right only; we always do left then right). */
baa81603
MB		 3105 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3106 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
9e6e96a1
MB		 3107 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3108 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
baa81603
MB		 3109 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3110 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
9e6e96a1
MB		 3111 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3112 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
baa81603
MB		 3113 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3114 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
9e6e96a1
MB		 3115 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3116 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
baa81603
MB		 3117 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3118 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
9e6e96a1
MB		 3119 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3120 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
baa81603
MB		 3121 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3122 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3123 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3124 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3125 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3126 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3127 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3128 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3129 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3130 WM8994_DAC1_VU, WM8994_DAC1_VU);
9e6e96a1
MB		 3131 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3132 WM8994_DAC1_VU, WM8994_DAC1_VU);
baa81603
MB		 3133 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3134 WM8994_DAC2_VU, WM8994_DAC2_VU);
9e6e96a1
MB		 3135 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3136 WM8994_DAC2_VU, WM8994_DAC2_VU);
3137
3138 /* Set the low bit of the 3D stereo depth so TLV matches */
3139 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3140 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3141 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3142 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3143 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3144 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3145 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3146 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3147 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3148
5b739670
MB		 3149 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3150 * use this; it only affects behaviour on idle TDM clock
3151 * cycles. */
3152 switch (control->type) {
3153 case WM8994:
3154 case WM8958:
3155 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3156 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3157 break;
3158 default:
3159 break;
3160 }
d1ce6b20 3161
9e6e96a1
MB		 3162 wm8994_update_class_w(codec);
3163
f0fba2ad 3164 wm8994_handle_pdata(wm8994);
9e6e96a1 3165
f0fba2ad
LG		 3166 wm_hubs_add_analogue_controls(codec);
3167 snd_soc_add_controls(codec, wm8994_snd_controls,
3168 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3169 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3170 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3171
3172 switch (control->type) {
3173 case WM8994:
3174 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3175 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3176 if (wm8994->revision < 4) {
173efa09
DP		 3177 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3178 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3179 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3180 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3181 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3182 ARRAY_SIZE(wm8994_dac_revd_widgets));
3183 } else {
173efa09
DP		 3184 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3185 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 3186 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3187 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 3188 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3189 ARRAY_SIZE(wm8994_dac_widgets));
3190 }
c4431df0
MB		 3191 break;
3192 case WM8958:
3193 snd_soc_add_controls(codec, wm8958_snd_controls,
3194 ARRAY_SIZE(wm8958_snd_controls));
3195 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3196 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 3197 if (wm8994->revision < 1) {
3198 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3199 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3200 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3201 ARRAY_SIZE(wm8994_adc_revd_widgets));
3202 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3203 ARRAY_SIZE(wm8994_dac_revd_widgets));
3204 } else {
3205 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3206 ARRAY_SIZE(wm8994_lateclk_widgets));
3207 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3208 ARRAY_SIZE(wm8994_adc_widgets));
3209 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3210 ARRAY_SIZE(wm8994_dac_widgets));
3211 }
c4431df0
MB		 3212 break;
3213 }
3214
3215
f0fba2ad 3216 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3217 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3218
c4431df0
MB		 3219 switch (control->type) {
3220 case WM8994:
3221 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3222 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3223
173efa09 3224 if (wm8994->revision < 4) {
6ed8f148
MB		 3225 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3226 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3227 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3228 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3229 } else {
3230 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3231 ARRAY_SIZE(wm8994_lateclk_intercon));
3232 }
c4431df0
MB		 3233 break;
3234 case WM8958:
780e2806
MB		 3235 if (wm8994->revision < 1) {
3236 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3237 ARRAY_SIZE(wm8994_revd_intercon));
3238 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3239 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3240 } else {
3241 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3242 ARRAY_SIZE(wm8994_lateclk_intercon));
3243 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3244 ARRAY_SIZE(wm8958_intercon));
3245 }
f701a2e5
MB		 3246
3247 wm8958_dsp2_init(codec);
c4431df0
MB		 3248 break;
3249 }
3250
9e6e96a1
MB		 3251 return 0;
3252
88766984
MB		 3253err_irq:
3254 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3255 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3256 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3257 if (wm8994->micdet_irq)
3258 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932
MB		 3259 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3260 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3261 &wm8994->fll_locked[i]);
b30ead5f
MB		 3262 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3263 &wm8994->hubs);
3b1af3f8 3264 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
9e6e96a1
MB		 3265err:
3266 kfree(wm8994);
3267 return ret;
3268}
3269
f0fba2ad 3270static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3271{
f0fba2ad 3272 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3a423157 3273 struct wm8994 *control = codec->control_data;
c7ebf932 3274 int i;
9e6e96a1
MB		 3275
3276 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3277
39fb51a1
MB		 3278 pm_runtime_disable(codec->dev);
3279
c7ebf932
MB		 3280 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3281 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3282 &wm8994->fll_locked[i]);
3283
b30ead5f
MB		 3284 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3285 &wm8994->hubs);
3b1af3f8 3286 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
b30ead5f 3287
3a423157
MB		 3288 switch (control->type) {
3289 case WM8994:
9b7c525d
MB		 3290 if (wm8994->micdet_irq)
3291 free_irq(wm8994->micdet_irq, wm8994);
3a423157
MB		 3292 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3293 wm8994);
3294 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3295 wm8994);
3296 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3297 wm8994);
3298 break;
821edd2f
MB		 3299
3300 case WM8958:
9b7c525d
MB		 3301 if (wm8994->micdet_irq)
3302 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 3303 break;
3a423157 3304 }
fbbf5920
MB		 3305 if (wm8994->mbc)
3306 release_firmware(wm8994->mbc);
09e10d7f
MB		 3307 if (wm8994->mbc_vss)
3308 release_firmware(wm8994->mbc_vss);
31215871
MB		 3309 if (wm8994->enh_eq)
3310 release_firmware(wm8994->enh_eq);
24fb2b11
AL		 3311 kfree(wm8994->retune_mobile_texts);
3312 kfree(wm8994->drc_texts);
9e6e96a1 3313 kfree(wm8994);
9e6e96a1
MB		 3314
3315 return 0;
3316}
3317
f0fba2ad
LG		 3318static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3319 .probe = wm8994_codec_probe,
3320 .remove = wm8994_codec_remove,
3321 .suspend = wm8994_suspend,
3322 .resume = wm8994_resume,
ca9aef50
MB		 3323 .read = wm8994_read,
3324 .write = wm8994_write,
eba19fdd
MB		 3325 .readable_register = wm8994_readable,
3326 .volatile_register = wm8994_volatile,
f0fba2ad 3327 .set_bias_level = wm8994_set_bias_level,
ca9aef50
MB		 3328
3329 .reg_cache_size = WM8994_CACHE_SIZE,
3330 .reg_cache_default = wm8994_reg_defaults,
3331 .reg_word_size = 2,
2e19b0c8 3332 .compress_type = SND_SOC_RBTREE_COMPRESSION,
f0fba2ad
LG		 3333};
3334
3335static int __devinit wm8994_probe(struct platform_device *pdev)
3336{
3337 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3338 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3339}
3340
3341static int __devexit wm8994_remove(struct platform_device *pdev)
3342{
3343 snd_soc_unregister_codec(&pdev->dev);
3344 return 0;
3345}
3346
9e6e96a1
MB		 3347static struct platform_driver wm8994_codec_driver = {
3348 .driver = {
3349 .name = "wm8994-codec",
3350 .owner = THIS_MODULE,
3351 },
f0fba2ad
LG		 3352 .probe = wm8994_probe,
3353 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3354};
3355
3356static __init int wm8994_init(void)
3357{
3358 return platform_driver_register(&wm8994_codec_driver);
3359}
3360module_init(wm8994_init);
3361
3362static __exit void wm8994_exit(void)
3363{
3364 platform_driver_unregister(&wm8994_codec_driver);
3365}
3366module_exit(wm8994_exit);
3367
3368
3369MODULE_DESCRIPTION("ASoC WM8994 driver");
3370MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3371MODULE_LICENSE("GPL");
3372MODULE_ALIAS("platform:wm8994-codec");
Linux 6.x block layer and io_uring tree(s)