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ASoC: alc5632: Allow 8kHz stream support.
[linux-2.6-block.git] / sound / soc / codecs / wm8994.c
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9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
49static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53};
54
55static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59};
60
b00adf76
MB		 61static void wm8958_default_micdet(u16 status, void *data);
62
af6b6fe4 63static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
604533de
MB		 66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 68};
69
af6b6fe4
MB		 70static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75};
76
b00adf76
MB		 77static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78{
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
af6b6fe4
MB		 82 const struct wm8958_micd_rate *rates;
83 int num_rates;
b00adf76
MB		 84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
cd1707a9
MB		 96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
af6b6fe4
MB		 100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
b00adf76 107 best = 0;
af6b6fe4
MB		 108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
b00adf76 110 continue;
af6b6fe4
MB		 111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
b00adf76 113 best = i;
af6b6fe4 114 else if (rates[best].idle != idle)
b00adf76
MB		 115 best = i;
116 }
117
af6b6fe4
MB		 118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76
MB		 120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124}
125
9e6e96a1
MB		 126static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127{
b2c812e2 128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 129 int rate;
130 int reg1 = 0;
131 int offset;
132
133 if (aif)
134 offset = 4;
135 else
136 offset = 0;
137
138 switch (wm8994->sysclk[aif]) {
139 case WM8994_SYSCLK_MCLK1:
140 rate = wm8994->mclk[0];
141 break;
142
143 case WM8994_SYSCLK_MCLK2:
144 reg1 |= 0x8;
145 rate = wm8994->mclk[1];
146 break;
147
148 case WM8994_SYSCLK_FLL1:
149 reg1 |= 0x10;
150 rate = wm8994->fll[0].out;
151 break;
152
153 case WM8994_SYSCLK_FLL2:
154 reg1 |= 0x18;
155 rate = wm8994->fll[1].out;
156 break;
157
158 default:
159 return -EINVAL;
160 }
161
162 if (rate >= 13500000) {
163 rate /= 2;
164 reg1 |= WM8994_AIF1CLK_DIV;
165
166 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167 aif + 1, rate);
168 }
5e5e2bef 169
9e6e96a1
MB		 170 wm8994->aifclk[aif] = rate;
171
172 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174 reg1);
175
176 return 0;
177}
178
179static int configure_clock(struct snd_soc_codec *codec)
180{
b2c812e2 181 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 182 int change, new;
9e6e96a1
MB		 183
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec, 0);
186 configure_aif_clock(codec, 1);
187
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
191 * clocking.
192 */
193
194 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 195 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196 wm8958_micd_set_rate(codec);
9e6e96a1 197 return 0;
b00adf76 198 }
9e6e96a1
MB		 199
200 if (wm8994->aifclk[0] < wm8994->aifclk[1])
201 new = WM8994_SYSCLK_SRC;
202 else
203 new = 0;
204
04f45c49
AL		 205 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 207 if (change)
208 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 209
b00adf76
MB		 210 wm8958_micd_set_rate(codec);
211
9e6e96a1
MB		 212 return 0;
213}
214
215static int check_clk_sys(struct snd_soc_dapm_widget *source,
216 struct snd_soc_dapm_widget *sink)
217{
218 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219 const char *clk;
220
221 /* Check what we're currently using for CLK_SYS */
222 if (reg & WM8994_SYSCLK_SRC)
223 clk = "AIF2CLK";
224 else
225 clk = "AIF1CLK";
226
227 return strcmp(source->name, clk) == 0;
228}
229
230static const char *sidetone_hpf_text[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232};
233
234static const struct soc_enum sidetone_hpf =
235 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
146fd574
UK		 237static const char *adc_hpf_text[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
239};
240
241static const struct soc_enum aif1adc1_hpf =
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244static const struct soc_enum aif1adc2_hpf =
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247static const struct soc_enum aif2adc_hpf =
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
9e6e96a1
MB		 250static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 255static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 256static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 257
258#define WM8994_DRC_SWITCH(xname, reg, shift) \
259{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266{
267 struct soc_mixer_control *mc =
268 (struct soc_mixer_control *)kcontrol->private_value;
269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270 int mask, ret;
271
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275 WM8994_AIF1ADC1R_DRC_ENA_MASK;
276 else
277 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279 ret = snd_soc_read(codec, mc->reg);
280 if (ret < 0)
281 return ret;
282 if (ret & mask)
283 return -EINVAL;
284
285 return snd_soc_put_volsw(kcontrol, ucontrol);
286}
287
9e6e96a1
MB		 288static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289{
b2c812e2 290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 291 struct wm8994_pdata *pdata = wm8994->pdata;
292 int base = wm8994_drc_base[drc];
293 int cfg = wm8994->drc_cfg[drc];
294 int save, i;
295
296 /* Save any enables; the configuration should clear them. */
297 save = snd_soc_read(codec, base);
298 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299 WM8994_AIF1ADC1R_DRC_ENA;
300
301 for (i = 0; i < WM8994_DRC_REGS; i++)
302 snd_soc_update_bits(codec, base + i, 0xffff,
303 pdata->drc_cfgs[cfg].regs[i]);
304
305 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306 WM8994_AIF1ADC1L_DRC_ENA |
307 WM8994_AIF1ADC1R_DRC_ENA, save);
308}
309
310/* Icky as hell but saves code duplication */
311static int wm8994_get_drc(const char *name)
312{
313 if (strcmp(name, "AIF1DRC1 Mode") == 0)
314 return 0;
315 if (strcmp(name, "AIF1DRC2 Mode") == 0)
316 return 1;
317 if (strcmp(name, "AIF2DRC Mode") == 0)
318 return 2;
319 return -EINVAL;
320}
321
322static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
324{
325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int drc = wm8994_get_drc(kcontrol->id.name);
329 int value = ucontrol->value.integer.value[0];
330
331 if (drc < 0)
332 return drc;
333
334 if (value >= pdata->num_drc_cfgs)
335 return -EINVAL;
336
337 wm8994->drc_cfg[drc] = value;
338
339 wm8994_set_drc(codec, drc);
340
341 return 0;
342}
343
344static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_value *ucontrol)
346{
347 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 348 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 349 int drc = wm8994_get_drc(kcontrol->id.name);
350
351 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353 return 0;
354}
355
356static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357{
b2c812e2 358 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 359 struct wm8994_pdata *pdata = wm8994->pdata;
360 int base = wm8994_retune_mobile_base[block];
361 int iface, best, best_val, save, i, cfg;
362
363 if (!pdata || !wm8994->num_retune_mobile_texts)
364 return;
365
366 switch (block) {
367 case 0:
368 case 1:
369 iface = 0;
370 break;
371 case 2:
372 iface = 1;
373 break;
374 default:
375 return;
376 }
377
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg = wm8994->retune_mobile_cfg[block];
381 best = 0;
382 best_val = INT_MAX;
383 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385 wm8994->retune_mobile_texts[cfg]) == 0 &&
386 abs(pdata->retune_mobile_cfgs[i].rate
387 - wm8994->dac_rates[iface]) < best_val) {
388 best = i;
389 best_val = abs(pdata->retune_mobile_cfgs[i].rate
390 - wm8994->dac_rates[iface]);
391 }
392 }
393
394 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395 block,
396 pdata->retune_mobile_cfgs[best].name,
397 pdata->retune_mobile_cfgs[best].rate,
398 wm8994->dac_rates[iface]);
399
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
402 */
403 save = snd_soc_read(codec, base);
404 save &= WM8994_AIF1DAC1_EQ_ENA;
405
406 for (i = 0; i < WM8994_EQ_REGS; i++)
407 snd_soc_update_bits(codec, base + i, 0xffff,
408 pdata->retune_mobile_cfgs[best].regs[i]);
409
410 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411}
412
413/* Icky as hell but saves code duplication */
414static int wm8994_get_retune_mobile_block(const char *name)
415{
416 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417 return 0;
418 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419 return 1;
420 if (strcmp(name, "AIF2 EQ Mode") == 0)
421 return 2;
422 return -EINVAL;
423}
424
425static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427{
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 430 struct wm8994_pdata *pdata = wm8994->pdata;
431 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432 int value = ucontrol->value.integer.value[0];
433
434 if (block < 0)
435 return block;
436
437 if (value >= pdata->num_retune_mobile_cfgs)
438 return -EINVAL;
439
440 wm8994->retune_mobile_cfg[block] = value;
441
442 wm8994_set_retune_mobile(codec, block);
443
444 return 0;
445}
446
447static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449{
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 451 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 452 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456 return 0;
457}
458
96b101ef 459static const char *aif_chan_src_text[] = {
f554885f
MB		 460 "Left", "Right"
461};
462
96b101ef
MB		 463static const struct soc_enum aif1adcl_src =
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466static const struct soc_enum aif1adcr_src =
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469static const struct soc_enum aif2adcl_src =
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472static const struct soc_enum aif2adcr_src =
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
f554885f 475static const struct soc_enum aif1dacl_src =
96b101ef 476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 477
478static const struct soc_enum aif1dacr_src =
96b101ef 479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 480
481static const struct soc_enum aif2dacl_src =
96b101ef 482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 483
484static const struct soc_enum aif2dacr_src =
96b101ef 485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 486
154b26aa
MB		 487static const char *osr_text[] = {
488 "Low Power", "High Performance",
489};
490
491static const struct soc_enum dac_osr =
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494static const struct soc_enum adc_osr =
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
9e6e96a1
MB		 497static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME,
500 1, 119, 0, digital_tlv),
501SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME,
503 1, 119, 0, digital_tlv),
504SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505 WM8994_AIF2_ADC_RIGHT_VOLUME,
506 1, 119, 0, digital_tlv),
507
96b101ef
MB		 508SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 510SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 512
f554885f
MB		 513SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 515SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 517
9e6e96a1
MB		 518SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545 5, 12, 0, st_tlv),
546SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547 0, 12, 0, st_tlv),
548SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549 5, 12, 0, st_tlv),
550SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551 0, 12, 0, st_tlv),
552SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
146fd574
UK		 555SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
154b26aa
MB		 564SOC_ENUM("ADC OSR", adc_osr),
565SOC_ENUM("DAC OSR", dac_osr),
566
9e6e96a1
MB		 567SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578 6, 1, 1, wm_hubs_spkmix_tlv),
579SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580 2, 1, 1, wm_hubs_spkmix_tlv),
581
582SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583 6, 1, 1, wm_hubs_spkmix_tlv),
584SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585 2, 1, 1, wm_hubs_spkmix_tlv),
586
587SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588 10, 15, 0, wm8994_3d_tlv),
458350b3 589SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 590 8, 1, 0),
591SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592 10, 15, 0, wm8994_3d_tlv),
593SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594 8, 1, 0),
458350b3 595SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 596 10, 15, 0, wm8994_3d_tlv),
458350b3 597SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 598 8, 1, 0),
599};
600
601static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603 eq_tlv),
604SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605 eq_tlv),
606SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607 eq_tlv),
608SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609 eq_tlv),
610SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611 eq_tlv),
612
613SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614 eq_tlv),
615SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616 eq_tlv),
617SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618 eq_tlv),
619SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620 eq_tlv),
621SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622 eq_tlv),
623
624SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625 eq_tlv),
626SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627 eq_tlv),
628SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629 eq_tlv),
630SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631 eq_tlv),
632SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633 eq_tlv),
634};
635
1ddc07d0
MB		 636static const char *wm8958_ng_text[] = {
637 "30ms", "125ms", "250ms", "500ms",
638};
639
640static const struct soc_enum wm8958_aif1dac1_ng_hold =
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644static const struct soc_enum wm8958_aif1dac2_ng_hold =
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648static const struct soc_enum wm8958_aif2dac_ng_hold =
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
c4431df0
MB		 652static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 654
655SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660 7, 1, ng_tlv),
661
662SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667 7, 1, ng_tlv),
668
669SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674 7, 1, ng_tlv),
c4431df0
MB		 675};
676
81204c84
MB		 677static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679 mixin_boost_tlv),
680SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681 mixin_boost_tlv),
682};
683
af6b6fe4
MB		 684/* We run all mode setting through a function to enforce audio mode */
685static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686{
687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
689 if (wm8994->active_refcount)
690 mode = WM1811_JACKDET_MODE_AUDIO;
691
692 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
693 WM1811_JACKDET_MODE_MASK, mode);
694
695 if (mode == WM1811_JACKDET_MODE_MIC)
696 msleep(2);
697}
698
699static void active_reference(struct snd_soc_codec *codec)
700{
701 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
702
703 mutex_lock(&wm8994->accdet_lock);
704
705 wm8994->active_refcount++;
706
707 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
708 wm8994->active_refcount);
709
710 if (wm8994->active_refcount == 1) {
711 /* If we're using jack detection go into audio mode */
712 if (wm8994->jackdet && wm8994->jack_cb) {
713 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
714 WM1811_JACKDET_MODE_MASK,
715 WM1811_JACKDET_MODE_AUDIO);
716 msleep(2);
717 }
718 }
719
720 mutex_unlock(&wm8994->accdet_lock);
721}
722
723static void active_dereference(struct snd_soc_codec *codec)
724{
725 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
726 u16 mode;
727
728 mutex_lock(&wm8994->accdet_lock);
729
730 wm8994->active_refcount--;
731
732 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
733 wm8994->active_refcount);
734
735 if (wm8994->active_refcount == 0) {
736 /* Go into appropriate detection only mode */
737 if (wm8994->jackdet && wm8994->jack_cb) {
738 if (wm8994->jack_mic || wm8994->mic_detecting)
739 mode = WM1811_JACKDET_MODE_MIC;
740 else
741 mode = WM1811_JACKDET_MODE_JACK;
742
743 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
744 WM1811_JACKDET_MODE_MASK,
745 mode);
746 }
747 }
748
749 mutex_unlock(&wm8994->accdet_lock);
750}
751
9e6e96a1
MB		 752static int clk_sys_event(struct snd_soc_dapm_widget *w,
753 struct snd_kcontrol *kcontrol, int event)
754{
755 struct snd_soc_codec *codec = w->codec;
756
757 switch (event) {
758 case SND_SOC_DAPM_PRE_PMU:
759 return configure_clock(codec);
760
761 case SND_SOC_DAPM_POST_PMD:
762 configure_clock(codec);
763 break;
764 }
765
766 return 0;
767}
768
4b7ed83a
MB		 769static void vmid_reference(struct snd_soc_codec *codec)
770{
771 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
772
db966f8a
MB		 773 pm_runtime_get_sync(codec->dev);
774
4b7ed83a
MB		 775 wm8994->vmid_refcount++;
776
777 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
778 wm8994->vmid_refcount);
779
780 if (wm8994->vmid_refcount == 1) {
781 /* Startup bias, VMID ramp & buffer */
782 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
783 WM8994_STARTUP_BIAS_ENA |
784 WM8994_VMID_BUF_ENA |
785 WM8994_VMID_RAMP_MASK,
786 WM8994_STARTUP_BIAS_ENA |
787 WM8994_VMID_BUF_ENA |
f647e152 788 (0x3 << WM8994_VMID_RAMP_SHIFT));
4b7ed83a 789
a7c4183b
MB		 790 /* Remove discharge for line out */
791 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
792 WM8994_LINEOUT1_DISCH |
793 WM8994_LINEOUT2_DISCH, 0);
4b7ed83a
MB		 794
795 /* Main bias enable, VMID=2x40k */
796 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
797 WM8994_BIAS_ENA |
798 WM8994_VMID_SEL_MASK,
799 WM8994_BIAS_ENA | 0x2);
800
801 msleep(20);
802 }
803}
804
805static void vmid_dereference(struct snd_soc_codec *codec)
806{
807 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
808
809 wm8994->vmid_refcount--;
810
811 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
812 wm8994->vmid_refcount);
813
814 if (wm8994->vmid_refcount == 0) {
815 /* Switch over to startup biases */
816 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
817 WM8994_BIAS_SRC |
818 WM8994_STARTUP_BIAS_ENA |
819 WM8994_VMID_BUF_ENA |
820 WM8994_VMID_RAMP_MASK,
821 WM8994_BIAS_SRC |
822 WM8994_STARTUP_BIAS_ENA |
823 WM8994_VMID_BUF_ENA |
824 (1 << WM8994_VMID_RAMP_SHIFT));
825
826 /* Disable main biases */
827 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
828 WM8994_BIAS_ENA |
829 WM8994_VMID_SEL_MASK, 0);
830
831 /* Discharge line */
832 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
833 WM8994_LINEOUT1_DISCH |
834 WM8994_LINEOUT2_DISCH,
835 WM8994_LINEOUT1_DISCH |
836 WM8994_LINEOUT2_DISCH);
837
838 msleep(5);
839
840 /* Switch off startup biases */
841 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
842 WM8994_BIAS_SRC |
843 WM8994_STARTUP_BIAS_ENA |
844 WM8994_VMID_BUF_ENA |
845 WM8994_VMID_RAMP_MASK, 0);
846 }
db966f8a
MB		 847
848 pm_runtime_put(codec->dev);
4b7ed83a
MB		 849}
850
851static int vmid_event(struct snd_soc_dapm_widget *w,
852 struct snd_kcontrol *kcontrol, int event)
853{
854 struct snd_soc_codec *codec = w->codec;
855
856 switch (event) {
857 case SND_SOC_DAPM_PRE_PMU:
858 vmid_reference(codec);
859 break;
860
861 case SND_SOC_DAPM_POST_PMD:
862 vmid_dereference(codec);
863 break;
864 }
865
866 return 0;
867}
868
9e6e96a1
MB		 869static void wm8994_update_class_w(struct snd_soc_codec *codec)
870{
fec6dd83 871 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 872 int enable = 1;
873 int source = 0; /* GCC flow analysis can't track enable */
874 int reg, reg_r;
875
876 /* Only support direct DAC->headphone paths */
877 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
878 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 879 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 880 enable = 0;
881 }
882
883 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
884 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 885 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 886 enable = 0;
887 }
888
889 /* We also need the same setting for L/R and only one path */
890 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
891 switch (reg) {
892 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 893 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 894 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
895 break;
896 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 897 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 898 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
899 break;
900 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 901 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 902 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
903 break;
904 default:
ee839a21 905 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 906 enable = 0;
907 break;
908 }
909
910 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
911 if (reg_r != reg) {
ee839a21 912 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 913 enable = 0;
914 }
915
916 if (enable) {
917 dev_dbg(codec->dev, "Class W enabled\n");
918 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
919 WM8994_CP_DYN_PWR |
920 WM8994_CP_DYN_SRC_SEL_MASK,
921 source | WM8994_CP_DYN_PWR);
fec6dd83 922 wm8994->hubs.class_w = true;
9e6e96a1
MB		 923
924 } else {
925 dev_dbg(codec->dev, "Class W disabled\n");
926 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
927 WM8994_CP_DYN_PWR, 0);
fec6dd83 928 wm8994->hubs.class_w = false;
9e6e96a1
MB		 929 }
930}
931
173efa09
DP		 932static int late_enable_ev(struct snd_soc_dapm_widget *w,
933 struct snd_kcontrol *kcontrol, int event)
934{
935 struct snd_soc_codec *codec = w->codec;
936 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
937
938 switch (event) {
939 case SND_SOC_DAPM_PRE_PMU:
a3cff81a 940 if (wm8994->aif1clk_enable) {
173efa09
DP		 941 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
942 WM8994_AIF1CLK_ENA_MASK,
943 WM8994_AIF1CLK_ENA);
a3cff81a
DP		 944 wm8994->aif1clk_enable = 0;
945 }
946 if (wm8994->aif2clk_enable) {
173efa09
DP		 947 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
948 WM8994_AIF2CLK_ENA_MASK,
949 WM8994_AIF2CLK_ENA);
a3cff81a
DP		 950 wm8994->aif2clk_enable = 0;
951 }
173efa09
DP		 952 break;
953 }
954
c6b7b570
MB		 955 /* We may also have postponed startup of DSP, handle that. */
956 wm8958_aif_ev(w, kcontrol, event);
957
173efa09
DP		 958 return 0;
959}
960
961static int late_disable_ev(struct snd_soc_dapm_widget *w,
962 struct snd_kcontrol *kcontrol, int event)
963{
964 struct snd_soc_codec *codec = w->codec;
965 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
966
967 switch (event) {
968 case SND_SOC_DAPM_POST_PMD:
a3cff81a 969 if (wm8994->aif1clk_disable) {
173efa09
DP		 970 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
971 WM8994_AIF1CLK_ENA_MASK, 0);
a3cff81a 972 wm8994->aif1clk_disable = 0;
173efa09 973 }
a3cff81a 974 if (wm8994->aif2clk_disable) {
173efa09
DP		 975 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
976 WM8994_AIF2CLK_ENA_MASK, 0);
a3cff81a 977 wm8994->aif2clk_disable = 0;
173efa09
DP		 978 }
979 break;
980 }
981
982 return 0;
983}
984
985static int aif1clk_ev(struct snd_soc_dapm_widget *w,
986 struct snd_kcontrol *kcontrol, int event)
987{
988 struct snd_soc_codec *codec = w->codec;
989 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
990
991 switch (event) {
992 case SND_SOC_DAPM_PRE_PMU:
993 wm8994->aif1clk_enable = 1;
994 break;
a3cff81a
DP		 995 case SND_SOC_DAPM_POST_PMD:
996 wm8994->aif1clk_disable = 1;
997 break;
173efa09
DP		 998 }
999
1000 return 0;
1001}
1002
1003static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1004 struct snd_kcontrol *kcontrol, int event)
1005{
1006 struct snd_soc_codec *codec = w->codec;
1007 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1008
1009 switch (event) {
1010 case SND_SOC_DAPM_PRE_PMU:
1011 wm8994->aif2clk_enable = 1;
1012 break;
a3cff81a
DP		 1013 case SND_SOC_DAPM_POST_PMD:
1014 wm8994->aif2clk_disable = 1;
1015 break;
173efa09
DP		 1016 }
1017
1018 return 0;
1019}
1020
04d28681
DP		 1021static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1022 struct snd_kcontrol *kcontrol, int event)
1023{
1024 late_enable_ev(w, kcontrol, event);
1025 return 0;
1026}
1027
b462c6e6
DP		 1028static int micbias_ev(struct snd_soc_dapm_widget *w,
1029 struct snd_kcontrol *kcontrol, int event)
1030{
1031 late_enable_ev(w, kcontrol, event);
1032 return 0;
1033}
1034
c52fd021
DP		 1035static int dac_ev(struct snd_soc_dapm_widget *w,
1036 struct snd_kcontrol *kcontrol, int event)
1037{
1038 struct snd_soc_codec *codec = w->codec;
1039 unsigned int mask = 1 << w->shift;
1040
1041 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1042 mask, mask);
1043 return 0;
1044}
1045
9e6e96a1
MB		 1046static const char *hp_mux_text[] = {
1047 "Mixer",
1048 "DAC",
1049};
1050
1051#define WM8994_HP_ENUM(xname, xenum) \
1052{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1053 .info = snd_soc_info_enum_double, \
1054 .get = snd_soc_dapm_get_enum_double, \
1055 .put = wm8994_put_hp_enum, \
1056 .private_value = (unsigned long)&xenum }
1057
1058static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1059 struct snd_ctl_elem_value *ucontrol)
1060{
9d03545d
JN		 1061 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1062 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1063 struct snd_soc_codec *codec = w->codec;
1064 int ret;
1065
1066 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1067
1068 wm8994_update_class_w(codec);
1069
1070 return ret;
1071}
1072
1073static const struct soc_enum hpl_enum =
1074 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1075
1076static const struct snd_kcontrol_new hpl_mux =
1077 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1078
1079static const struct soc_enum hpr_enum =
1080 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1081
1082static const struct snd_kcontrol_new hpr_mux =
1083 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1084
1085static const char *adc_mux_text[] = {
1086 "ADC",
1087 "DMIC",
1088};
1089
1090static const struct soc_enum adc_enum =
1091 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1092
1093static const struct snd_kcontrol_new adcl_mux =
1094 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1095
1096static const struct snd_kcontrol_new adcr_mux =
1097 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1098
1099static const struct snd_kcontrol_new left_speaker_mixer[] = {
1100SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1101SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1102SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1103SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1104SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1105};
1106
1107static const struct snd_kcontrol_new right_speaker_mixer[] = {
1108SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1109SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1110SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1111SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1112SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1113};
1114
1115/* Debugging; dump chip status after DAPM transitions */
1116static int post_ev(struct snd_soc_dapm_widget *w,
1117 struct snd_kcontrol *kcontrol, int event)
1118{
1119 struct snd_soc_codec *codec = w->codec;
1120 dev_dbg(codec->dev, "SRC status: %x\n",
1121 snd_soc_read(codec,
1122 WM8994_RATE_STATUS));
1123 return 0;
1124}
1125
1126static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1127SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1128 1, 1, 0),
1129SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1130 0, 1, 0),
1131};
1132
1133static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1134SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1135 1, 1, 0),
1136SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1137 0, 1, 0),
1138};
1139
a3257ba8
MB		 1140static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1141SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1142 1, 1, 0),
1143SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1144 0, 1, 0),
1145};
1146
1147static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1148SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1149 1, 1, 0),
1150SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1151 0, 1, 0),
1152};
1153
9e6e96a1
MB		 1154static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1155SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1156 5, 1, 0),
1157SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1158 4, 1, 0),
1159SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1160 2, 1, 0),
1161SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1162 1, 1, 0),
1163SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1164 0, 1, 0),
1165};
1166
1167static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1168SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1169 5, 1, 0),
1170SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1171 4, 1, 0),
1172SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1173 2, 1, 0),
1174SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1175 1, 1, 0),
1176SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1177 0, 1, 0),
1178};
1179
1180#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1181{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1182 .info = snd_soc_info_volsw, \
1183 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1184 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1185
1186static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1187 struct snd_ctl_elem_value *ucontrol)
1188{
9d03545d
JN		 1189 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1190 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1191 struct snd_soc_codec *codec = w->codec;
1192 int ret;
1193
1194 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1195
1196 wm8994_update_class_w(codec);
1197
1198 return ret;
1199}
1200
1201static const struct snd_kcontrol_new dac1l_mix[] = {
1202WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1203 5, 1, 0),
1204WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1205 4, 1, 0),
1206WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1207 2, 1, 0),
1208WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1209 1, 1, 0),
1210WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1211 0, 1, 0),
1212};
1213
1214static const struct snd_kcontrol_new dac1r_mix[] = {
1215WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1216 5, 1, 0),
1217WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1218 4, 1, 0),
1219WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1220 2, 1, 0),
1221WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1222 1, 1, 0),
1223WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1224 0, 1, 0),
1225};
1226
1227static const char *sidetone_text[] = {
1228 "ADC/DMIC1", "DMIC2",
1229};
1230
1231static const struct soc_enum sidetone1_enum =
1232 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1233
1234static const struct snd_kcontrol_new sidetone1_mux =
1235 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1236
1237static const struct soc_enum sidetone2_enum =
1238 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1239
1240static const struct snd_kcontrol_new sidetone2_mux =
1241 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1242
1243static const char *aif1dac_text[] = {
1244 "AIF1DACDAT", "AIF3DACDAT",
1245};
1246
1247static const struct soc_enum aif1dac_enum =
1248 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1249
1250static const struct snd_kcontrol_new aif1dac_mux =
1251 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1252
1253static const char *aif2dac_text[] = {
1254 "AIF2DACDAT", "AIF3DACDAT",
1255};
1256
1257static const struct soc_enum aif2dac_enum =
1258 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1259
1260static const struct snd_kcontrol_new aif2dac_mux =
1261 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1262
1263static const char *aif2adc_text[] = {
1264 "AIF2ADCDAT", "AIF3DACDAT",
1265};
1266
1267static const struct soc_enum aif2adc_enum =
1268 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1269
1270static const struct snd_kcontrol_new aif2adc_mux =
1271 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1272
1273static const char *aif3adc_text[] = {
c4431df0 1274 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1275};
1276
c4431df0 1277static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1278 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1279
c4431df0
MB		 1280static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1281 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1282
1283static const struct soc_enum wm8958_aif3adc_enum =
1284 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1285
1286static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1287 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1288
1289static const char *mono_pcm_out_text[] = {
1290 "None", "AIF2ADCL", "AIF2ADCR",
1291};
1292
1293static const struct soc_enum mono_pcm_out_enum =
1294 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1295
1296static const struct snd_kcontrol_new mono_pcm_out_mux =
1297 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1298
1299static const char *aif2dac_src_text[] = {
1300 "AIF2", "AIF3",
1301};
1302
1303/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1304static const struct soc_enum aif2dacl_src_enum =
1305 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1306
1307static const struct snd_kcontrol_new aif2dacl_src_mux =
1308 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1309
1310static const struct soc_enum aif2dacr_src_enum =
1311 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1312
1313static const struct snd_kcontrol_new aif2dacr_src_mux =
1314 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1315
173efa09
DP		 1316static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1317SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1318 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1319SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1320 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1321
1322SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1323 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1324SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1325 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1326SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1327 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1328SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1329 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1330SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1331 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1332
1333SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1334 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1335 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1336SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1337 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1338 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1339SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1340 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1341SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1342 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1343
1344SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1345};
1346
1347static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1348SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
b70a51ba
MB		 1349SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1350SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1351SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1352 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1353SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1354 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1355SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1356SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
173efa09
DP		 1357};
1358
c52fd021
DP		 1359static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1360SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1361 dac_ev, SND_SOC_DAPM_PRE_PMU),
1362SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1363 dac_ev, SND_SOC_DAPM_PRE_PMU),
1364SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1365 dac_ev, SND_SOC_DAPM_PRE_PMU),
1366SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1367 dac_ev, SND_SOC_DAPM_PRE_PMU),
1368};
1369
1370static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1371SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1372SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1373SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1374SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1375};
1376
04d28681 1377static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1378SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1379 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1380SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1381 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1382};
1383
1384static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1385SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1386SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1387};
1388
9e6e96a1
MB		 1389static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1390SND_SOC_DAPM_INPUT("DMIC1DAT"),
1391SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1392SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1393
b462c6e6
DP		 1394SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1395 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1396SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1397 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1398
9e6e96a1
MB		 1399SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1400 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1401
1402SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1403SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1404SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1405
7f94de48 1406SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1407 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1408SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1409 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1410SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1411 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1412 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1413SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1414 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1415 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1416
7f94de48 1417SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1418 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1419SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1420 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1421SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1422 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1423 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1424SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1425 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1426 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1427
1428SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1429 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1430SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1431 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1432
a3257ba8
MB		 1433SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1434 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1435SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1436 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1437
9e6e96a1
MB		 1438SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1439 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1440SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1441 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1442
1443SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1444SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1445
1446SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1447 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1448SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1449 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1450
1451SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1452 WM8994_POWER_MANAGEMENT_4, 13, 0),
1453SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1454 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1455SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1456 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1457 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1458SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1459 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1460 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1461
1462SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1463SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
7f94de48 1464SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1465SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1466
1467SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1468SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1469SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1470
1471SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
35024f49 1472SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1473
1474SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1475
1476SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1477SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1478SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1479SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1480
1481/* Power is done with the muxes since the ADC power also controls the
1482 * downsampling chain, the chip will automatically manage the analogue
1483 * specific portions.
1484 */
1485SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1486SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1487
9e6e96a1
MB		 1488SND_SOC_DAPM_POST("Debug log", post_ev),
1489};
1490
c4431df0
MB		 1491static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1492SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1493};
9e6e96a1 1494
c4431df0
MB		 1495static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1496SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1497SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1498SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1499SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1500};
1501
1502static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1503 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1504 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1505
1506 { "DSP1CLK", NULL, "CLK_SYS" },
1507 { "DSP2CLK", NULL, "CLK_SYS" },
1508 { "DSPINTCLK", NULL, "CLK_SYS" },
1509
1510 { "AIF1ADC1L", NULL, "AIF1CLK" },
1511 { "AIF1ADC1L", NULL, "DSP1CLK" },
1512 { "AIF1ADC1R", NULL, "AIF1CLK" },
1513 { "AIF1ADC1R", NULL, "DSP1CLK" },
1514 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1515
1516 { "AIF1DAC1L", NULL, "AIF1CLK" },
1517 { "AIF1DAC1L", NULL, "DSP1CLK" },
1518 { "AIF1DAC1R", NULL, "AIF1CLK" },
1519 { "AIF1DAC1R", NULL, "DSP1CLK" },
1520 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1521
1522 { "AIF1ADC2L", NULL, "AIF1CLK" },
1523 { "AIF1ADC2L", NULL, "DSP1CLK" },
1524 { "AIF1ADC2R", NULL, "AIF1CLK" },
1525 { "AIF1ADC2R", NULL, "DSP1CLK" },
1526 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1527
1528 { "AIF1DAC2L", NULL, "AIF1CLK" },
1529 { "AIF1DAC2L", NULL, "DSP1CLK" },
1530 { "AIF1DAC2R", NULL, "AIF1CLK" },
1531 { "AIF1DAC2R", NULL, "DSP1CLK" },
1532 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1533
1534 { "AIF2ADCL", NULL, "AIF2CLK" },
1535 { "AIF2ADCL", NULL, "DSP2CLK" },
1536 { "AIF2ADCR", NULL, "AIF2CLK" },
1537 { "AIF2ADCR", NULL, "DSP2CLK" },
1538 { "AIF2ADCR", NULL, "DSPINTCLK" },
1539
1540 { "AIF2DACL", NULL, "AIF2CLK" },
1541 { "AIF2DACL", NULL, "DSP2CLK" },
1542 { "AIF2DACR", NULL, "AIF2CLK" },
1543 { "AIF2DACR", NULL, "DSP2CLK" },
1544 { "AIF2DACR", NULL, "DSPINTCLK" },
1545
1546 { "DMIC1L", NULL, "DMIC1DAT" },
1547 { "DMIC1L", NULL, "CLK_SYS" },
1548 { "DMIC1R", NULL, "DMIC1DAT" },
1549 { "DMIC1R", NULL, "CLK_SYS" },
1550 { "DMIC2L", NULL, "DMIC2DAT" },
1551 { "DMIC2L", NULL, "CLK_SYS" },
1552 { "DMIC2R", NULL, "DMIC2DAT" },
1553 { "DMIC2R", NULL, "CLK_SYS" },
1554
1555 { "ADCL", NULL, "AIF1CLK" },
1556 { "ADCL", NULL, "DSP1CLK" },
1557 { "ADCL", NULL, "DSPINTCLK" },
1558
1559 { "ADCR", NULL, "AIF1CLK" },
1560 { "ADCR", NULL, "DSP1CLK" },
1561 { "ADCR", NULL, "DSPINTCLK" },
1562
1563 { "ADCL Mux", "ADC", "ADCL" },
1564 { "ADCL Mux", "DMIC", "DMIC1L" },
1565 { "ADCR Mux", "ADC", "ADCR" },
1566 { "ADCR Mux", "DMIC", "DMIC1R" },
1567
1568 { "DAC1L", NULL, "AIF1CLK" },
1569 { "DAC1L", NULL, "DSP1CLK" },
1570 { "DAC1L", NULL, "DSPINTCLK" },
1571
1572 { "DAC1R", NULL, "AIF1CLK" },
1573 { "DAC1R", NULL, "DSP1CLK" },
1574 { "DAC1R", NULL, "DSPINTCLK" },
1575
1576 { "DAC2L", NULL, "AIF2CLK" },
1577 { "DAC2L", NULL, "DSP2CLK" },
1578 { "DAC2L", NULL, "DSPINTCLK" },
1579
1580 { "DAC2R", NULL, "AIF2DACR" },
1581 { "DAC2R", NULL, "AIF2CLK" },
1582 { "DAC2R", NULL, "DSP2CLK" },
1583 { "DAC2R", NULL, "DSPINTCLK" },
1584
1585 { "TOCLK", NULL, "CLK_SYS" },
1586
1587 /* AIF1 outputs */
1588 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1589 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1590 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1591
1592 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1593 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1594 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1595
a3257ba8
MB		 1596 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1597 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1598 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1599
1600 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1601 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1602 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1603
9e6e96a1
MB		 1604 /* Pin level routing for AIF3 */
1605 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1606 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1607 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1608 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1609
9e6e96a1
MB		 1610 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1611 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1612 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1613 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1614 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1615 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1616 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1617
1618 /* DAC1 inputs */
9e6e96a1
MB		 1619 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1620 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1621 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1622 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1623 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1624
9e6e96a1
MB		 1625 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1626 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1627 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1628 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1629 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1630
1631 /* DAC2/AIF2 outputs */
1632 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1633 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1634 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1635 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1636 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1637 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1638
1639 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1640 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1641 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1642 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1643 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1644 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1645
7f94de48
MB		 1646 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1647 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1648 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1649 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1650
9e6e96a1
MB		 1651 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1652
1653 /* AIF3 output */
1654 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1655 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1656 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1657 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1658 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1659 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1660 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1661 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1662
1663 /* Sidetone */
1664 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1665 { "Left Sidetone", "DMIC2", "DMIC2L" },
1666 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1667 { "Right Sidetone", "DMIC2", "DMIC2R" },
1668
1669 /* Output stages */
1670 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1671 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1672
1673 { "SPKL", "DAC1 Switch", "DAC1L" },
1674 { "SPKL", "DAC2 Switch", "DAC2L" },
1675
1676 { "SPKR", "DAC1 Switch", "DAC1R" },
1677 { "SPKR", "DAC2 Switch", "DAC2R" },
1678
1679 { "Left Headphone Mux", "DAC", "DAC1L" },
1680 { "Right Headphone Mux", "DAC", "DAC1R" },
1681};
1682
173efa09
DP		 1683static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1684 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1685 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1686 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1687 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1688 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1689 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1690 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1691 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1692};
1693
1694static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1695 { "DAC1L", NULL, "DAC1L Mixer" },
1696 { "DAC1R", NULL, "DAC1R Mixer" },
1697 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1698 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1699};
1700
6ed8f148
MB		 1701static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1702 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1703 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1704 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1705 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1706 { "MICBIAS1", NULL, "CLK_SYS" },
1707 { "MICBIAS1", NULL, "MICBIAS Supply" },
1708 { "MICBIAS2", NULL, "CLK_SYS" },
1709 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1710};
1711
c4431df0
MB		 1712static const struct snd_soc_dapm_route wm8994_intercon[] = {
1713 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1714 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1715 { "MICBIAS1", NULL, "VMID" },
1716 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1717};
1718
1719static const struct snd_soc_dapm_route wm8958_intercon[] = {
1720 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1721 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1722
1723 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1724 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1725 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1726 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1727
1728 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1729 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1730
1731 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1732};
1733
9e6e96a1
MB		 1734/* The size in bits of the FLL divide multiplied by 10
1735 * to allow rounding later */
1736#define FIXED_FLL_SIZE ((1 << 16) * 10)
1737
1738struct fll_div {
1739 u16 outdiv;
1740 u16 n;
1741 u16 k;
1742 u16 clk_ref_div;
1743 u16 fll_fratio;
1744};
1745
1746static int wm8994_get_fll_config(struct fll_div *fll,
1747 int freq_in, int freq_out)
1748{
1749 u64 Kpart;
1750 unsigned int K, Ndiv, Nmod;
1751
1752 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1753
1754 /* Scale the input frequency down to <= 13.5MHz */
1755 fll->clk_ref_div = 0;
1756 while (freq_in > 13500000) {
1757 fll->clk_ref_div++;
1758 freq_in /= 2;
1759
1760 if (fll->clk_ref_div > 3)
1761 return -EINVAL;
1762 }
1763 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1764
1765 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1766 fll->outdiv = 3;
1767 while (freq_out * (fll->outdiv + 1) < 90000000) {
1768 fll->outdiv++;
1769 if (fll->outdiv > 63)
1770 return -EINVAL;
1771 }
1772 freq_out *= fll->outdiv + 1;
1773 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1774
1775 if (freq_in > 1000000) {
1776 fll->fll_fratio = 0;
7d48a6ac
MB		 1777 } else if (freq_in > 256000) {
1778 fll->fll_fratio = 1;
1779 freq_in *= 2;
1780 } else if (freq_in > 128000) {
1781 fll->fll_fratio = 2;
1782 freq_in *= 4;
1783 } else if (freq_in > 64000) {
9e6e96a1
MB		 1784 fll->fll_fratio = 3;
1785 freq_in *= 8;
7d48a6ac
MB		 1786 } else {
1787 fll->fll_fratio = 4;
1788 freq_in *= 16;
9e6e96a1
MB		 1789 }
1790 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1791
1792 /* Now, calculate N.K */
1793 Ndiv = freq_out / freq_in;
1794
1795 fll->n = Ndiv;
1796 Nmod = freq_out % freq_in;
1797 pr_debug("Nmod=%d\n", Nmod);
1798
1799 /* Calculate fractional part - scale up so we can round. */
1800 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1801
1802 do_div(Kpart, freq_in);
1803
1804 K = Kpart & 0xFFFFFFFF;
1805
1806 if ((K % 10) >= 5)
1807 K += 5;
1808
1809 /* Move down to proper range now rounding is done */
1810 fll->k = K / 10;
1811
1812 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1813
1814 return 0;
1815}
1816
f0fba2ad 1817static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1818 unsigned int freq_in, unsigned int freq_out)
1819{
b2c812e2 1820 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 1821 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 1822 int reg_offset, ret;
1823 struct fll_div fll;
1824 u16 reg, aif1, aif2;
c7ebf932 1825 unsigned long timeout;
4b7ed83a 1826 bool was_enabled;
9e6e96a1
MB		 1827
1828 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1829 & WM8994_AIF1CLK_ENA;
1830
1831 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1832 & WM8994_AIF2CLK_ENA;
1833
1834 switch (id) {
1835 case WM8994_FLL1:
1836 reg_offset = 0;
1837 id = 0;
1838 break;
1839 case WM8994_FLL2:
1840 reg_offset = 0x20;
1841 id = 1;
1842 break;
1843 default:
1844 return -EINVAL;
1845 }
1846
4b7ed83a
MB		 1847 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1848 was_enabled = reg & WM8994_FLL1_ENA;
1849
136ff2a2 1850 switch (src) {
7add84aa
MB		 1851 case 0:
1852 /* Allow no source specification when stopping */
1853 if (freq_out)
1854 return -EINVAL;
4514e899 1855 src = wm8994->fll[id].src;
7add84aa 1856 break;
136ff2a2
MB		 1857 case WM8994_FLL_SRC_MCLK1:
1858 case WM8994_FLL_SRC_MCLK2:
1859 case WM8994_FLL_SRC_LRCLK:
1860 case WM8994_FLL_SRC_BCLK:
1861 break;
1862 default:
1863 return -EINVAL;
1864 }
1865
9e6e96a1
MB		 1866 /* Are we changing anything? */
1867 if (wm8994->fll[id].src == src &&
1868 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1869 return 0;
1870
1871 /* If we're stopping the FLL redo the old config - no
1872 * registers will actually be written but we avoid GCC flow
1873 * analysis bugs spewing warnings.
1874 */
1875 if (freq_out)
1876 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1877 else
1878 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1879 wm8994->fll[id].out);
1880 if (ret < 0)
1881 return ret;
1882
1883 /* Gate the AIF clocks while we reclock */
1884 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1885 WM8994_AIF1CLK_ENA, 0);
1886 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1887 WM8994_AIF2CLK_ENA, 0);
1888
1889 /* We always need to disable the FLL while reconfiguring */
1890 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1891 WM8994_FLL1_ENA, 0);
1892
1893 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1894 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1895 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1896 WM8994_FLL1_OUTDIV_MASK |
1897 WM8994_FLL1_FRATIO_MASK, reg);
1898
1899 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1900
1901 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1902 WM8994_FLL1_N_MASK,
1903 fll.n << WM8994_FLL1_N_SHIFT);
1904
1905 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1906 WM8994_FLL1_REFCLK_DIV_MASK |
1907 WM8994_FLL1_REFCLK_SRC_MASK,
1908 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1909 (src - 1));
9e6e96a1 1910
f0f5039c
MB		 1911 /* Clear any pending completion from a previous failure */
1912 try_wait_for_completion(&wm8994->fll_locked[id]);
1913
9e6e96a1
MB		 1914 /* Enable (with fractional mode if required) */
1915 if (freq_out) {
4b7ed83a
MB		 1916 /* Enable VMID if we need it */
1917 if (!was_enabled) {
af6b6fe4
MB		 1918 active_reference(codec);
1919
4b7ed83a
MB		 1920 switch (control->type) {
1921 case WM8994:
1922 vmid_reference(codec);
1923 break;
1924 case WM8958:
1925 if (wm8994->revision < 1)
1926 vmid_reference(codec);
1927 break;
1928 default:
1929 break;
1930 }
1931 }
1932
9e6e96a1
MB		 1933 if (fll.k)
1934 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1935 else
1936 reg = WM8994_FLL1_ENA;
1937 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1938 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1939 reg);
8e9ddf81 1940
c7ebf932
MB		 1941 if (wm8994->fll_locked_irq) {
1942 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1943 msecs_to_jiffies(10));
1944 if (timeout == 0)
1945 dev_warn(codec->dev,
1946 "Timed out waiting for FLL lock\n");
1947 } else {
1948 msleep(5);
1949 }
4b7ed83a
MB		 1950 } else {
1951 if (was_enabled) {
1952 switch (control->type) {
1953 case WM8994:
1954 vmid_dereference(codec);
1955 break;
1956 case WM8958:
1957 if (wm8994->revision < 1)
1958 vmid_dereference(codec);
1959 break;
1960 default:
1961 break;
1962 }
af6b6fe4
MB		 1963
1964 active_dereference(codec);
4b7ed83a 1965 }
9e6e96a1
MB		 1966 }
1967
1968 wm8994->fll[id].in = freq_in;
1969 wm8994->fll[id].out = freq_out;
136ff2a2 1970 wm8994->fll[id].src = src;
9e6e96a1
MB		 1971
1972 /* Enable any gated AIF clocks */
1973 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1974 WM8994_AIF1CLK_ENA, aif1);
1975 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1976 WM8994_AIF2CLK_ENA, aif2);
1977
1978 configure_clock(codec);
1979
1980 return 0;
1981}
1982
c7ebf932
MB		 1983static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1984{
1985 struct completion *completion = data;
1986
1987 complete(completion);
1988
1989 return IRQ_HANDLED;
1990}
f0fba2ad 1991
66b47fdb
MB		 1992static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1993
f0fba2ad
LG		 1994static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1995 unsigned int freq_in, unsigned int freq_out)
1996{
1997 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1998}
1999
9e6e96a1
MB		 2000static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2001 int clk_id, unsigned int freq, int dir)
2002{
2003 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2004 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2005 int i;
9e6e96a1
MB		 2006
2007 switch (dai->id) {
2008 case 1:
2009 case 2:
2010 break;
2011
2012 default:
2013 /* AIF3 shares clocking with AIF1/2 */
2014 return -EINVAL;
2015 }
2016
2017 switch (clk_id) {
2018 case WM8994_SYSCLK_MCLK1:
2019 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2020 wm8994->mclk[0] = freq;
2021 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2022 dai->id, freq);
2023 break;
2024
2025 case WM8994_SYSCLK_MCLK2:
2026 /* TODO: Set GPIO AF */
2027 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2028 wm8994->mclk[1] = freq;
2029 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2030 dai->id, freq);
2031 break;
2032
2033 case WM8994_SYSCLK_FLL1:
2034 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2035 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2036 break;
2037
2038 case WM8994_SYSCLK_FLL2:
2039 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2040 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2041 break;
2042
66b47fdb
MB		 2043 case WM8994_SYSCLK_OPCLK:
2044 /* Special case - a division (times 10) is given and
2045 * no effect on main clocking.
2046 */
2047 if (freq) {
2048 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2049 if (opclk_divs[i] == freq)
2050 break;
2051 if (i == ARRAY_SIZE(opclk_divs))
2052 return -EINVAL;
2053 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2054 WM8994_OPCLK_DIV_MASK, i);
2055 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2056 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2057 } else {
2058 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2059 WM8994_OPCLK_ENA, 0);
2060 }
2061
9e6e96a1
MB		 2062 default:
2063 return -EINVAL;
2064 }
2065
2066 configure_clock(codec);
2067
2068 return 0;
2069}
2070
2071static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2072 enum snd_soc_bias_level level)
2073{
b6b05691 2074 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2075 struct wm8994 *control = wm8994->wm8994;
b6b05691 2076
9e6e96a1
MB		 2077 switch (level) {
2078 case SND_SOC_BIAS_ON:
2079 break;
2080
2081 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2082 /* MICBIAS into regulating mode */
2083 switch (control->type) {
2084 case WM8958:
2085 case WM1811:
2086 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2087 WM8958_MICB1_MODE, 0);
2088 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2089 WM8958_MICB2_MODE, 0);
2090 break;
2091 default:
2092 break;
2093 }
af6b6fe4
MB		 2094
2095 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2096 active_reference(codec);
9e6e96a1
MB		 2097 break;
2098
2099 case SND_SOC_BIAS_STANDBY:
ce6120cc 2100 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2
MB		 2101 switch (control->type) {
2102 case WM8994:
2103 if (wm8994->revision < 4) {
2104 /* Tweak DC servo and DSP
2105 * configuration for improved
2106 * performance. */
2107 snd_soc_write(codec, 0x102, 0x3);
2108 snd_soc_write(codec, 0x56, 0x3);
2109 snd_soc_write(codec, 0x817, 0);
2110 snd_soc_write(codec, 0x102, 0);
2111 }
2112 break;
2113
2114 case WM8958:
2115 if (wm8994->revision == 0) {
2116 /* Optimise performance for rev A */
2117 snd_soc_write(codec, 0x102, 0x3);
2118 snd_soc_write(codec, 0xcb, 0x81);
2119 snd_soc_write(codec, 0x817, 0);
2120 snd_soc_write(codec, 0x102, 0);
2121
2122 snd_soc_update_bits(codec,
2123 WM8958_CHARGE_PUMP_2,
2124 WM8958_CP_DISCH,
2125 WM8958_CP_DISCH);
2126 }
2127 break;
81204c84
MB		 2128
2129 case WM1811:
2130 if (wm8994->revision < 2) {
2131 snd_soc_write(codec, 0x102, 0x3);
2132 snd_soc_write(codec, 0x5d, 0x7e);
2133 snd_soc_write(codec, 0x5e, 0x0);
2134 snd_soc_write(codec, 0x102, 0x0);
2135 }
2136 break;
b6b05691 2137 }
9e6e96a1
MB		 2138
2139 /* Discharge LINEOUT1 & 2 */
2140 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2141 WM8994_LINEOUT1_DISCH |
2142 WM8994_LINEOUT2_DISCH,
2143 WM8994_LINEOUT1_DISCH |
2144 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2145 }
2146
af6b6fe4
MB		 2147 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2148 active_dereference(codec);
2149
500fa30e
MB		 2150 /* MICBIAS into bypass mode on newer devices */
2151 switch (control->type) {
2152 case WM8958:
2153 case WM1811:
2154 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2155 WM8958_MICB1_MODE,
2156 WM8958_MICB1_MODE);
2157 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2158 WM8958_MICB2_MODE,
2159 WM8958_MICB2_MODE);
2160 break;
2161 default:
2162 break;
2163 }
9e6e96a1
MB		 2164 break;
2165
2166 case SND_SOC_BIAS_OFF:
4105ab84 2167 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2168 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2169 break;
2170 }
ce6120cc 2171 codec->dapm.bias_level = level;
af6b6fe4 2172
9e6e96a1
MB		 2173 return 0;
2174}
2175
2176static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2177{
2178 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2179 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2180 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2181 int ms_reg;
2182 int aif1_reg;
2183 int ms = 0;
2184 int aif1 = 0;
2185
2186 switch (dai->id) {
2187 case 1:
2188 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2189 aif1_reg = WM8994_AIF1_CONTROL_1;
2190 break;
2191 case 2:
2192 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2193 aif1_reg = WM8994_AIF2_CONTROL_1;
2194 break;
2195 default:
2196 return -EINVAL;
2197 }
2198
2199 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2200 case SND_SOC_DAIFMT_CBS_CFS:
2201 break;
2202 case SND_SOC_DAIFMT_CBM_CFM:
2203 ms = WM8994_AIF1_MSTR;
2204 break;
2205 default:
2206 return -EINVAL;
2207 }
2208
2209 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2210 case SND_SOC_DAIFMT_DSP_B:
2211 aif1 |= WM8994_AIF1_LRCLK_INV;
2212 case SND_SOC_DAIFMT_DSP_A:
2213 aif1 |= 0x18;
2214 break;
2215 case SND_SOC_DAIFMT_I2S:
2216 aif1 |= 0x10;
2217 break;
2218 case SND_SOC_DAIFMT_RIGHT_J:
2219 break;
2220 case SND_SOC_DAIFMT_LEFT_J:
2221 aif1 |= 0x8;
2222 break;
2223 default:
2224 return -EINVAL;
2225 }
2226
2227 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2228 case SND_SOC_DAIFMT_DSP_A:
2229 case SND_SOC_DAIFMT_DSP_B:
2230 /* frame inversion not valid for DSP modes */
2231 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2232 case SND_SOC_DAIFMT_NB_NF:
2233 break;
2234 case SND_SOC_DAIFMT_IB_NF:
2235 aif1 |= WM8994_AIF1_BCLK_INV;
2236 break;
2237 default:
2238 return -EINVAL;
2239 }
2240 break;
2241
2242 case SND_SOC_DAIFMT_I2S:
2243 case SND_SOC_DAIFMT_RIGHT_J:
2244 case SND_SOC_DAIFMT_LEFT_J:
2245 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2246 case SND_SOC_DAIFMT_NB_NF:
2247 break;
2248 case SND_SOC_DAIFMT_IB_IF:
2249 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2250 break;
2251 case SND_SOC_DAIFMT_IB_NF:
2252 aif1 |= WM8994_AIF1_BCLK_INV;
2253 break;
2254 case SND_SOC_DAIFMT_NB_IF:
2255 aif1 |= WM8994_AIF1_LRCLK_INV;
2256 break;
2257 default:
2258 return -EINVAL;
2259 }
2260 break;
2261 default:
2262 return -EINVAL;
2263 }
2264
c4431df0
MB		 2265 /* The AIF2 format configuration needs to be mirrored to AIF3
2266 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2267 switch (control->type) {
2268 case WM1811:
2269 case WM8958:
2270 if (dai->id == 2)
2271 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2272 WM8994_AIF1_LRCLK_INV |
2273 WM8958_AIF3_FMT_MASK, aif1);
2274 break;
2275
2276 default:
2277 break;
2278 }
c4431df0 2279
9e6e96a1
MB		 2280 snd_soc_update_bits(codec, aif1_reg,
2281 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2282 WM8994_AIF1_FMT_MASK,
2283 aif1);
2284 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2285 ms);
2286
2287 return 0;
2288}
2289
2290static struct {
2291 int val, rate;
2292} srs[] = {
2293 { 0, 8000 },
2294 { 1, 11025 },
2295 { 2, 12000 },
2296 { 3, 16000 },
2297 { 4, 22050 },
2298 { 5, 24000 },
2299 { 6, 32000 },
2300 { 7, 44100 },
2301 { 8, 48000 },
2302 { 9, 88200 },
2303 { 10, 96000 },
2304};
2305
2306static int fs_ratios[] = {
2307 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2308};
2309
2310static int bclk_divs[] = {
2311 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2312 640, 880, 960, 1280, 1760, 1920
2313};
2314
2315static int wm8994_hw_params(struct snd_pcm_substream *substream,
2316 struct snd_pcm_hw_params *params,
2317 struct snd_soc_dai *dai)
2318{
2319 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2320 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2321 int aif1_reg;
b1e43d93 2322 int aif2_reg;
9e6e96a1
MB		 2323 int bclk_reg;
2324 int lrclk_reg;
2325 int rate_reg;
2326 int aif1 = 0;
b1e43d93 2327 int aif2 = 0;
9e6e96a1
MB		 2328 int bclk = 0;
2329 int lrclk = 0;
2330 int rate_val = 0;
2331 int id = dai->id - 1;
2332
2333 int i, cur_val, best_val, bclk_rate, best;
2334
2335 switch (dai->id) {
2336 case 1:
2337 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2338 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2339 bclk_reg = WM8994_AIF1_BCLK;
2340 rate_reg = WM8994_AIF1_RATE;
2341 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2342 wm8994->lrclk_shared[0]) {
9e6e96a1 2343 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2344 } else {
9e6e96a1 2345 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2346 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2347 }
9e6e96a1
MB		 2348 break;
2349 case 2:
2350 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2351 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2352 bclk_reg = WM8994_AIF2_BCLK;
2353 rate_reg = WM8994_AIF2_RATE;
2354 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2355 wm8994->lrclk_shared[1]) {
9e6e96a1 2356 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2357 } else {
9e6e96a1 2358 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2359 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2360 }
9e6e96a1
MB		 2361 break;
2362 default:
2363 return -EINVAL;
2364 }
2365
2366 bclk_rate = params_rate(params) * 2;
2367 switch (params_format(params)) {
2368 case SNDRV_PCM_FORMAT_S16_LE:
2369 bclk_rate *= 16;
2370 break;
2371 case SNDRV_PCM_FORMAT_S20_3LE:
2372 bclk_rate *= 20;
2373 aif1 |= 0x20;
2374 break;
2375 case SNDRV_PCM_FORMAT_S24_LE:
2376 bclk_rate *= 24;
2377 aif1 |= 0x40;
2378 break;
2379 case SNDRV_PCM_FORMAT_S32_LE:
2380 bclk_rate *= 32;
2381 aif1 |= 0x60;
2382 break;
2383 default:
2384 return -EINVAL;
2385 }
2386
2387 /* Try to find an appropriate sample rate; look for an exact match. */
2388 for (i = 0; i < ARRAY_SIZE(srs); i++)
2389 if (srs[i].rate == params_rate(params))
2390 break;
2391 if (i == ARRAY_SIZE(srs))
2392 return -EINVAL;
2393 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2394
2395 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2396 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2397 dai->id, wm8994->aifclk[id], bclk_rate);
2398
b1e43d93
MB		 2399 if (params_channels(params) == 1 &&
2400 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2401 aif2 |= WM8994_AIF1_MONO;
2402
9e6e96a1
MB		 2403 if (wm8994->aifclk[id] == 0) {
2404 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2405 return -EINVAL;
2406 }
2407
2408 /* AIFCLK/fs ratio; look for a close match in either direction */
2409 best = 0;
2410 best_val = abs((fs_ratios[0] * params_rate(params))
2411 - wm8994->aifclk[id]);
2412 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2413 cur_val = abs((fs_ratios[i] * params_rate(params))
2414 - wm8994->aifclk[id]);
2415 if (cur_val >= best_val)
2416 continue;
2417 best = i;
2418 best_val = cur_val;
2419 }
2420 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2421 dai->id, fs_ratios[best]);
2422 rate_val |= best;
2423
2424 /* We may not get quite the right frequency if using
2425 * approximate clocks so look for the closest match that is
2426 * higher than the target (we need to ensure that there enough
2427 * BCLKs to clock out the samples).
2428 */
2429 best = 0;
2430 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2431 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2432 if (cur_val < 0) /* BCLK table is sorted */
2433 break;
2434 best = i;
2435 }
07cd8ada 2436 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2437 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2438 bclk_divs[best], bclk_rate);
2439 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2440
2441 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2442 if (!lrclk) {
2443 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2444 bclk_rate);
2445 return -EINVAL;
2446 }
9e6e96a1
MB		 2447 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2448 lrclk, bclk_rate / lrclk);
2449
2450 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2451 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2452 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2453 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2454 lrclk);
2455 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2456 WM8994_AIF1CLK_RATE_MASK, rate_val);
2457
2458 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2459 switch (dai->id) {
2460 case 1:
2461 wm8994->dac_rates[0] = params_rate(params);
2462 wm8994_set_retune_mobile(codec, 0);
2463 wm8994_set_retune_mobile(codec, 1);
2464 break;
2465 case 2:
2466 wm8994->dac_rates[1] = params_rate(params);
2467 wm8994_set_retune_mobile(codec, 2);
2468 break;
2469 }
2470 }
2471
2472 return 0;
2473}
2474
c4431df0
MB		 2475static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2476 struct snd_pcm_hw_params *params,
2477 struct snd_soc_dai *dai)
2478{
2479 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2480 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2481 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2482 int aif1_reg;
2483 int aif1 = 0;
2484
2485 switch (dai->id) {
2486 case 3:
2487 switch (control->type) {
81204c84 2488 case WM1811:
c4431df0
MB		 2489 case WM8958:
2490 aif1_reg = WM8958_AIF3_CONTROL_1;
2491 break;
2492 default:
2493 return 0;
2494 }
2495 default:
2496 return 0;
2497 }
2498
2499 switch (params_format(params)) {
2500 case SNDRV_PCM_FORMAT_S16_LE:
2501 break;
2502 case SNDRV_PCM_FORMAT_S20_3LE:
2503 aif1 |= 0x20;
2504 break;
2505 case SNDRV_PCM_FORMAT_S24_LE:
2506 aif1 |= 0x40;
2507 break;
2508 case SNDRV_PCM_FORMAT_S32_LE:
2509 aif1 |= 0x60;
2510 break;
2511 default:
2512 return -EINVAL;
2513 }
2514
2515 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2516}
2517
7d02173c
MB		 2518static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2519 struct snd_soc_dai *dai)
2520{
2521 struct snd_soc_codec *codec = dai->codec;
2522 int rate_reg = 0;
2523
2524 switch (dai->id) {
2525 case 1:
2526 rate_reg = WM8994_AIF1_RATE;
2527 break;
2528 case 2:
c527e6aa 2529 rate_reg = WM8994_AIF2_RATE;
7d02173c
MB		 2530 break;
2531 default:
2532 break;
2533 }
2534
2535 /* If the DAI is idle then configure the divider tree for the
2536 * lowest output rate to save a little power if the clock is
2537 * still active (eg, because it is system clock).
2538 */
2539 if (rate_reg && !dai->playback_active && !dai->capture_active)
2540 snd_soc_update_bits(codec, rate_reg,
2541 WM8994_AIF1_SR_MASK |
2542 WM8994_AIF1CLK_RATE_MASK, 0x9);
2543}
2544
9e6e96a1
MB		 2545static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2546{
2547 struct snd_soc_codec *codec = codec_dai->codec;
2548 int mute_reg;
2549 int reg;
2550
2551 switch (codec_dai->id) {
2552 case 1:
2553 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2554 break;
2555 case 2:
2556 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2557 break;
2558 default:
2559 return -EINVAL;
2560 }
2561
2562 if (mute)
2563 reg = WM8994_AIF1DAC1_MUTE;
2564 else
2565 reg = 0;
2566
2567 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2568
2569 return 0;
2570}
2571
778a76e2
MB		 2572static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2573{
2574 struct snd_soc_codec *codec = codec_dai->codec;
2575 int reg, val, mask;
2576
2577 switch (codec_dai->id) {
2578 case 1:
2579 reg = WM8994_AIF1_MASTER_SLAVE;
2580 mask = WM8994_AIF1_TRI;
2581 break;
2582 case 2:
2583 reg = WM8994_AIF2_MASTER_SLAVE;
2584 mask = WM8994_AIF2_TRI;
2585 break;
2586 case 3:
2587 reg = WM8994_POWER_MANAGEMENT_6;
2588 mask = WM8994_AIF3_TRI;
2589 break;
2590 default:
2591 return -EINVAL;
2592 }
2593
2594 if (tristate)
2595 val = mask;
2596 else
2597 val = 0;
2598
78b3fb46 2599 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2600}
2601
d09f3ecf
MB		 2602static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2603{
2604 struct snd_soc_codec *codec = dai->codec;
2605
2606 /* Disable the pulls on the AIF if we're using it to save power. */
2607 snd_soc_update_bits(codec, WM8994_GPIO_3,
2608 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2609 snd_soc_update_bits(codec, WM8994_GPIO_4,
2610 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2611 snd_soc_update_bits(codec, WM8994_GPIO_5,
2612 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2613
2614 return 0;
2615}
2616
9e6e96a1
MB		 2617#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2618
2619#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2620 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2621
85e7652d 2622static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2623 .set_sysclk = wm8994_set_dai_sysclk,
2624 .set_fmt = wm8994_set_dai_fmt,
2625 .hw_params = wm8994_hw_params,
7d02173c 2626 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2627 .digital_mute = wm8994_aif_mute,
2628 .set_pll = wm8994_set_fll,
778a76e2 2629 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2630};
2631
85e7652d 2632static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2633 .set_sysclk = wm8994_set_dai_sysclk,
2634 .set_fmt = wm8994_set_dai_fmt,
2635 .hw_params = wm8994_hw_params,
7d02173c 2636 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2637 .digital_mute = wm8994_aif_mute,
2638 .set_pll = wm8994_set_fll,
778a76e2
MB		 2639 .set_tristate = wm8994_set_tristate,
2640};
2641
85e7652d 2642static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2643 .hw_params = wm8994_aif3_hw_params,
778a76e2 2644 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2645};
2646
f0fba2ad 2647static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2648 {
f0fba2ad 2649 .name = "wm8994-aif1",
8c7f78b3 2650 .id = 1,
9e6e96a1
MB		 2651 .playback = {
2652 .stream_name = "AIF1 Playback",
b1e43d93 2653 .channels_min = 1,
9e6e96a1
MB		 2654 .channels_max = 2,
2655 .rates = WM8994_RATES,
2656 .formats = WM8994_FORMATS,
99b0292d 2657 .sig_bits = 24,
9e6e96a1
MB		 2658 },
2659 .capture = {
2660 .stream_name = "AIF1 Capture",
b1e43d93 2661 .channels_min = 1,
9e6e96a1
MB		 2662 .channels_max = 2,
2663 .rates = WM8994_RATES,
2664 .formats = WM8994_FORMATS,
99b0292d 2665 .sig_bits = 24,
9e6e96a1
MB		 2666 },
2667 .ops = &wm8994_aif1_dai_ops,
2668 },
2669 {
f0fba2ad 2670 .name = "wm8994-aif2",
8c7f78b3 2671 .id = 2,
9e6e96a1
MB		 2672 .playback = {
2673 .stream_name = "AIF2 Playback",
b1e43d93 2674 .channels_min = 1,
9e6e96a1
MB		 2675 .channels_max = 2,
2676 .rates = WM8994_RATES,
2677 .formats = WM8994_FORMATS,
99b0292d 2678 .sig_bits = 24,
9e6e96a1
MB		 2679 },
2680 .capture = {
2681 .stream_name = "AIF2 Capture",
b1e43d93 2682 .channels_min = 1,
9e6e96a1
MB		 2683 .channels_max = 2,
2684 .rates = WM8994_RATES,
2685 .formats = WM8994_FORMATS,
99b0292d 2686 .sig_bits = 24,
9e6e96a1 2687 },
d09f3ecf 2688 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2689 .ops = &wm8994_aif2_dai_ops,
2690 },
2691 {
f0fba2ad 2692 .name = "wm8994-aif3",
8c7f78b3 2693 .id = 3,
9e6e96a1
MB		 2694 .playback = {
2695 .stream_name = "AIF3 Playback",
b1e43d93 2696 .channels_min = 1,
9e6e96a1
MB		 2697 .channels_max = 2,
2698 .rates = WM8994_RATES,
2699 .formats = WM8994_FORMATS,
99b0292d 2700 .sig_bits = 24,
9e6e96a1 2701 },
a8462bde 2702 .capture = {
9e6e96a1 2703 .stream_name = "AIF3 Capture",
b1e43d93 2704 .channels_min = 1,
9e6e96a1
MB		 2705 .channels_max = 2,
2706 .rates = WM8994_RATES,
2707 .formats = WM8994_FORMATS,
99b0292d
MB		 2708 .sig_bits = 24,
2709 },
778a76e2 2710 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2711 }
2712};
9e6e96a1
MB		 2713
2714#ifdef CONFIG_PM
84b315ee 2715static int wm8994_suspend(struct snd_soc_codec *codec)
9e6e96a1 2716{
b2c812e2 2717 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2718 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2719 int i, ret;
2720
ca629928
MB		 2721 switch (control->type) {
2722 case WM8994:
2723 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2724 break;
81204c84 2725 case WM1811:
af6b6fe4
MB		 2726 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2727 WM1811_JACKDET_MODE_MASK, 0);
2728 /* Fall through */
ca629928
MB		 2729 case WM8958:
2730 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2731 WM8958_MICD_ENA, 0);
2732 break;
2733 }
2734
9e6e96a1
MB		 2735 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2736 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2737 sizeof(struct wm8994_fll_config));
f0fba2ad 2738 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2739 if (ret < 0)
2740 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2741 i + 1, ret);
2742 }
2743
2744 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2745
2746 return 0;
2747}
2748
f0fba2ad 2749static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2750{
b2c812e2 2751 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2752 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 2753 int i, ret;
c52fd021
DP		 2754 unsigned int val, mask;
2755
2756 if (wm8994->revision < 4) {
2757 /* force a HW read */
d9a7666f
MB		 2758 ret = regmap_read(control->regmap,
2759 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 2760
2761 /* modify the cache only */
2762 codec->cache_only = 1;
2763 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2764 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2765 val &= mask;
2766 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2767 mask, val);
2768 codec->cache_only = 0;
2769 }
9e6e96a1 2770
9e6e96a1 2771 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2772 if (!wm8994->fll_suspend[i].out)
2773 continue;
2774
f0fba2ad 2775 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2776 wm8994->fll_suspend[i].src,
2777 wm8994->fll_suspend[i].in,
2778 wm8994->fll_suspend[i].out);
2779 if (ret < 0)
2780 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2781 i + 1, ret);
2782 }
2783
ca629928
MB		 2784 switch (control->type) {
2785 case WM8994:
2786 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2787 snd_soc_update_bits(codec, WM8994_MICBIAS,
2788 WM8994_MICD_ENA, WM8994_MICD_ENA);
2789 break;
81204c84 2790 case WM1811:
af6b6fe4
MB		 2791 if (wm8994->jackdet && wm8994->jack_cb) {
2792 /* Restart from idle */
2793 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2794 WM1811_JACKDET_MODE_MASK,
2795 WM1811_JACKDET_MODE_JACK);
2796 break;
2797 }
ca629928
MB		 2798 case WM8958:
2799 if (wm8994->jack_cb)
2800 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2801 WM8958_MICD_ENA, WM8958_MICD_ENA);
2802 break;
2803 }
2804
9e6e96a1
MB		 2805 return 0;
2806}
2807#else
2808#define wm8994_suspend NULL
2809#define wm8994_resume NULL
2810#endif
2811
2812static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2813{
f0fba2ad 2814 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2815 struct wm8994_pdata *pdata = wm8994->pdata;
2816 struct snd_kcontrol_new controls[] = {
2817 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2818 wm8994->retune_mobile_enum,
2819 wm8994_get_retune_mobile_enum,
2820 wm8994_put_retune_mobile_enum),
2821 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2822 wm8994->retune_mobile_enum,
2823 wm8994_get_retune_mobile_enum,
2824 wm8994_put_retune_mobile_enum),
2825 SOC_ENUM_EXT("AIF2 EQ Mode",
2826 wm8994->retune_mobile_enum,
2827 wm8994_get_retune_mobile_enum,
2828 wm8994_put_retune_mobile_enum),
2829 };
2830 int ret, i, j;
2831 const char **t;
2832
2833 /* We need an array of texts for the enum API but the number
2834 * of texts is likely to be less than the number of
2835 * configurations due to the sample rate dependency of the
2836 * configurations. */
2837 wm8994->num_retune_mobile_texts = 0;
2838 wm8994->retune_mobile_texts = NULL;
2839 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2840 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2841 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2842 wm8994->retune_mobile_texts[j]) == 0)
2843 break;
2844 }
2845
2846 if (j != wm8994->num_retune_mobile_texts)
2847 continue;
2848
2849 /* Expand the array... */
2850 t = krealloc(wm8994->retune_mobile_texts,
2851 sizeof(char *) *
2852 (wm8994->num_retune_mobile_texts + 1),
2853 GFP_KERNEL);
2854 if (t == NULL)
2855 continue;
2856
2857 /* ...store the new entry... */
2858 t[wm8994->num_retune_mobile_texts] =
2859 pdata->retune_mobile_cfgs[i].name;
2860
2861 /* ...and remember the new version. */
2862 wm8994->num_retune_mobile_texts++;
2863 wm8994->retune_mobile_texts = t;
2864 }
2865
2866 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2867 wm8994->num_retune_mobile_texts);
2868
2869 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2870 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2871
022658be 2872 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 2873 ARRAY_SIZE(controls));
2874 if (ret != 0)
f0fba2ad 2875 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2876 "Failed to add ReTune Mobile controls: %d\n", ret);
2877}
2878
2879static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2880{
f0fba2ad 2881 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2882 struct wm8994_pdata *pdata = wm8994->pdata;
2883 int ret, i;
2884
2885 if (!pdata)
2886 return;
2887
2888 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2889 pdata->lineout2_diff,
2890 pdata->lineout1fb,
2891 pdata->lineout2fb,
2892 pdata->jd_scthr,
2893 pdata->jd_thr,
2894 pdata->micbias1_lvl,
2895 pdata->micbias2_lvl);
2896
2897 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2898
2899 if (pdata->num_drc_cfgs) {
2900 struct snd_kcontrol_new controls[] = {
2901 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2902 wm8994_get_drc_enum, wm8994_put_drc_enum),
2903 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2904 wm8994_get_drc_enum, wm8994_put_drc_enum),
2905 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2906 wm8994_get_drc_enum, wm8994_put_drc_enum),
2907 };
2908
2909 /* We need an array of texts for the enum API */
7270cebe
MB		 2910 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2911 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 2912 if (!wm8994->drc_texts) {
f0fba2ad 2913 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2914 "Failed to allocate %d DRC config texts\n",
2915 pdata->num_drc_cfgs);
2916 return;
2917 }
2918
2919 for (i = 0; i < pdata->num_drc_cfgs; i++)
2920 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2921
2922 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2923 wm8994->drc_enum.texts = wm8994->drc_texts;
2924
022658be 2925 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 2926 ARRAY_SIZE(controls));
2927 if (ret != 0)
f0fba2ad 2928 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2929 "Failed to add DRC mode controls: %d\n", ret);
2930
2931 for (i = 0; i < WM8994_NUM_DRC; i++)
2932 wm8994_set_drc(codec, i);
2933 }
2934
2935 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2936 pdata->num_retune_mobile_cfgs);
2937
2938 if (pdata->num_retune_mobile_cfgs)
2939 wm8994_handle_retune_mobile_pdata(wm8994);
2940 else
022658be 2941 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 2942 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 2943
2944 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2945 if (pdata->micbias[i]) {
2946 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2947 pdata->micbias[i] & 0xffff);
2948 }
2949 }
9e6e96a1
MB		 2950}
2951
88766984
MB		 2952/**
2953 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2954 *
2955 * @codec: WM8994 codec
2956 * @jack: jack to report detection events on
2957 * @micbias: microphone bias to detect on
88766984
MB		 2958 *
2959 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2960 * being used to bring out signals to the processor then only platform
5ab230a7 2961 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2962 * be configured using snd_soc_jack_add_gpios() instead.
2963 *
2964 * Configuration of detection levels is available via the micbias1_lvl
2965 * and micbias2_lvl platform data members.
2966 */
2967int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 2968 int micbias)
88766984 2969{
b2c812e2 2970 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2971 struct wm8994_micdet *micdet;
2a8a856d 2972 struct wm8994 *control = wm8994->wm8994;
87092e3c 2973 int reg, ret;
88766984 2974
87092e3c
MB		 2975 if (control->type != WM8994) {
2976 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 2977 return -EINVAL;
87092e3c 2978 }
3a423157 2979
88766984
MB		 2980 switch (micbias) {
2981 case 1:
2982 micdet = &wm8994->micdet[0];
87092e3c
MB		 2983 if (jack)
2984 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
2985 "MICBIAS1");
2986 else
2987 ret = snd_soc_dapm_disable_pin(&codec->dapm,
2988 "MICBIAS1");
88766984
MB		 2989 break;
2990 case 2:
2991 micdet = &wm8994->micdet[1];
87092e3c
MB		 2992 if (jack)
2993 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
2994 "MICBIAS1");
2995 else
2996 ret = snd_soc_dapm_disable_pin(&codec->dapm,
2997 "MICBIAS1");
88766984
MB		 2998 break;
2999 default:
87092e3c 3000 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3001 return -EINVAL;
87092e3c 3002 }
88766984 3003
87092e3c
MB		 3004 if (ret != 0)
3005 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3006 micbias, ret);
3007
3008 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3009 micbias, jack);
88766984
MB		 3010
3011 /* Store the configuration */
3012 micdet->jack = jack;
87092e3c 3013 micdet->detecting = true;
88766984
MB		 3014
3015 /* If either of the jacks is set up then enable detection */
3016 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3017 reg = WM8994_MICD_ENA;
87092e3c 3018 else
88766984
MB		 3019 reg = 0;
3020
3021 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3022
87092e3c
MB		 3023 snd_soc_dapm_sync(&codec->dapm);
3024
88766984
MB		 3025 return 0;
3026}
3027EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3028
3029static irqreturn_t wm8994_mic_irq(int irq, void *data)
3030{
3031 struct wm8994_priv *priv = data;
f0fba2ad 3032 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 3033 int reg;
3034 int report;
3035
7116f452 3036#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3037 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3038#endif
2bbb5d66 3039
88766984
MB		 3040 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3041 if (reg < 0) {
3042 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3043 reg);
3044 return IRQ_HANDLED;
3045 }
3046
3047 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3048
3049 report = 0;
87092e3c
MB		 3050 if (reg & WM8994_MIC1_DET_STS) {
3051 if (priv->micdet[0].detecting)
3052 report = SND_JACK_HEADSET;
3053 }
3054 if (reg & WM8994_MIC1_SHRT_STS) {
3055 if (priv->micdet[0].detecting)
3056 report = SND_JACK_HEADPHONE;
3057 else
3058 report |= SND_JACK_BTN_0;
3059 }
3060 if (report)
3061 priv->micdet[0].detecting = false;
3062 else
3063 priv->micdet[0].detecting = true;
3064
88766984 3065 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3066 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3067
3068 report = 0;
87092e3c
MB		 3069 if (reg & WM8994_MIC2_DET_STS) {
3070 if (priv->micdet[1].detecting)
3071 report = SND_JACK_HEADSET;
3072 }
3073 if (reg & WM8994_MIC2_SHRT_STS) {
3074 if (priv->micdet[1].detecting)
3075 report = SND_JACK_HEADPHONE;
3076 else
3077 report |= SND_JACK_BTN_0;
3078 }
3079 if (report)
3080 priv->micdet[1].detecting = false;
3081 else
3082 priv->micdet[1].detecting = true;
3083
88766984 3084 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3085 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3086
3087 return IRQ_HANDLED;
3088}
3089
821edd2f
MB		 3090/* Default microphone detection handler for WM8958 - the user can
3091 * override this if they wish.
3092 */
3093static void wm8958_default_micdet(u16 status, void *data)
3094{
3095 struct snd_soc_codec *codec = data;
3096 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3097 int report;
821edd2f 3098
a1691343
MB		 3099 dev_dbg(codec->dev, "MICDET %x\n", status);
3100
af6b6fe4 3101 /* Either nothing present or just starting detection */
b00adf76 3102 if (!(status & WM8958_MICD_STS)) {
af6b6fe4
MB		 3103 if (!wm8994->jackdet) {
3104 /* If nothing present then clear our statuses */
3105 dev_dbg(codec->dev, "Detected open circuit\n");
3106 wm8994->jack_mic = false;
3107 wm8994->mic_detecting = true;
b00adf76 3108
af6b6fe4 3109 wm8958_micd_set_rate(codec);
b00adf76 3110
af6b6fe4
MB		 3111 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3112 wm8994->btn_mask |
3113 SND_JACK_HEADSET);
3114 }
b00adf76
MB		 3115 return;
3116 }
821edd2f 3117
b00adf76
MB		 3118 /* If the measurement is showing a high impedence we've got a
3119 * microphone.
3120 */
157a75e6 3121 if (wm8994->mic_detecting && (status & 0x600)) {
b00adf76
MB		 3122 dev_dbg(codec->dev, "Detected microphone\n");
3123
157a75e6 3124 wm8994->mic_detecting = false;
b00adf76
MB		 3125 wm8994->jack_mic = true;
3126
3127 wm8958_micd_set_rate(codec);
3128
3129 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3130 SND_JACK_HEADSET);
3131 }
821edd2f 3132
b00adf76 3133
7c08b51f 3134 if (wm8994->mic_detecting && status & 0xfc) {
b00adf76 3135 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3136 wm8994->mic_detecting = false;
b00adf76
MB		 3137
3138 wm8958_micd_set_rate(codec);
3139
3140 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3141 SND_JACK_HEADSET);
af6b6fe4
MB		 3142
3143 /* If we have jackdet that will detect removal */
3144 if (wm8994->jackdet) {
3145 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3146 WM8958_MICD_ENA, 0);
3147
3148 wm1811_jackdet_set_mode(codec,
3149 WM1811_JACKDET_MODE_JACK);
3150 }
b00adf76
MB		 3151 }
3152
3153 /* Report short circuit as a button */
3154 if (wm8994->jack_mic) {
4585790d 3155 report = 0;
b00adf76 3156 if (status & 0x4)
4585790d
MB		 3157 report |= SND_JACK_BTN_0;
3158
3159 if (status & 0x8)
3160 report |= SND_JACK_BTN_1;
3161
3162 if (status & 0x10)
3163 report |= SND_JACK_BTN_2;
3164
3165 if (status & 0x20)
3166 report |= SND_JACK_BTN_3;
3167
3168 if (status & 0x40)
3169 report |= SND_JACK_BTN_4;
3170
3171 if (status & 0x80)
3172 report |= SND_JACK_BTN_5;
3173
3174 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3175 wm8994->btn_mask);
b00adf76 3176 }
821edd2f
MB		 3177}
3178
af6b6fe4
MB		 3179static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3180{
3181 struct wm8994_priv *wm8994 = data;
3182 struct snd_soc_codec *codec = wm8994->codec;
3183 int reg;
3184
3185 mutex_lock(&wm8994->accdet_lock);
3186
3187 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3188 if (reg < 0) {
3189 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3190 mutex_unlock(&wm8994->accdet_lock);
3191 return IRQ_NONE;
3192 }
3193
3194 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3195
3196 if (reg & WM1811_JACKDET_LVL) {
3197 dev_dbg(codec->dev, "Jack detected\n");
3198
3199 snd_soc_jack_report(wm8994->micdet[0].jack,
3200 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3201
3202 /*
3203 * Start off measument of microphone impedence to find
3204 * out what's actually there.
3205 */
3206 wm8994->mic_detecting = true;
3207 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3208 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3209 WM8958_MICD_ENA, WM8958_MICD_ENA);
3210 } else {
3211 dev_dbg(codec->dev, "Jack not detected\n");
3212
3213 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3214 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3215 wm8994->btn_mask);
3216
3217 wm8994->mic_detecting = false;
3218 wm8994->jack_mic = false;
3219 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3220 WM8958_MICD_ENA, 0);
3221 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3222 }
3223
3224 mutex_unlock(&wm8994->accdet_lock);
3225
3226 return IRQ_HANDLED;
3227}
3228
821edd2f
MB		 3229/**
3230 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3231 *
3232 * @codec: WM8958 codec
3233 * @jack: jack to report detection events on
3234 *
3235 * Enable microphone detection functionality for the WM8958. By
3236 * default simple detection which supports the detection of up to 6
3237 * buttons plus video and microphone functionality is supported.
3238 *
3239 * The WM8958 has an advanced jack detection facility which is able to
3240 * support complex accessory detection, especially when used in
3241 * conjunction with external circuitry. In order to provide maximum
3242 * flexiblity a callback is provided which allows a completely custom
3243 * detection algorithm.
3244 */
3245int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3246 wm8958_micdet_cb cb, void *cb_data)
3247{
3248 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3249 struct wm8994 *control = wm8994->wm8994;
4585790d 3250 u16 micd_lvl_sel;
821edd2f 3251
81204c84
MB		 3252 switch (control->type) {
3253 case WM1811:
3254 case WM8958:
3255 break;
3256 default:
821edd2f 3257 return -EINVAL;
81204c84 3258 }
821edd2f
MB		 3259
3260 if (jack) {
3261 if (!cb) {
3262 dev_dbg(codec->dev, "Using default micdet callback\n");
3263 cb = wm8958_default_micdet;
3264 cb_data = codec;
3265 }
3266
4cdf5e49
MB		 3267 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3268
821edd2f
MB		 3269 wm8994->micdet[0].jack = jack;
3270 wm8994->jack_cb = cb;
3271 wm8994->jack_cb_data = cb_data;
3272
157a75e6 3273 wm8994->mic_detecting = true;
b00adf76
MB		 3274 wm8994->jack_mic = false;
3275
3276 wm8958_micd_set_rate(codec);
3277
4585790d
MB		 3278 /* Detect microphones and short circuits by default */
3279 if (wm8994->pdata->micd_lvl_sel)
3280 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3281 else
3282 micd_lvl_sel = 0x41;
3283
3284 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3285 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3286 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3287
b00adf76 3288 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3289 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3290
af6b6fe4
MB		 3291 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3292
3293 /*
3294 * If we can use jack detection start off with that,
3295 * otherwise jump straight to microphone detection.
3296 */
3297 if (wm8994->jackdet) {
3298 snd_soc_update_bits(codec, WM8994_LDO_1,
3299 WM8994_LDO1_DISCH, 0);
3300 wm1811_jackdet_set_mode(codec,
3301 WM1811_JACKDET_MODE_JACK);
3302 } else {
3303 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3304 WM8958_MICD_ENA, WM8958_MICD_ENA);
3305 }
3306
821edd2f
MB		 3307 } else {
3308 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3309 WM8958_MICD_ENA, 0);
4cdf5e49 3310 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
821edd2f
MB		 3311 }
3312
3313 return 0;
3314}
3315EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3316
3317static irqreturn_t wm8958_mic_irq(int irq, void *data)
3318{
3319 struct wm8994_priv *wm8994 = data;
3320 struct snd_soc_codec *codec = wm8994->codec;
19940b3d 3321 int reg, count;
821edd2f 3322
af6b6fe4
MB		 3323 mutex_lock(&wm8994->accdet_lock);
3324
3325 /*
3326 * Jack detection may have detected a removal simulataneously
3327 * with an update of the MICDET status; if so it will have
3328 * stopped detection and we can ignore this interrupt.
3329 */
3330 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3331 mutex_unlock(&wm8994->accdet_lock);
3332 return IRQ_HANDLED;
3333 }
3334
19940b3d
MB		 3335 /* We may occasionally read a detection without an impedence
3336 * range being provided - if that happens loop again.
3337 */
3338 count = 10;
3339 do {
3340 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3341 if (reg < 0) {
af6b6fe4 3342 mutex_unlock(&wm8994->accdet_lock);
19940b3d
MB		 3343 dev_err(codec->dev,
3344 "Failed to read mic detect status: %d\n",
3345 reg);
3346 return IRQ_NONE;
3347 }
821edd2f 3348
19940b3d
MB		 3349 if (!(reg & WM8958_MICD_VALID)) {
3350 dev_dbg(codec->dev, "Mic detect data not valid\n");
3351 goto out;
3352 }
3353
3354 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3355 break;
3356
3357 msleep(1);
3358 } while (count--);
3359
3360 if (count == 0)
3361 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3362
7116f452 3363#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3364 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3365#endif
2bbb5d66 3366
821edd2f
MB		 3367 if (wm8994->jack_cb)
3368 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3369 else
3370 dev_warn(codec->dev, "Accessory detection with no callback\n");
3371
3372out:
af6b6fe4
MB		 3373 mutex_unlock(&wm8994->accdet_lock);
3374
821edd2f
MB		 3375 return IRQ_HANDLED;
3376}
3377
3b1af3f8
MB		 3378static irqreturn_t wm8994_fifo_error(int irq, void *data)
3379{
3380 struct snd_soc_codec *codec = data;
3381
3382 dev_err(codec->dev, "FIFO error\n");
3383
3384 return IRQ_HANDLED;
3385}
3386
f0b182b0
MB		 3387static irqreturn_t wm8994_temp_warn(int irq, void *data)
3388{
3389 struct snd_soc_codec *codec = data;
3390
3391 dev_err(codec->dev, "Thermal warning\n");
3392
3393 return IRQ_HANDLED;
3394}
3395
3396static irqreturn_t wm8994_temp_shut(int irq, void *data)
3397{
3398 struct snd_soc_codec *codec = data;
3399
3400 dev_crit(codec->dev, "Thermal shutdown\n");
3401
3402 return IRQ_HANDLED;
3403}
3404
f0fba2ad 3405static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3406{
d9a7666f 3407 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
9e6e96a1 3408 struct wm8994_priv *wm8994;
ce6120cc 3409 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3410 unsigned int reg;
ec62dbd7 3411 int ret, i;
9e6e96a1 3412
d9a7666f 3413 codec->control_data = control->regmap;
9e6e96a1 3414
7270cebe
MB		 3415 wm8994 = devm_kzalloc(codec->dev, sizeof(struct wm8994_priv),
3416 GFP_KERNEL);
f0fba2ad 3417 if (wm8994 == NULL)
9e6e96a1 3418 return -ENOMEM;
b2c812e2 3419 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad 3420
d9a7666f 3421 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d
MB		 3422
3423 wm8994->wm8994 = dev_get_drvdata(codec->dev->parent);
f0fba2ad
LG		 3424 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3425 wm8994->codec = codec;
9e6e96a1 3426
af6b6fe4
MB		 3427 mutex_init(&wm8994->accdet_lock);
3428
c7ebf932
MB		 3429 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3430 init_completion(&wm8994->fll_locked[i]);
3431
9b7c525d
MB		 3432 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3433 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3434 else if (wm8994->pdata && wm8994->pdata->irq_base)
3435 wm8994->micdet_irq = wm8994->pdata->irq_base +
3436 WM8994_IRQ_MIC1_DET;
3437
39fb51a1 3438 pm_runtime_enable(codec->dev);
5fab5174 3439 pm_runtime_idle(codec->dev);
39fb51a1 3440
f959dee9
MB		 3441 /* By default use idle_bias_off, will override for WM8994 */
3442 codec->dapm.idle_bias_off = 1;
3443
9e6e96a1 3444 /* Set revision-specific configuration */
b6b05691 3445 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3446 switch (control->type) {
3447 case WM8994:
f959dee9
MB		 3448 /* Single ended line outputs should have VMID on. */
3449 if (!wm8994->pdata->lineout1_diff ||
3450 !wm8994->pdata->lineout2_diff)
3451 codec->dapm.idle_bias_off = 0;
3452
3a423157
MB		 3453 switch (wm8994->revision) {
3454 case 2:
3455 case 3:
4537c4e7
MB		 3456 wm8994->hubs.dcs_codes_l = -5;
3457 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3458 wm8994->hubs.hp_startup_mode = 1;
3459 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3460 wm8994->hubs.series_startup = 1;
3a423157
MB		 3461 break;
3462 default:
79ef0abc 3463 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3464 break;
3465 }
280ec8b7 3466 break;
3a423157
MB		 3467
3468 case WM8958:
8437f700 3469 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 3470 break;
3a423157 3471
81204c84
MB		 3472 case WM1811:
3473 wm8994->hubs.dcs_readback_mode = 2;
3474 wm8994->hubs.no_series_update = 1;
3475
3476 switch (wm8994->revision) {
3477 case 0:
3478 case 1:
fc8e6e86
MB		 3479 case 2:
3480 case 3:
6473a148
MB		 3481 wm8994->hubs.dcs_codes_l = -9;
3482 wm8994->hubs.dcs_codes_r = -5;
81204c84
MB		 3483 break;
3484 default:
3485 break;
3486 }
3487
3488 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3489 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3490 break;
3491
9e6e96a1
MB		 3492 default:
3493 break;
3494 }
9e6e96a1 3495
2a8a856d 3496 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3497 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3498 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3499 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3500 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3501 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3502
2a8a856d 3503 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3504 wm_hubs_dcs_done, "DC servo done",
3505 &wm8994->hubs);
3506 if (ret == 0)
3507 wm8994->hubs.dcs_done_irq = true;
3508
3a423157
MB		 3509 switch (control->type) {
3510 case WM8994:
9b7c525d
MB		 3511 if (wm8994->micdet_irq) {
3512 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3513 wm8994_mic_irq,
3514 IRQF_TRIGGER_RISING,
3515 "Mic1 detect",
3516 wm8994);
3517 if (ret != 0)
3518 dev_warn(codec->dev,
3519 "Failed to request Mic1 detect IRQ: %d\n",
3520 ret);
3521 }
3a423157 3522
2a8a856d 3523 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3524 WM8994_IRQ_MIC1_SHRT,
3525 wm8994_mic_irq, "Mic 1 short",
3526 wm8994);
3527 if (ret != 0)
3528 dev_warn(codec->dev,
3529 "Failed to request Mic1 short IRQ: %d\n",
3530 ret);
3531
2a8a856d 3532 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3533 WM8994_IRQ_MIC2_DET,
3534 wm8994_mic_irq, "Mic 2 detect",
3535 wm8994);
3536 if (ret != 0)
3537 dev_warn(codec->dev,
3538 "Failed to request Mic2 detect IRQ: %d\n",
3539 ret);
3540
2a8a856d 3541 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3542 WM8994_IRQ_MIC2_SHRT,
3543 wm8994_mic_irq, "Mic 2 short",
3544 wm8994);
3545 if (ret != 0)
3546 dev_warn(codec->dev,
3547 "Failed to request Mic2 short IRQ: %d\n",
3548 ret);
3549 break;
821edd2f
MB		 3550
3551 case WM8958:
81204c84 3552 case WM1811:
9b7c525d
MB		 3553 if (wm8994->micdet_irq) {
3554 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3555 wm8958_mic_irq,
3556 IRQF_TRIGGER_RISING,
3557 "Mic detect",
3558 wm8994);
3559 if (ret != 0)
3560 dev_warn(codec->dev,
3561 "Failed to request Mic detect IRQ: %d\n",
3562 ret);
3563 }
3a423157 3564 }
88766984 3565
af6b6fe4
MB		 3566 switch (control->type) {
3567 case WM1811:
3568 if (wm8994->revision > 1) {
3569 ret = wm8994_request_irq(wm8994->wm8994,
3570 WM8994_IRQ_GPIO(6),
3571 wm1811_jackdet_irq, "JACKDET",
3572 wm8994);
3573 if (ret == 0)
3574 wm8994->jackdet = true;
3575 }
3576 break;
3577 default:
3578 break;
3579 }
3580
c7ebf932
MB		 3581 wm8994->fll_locked_irq = true;
3582 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3583 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3584 WM8994_IRQ_FLL1_LOCK + i,
3585 wm8994_fll_locked_irq, "FLL lock",
3586 &wm8994->fll_locked[i]);
3587 if (ret != 0)
3588 wm8994->fll_locked_irq = false;
3589 }
3590
27060b3c
MB		 3591 /* Make sure we can read from the GPIOs if they're inputs */
3592 pm_runtime_get_sync(codec->dev);
3593
9e6e96a1
MB		 3594 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3595 * configured on init - if a system wants to do this dynamically
3596 * at runtime we can deal with that then.
3597 */
d9a7666f 3598 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 3599 if (ret < 0) {
3600 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3601 goto err_irq;
9e6e96a1 3602 }
d9a7666f 3603 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3604 wm8994->lrclk_shared[0] = 1;
3605 wm8994_dai[0].symmetric_rates = 1;
3606 } else {
3607 wm8994->lrclk_shared[0] = 0;
3608 }
3609
d9a7666f 3610 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 3611 if (ret < 0) {
3612 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3613 goto err_irq;
9e6e96a1 3614 }
d9a7666f 3615 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3616 wm8994->lrclk_shared[1] = 1;
3617 wm8994_dai[1].symmetric_rates = 1;
3618 } else {
3619 wm8994->lrclk_shared[1] = 0;
3620 }
3621
27060b3c
MB		 3622 pm_runtime_put(codec->dev);
3623
9e6e96a1 3624 /* Latch volume updates (right only; we always do left then right). */
baa81603
MB		 3625 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3626 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
9e6e96a1
MB		 3627 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3628 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
baa81603
MB		 3629 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3630 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
9e6e96a1
MB		 3631 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3632 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
baa81603
MB		 3633 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3634 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
9e6e96a1
MB		 3635 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3636 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
baa81603
MB		 3637 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3638 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
9e6e96a1
MB		 3639 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3640 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
baa81603
MB		 3641 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3642 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3643 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3644 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3645 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3646 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3647 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3648 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3649 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3650 WM8994_DAC1_VU, WM8994_DAC1_VU);
9e6e96a1
MB		 3651 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3652 WM8994_DAC1_VU, WM8994_DAC1_VU);
baa81603
MB		 3653 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3654 WM8994_DAC2_VU, WM8994_DAC2_VU);
9e6e96a1
MB		 3655 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3656 WM8994_DAC2_VU, WM8994_DAC2_VU);
3657
3658 /* Set the low bit of the 3D stereo depth so TLV matches */
3659 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3660 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3661 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3662 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3663 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3664 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3665 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3666 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3667 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3668
5b739670
MB		 3669 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3670 * use this; it only affects behaviour on idle TDM clock
3671 * cycles. */
3672 switch (control->type) {
3673 case WM8994:
3674 case WM8958:
3675 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3676 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3677 break;
3678 default:
3679 break;
3680 }
d1ce6b20 3681
500fa30e
MB		 3682 /* Put MICBIAS into bypass mode by default on newer devices */
3683 switch (control->type) {
3684 case WM8958:
3685 case WM1811:
3686 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3687 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3688 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3689 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3690 break;
3691 default:
3692 break;
3693 }
3694
9e6e96a1
MB		 3695 wm8994_update_class_w(codec);
3696
f0fba2ad 3697 wm8994_handle_pdata(wm8994);
9e6e96a1 3698
f0fba2ad 3699 wm_hubs_add_analogue_controls(codec);
022658be 3700 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 3701 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3702 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3703 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3704
3705 switch (control->type) {
3706 case WM8994:
3707 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3708 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3709 if (wm8994->revision < 4) {
173efa09
DP		 3710 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3711 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3712 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3713 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3714 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3715 ARRAY_SIZE(wm8994_dac_revd_widgets));
3716 } else {
173efa09
DP		 3717 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3718 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 3719 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3720 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 3721 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3722 ARRAY_SIZE(wm8994_dac_widgets));
3723 }
c4431df0
MB		 3724 break;
3725 case WM8958:
022658be 3726 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 3727 ARRAY_SIZE(wm8958_snd_controls));
3728 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3729 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 3730 if (wm8994->revision < 1) {
3731 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3732 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3733 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3734 ARRAY_SIZE(wm8994_adc_revd_widgets));
3735 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3736 ARRAY_SIZE(wm8994_dac_revd_widgets));
3737 } else {
3738 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3739 ARRAY_SIZE(wm8994_lateclk_widgets));
3740 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3741 ARRAY_SIZE(wm8994_adc_widgets));
3742 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3743 ARRAY_SIZE(wm8994_dac_widgets));
3744 }
c4431df0 3745 break;
81204c84
MB		 3746
3747 case WM1811:
022658be 3748 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 3749 ARRAY_SIZE(wm8958_snd_controls));
3750 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3751 ARRAY_SIZE(wm8958_dapm_widgets));
3752 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3753 ARRAY_SIZE(wm8994_lateclk_widgets));
3754 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3755 ARRAY_SIZE(wm8994_adc_widgets));
3756 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3757 ARRAY_SIZE(wm8994_dac_widgets));
3758 break;
c4431df0
MB		 3759 }
3760
3761
f0fba2ad 3762 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3763 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3764
c4431df0
MB		 3765 switch (control->type) {
3766 case WM8994:
3767 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3768 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3769
173efa09 3770 if (wm8994->revision < 4) {
6ed8f148
MB		 3771 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3772 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3773 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3774 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3775 } else {
3776 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3777 ARRAY_SIZE(wm8994_lateclk_intercon));
3778 }
c4431df0
MB		 3779 break;
3780 case WM8958:
780e2806
MB		 3781 if (wm8994->revision < 1) {
3782 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3783 ARRAY_SIZE(wm8994_revd_intercon));
3784 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3785 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3786 } else {
3787 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3788 ARRAY_SIZE(wm8994_lateclk_intercon));
3789 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3790 ARRAY_SIZE(wm8958_intercon));
3791 }
f701a2e5
MB		 3792
3793 wm8958_dsp2_init(codec);
c4431df0 3794 break;
81204c84
MB		 3795 case WM1811:
3796 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3797 ARRAY_SIZE(wm8994_lateclk_intercon));
3798 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3799 ARRAY_SIZE(wm8958_intercon));
3800 break;
c4431df0
MB		 3801 }
3802
9e6e96a1
MB		 3803 return 0;
3804
88766984 3805err_irq:
af6b6fe4
MB		 3806 if (wm8994->jackdet)
3807 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 3808 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3809 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3810 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3811 if (wm8994->micdet_irq)
3812 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 3813 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3814 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 3815 &wm8994->fll_locked[i]);
2a8a856d 3816 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3817 &wm8994->hubs);
2a8a856d
MB		 3818 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3819 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3820 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 3821
9e6e96a1
MB		 3822 return ret;
3823}
3824
f0fba2ad 3825static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3826{
f0fba2ad 3827 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3828 struct wm8994 *control = wm8994->wm8994;
c7ebf932 3829 int i;
9e6e96a1
MB		 3830
3831 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3832
39fb51a1
MB		 3833 pm_runtime_disable(codec->dev);
3834
c7ebf932 3835 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3836 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 3837 &wm8994->fll_locked[i]);
3838
2a8a856d 3839 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3840 &wm8994->hubs);
2a8a856d
MB		 3841 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3842 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3843 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 3844
af6b6fe4
MB		 3845 if (wm8994->jackdet)
3846 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3847
3a423157
MB		 3848 switch (control->type) {
3849 case WM8994:
9b7c525d
MB		 3850 if (wm8994->micdet_irq)
3851 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 3852 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 3853 wm8994);
2a8a856d 3854 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 3855 wm8994);
2a8a856d 3856 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 3857 wm8994);
3858 break;
821edd2f 3859
81204c84 3860 case WM1811:
821edd2f 3861 case WM8958:
9b7c525d
MB		 3862 if (wm8994->micdet_irq)
3863 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 3864 break;
3a423157 3865 }
fbbf5920
MB		 3866 if (wm8994->mbc)
3867 release_firmware(wm8994->mbc);
09e10d7f
MB		 3868 if (wm8994->mbc_vss)
3869 release_firmware(wm8994->mbc_vss);
31215871
MB		 3870 if (wm8994->enh_eq)
3871 release_firmware(wm8994->enh_eq);
24fb2b11 3872 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 3873
3874 return 0;
3875}
3876
1b39bf34
MB		 3877static int wm8994_soc_volatile(struct snd_soc_codec *codec,
3878 unsigned int reg)
3879{
3880 return true;
3881}
3882
f0fba2ad
LG		 3883static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3884 .probe = wm8994_codec_probe,
3885 .remove = wm8994_codec_remove,
3886 .suspend = wm8994_suspend,
3887 .resume = wm8994_resume,
f0fba2ad 3888 .set_bias_level = wm8994_set_bias_level,
1b39bf34
MB		 3889 .reg_cache_size = WM8994_MAX_REGISTER,
3890 .volatile_register = wm8994_soc_volatile,
f0fba2ad
LG		 3891};
3892
3893static int __devinit wm8994_probe(struct platform_device *pdev)
3894{
3895 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3896 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3897}
3898
3899static int __devexit wm8994_remove(struct platform_device *pdev)
3900{
3901 snd_soc_unregister_codec(&pdev->dev);
3902 return 0;
3903}
3904
9e6e96a1
MB		 3905static struct platform_driver wm8994_codec_driver = {
3906 .driver = {
3907 .name = "wm8994-codec",
3908 .owner = THIS_MODULE,
3909 },
f0fba2ad
LG		 3910 .probe = wm8994_probe,
3911 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3912};
3913
5bbcc3c0 3914module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 3915
3916MODULE_DESCRIPTION("ASoC WM8994 driver");
3917MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3918MODULE_LICENSE("GPL");
3919MODULE_ALIAS("platform:wm8994-codec");
Linux 6.x block layer and io_uring tree(s)