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942c435b MB |
1 | /* |
2 | * wm8993.c -- WM8993 ALSA SoC audio driver | |
3 | * | |
be587ef4 | 4 | * Copyright 2009, 2010 Wolfson Microelectronics plc |
942c435b MB |
5 | * |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/pm.h> | |
18 | #include <linux/i2c.h> | |
b37e399b | 19 | #include <linux/regulator/consumer.h> |
942c435b | 20 | #include <linux/spi/spi.h> |
5a0e3ad6 | 21 | #include <linux/slab.h> |
942c435b MB |
22 | #include <sound/core.h> |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/tlv.h> | |
26 | #include <sound/soc.h> | |
942c435b MB |
27 | #include <sound/initval.h> |
28 | #include <sound/wm8993.h> | |
29 | ||
30 | #include "wm8993.h" | |
a2342ae3 | 31 | #include "wm_hubs.h" |
942c435b | 32 | |
b37e399b MB |
33 | #define WM8993_NUM_SUPPLIES 6 |
34 | static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = { | |
35 | "DCVDD", | |
36 | "DBVDD", | |
37 | "AVDD1", | |
38 | "AVDD2", | |
39 | "CPVDD", | |
40 | "SPKVDD", | |
41 | }; | |
42 | ||
942c435b MB |
43 | static u16 wm8993_reg_defaults[WM8993_REGISTER_COUNT] = { |
44 | 0x8993, /* R0 - Software Reset */ | |
45 | 0x0000, /* R1 - Power Management (1) */ | |
46 | 0x6000, /* R2 - Power Management (2) */ | |
47 | 0x0000, /* R3 - Power Management (3) */ | |
48 | 0x4050, /* R4 - Audio Interface (1) */ | |
49 | 0x4000, /* R5 - Audio Interface (2) */ | |
50 | 0x01C8, /* R6 - Clocking 1 */ | |
51 | 0x0000, /* R7 - Clocking 2 */ | |
52 | 0x0000, /* R8 - Audio Interface (3) */ | |
53 | 0x0040, /* R9 - Audio Interface (4) */ | |
54 | 0x0004, /* R10 - DAC CTRL */ | |
55 | 0x00C0, /* R11 - Left DAC Digital Volume */ | |
56 | 0x00C0, /* R12 - Right DAC Digital Volume */ | |
57 | 0x0000, /* R13 - Digital Side Tone */ | |
58 | 0x0300, /* R14 - ADC CTRL */ | |
59 | 0x00C0, /* R15 - Left ADC Digital Volume */ | |
60 | 0x00C0, /* R16 - Right ADC Digital Volume */ | |
61 | 0x0000, /* R17 */ | |
62 | 0x0000, /* R18 - GPIO CTRL 1 */ | |
63 | 0x0010, /* R19 - GPIO1 */ | |
64 | 0x0000, /* R20 - IRQ_DEBOUNCE */ | |
65 | 0x0000, /* R21 */ | |
66 | 0x8000, /* R22 - GPIOCTRL 2 */ | |
67 | 0x0800, /* R23 - GPIO_POL */ | |
68 | 0x008B, /* R24 - Left Line Input 1&2 Volume */ | |
69 | 0x008B, /* R25 - Left Line Input 3&4 Volume */ | |
70 | 0x008B, /* R26 - Right Line Input 1&2 Volume */ | |
71 | 0x008B, /* R27 - Right Line Input 3&4 Volume */ | |
72 | 0x006D, /* R28 - Left Output Volume */ | |
73 | 0x006D, /* R29 - Right Output Volume */ | |
74 | 0x0066, /* R30 - Line Outputs Volume */ | |
75 | 0x0020, /* R31 - HPOUT2 Volume */ | |
76 | 0x0079, /* R32 - Left OPGA Volume */ | |
77 | 0x0079, /* R33 - Right OPGA Volume */ | |
78 | 0x0003, /* R34 - SPKMIXL Attenuation */ | |
79 | 0x0003, /* R35 - SPKMIXR Attenuation */ | |
80 | 0x0011, /* R36 - SPKOUT Mixers */ | |
81 | 0x0100, /* R37 - SPKOUT Boost */ | |
82 | 0x0079, /* R38 - Speaker Volume Left */ | |
83 | 0x0079, /* R39 - Speaker Volume Right */ | |
84 | 0x0000, /* R40 - Input Mixer2 */ | |
85 | 0x0000, /* R41 - Input Mixer3 */ | |
86 | 0x0000, /* R42 - Input Mixer4 */ | |
87 | 0x0000, /* R43 - Input Mixer5 */ | |
88 | 0x0000, /* R44 - Input Mixer6 */ | |
89 | 0x0000, /* R45 - Output Mixer1 */ | |
90 | 0x0000, /* R46 - Output Mixer2 */ | |
91 | 0x0000, /* R47 - Output Mixer3 */ | |
92 | 0x0000, /* R48 - Output Mixer4 */ | |
93 | 0x0000, /* R49 - Output Mixer5 */ | |
94 | 0x0000, /* R50 - Output Mixer6 */ | |
95 | 0x0000, /* R51 - HPOUT2 Mixer */ | |
96 | 0x0000, /* R52 - Line Mixer1 */ | |
97 | 0x0000, /* R53 - Line Mixer2 */ | |
98 | 0x0000, /* R54 - Speaker Mixer */ | |
99 | 0x0000, /* R55 - Additional Control */ | |
100 | 0x0000, /* R56 - AntiPOP1 */ | |
101 | 0x0000, /* R57 - AntiPOP2 */ | |
102 | 0x0000, /* R58 - MICBIAS */ | |
103 | 0x0000, /* R59 */ | |
104 | 0x0000, /* R60 - FLL Control 1 */ | |
105 | 0x0000, /* R61 - FLL Control 2 */ | |
106 | 0x0000, /* R62 - FLL Control 3 */ | |
107 | 0x2EE0, /* R63 - FLL Control 4 */ | |
108 | 0x0002, /* R64 - FLL Control 5 */ | |
109 | 0x2287, /* R65 - Clocking 3 */ | |
110 | 0x025F, /* R66 - Clocking 4 */ | |
111 | 0x0000, /* R67 - MW Slave Control */ | |
112 | 0x0000, /* R68 */ | |
113 | 0x0002, /* R69 - Bus Control 1 */ | |
114 | 0x0000, /* R70 - Write Sequencer 0 */ | |
115 | 0x0000, /* R71 - Write Sequencer 1 */ | |
116 | 0x0000, /* R72 - Write Sequencer 2 */ | |
117 | 0x0000, /* R73 - Write Sequencer 3 */ | |
118 | 0x0000, /* R74 - Write Sequencer 4 */ | |
119 | 0x0000, /* R75 - Write Sequencer 5 */ | |
120 | 0x1F25, /* R76 - Charge Pump 1 */ | |
121 | 0x0000, /* R77 */ | |
122 | 0x0000, /* R78 */ | |
123 | 0x0000, /* R79 */ | |
124 | 0x0000, /* R80 */ | |
125 | 0x0000, /* R81 - Class W 0 */ | |
126 | 0x0000, /* R82 */ | |
127 | 0x0000, /* R83 */ | |
128 | 0x0000, /* R84 - DC Servo 0 */ | |
129 | 0x054A, /* R85 - DC Servo 1 */ | |
130 | 0x0000, /* R86 */ | |
131 | 0x0000, /* R87 - DC Servo 3 */ | |
132 | 0x0000, /* R88 - DC Servo Readback 0 */ | |
133 | 0x0000, /* R89 - DC Servo Readback 1 */ | |
134 | 0x0000, /* R90 - DC Servo Readback 2 */ | |
135 | 0x0000, /* R91 */ | |
136 | 0x0000, /* R92 */ | |
137 | 0x0000, /* R93 */ | |
138 | 0x0000, /* R94 */ | |
139 | 0x0000, /* R95 */ | |
140 | 0x0100, /* R96 - Analogue HP 0 */ | |
141 | 0x0000, /* R97 */ | |
142 | 0x0000, /* R98 - EQ1 */ | |
143 | 0x000C, /* R99 - EQ2 */ | |
144 | 0x000C, /* R100 - EQ3 */ | |
145 | 0x000C, /* R101 - EQ4 */ | |
146 | 0x000C, /* R102 - EQ5 */ | |
147 | 0x000C, /* R103 - EQ6 */ | |
148 | 0x0FCA, /* R104 - EQ7 */ | |
149 | 0x0400, /* R105 - EQ8 */ | |
150 | 0x00D8, /* R106 - EQ9 */ | |
151 | 0x1EB5, /* R107 - EQ10 */ | |
152 | 0xF145, /* R108 - EQ11 */ | |
153 | 0x0B75, /* R109 - EQ12 */ | |
154 | 0x01C5, /* R110 - EQ13 */ | |
155 | 0x1C58, /* R111 - EQ14 */ | |
156 | 0xF373, /* R112 - EQ15 */ | |
157 | 0x0A54, /* R113 - EQ16 */ | |
158 | 0x0558, /* R114 - EQ17 */ | |
159 | 0x168E, /* R115 - EQ18 */ | |
160 | 0xF829, /* R116 - EQ19 */ | |
161 | 0x07AD, /* R117 - EQ20 */ | |
162 | 0x1103, /* R118 - EQ21 */ | |
163 | 0x0564, /* R119 - EQ22 */ | |
164 | 0x0559, /* R120 - EQ23 */ | |
165 | 0x4000, /* R121 - EQ24 */ | |
166 | 0x0000, /* R122 - Digital Pulls */ | |
167 | 0x0F08, /* R123 - DRC Control 1 */ | |
168 | 0x0000, /* R124 - DRC Control 2 */ | |
169 | 0x0080, /* R125 - DRC Control 3 */ | |
170 | 0x0000, /* R126 - DRC Control 4 */ | |
171 | }; | |
172 | ||
173 | static struct { | |
174 | int ratio; | |
175 | int clk_sys_rate; | |
176 | } clk_sys_rates[] = { | |
177 | { 64, 0 }, | |
178 | { 128, 1 }, | |
179 | { 192, 2 }, | |
180 | { 256, 3 }, | |
181 | { 384, 4 }, | |
182 | { 512, 5 }, | |
183 | { 768, 6 }, | |
184 | { 1024, 7 }, | |
185 | { 1408, 8 }, | |
186 | { 1536, 9 }, | |
187 | }; | |
188 | ||
189 | static struct { | |
190 | int rate; | |
191 | int sample_rate; | |
192 | } sample_rates[] = { | |
193 | { 8000, 0 }, | |
194 | { 11025, 1 }, | |
195 | { 12000, 1 }, | |
196 | { 16000, 2 }, | |
197 | { 22050, 3 }, | |
198 | { 24000, 3 }, | |
199 | { 32000, 4 }, | |
200 | { 44100, 5 }, | |
201 | { 48000, 5 }, | |
202 | }; | |
203 | ||
204 | static struct { | |
205 | int div; /* *10 due to .5s */ | |
206 | int bclk_div; | |
207 | } bclk_divs[] = { | |
208 | { 10, 0 }, | |
209 | { 15, 1 }, | |
210 | { 20, 2 }, | |
211 | { 30, 3 }, | |
212 | { 40, 4 }, | |
213 | { 55, 5 }, | |
214 | { 60, 6 }, | |
215 | { 80, 7 }, | |
216 | { 110, 8 }, | |
217 | { 120, 9 }, | |
218 | { 160, 10 }, | |
219 | { 220, 11 }, | |
220 | { 240, 12 }, | |
221 | { 320, 13 }, | |
222 | { 440, 14 }, | |
223 | { 480, 15 }, | |
224 | }; | |
225 | ||
226 | struct wm8993_priv { | |
3ed7074c | 227 | struct wm_hubs_data hubs_data; |
b37e399b | 228 | struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES]; |
942c435b | 229 | struct wm8993_platform_data pdata; |
f0fba2ad | 230 | enum snd_soc_control_type control_type; |
942c435b MB |
231 | int master; |
232 | int sysclk_source; | |
d3c9e9a1 MB |
233 | int tdm_slots; |
234 | int tdm_width; | |
942c435b MB |
235 | unsigned int mclk_rate; |
236 | unsigned int sysclk_rate; | |
237 | unsigned int fs; | |
238 | unsigned int bclk; | |
239 | int class_w_users; | |
240 | unsigned int fll_fref; | |
241 | unsigned int fll_fout; | |
53242c68 | 242 | int fll_src; |
942c435b MB |
243 | }; |
244 | ||
d4754ec9 | 245 | static int wm8993_volatile(struct snd_soc_codec *codec, unsigned int reg) |
942c435b MB |
246 | { |
247 | switch (reg) { | |
248 | case WM8993_SOFTWARE_RESET: | |
249 | case WM8993_DC_SERVO_0: | |
250 | case WM8993_DC_SERVO_READBACK_0: | |
251 | case WM8993_DC_SERVO_READBACK_1: | |
252 | case WM8993_DC_SERVO_READBACK_2: | |
253 | return 1; | |
254 | default: | |
255 | return 0; | |
256 | } | |
257 | } | |
258 | ||
942c435b MB |
259 | struct _fll_div { |
260 | u16 fll_fratio; | |
261 | u16 fll_outdiv; | |
262 | u16 fll_clk_ref_div; | |
263 | u16 n; | |
264 | u16 k; | |
265 | }; | |
266 | ||
267 | /* The size in bits of the FLL divide multiplied by 10 | |
268 | * to allow rounding later */ | |
269 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
270 | ||
271 | static struct { | |
272 | unsigned int min; | |
273 | unsigned int max; | |
274 | u16 fll_fratio; | |
275 | int ratio; | |
276 | } fll_fratios[] = { | |
277 | { 0, 64000, 4, 16 }, | |
278 | { 64000, 128000, 3, 8 }, | |
279 | { 128000, 256000, 2, 4 }, | |
280 | { 256000, 1000000, 1, 2 }, | |
281 | { 1000000, 13500000, 0, 1 }, | |
282 | }; | |
283 | ||
284 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | |
285 | unsigned int Fout) | |
286 | { | |
287 | u64 Kpart; | |
288 | unsigned int K, Ndiv, Nmod, target; | |
289 | unsigned int div; | |
290 | int i; | |
291 | ||
292 | /* Fref must be <=13.5MHz */ | |
293 | div = 1; | |
0c11f655 | 294 | fll_div->fll_clk_ref_div = 0; |
942c435b MB |
295 | while ((Fref / div) > 13500000) { |
296 | div *= 2; | |
0c11f655 | 297 | fll_div->fll_clk_ref_div++; |
942c435b MB |
298 | |
299 | if (div > 8) { | |
300 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", | |
301 | Fref); | |
302 | return -EINVAL; | |
303 | } | |
304 | } | |
305 | ||
306 | pr_debug("Fref=%u Fout=%u\n", Fref, Fout); | |
307 | ||
308 | /* Apply the division for our remaining calculations */ | |
309 | Fref /= div; | |
310 | ||
311 | /* Fvco should be 90-100MHz; don't check the upper bound */ | |
312 | div = 0; | |
313 | target = Fout * 2; | |
314 | while (target < 90000000) { | |
315 | div++; | |
316 | target *= 2; | |
317 | if (div > 7) { | |
318 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", | |
319 | Fout); | |
320 | return -EINVAL; | |
321 | } | |
322 | } | |
323 | fll_div->fll_outdiv = div; | |
324 | ||
325 | pr_debug("Fvco=%dHz\n", target); | |
326 | ||
25985edc | 327 | /* Find an appropriate FLL_FRATIO and factor it out of the target */ |
942c435b MB |
328 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { |
329 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { | |
330 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; | |
331 | target /= fll_fratios[i].ratio; | |
332 | break; | |
333 | } | |
334 | } | |
335 | if (i == ARRAY_SIZE(fll_fratios)) { | |
336 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); | |
337 | return -EINVAL; | |
338 | } | |
339 | ||
340 | /* Now, calculate N.K */ | |
341 | Ndiv = target / Fref; | |
342 | ||
343 | fll_div->n = Ndiv; | |
344 | Nmod = target % Fref; | |
345 | pr_debug("Nmod=%d\n", Nmod); | |
346 | ||
347 | /* Calculate fractional part - scale up so we can round. */ | |
348 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
349 | ||
350 | do_div(Kpart, Fref); | |
351 | ||
352 | K = Kpart & 0xFFFFFFFF; | |
353 | ||
354 | if ((K % 10) >= 5) | |
355 | K += 5; | |
356 | ||
357 | /* Move down to proper range now rounding is done */ | |
358 | fll_div->k = K / 10; | |
359 | ||
360 | pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", | |
361 | fll_div->n, fll_div->k, | |
362 | fll_div->fll_fratio, fll_div->fll_outdiv, | |
363 | fll_div->fll_clk_ref_div); | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
f0fba2ad | 368 | static int _wm8993_set_fll(struct snd_soc_codec *codec, int fll_id, int source, |
942c435b MB |
369 | unsigned int Fref, unsigned int Fout) |
370 | { | |
b2c812e2 | 371 | struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); |
942c435b MB |
372 | u16 reg1, reg4, reg5; |
373 | struct _fll_div fll_div; | |
374 | int ret; | |
375 | ||
376 | /* Any change? */ | |
377 | if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout) | |
378 | return 0; | |
379 | ||
380 | /* Disable the FLL */ | |
381 | if (Fout == 0) { | |
382 | dev_dbg(codec->dev, "FLL disabled\n"); | |
383 | wm8993->fll_fref = 0; | |
384 | wm8993->fll_fout = 0; | |
385 | ||
3bf6e421 | 386 | reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1); |
942c435b | 387 | reg1 &= ~WM8993_FLL_ENA; |
3bf6e421 | 388 | snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); |
942c435b MB |
389 | |
390 | return 0; | |
391 | } | |
392 | ||
393 | ret = fll_factors(&fll_div, Fref, Fout); | |
394 | if (ret != 0) | |
395 | return ret; | |
396 | ||
3bf6e421 | 397 | reg5 = snd_soc_read(codec, WM8993_FLL_CONTROL_5); |
942c435b MB |
398 | reg5 &= ~WM8993_FLL_CLK_SRC_MASK; |
399 | ||
400 | switch (fll_id) { | |
401 | case WM8993_FLL_MCLK: | |
402 | break; | |
403 | ||
404 | case WM8993_FLL_LRCLK: | |
405 | reg5 |= 1; | |
406 | break; | |
407 | ||
408 | case WM8993_FLL_BCLK: | |
409 | reg5 |= 2; | |
410 | break; | |
411 | ||
412 | default: | |
413 | dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); | |
414 | return -EINVAL; | |
415 | } | |
416 | ||
417 | /* Any FLL configuration change requires that the FLL be | |
418 | * disabled first. */ | |
3bf6e421 | 419 | reg1 = snd_soc_read(codec, WM8993_FLL_CONTROL_1); |
942c435b | 420 | reg1 &= ~WM8993_FLL_ENA; |
3bf6e421 | 421 | snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); |
942c435b MB |
422 | |
423 | /* Apply the configuration */ | |
424 | if (fll_div.k) | |
425 | reg1 |= WM8993_FLL_FRAC_MASK; | |
426 | else | |
427 | reg1 &= ~WM8993_FLL_FRAC_MASK; | |
3bf6e421 | 428 | snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1); |
942c435b | 429 | |
3bf6e421 MB |
430 | snd_soc_write(codec, WM8993_FLL_CONTROL_2, |
431 | (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) | | |
432 | (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT)); | |
433 | snd_soc_write(codec, WM8993_FLL_CONTROL_3, fll_div.k); | |
942c435b | 434 | |
3bf6e421 | 435 | reg4 = snd_soc_read(codec, WM8993_FLL_CONTROL_4); |
942c435b MB |
436 | reg4 &= ~WM8993_FLL_N_MASK; |
437 | reg4 |= fll_div.n << WM8993_FLL_N_SHIFT; | |
3bf6e421 | 438 | snd_soc_write(codec, WM8993_FLL_CONTROL_4, reg4); |
942c435b MB |
439 | |
440 | reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK; | |
441 | reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT; | |
3bf6e421 | 442 | snd_soc_write(codec, WM8993_FLL_CONTROL_5, reg5); |
942c435b MB |
443 | |
444 | /* Enable the FLL */ | |
3bf6e421 | 445 | snd_soc_write(codec, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA); |
942c435b MB |
446 | |
447 | dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout); | |
448 | ||
449 | wm8993->fll_fref = Fref; | |
450 | wm8993->fll_fout = Fout; | |
53242c68 | 451 | wm8993->fll_src = source; |
942c435b MB |
452 | |
453 | return 0; | |
454 | } | |
455 | ||
f0fba2ad LG |
456 | static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source, |
457 | unsigned int Fref, unsigned int Fout) | |
458 | { | |
459 | return _wm8993_set_fll(dai->codec, fll_id, source, Fref, Fout); | |
460 | } | |
461 | ||
942c435b MB |
462 | static int configure_clock(struct snd_soc_codec *codec) |
463 | { | |
b2c812e2 | 464 | struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); |
942c435b MB |
465 | unsigned int reg; |
466 | ||
467 | /* This should be done on init() for bypass paths */ | |
468 | switch (wm8993->sysclk_source) { | |
469 | case WM8993_SYSCLK_MCLK: | |
470 | dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8993->mclk_rate); | |
471 | ||
3bf6e421 | 472 | reg = snd_soc_read(codec, WM8993_CLOCKING_2); |
0182dcc5 | 473 | reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC); |
942c435b MB |
474 | if (wm8993->mclk_rate > 13500000) { |
475 | reg |= WM8993_MCLK_DIV; | |
476 | wm8993->sysclk_rate = wm8993->mclk_rate / 2; | |
477 | } else { | |
478 | reg &= ~WM8993_MCLK_DIV; | |
479 | wm8993->sysclk_rate = wm8993->mclk_rate; | |
480 | } | |
3bf6e421 | 481 | snd_soc_write(codec, WM8993_CLOCKING_2, reg); |
942c435b MB |
482 | break; |
483 | ||
484 | case WM8993_SYSCLK_FLL: | |
485 | dev_dbg(codec->dev, "Using %dHz FLL clock\n", | |
486 | wm8993->fll_fout); | |
487 | ||
3bf6e421 | 488 | reg = snd_soc_read(codec, WM8993_CLOCKING_2); |
942c435b MB |
489 | reg |= WM8993_SYSCLK_SRC; |
490 | if (wm8993->fll_fout > 13500000) { | |
491 | reg |= WM8993_MCLK_DIV; | |
492 | wm8993->sysclk_rate = wm8993->fll_fout / 2; | |
493 | } else { | |
494 | reg &= ~WM8993_MCLK_DIV; | |
495 | wm8993->sysclk_rate = wm8993->fll_fout; | |
496 | } | |
3bf6e421 | 497 | snd_soc_write(codec, WM8993_CLOCKING_2, reg); |
942c435b MB |
498 | break; |
499 | ||
500 | default: | |
501 | dev_err(codec->dev, "System clock not configured\n"); | |
502 | return -EINVAL; | |
503 | } | |
504 | ||
505 | dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
942c435b MB |
510 | static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); |
511 | static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0); | |
512 | static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0); | |
513 | static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0); | |
514 | static const unsigned int drc_max_tlv[] = { | |
dac678f5 | 515 | TLV_DB_RANGE_HEAD(2), |
942c435b MB |
516 | 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0), |
517 | 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0), | |
518 | }; | |
519 | static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0); | |
520 | static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0); | |
521 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
522 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
523 | static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); | |
942c435b MB |
524 | |
525 | static const char *dac_deemph_text[] = { | |
526 | "None", | |
527 | "32kHz", | |
528 | "44.1kHz", | |
529 | "48kHz", | |
530 | }; | |
531 | ||
532 | static const struct soc_enum dac_deemph = | |
533 | SOC_ENUM_SINGLE(WM8993_DAC_CTRL, 4, 4, dac_deemph_text); | |
534 | ||
535 | static const char *adc_hpf_text[] = { | |
536 | "Hi-Fi", | |
537 | "Voice 1", | |
538 | "Voice 2", | |
539 | "Voice 3", | |
540 | }; | |
541 | ||
542 | static const struct soc_enum adc_hpf = | |
543 | SOC_ENUM_SINGLE(WM8993_ADC_CTRL, 5, 4, adc_hpf_text); | |
544 | ||
545 | static const char *drc_path_text[] = { | |
546 | "ADC", | |
547 | "DAC" | |
548 | }; | |
549 | ||
550 | static const struct soc_enum drc_path = | |
551 | SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 14, 2, drc_path_text); | |
552 | ||
553 | static const char *drc_r0_text[] = { | |
554 | "1", | |
555 | "1/2", | |
556 | "1/4", | |
557 | "1/8", | |
558 | "1/16", | |
559 | "0", | |
560 | }; | |
561 | ||
562 | static const struct soc_enum drc_r0 = | |
563 | SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 8, 6, drc_r0_text); | |
564 | ||
565 | static const char *drc_r1_text[] = { | |
566 | "1", | |
567 | "1/2", | |
568 | "1/4", | |
569 | "1/8", | |
570 | "0", | |
571 | }; | |
572 | ||
573 | static const struct soc_enum drc_r1 = | |
574 | SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_4, 13, 5, drc_r1_text); | |
575 | ||
576 | static const char *drc_attack_text[] = { | |
577 | "Reserved", | |
578 | "181us", | |
579 | "363us", | |
580 | "726us", | |
581 | "1.45ms", | |
582 | "2.9ms", | |
583 | "5.8ms", | |
584 | "11.6ms", | |
585 | "23.2ms", | |
586 | "46.4ms", | |
587 | "92.8ms", | |
588 | "185.6ms", | |
589 | }; | |
590 | ||
591 | static const struct soc_enum drc_attack = | |
592 | SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 12, 12, drc_attack_text); | |
593 | ||
594 | static const char *drc_decay_text[] = { | |
595 | "186ms", | |
596 | "372ms", | |
597 | "743ms", | |
598 | "1.49s", | |
599 | "2.97ms", | |
600 | "5.94ms", | |
601 | "11.89ms", | |
602 | "23.78ms", | |
603 | "47.56ms", | |
604 | }; | |
605 | ||
606 | static const struct soc_enum drc_decay = | |
607 | SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_2, 8, 9, drc_decay_text); | |
608 | ||
609 | static const char *drc_ff_text[] = { | |
610 | "5 samples", | |
611 | "9 samples", | |
612 | }; | |
613 | ||
614 | static const struct soc_enum drc_ff = | |
615 | SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 7, 2, drc_ff_text); | |
616 | ||
617 | static const char *drc_qr_rate_text[] = { | |
618 | "0.725ms", | |
619 | "1.45ms", | |
620 | "5.8ms", | |
621 | }; | |
622 | ||
623 | static const struct soc_enum drc_qr_rate = | |
624 | SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_3, 0, 3, drc_qr_rate_text); | |
625 | ||
626 | static const char *drc_smooth_text[] = { | |
627 | "Low", | |
628 | "Medium", | |
629 | "High", | |
630 | }; | |
631 | ||
632 | static const struct soc_enum drc_smooth = | |
633 | SOC_ENUM_SINGLE(WM8993_DRC_CONTROL_1, 4, 3, drc_smooth_text); | |
634 | ||
942c435b | 635 | static const struct snd_kcontrol_new wm8993_snd_controls[] = { |
942c435b MB |
636 | SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE, |
637 | 5, 9, 12, 0, sidetone_tlv), | |
638 | ||
639 | SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0), | |
640 | SOC_ENUM("DRC Path", drc_path), | |
af901ca1 | 641 | SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2, |
942c435b MB |
642 | 2, 60, 1, drc_comp_threash), |
643 | SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3, | |
644 | 11, 30, 1, drc_comp_amp), | |
645 | SOC_ENUM("DRC R0", drc_r0), | |
646 | SOC_ENUM("DRC R1", drc_r1), | |
647 | SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1, | |
648 | drc_min_tlv), | |
649 | SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0, | |
650 | drc_max_tlv), | |
651 | SOC_ENUM("DRC Attack Rate", drc_attack), | |
652 | SOC_ENUM("DRC Decay Rate", drc_decay), | |
653 | SOC_ENUM("DRC FF Delay", drc_ff), | |
654 | SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0), | |
655 | SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0), | |
656 | SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0, | |
657 | drc_qr_tlv), | |
658 | SOC_ENUM("DRC Quick Release Rate", drc_qr_rate), | |
659 | SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0), | |
660 | SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0), | |
af901ca1 | 661 | SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth), |
942c435b MB |
662 | SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0, |
663 | drc_startup_tlv), | |
664 | ||
665 | SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0), | |
666 | ||
667 | SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME, | |
668 | WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv), | |
669 | SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0), | |
670 | SOC_ENUM("ADC High Pass Filter Mode", adc_hpf), | |
671 | ||
672 | SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME, | |
673 | WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv), | |
674 | SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0, | |
675 | dac_boost_tlv), | |
676 | SOC_ENUM("DAC Deemphasis", dac_deemph), | |
677 | ||
942c435b | 678 | SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION, |
a2342ae3 | 679 | 2, 1, 1, wm_hubs_spkmix_tlv), |
942c435b | 680 | |
a2342ae3 MB |
681 | SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION, |
682 | 2, 1, 1, wm_hubs_spkmix_tlv), | |
942c435b MB |
683 | }; |
684 | ||
685 | static const struct snd_kcontrol_new wm8993_eq_controls[] = { | |
686 | SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv), | |
687 | SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv), | |
688 | SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv), | |
689 | SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv), | |
690 | SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv), | |
691 | }; | |
692 | ||
942c435b MB |
693 | static int clk_sys_event(struct snd_soc_dapm_widget *w, |
694 | struct snd_kcontrol *kcontrol, int event) | |
695 | { | |
696 | struct snd_soc_codec *codec = w->codec; | |
697 | ||
698 | switch (event) { | |
699 | case SND_SOC_DAPM_PRE_PMU: | |
700 | return configure_clock(codec); | |
701 | ||
702 | case SND_SOC_DAPM_POST_PMD: | |
703 | break; | |
704 | } | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | /* | |
710 | * When used with DAC outputs only the WM8993 charge pump supports | |
711 | * operation in class W mode, providing very low power consumption | |
712 | * when used with digital sources. Enable and disable this mode | |
713 | * automatically depending on the mixer configuration. | |
714 | * | |
715 | * Currently the only supported paths are the direct DAC->headphone | |
716 | * paths (which provide minimum power consumption anyway). | |
717 | */ | |
a2342ae3 MB |
718 | static int class_w_put(struct snd_kcontrol *kcontrol, |
719 | struct snd_ctl_elem_value *ucontrol) | |
942c435b | 720 | { |
9d03545d JN |
721 | struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); |
722 | struct snd_soc_dapm_widget *widget = wlist->widgets[0]; | |
942c435b | 723 | struct snd_soc_codec *codec = widget->codec; |
b2c812e2 | 724 | struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); |
942c435b MB |
725 | int ret; |
726 | ||
727 | /* Turn it off if we're using the main output mixer */ | |
728 | if (ucontrol->value.integer.value[0] == 0) { | |
729 | if (wm8993->class_w_users == 0) { | |
730 | dev_dbg(codec->dev, "Disabling Class W\n"); | |
731 | snd_soc_update_bits(codec, WM8993_CLASS_W_0, | |
732 | WM8993_CP_DYN_FREQ | | |
733 | WM8993_CP_DYN_V, | |
734 | 0); | |
735 | } | |
736 | wm8993->class_w_users++; | |
fec6dd83 | 737 | wm8993->hubs_data.class_w = true; |
942c435b MB |
738 | } |
739 | ||
740 | /* Implement the change */ | |
741 | ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); | |
742 | ||
743 | /* Enable it if we're using the direct DAC path */ | |
744 | if (ucontrol->value.integer.value[0] == 1) { | |
745 | if (wm8993->class_w_users == 1) { | |
746 | dev_dbg(codec->dev, "Enabling Class W\n"); | |
747 | snd_soc_update_bits(codec, WM8993_CLASS_W_0, | |
748 | WM8993_CP_DYN_FREQ | | |
749 | WM8993_CP_DYN_V, | |
750 | WM8993_CP_DYN_FREQ | | |
751 | WM8993_CP_DYN_V); | |
752 | } | |
753 | wm8993->class_w_users--; | |
fec6dd83 | 754 | wm8993->hubs_data.class_w = false; |
942c435b MB |
755 | } |
756 | ||
757 | dev_dbg(codec->dev, "Indirect DAC use count now %d\n", | |
758 | wm8993->class_w_users); | |
759 | ||
760 | return ret; | |
761 | } | |
762 | ||
763 | #define SOC_DAPM_ENUM_W(xname, xenum) \ | |
764 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
765 | .info = snd_soc_info_enum_double, \ | |
766 | .get = snd_soc_dapm_get_enum_double, \ | |
a2342ae3 | 767 | .put = class_w_put, \ |
942c435b MB |
768 | .private_value = (unsigned long)&xenum } |
769 | ||
942c435b MB |
770 | static const char *hp_mux_text[] = { |
771 | "Mixer", | |
772 | "DAC", | |
773 | }; | |
774 | ||
775 | static const struct soc_enum hpl_enum = | |
776 | SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER1, 8, 2, hp_mux_text); | |
777 | ||
778 | static const struct snd_kcontrol_new hpl_mux = | |
779 | SOC_DAPM_ENUM_W("Left Headphone Mux", hpl_enum); | |
780 | ||
781 | static const struct soc_enum hpr_enum = | |
782 | SOC_ENUM_SINGLE(WM8993_OUTPUT_MIXER2, 8, 2, hp_mux_text); | |
783 | ||
784 | static const struct snd_kcontrol_new hpr_mux = | |
785 | SOC_DAPM_ENUM_W("Right Headphone Mux", hpr_enum); | |
786 | ||
a2342ae3 MB |
787 | static const struct snd_kcontrol_new left_speaker_mixer[] = { |
788 | SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0), | |
789 | SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0), | |
790 | SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0), | |
791 | SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0), | |
942c435b MB |
792 | }; |
793 | ||
a2342ae3 MB |
794 | static const struct snd_kcontrol_new right_speaker_mixer[] = { |
795 | SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0), | |
796 | SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0), | |
797 | SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0), | |
798 | SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0), | |
942c435b MB |
799 | }; |
800 | ||
59ae07a5 MB |
801 | static const char *aif_text[] = { |
802 | "Left", "Right" | |
803 | }; | |
804 | ||
805 | static const struct soc_enum aifoutl_enum = | |
806 | SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 15, 2, aif_text); | |
807 | ||
808 | static const struct snd_kcontrol_new aifoutl_mux = | |
809 | SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); | |
810 | ||
811 | static const struct soc_enum aifoutr_enum = | |
812 | SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_1, 14, 2, aif_text); | |
813 | ||
814 | static const struct snd_kcontrol_new aifoutr_mux = | |
815 | SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); | |
816 | ||
817 | static const struct soc_enum aifinl_enum = | |
818 | SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 15, 2, aif_text); | |
819 | ||
820 | static const struct snd_kcontrol_new aifinl_mux = | |
821 | SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); | |
822 | ||
823 | static const struct soc_enum aifinr_enum = | |
824 | SOC_ENUM_SINGLE(WM8993_AUDIO_INTERFACE_2, 14, 2, aif_text); | |
825 | ||
826 | static const struct snd_kcontrol_new aifinr_mux = | |
827 | SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); | |
828 | ||
829 | static const char *sidetone_text[] = { | |
830 | "None", "Left", "Right" | |
831 | }; | |
832 | ||
833 | static const struct soc_enum sidetonel_enum = | |
834 | SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 2, 3, sidetone_text); | |
835 | ||
836 | static const struct snd_kcontrol_new sidetonel_mux = | |
837 | SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum); | |
838 | ||
839 | static const struct soc_enum sidetoner_enum = | |
840 | SOC_ENUM_SINGLE(WM8993_DIGITAL_SIDE_TONE, 0, 3, sidetone_text); | |
841 | ||
842 | static const struct snd_kcontrol_new sidetoner_mux = | |
843 | SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum); | |
844 | ||
942c435b | 845 | static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = { |
942c435b MB |
846 | SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event, |
847 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
848 | SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0), | |
849 | SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0), | |
4e04adaf | 850 | SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0), |
942c435b | 851 | |
59ae07a5 MB |
852 | SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0), |
853 | SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0), | |
854 | ||
855 | SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), | |
856 | SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), | |
857 | ||
858 | SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), | |
859 | SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), | |
942c435b | 860 | |
59ae07a5 MB |
861 | SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), |
862 | SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), | |
942c435b | 863 | |
59ae07a5 MB |
864 | SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), |
865 | SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), | |
866 | ||
867 | SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux), | |
868 | SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux), | |
869 | ||
870 | SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0), | |
871 | SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0), | |
942c435b | 872 | |
a2342ae3 MB |
873 | SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), |
874 | SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), | |
942c435b MB |
875 | |
876 | SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0, | |
877 | left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), | |
878 | SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0, | |
879 | right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), | |
b70a51ba | 880 | SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), |
942c435b MB |
881 | }; |
882 | ||
883 | static const struct snd_soc_dapm_route routes[] = { | |
4e04adaf MB |
884 | { "MICBIAS1", NULL, "VMID" }, |
885 | { "MICBIAS2", NULL, "VMID" }, | |
886 | ||
942c435b MB |
887 | { "ADCL", NULL, "CLK_SYS" }, |
888 | { "ADCL", NULL, "CLK_DSP" }, | |
942c435b MB |
889 | { "ADCR", NULL, "CLK_SYS" }, |
890 | { "ADCR", NULL, "CLK_DSP" }, | |
891 | ||
59ae07a5 MB |
892 | { "AIFOUTL Mux", "Left", "ADCL" }, |
893 | { "AIFOUTL Mux", "Right", "ADCR" }, | |
894 | { "AIFOUTR Mux", "Left", "ADCL" }, | |
895 | { "AIFOUTR Mux", "Right", "ADCR" }, | |
896 | ||
897 | { "AIFOUTL", NULL, "AIFOUTL Mux" }, | |
898 | { "AIFOUTR", NULL, "AIFOUTR Mux" }, | |
899 | ||
900 | { "DACL Mux", "Left", "AIFINL" }, | |
901 | { "DACL Mux", "Right", "AIFINR" }, | |
902 | { "DACR Mux", "Left", "AIFINL" }, | |
903 | { "DACR Mux", "Right", "AIFINR" }, | |
904 | ||
905 | { "DACL Sidetone", "Left", "ADCL" }, | |
906 | { "DACL Sidetone", "Right", "ADCR" }, | |
907 | { "DACR Sidetone", "Left", "ADCL" }, | |
908 | { "DACR Sidetone", "Right", "ADCR" }, | |
909 | ||
942c435b MB |
910 | { "DACL", NULL, "CLK_SYS" }, |
911 | { "DACL", NULL, "CLK_DSP" }, | |
59ae07a5 MB |
912 | { "DACL", NULL, "DACL Mux" }, |
913 | { "DACL", NULL, "DACL Sidetone" }, | |
942c435b MB |
914 | { "DACR", NULL, "CLK_SYS" }, |
915 | { "DACR", NULL, "CLK_DSP" }, | |
59ae07a5 MB |
916 | { "DACR", NULL, "DACR Mux" }, |
917 | { "DACR", NULL, "DACR Sidetone" }, | |
942c435b | 918 | |
942c435b MB |
919 | { "Left Output Mixer", "DAC Switch", "DACL" }, |
920 | ||
942c435b MB |
921 | { "Right Output Mixer", "DAC Switch", "DACR" }, |
922 | ||
942c435b | 923 | { "Left Output PGA", NULL, "CLK_SYS" }, |
942c435b | 924 | |
942c435b | 925 | { "Right Output PGA", NULL, "CLK_SYS" }, |
942c435b | 926 | |
942c435b MB |
927 | { "SPKL", "DAC Switch", "DACL" }, |
928 | { "SPKL", NULL, "CLK_SYS" }, | |
942c435b | 929 | |
942c435b MB |
930 | { "SPKR", "DAC Switch", "DACR" }, |
931 | { "SPKR", NULL, "CLK_SYS" }, | |
942c435b MB |
932 | |
933 | { "Left Headphone Mux", "DAC", "DACL" }, | |
942c435b | 934 | { "Right Headphone Mux", "DAC", "DACR" }, |
942c435b MB |
935 | }; |
936 | ||
cf56f627 MB |
937 | static void wm8993_cache_restore(struct snd_soc_codec *codec) |
938 | { | |
939 | u16 *cache = codec->reg_cache; | |
940 | int i; | |
941 | ||
942 | if (!codec->cache_sync) | |
943 | return; | |
944 | ||
945 | /* Reenable hardware writes */ | |
946 | codec->cache_only = 0; | |
947 | ||
948 | /* Restore the register settings */ | |
949 | for (i = 1; i < WM8993_MAX_REGISTER; i++) { | |
950 | if (cache[i] == wm8993_reg_defaults[i]) | |
951 | continue; | |
952 | snd_soc_write(codec, i, cache[i]); | |
953 | } | |
954 | ||
955 | /* We're in sync again */ | |
956 | codec->cache_sync = 0; | |
957 | } | |
958 | ||
942c435b MB |
959 | static int wm8993_set_bias_level(struct snd_soc_codec *codec, |
960 | enum snd_soc_bias_level level) | |
961 | { | |
b2c812e2 | 962 | struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); |
cf56f627 | 963 | int ret; |
942c435b MB |
964 | |
965 | switch (level) { | |
966 | case SND_SOC_BIAS_ON: | |
967 | case SND_SOC_BIAS_PREPARE: | |
968 | /* VMID=2*40k */ | |
969 | snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, | |
970 | WM8993_VMID_SEL_MASK, 0x2); | |
971 | snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2, | |
972 | WM8993_TSHUT_ENA, WM8993_TSHUT_ENA); | |
973 | break; | |
974 | ||
975 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 976 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
cf56f627 MB |
977 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies), |
978 | wm8993->supplies); | |
979 | if (ret != 0) | |
980 | return ret; | |
981 | ||
982 | wm8993_cache_restore(codec); | |
983 | ||
3ed7074c MB |
984 | /* Tune DC servo configuration */ |
985 | snd_soc_write(codec, 0x44, 3); | |
986 | snd_soc_write(codec, 0x56, 3); | |
987 | snd_soc_write(codec, 0x44, 0); | |
988 | ||
942c435b MB |
989 | /* Bring up VMID with fast soft start */ |
990 | snd_soc_update_bits(codec, WM8993_ANTIPOP2, | |
991 | WM8993_STARTUP_BIAS_ENA | | |
992 | WM8993_VMID_BUF_ENA | | |
993 | WM8993_VMID_RAMP_MASK | | |
994 | WM8993_BIAS_SRC, | |
995 | WM8993_STARTUP_BIAS_ENA | | |
996 | WM8993_VMID_BUF_ENA | | |
997 | WM8993_VMID_RAMP_MASK | | |
998 | WM8993_BIAS_SRC); | |
999 | ||
1000 | /* If either line output is single ended we | |
1001 | * need the VMID buffer */ | |
1002 | if (!wm8993->pdata.lineout1_diff || | |
1003 | !wm8993->pdata.lineout2_diff) | |
1004 | snd_soc_update_bits(codec, WM8993_ANTIPOP1, | |
1005 | WM8993_LINEOUT_VMID_BUF_ENA, | |
1006 | WM8993_LINEOUT_VMID_BUF_ENA); | |
1007 | ||
1008 | /* VMID=2*40k */ | |
1009 | snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, | |
1010 | WM8993_VMID_SEL_MASK | | |
1011 | WM8993_BIAS_ENA, | |
1012 | WM8993_BIAS_ENA | 0x2); | |
1013 | msleep(32); | |
1014 | ||
1015 | /* Switch to normal bias */ | |
1016 | snd_soc_update_bits(codec, WM8993_ANTIPOP2, | |
1017 | WM8993_BIAS_SRC | | |
1018 | WM8993_STARTUP_BIAS_ENA, 0); | |
1019 | } | |
1020 | ||
1021 | /* VMID=2*240k */ | |
1022 | snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, | |
1023 | WM8993_VMID_SEL_MASK, 0x4); | |
1024 | ||
1025 | snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_2, | |
1026 | WM8993_TSHUT_ENA, 0); | |
1027 | break; | |
1028 | ||
1029 | case SND_SOC_BIAS_OFF: | |
1030 | snd_soc_update_bits(codec, WM8993_ANTIPOP1, | |
1031 | WM8993_LINEOUT_VMID_BUF_ENA, 0); | |
1032 | ||
1033 | snd_soc_update_bits(codec, WM8993_POWER_MANAGEMENT_1, | |
1034 | WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA, | |
1035 | 0); | |
cf56f627 | 1036 | |
83b65425 MB |
1037 | snd_soc_update_bits(codec, WM8993_ANTIPOP2, |
1038 | WM8993_STARTUP_BIAS_ENA | | |
1039 | WM8993_VMID_BUF_ENA | | |
1040 | WM8993_VMID_RAMP_MASK | | |
1041 | WM8993_BIAS_SRC, 0); | |
1042 | ||
cf56f627 MB |
1043 | #ifdef CONFIG_REGULATOR |
1044 | /* Post 2.6.34 we will be able to get a callback when | |
1045 | * the regulators are disabled which we can use but | |
1046 | * for now just assume that the power will be cut if | |
1047 | * the regulator API is in use. | |
1048 | */ | |
1049 | codec->cache_sync = 1; | |
1050 | #endif | |
1051 | ||
1052 | regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), | |
1053 | wm8993->supplies); | |
942c435b MB |
1054 | break; |
1055 | } | |
1056 | ||
ce6120cc | 1057 | codec->dapm.bias_level = level; |
942c435b MB |
1058 | |
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai, | |
1063 | int clk_id, unsigned int freq, int dir) | |
1064 | { | |
1065 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1066 | struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); |
942c435b MB |
1067 | |
1068 | switch (clk_id) { | |
1069 | case WM8993_SYSCLK_MCLK: | |
1070 | wm8993->mclk_rate = freq; | |
1071 | case WM8993_SYSCLK_FLL: | |
1072 | wm8993->sysclk_source = clk_id; | |
1073 | break; | |
1074 | ||
1075 | default: | |
1076 | return -EINVAL; | |
1077 | } | |
1078 | ||
1079 | return 0; | |
1080 | } | |
1081 | ||
1082 | static int wm8993_set_dai_fmt(struct snd_soc_dai *dai, | |
1083 | unsigned int fmt) | |
1084 | { | |
1085 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1086 | struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); |
3bf6e421 MB |
1087 | unsigned int aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1); |
1088 | unsigned int aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4); | |
942c435b MB |
1089 | |
1090 | aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV | | |
1091 | WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK); | |
1092 | aif4 &= ~WM8993_LRCLK_DIR; | |
1093 | ||
1094 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1095 | case SND_SOC_DAIFMT_CBS_CFS: | |
1096 | wm8993->master = 0; | |
1097 | break; | |
1098 | case SND_SOC_DAIFMT_CBS_CFM: | |
1099 | aif4 |= WM8993_LRCLK_DIR; | |
1100 | wm8993->master = 1; | |
1101 | break; | |
1102 | case SND_SOC_DAIFMT_CBM_CFS: | |
1103 | aif1 |= WM8993_BCLK_DIR; | |
1104 | wm8993->master = 1; | |
1105 | break; | |
1106 | case SND_SOC_DAIFMT_CBM_CFM: | |
1107 | aif1 |= WM8993_BCLK_DIR; | |
1108 | aif4 |= WM8993_LRCLK_DIR; | |
1109 | wm8993->master = 1; | |
1110 | break; | |
1111 | default: | |
1112 | return -EINVAL; | |
1113 | } | |
1114 | ||
1115 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1116 | case SND_SOC_DAIFMT_DSP_B: | |
1117 | aif1 |= WM8993_AIF_LRCLK_INV; | |
1118 | case SND_SOC_DAIFMT_DSP_A: | |
1119 | aif1 |= 0x18; | |
1120 | break; | |
1121 | case SND_SOC_DAIFMT_I2S: | |
1122 | aif1 |= 0x10; | |
1123 | break; | |
1124 | case SND_SOC_DAIFMT_RIGHT_J: | |
1125 | break; | |
1126 | case SND_SOC_DAIFMT_LEFT_J: | |
1127 | aif1 |= 0x8; | |
1128 | break; | |
1129 | default: | |
1130 | return -EINVAL; | |
1131 | } | |
1132 | ||
1133 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1134 | case SND_SOC_DAIFMT_DSP_A: | |
1135 | case SND_SOC_DAIFMT_DSP_B: | |
1136 | /* frame inversion not valid for DSP modes */ | |
1137 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1138 | case SND_SOC_DAIFMT_NB_NF: | |
1139 | break; | |
1140 | case SND_SOC_DAIFMT_IB_NF: | |
1141 | aif1 |= WM8993_AIF_BCLK_INV; | |
1142 | break; | |
1143 | default: | |
1144 | return -EINVAL; | |
1145 | } | |
1146 | break; | |
1147 | ||
1148 | case SND_SOC_DAIFMT_I2S: | |
1149 | case SND_SOC_DAIFMT_RIGHT_J: | |
1150 | case SND_SOC_DAIFMT_LEFT_J: | |
1151 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1152 | case SND_SOC_DAIFMT_NB_NF: | |
1153 | break; | |
1154 | case SND_SOC_DAIFMT_IB_IF: | |
1155 | aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV; | |
1156 | break; | |
1157 | case SND_SOC_DAIFMT_IB_NF: | |
1158 | aif1 |= WM8993_AIF_BCLK_INV; | |
1159 | break; | |
1160 | case SND_SOC_DAIFMT_NB_IF: | |
1161 | aif1 |= WM8993_AIF_LRCLK_INV; | |
1162 | break; | |
1163 | default: | |
1164 | return -EINVAL; | |
1165 | } | |
1166 | break; | |
1167 | default: | |
1168 | return -EINVAL; | |
1169 | } | |
1170 | ||
3bf6e421 MB |
1171 | snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1); |
1172 | snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4); | |
942c435b MB |
1173 | |
1174 | return 0; | |
1175 | } | |
1176 | ||
1177 | static int wm8993_hw_params(struct snd_pcm_substream *substream, | |
1178 | struct snd_pcm_hw_params *params, | |
1179 | struct snd_soc_dai *dai) | |
1180 | { | |
1181 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1182 | struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); |
942c435b MB |
1183 | int ret, i, best, best_val, cur_val; |
1184 | unsigned int clocking1, clocking3, aif1, aif4; | |
1185 | ||
3bf6e421 | 1186 | clocking1 = snd_soc_read(codec, WM8993_CLOCKING_1); |
942c435b MB |
1187 | clocking1 &= ~WM8993_BCLK_DIV_MASK; |
1188 | ||
3bf6e421 | 1189 | clocking3 = snd_soc_read(codec, WM8993_CLOCKING_3); |
942c435b MB |
1190 | clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK); |
1191 | ||
3bf6e421 | 1192 | aif1 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_1); |
942c435b MB |
1193 | aif1 &= ~WM8993_AIF_WL_MASK; |
1194 | ||
3bf6e421 | 1195 | aif4 = snd_soc_read(codec, WM8993_AUDIO_INTERFACE_4); |
942c435b MB |
1196 | aif4 &= ~WM8993_LRCLK_RATE_MASK; |
1197 | ||
1198 | /* What BCLK do we need? */ | |
1199 | wm8993->fs = params_rate(params); | |
1200 | wm8993->bclk = 2 * wm8993->fs; | |
d3c9e9a1 MB |
1201 | if (wm8993->tdm_slots) { |
1202 | dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", | |
1203 | wm8993->tdm_slots, wm8993->tdm_width); | |
1204 | wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots; | |
1205 | } else { | |
1206 | switch (params_format(params)) { | |
1207 | case SNDRV_PCM_FORMAT_S16_LE: | |
1208 | wm8993->bclk *= 16; | |
1209 | break; | |
1210 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1211 | wm8993->bclk *= 20; | |
1212 | aif1 |= 0x8; | |
1213 | break; | |
1214 | case SNDRV_PCM_FORMAT_S24_LE: | |
1215 | wm8993->bclk *= 24; | |
1216 | aif1 |= 0x10; | |
1217 | break; | |
1218 | case SNDRV_PCM_FORMAT_S32_LE: | |
1219 | wm8993->bclk *= 32; | |
1220 | aif1 |= 0x18; | |
1221 | break; | |
1222 | default: | |
1223 | return -EINVAL; | |
1224 | } | |
942c435b MB |
1225 | } |
1226 | ||
1227 | dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk); | |
1228 | ||
1229 | ret = configure_clock(codec); | |
1230 | if (ret != 0) | |
1231 | return ret; | |
1232 | ||
1233 | /* Select nearest CLK_SYS_RATE */ | |
1234 | best = 0; | |
1235 | best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio) | |
1236 | - wm8993->fs); | |
1237 | for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { | |
1238 | cur_val = abs((wm8993->sysclk_rate / | |
ef995e3a | 1239 | clk_sys_rates[i].ratio) - wm8993->fs); |
942c435b MB |
1240 | if (cur_val < best_val) { |
1241 | best = i; | |
1242 | best_val = cur_val; | |
1243 | } | |
1244 | } | |
1245 | dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", | |
1246 | clk_sys_rates[best].ratio); | |
1247 | clocking3 |= (clk_sys_rates[best].clk_sys_rate | |
1248 | << WM8993_CLK_SYS_RATE_SHIFT); | |
1249 | ||
1250 | /* SAMPLE_RATE */ | |
1251 | best = 0; | |
1252 | best_val = abs(wm8993->fs - sample_rates[0].rate); | |
1253 | for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { | |
1254 | /* Closest match */ | |
1255 | cur_val = abs(wm8993->fs - sample_rates[i].rate); | |
1256 | if (cur_val < best_val) { | |
1257 | best = i; | |
1258 | best_val = cur_val; | |
1259 | } | |
1260 | } | |
1261 | dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", | |
1262 | sample_rates[best].rate); | |
e465d544 MB |
1263 | clocking3 |= (sample_rates[best].sample_rate |
1264 | << WM8993_SAMPLE_RATE_SHIFT); | |
942c435b MB |
1265 | |
1266 | /* BCLK_DIV */ | |
1267 | best = 0; | |
1268 | best_val = INT_MAX; | |
1269 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
1270 | cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div) | |
1271 | - wm8993->bclk; | |
1272 | if (cur_val < 0) /* Table is sorted */ | |
1273 | break; | |
1274 | if (cur_val < best_val) { | |
1275 | best = i; | |
1276 | best_val = cur_val; | |
1277 | } | |
1278 | } | |
1279 | wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div; | |
1280 | dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", | |
1281 | bclk_divs[best].div, wm8993->bclk); | |
1282 | clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT; | |
1283 | ||
1284 | /* LRCLK is a simple fraction of BCLK */ | |
1285 | dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs); | |
1286 | aif4 |= wm8993->bclk / wm8993->fs; | |
1287 | ||
3bf6e421 MB |
1288 | snd_soc_write(codec, WM8993_CLOCKING_1, clocking1); |
1289 | snd_soc_write(codec, WM8993_CLOCKING_3, clocking3); | |
1290 | snd_soc_write(codec, WM8993_AUDIO_INTERFACE_1, aif1); | |
1291 | snd_soc_write(codec, WM8993_AUDIO_INTERFACE_4, aif4); | |
942c435b MB |
1292 | |
1293 | /* ReTune Mobile? */ | |
1294 | if (wm8993->pdata.num_retune_configs) { | |
3bf6e421 | 1295 | u16 eq1 = snd_soc_read(codec, WM8993_EQ1); |
942c435b MB |
1296 | struct wm8993_retune_mobile_setting *s; |
1297 | ||
1298 | best = 0; | |
1299 | best_val = abs(wm8993->pdata.retune_configs[0].rate | |
1300 | - wm8993->fs); | |
1301 | for (i = 0; i < wm8993->pdata.num_retune_configs; i++) { | |
1302 | cur_val = abs(wm8993->pdata.retune_configs[i].rate | |
1303 | - wm8993->fs); | |
1304 | if (cur_val < best_val) { | |
1305 | best_val = cur_val; | |
1306 | best = i; | |
1307 | } | |
1308 | } | |
1309 | s = &wm8993->pdata.retune_configs[best]; | |
1310 | ||
1311 | dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n", | |
1312 | s->name, s->rate); | |
1313 | ||
1314 | /* Disable EQ while we reconfigure */ | |
1315 | snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, 0); | |
1316 | ||
1317 | for (i = 1; i < ARRAY_SIZE(s->config); i++) | |
3bf6e421 | 1318 | snd_soc_write(codec, WM8993_EQ1 + i, s->config[i]); |
942c435b MB |
1319 | |
1320 | snd_soc_update_bits(codec, WM8993_EQ1, WM8993_EQ_ENA, eq1); | |
1321 | } | |
1322 | ||
1323 | return 0; | |
1324 | } | |
1325 | ||
1326 | static int wm8993_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
1327 | { | |
1328 | struct snd_soc_codec *codec = codec_dai->codec; | |
1329 | unsigned int reg; | |
1330 | ||
3bf6e421 | 1331 | reg = snd_soc_read(codec, WM8993_DAC_CTRL); |
942c435b MB |
1332 | |
1333 | if (mute) | |
1334 | reg |= WM8993_DAC_MUTE; | |
1335 | else | |
1336 | reg &= ~WM8993_DAC_MUTE; | |
1337 | ||
3bf6e421 | 1338 | snd_soc_write(codec, WM8993_DAC_CTRL, reg); |
942c435b MB |
1339 | |
1340 | return 0; | |
1341 | } | |
1342 | ||
d3c9e9a1 MB |
1343 | static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, |
1344 | unsigned int rx_mask, int slots, int slot_width) | |
1345 | { | |
1346 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1347 | struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); |
d3c9e9a1 MB |
1348 | int aif1 = 0; |
1349 | int aif2 = 0; | |
1350 | ||
1351 | /* Don't need to validate anything if we're turning off TDM */ | |
1352 | if (slots == 0) { | |
1353 | wm8993->tdm_slots = 0; | |
1354 | goto out; | |
1355 | } | |
1356 | ||
1357 | /* Note that we allow configurations we can't handle ourselves - | |
1358 | * for example, we can generate clocks for slots 2 and up even if | |
1359 | * we can't use those slots ourselves. | |
1360 | */ | |
1361 | aif1 |= WM8993_AIFADC_TDM; | |
1362 | aif2 |= WM8993_AIFDAC_TDM; | |
1363 | ||
1364 | switch (rx_mask) { | |
1365 | case 3: | |
1366 | break; | |
1367 | case 0xc: | |
1368 | aif1 |= WM8993_AIFADC_TDM_CHAN; | |
1369 | break; | |
1370 | default: | |
1371 | return -EINVAL; | |
1372 | } | |
1373 | ||
1374 | ||
1375 | switch (tx_mask) { | |
1376 | case 3: | |
1377 | break; | |
1378 | case 0xc: | |
1379 | aif2 |= WM8993_AIFDAC_TDM_CHAN; | |
1380 | break; | |
1381 | default: | |
1382 | return -EINVAL; | |
1383 | } | |
1384 | ||
1385 | out: | |
1386 | wm8993->tdm_width = slot_width; | |
1387 | wm8993->tdm_slots = slots / 2; | |
1388 | ||
1389 | snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_1, | |
1390 | WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1); | |
1391 | snd_soc_update_bits(codec, WM8993_AUDIO_INTERFACE_2, | |
1392 | WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2); | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | ||
942c435b MB |
1397 | static struct snd_soc_dai_ops wm8993_ops = { |
1398 | .set_sysclk = wm8993_set_sysclk, | |
1399 | .set_fmt = wm8993_set_dai_fmt, | |
1400 | .hw_params = wm8993_hw_params, | |
1401 | .digital_mute = wm8993_digital_mute, | |
1402 | .set_pll = wm8993_set_fll, | |
d3c9e9a1 | 1403 | .set_tdm_slot = wm8993_set_tdm_slot, |
942c435b MB |
1404 | }; |
1405 | ||
1406 | #define WM8993_RATES SNDRV_PCM_RATE_8000_48000 | |
1407 | ||
1408 | #define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
1409 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
1410 | SNDRV_PCM_FMTBIT_S24_LE |\ | |
1411 | SNDRV_PCM_FMTBIT_S32_LE) | |
1412 | ||
f0fba2ad LG |
1413 | static struct snd_soc_dai_driver wm8993_dai = { |
1414 | .name = "wm8993-hifi", | |
942c435b MB |
1415 | .playback = { |
1416 | .stream_name = "Playback", | |
1417 | .channels_min = 1, | |
1418 | .channels_max = 2, | |
1419 | .rates = WM8993_RATES, | |
1420 | .formats = WM8993_FORMATS, | |
1421 | }, | |
1422 | .capture = { | |
1423 | .stream_name = "Capture", | |
1424 | .channels_min = 1, | |
1425 | .channels_max = 2, | |
1426 | .rates = WM8993_RATES, | |
1427 | .formats = WM8993_FORMATS, | |
1428 | }, | |
1429 | .ops = &wm8993_ops, | |
1430 | .symmetric_rates = 1, | |
1431 | }; | |
942c435b | 1432 | |
f0fba2ad | 1433 | static int wm8993_probe(struct snd_soc_codec *codec) |
942c435b | 1434 | { |
f0fba2ad | 1435 | struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); |
ce6120cc | 1436 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
f0fba2ad LG |
1437 | int ret, i, val; |
1438 | ||
f0fba2ad | 1439 | wm8993->hubs_data.hp_startup_mode = 1; |
4537c4e7 MB |
1440 | wm8993->hubs_data.dcs_codes_l = -2; |
1441 | wm8993->hubs_data.dcs_codes_r = -2; | |
f9acf9fe | 1442 | wm8993->hubs_data.series_startup = 1; |
f0fba2ad LG |
1443 | |
1444 | ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); | |
1445 | if (ret != 0) { | |
1446 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
1447 | return ret; | |
1448 | } | |
1449 | ||
1450 | for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++) | |
1451 | wm8993->supplies[i].supply = wm8993_supply_names[i]; | |
942c435b | 1452 | |
f0fba2ad LG |
1453 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8993->supplies), |
1454 | wm8993->supplies); | |
1455 | if (ret != 0) { | |
1456 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
1457 | return ret; | |
942c435b MB |
1458 | } |
1459 | ||
f0fba2ad LG |
1460 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies), |
1461 | wm8993->supplies); | |
1462 | if (ret != 0) { | |
1463 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
1464 | goto err_get; | |
1465 | } | |
942c435b | 1466 | |
f0fba2ad LG |
1467 | val = snd_soc_read(codec, WM8993_SOFTWARE_RESET); |
1468 | if (val != wm8993_reg_defaults[WM8993_SOFTWARE_RESET]) { | |
1469 | dev_err(codec->dev, "Invalid ID register value %x\n", val); | |
1470 | ret = -EINVAL; | |
1471 | goto err_enable; | |
942c435b MB |
1472 | } |
1473 | ||
f0fba2ad LG |
1474 | ret = snd_soc_write(codec, WM8993_SOFTWARE_RESET, 0xffff); |
1475 | if (ret != 0) | |
1476 | goto err_enable; | |
1477 | ||
1478 | codec->cache_only = 1; | |
1479 | ||
1480 | /* By default we're using the output mixers */ | |
1481 | wm8993->class_w_users = 2; | |
1482 | ||
1483 | /* Latch volume update bits and default ZC on */ | |
1484 | snd_soc_update_bits(codec, WM8993_RIGHT_DAC_DIGITAL_VOLUME, | |
1485 | WM8993_DAC_VU, WM8993_DAC_VU); | |
1486 | snd_soc_update_bits(codec, WM8993_RIGHT_ADC_DIGITAL_VOLUME, | |
1487 | WM8993_ADC_VU, WM8993_ADC_VU); | |
1488 | ||
1489 | /* Manualy manage the HPOUT sequencing for independent stereo | |
1490 | * control. */ | |
1491 | snd_soc_update_bits(codec, WM8993_ANALOGUE_HP_0, | |
1492 | WM8993_HPOUT1_AUTO_PU, 0); | |
1493 | ||
1494 | /* Use automatic clock configuration */ | |
1495 | snd_soc_update_bits(codec, WM8993_CLOCKING_4, WM8993_SR_MODE, 0); | |
1496 | ||
1497 | wm_hubs_handle_analogue_pdata(codec, wm8993->pdata.lineout1_diff, | |
1498 | wm8993->pdata.lineout2_diff, | |
1499 | wm8993->pdata.lineout1fb, | |
1500 | wm8993->pdata.lineout2fb, | |
1501 | wm8993->pdata.jd_scthr, | |
1502 | wm8993->pdata.jd_thr, | |
1503 | wm8993->pdata.micbias1_lvl, | |
1504 | wm8993->pdata.micbias2_lvl); | |
1505 | ||
1506 | ret = wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1507 | if (ret != 0) | |
1508 | goto err_enable; | |
1509 | ||
942c435b MB |
1510 | snd_soc_add_controls(codec, wm8993_snd_controls, |
1511 | ARRAY_SIZE(wm8993_snd_controls)); | |
1512 | if (wm8993->pdata.num_retune_configs != 0) { | |
1513 | dev_dbg(codec->dev, "Using ReTune Mobile\n"); | |
1514 | } else { | |
1515 | dev_dbg(codec->dev, "No ReTune Mobile, using normal EQ\n"); | |
1516 | snd_soc_add_controls(codec, wm8993_eq_controls, | |
1517 | ARRAY_SIZE(wm8993_eq_controls)); | |
1518 | } | |
1519 | ||
ce6120cc | 1520 | snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets, |
942c435b | 1521 | ARRAY_SIZE(wm8993_dapm_widgets)); |
a2342ae3 | 1522 | wm_hubs_add_analogue_controls(codec); |
942c435b | 1523 | |
ce6120cc | 1524 | snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes)); |
a2342ae3 MB |
1525 | wm_hubs_add_analogue_routes(codec, wm8993->pdata.lineout1_diff, |
1526 | wm8993->pdata.lineout2_diff); | |
942c435b | 1527 | |
f0fba2ad | 1528 | return 0; |
942c435b | 1529 | |
f0fba2ad LG |
1530 | err_enable: |
1531 | regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); | |
1532 | err_get: | |
1533 | regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); | |
942c435b MB |
1534 | return ret; |
1535 | } | |
1536 | ||
f0fba2ad | 1537 | static int wm8993_remove(struct snd_soc_codec *codec) |
942c435b | 1538 | { |
f0fba2ad | 1539 | struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); |
942c435b | 1540 | |
f0fba2ad LG |
1541 | wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF); |
1542 | regulator_bulk_free(ARRAY_SIZE(wm8993->supplies), wm8993->supplies); | |
942c435b MB |
1543 | return 0; |
1544 | } | |
1545 | ||
53242c68 | 1546 | #ifdef CONFIG_PM |
f0fba2ad | 1547 | static int wm8993_suspend(struct snd_soc_codec *codec, pm_message_t state) |
53242c68 | 1548 | { |
b2c812e2 | 1549 | struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); |
53242c68 MB |
1550 | int fll_fout = wm8993->fll_fout; |
1551 | int fll_fref = wm8993->fll_fref; | |
1552 | int ret; | |
1553 | ||
1554 | /* Stop the FLL in an orderly fashion */ | |
f0fba2ad | 1555 | ret = _wm8993_set_fll(codec, 0, 0, 0, 0); |
53242c68 | 1556 | if (ret != 0) { |
f0fba2ad | 1557 | dev_err(codec->dev, "Failed to stop FLL\n"); |
53242c68 MB |
1558 | return ret; |
1559 | } | |
1560 | ||
1561 | wm8993->fll_fout = fll_fout; | |
1562 | wm8993->fll_fref = fll_fref; | |
1563 | ||
1564 | wm8993_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1565 | ||
1566 | return 0; | |
1567 | } | |
1568 | ||
f0fba2ad | 1569 | static int wm8993_resume(struct snd_soc_codec *codec) |
53242c68 | 1570 | { |
b2c812e2 | 1571 | struct wm8993_priv *wm8993 = snd_soc_codec_get_drvdata(codec); |
cf56f627 | 1572 | int ret; |
53242c68 MB |
1573 | |
1574 | wm8993_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1575 | ||
1576 | /* Restart the FLL? */ | |
1577 | if (wm8993->fll_fout) { | |
1578 | int fll_fout = wm8993->fll_fout; | |
1579 | int fll_fref = wm8993->fll_fref; | |
1580 | ||
1581 | wm8993->fll_fref = 0; | |
1582 | wm8993->fll_fout = 0; | |
1583 | ||
f0fba2ad | 1584 | ret = _wm8993_set_fll(codec, 0, wm8993->fll_src, |
53242c68 MB |
1585 | fll_fref, fll_fout); |
1586 | if (ret != 0) | |
1587 | dev_err(codec->dev, "Failed to restart FLL\n"); | |
1588 | } | |
1589 | ||
1590 | return 0; | |
1591 | } | |
1592 | #else | |
1593 | #define wm8993_suspend NULL | |
1594 | #define wm8993_resume NULL | |
1595 | #endif | |
1596 | ||
f0fba2ad | 1597 | static struct snd_soc_codec_driver soc_codec_dev_wm8993 = { |
942c435b MB |
1598 | .probe = wm8993_probe, |
1599 | .remove = wm8993_remove, | |
53242c68 MB |
1600 | .suspend = wm8993_suspend, |
1601 | .resume = wm8993_resume, | |
f0fba2ad | 1602 | .set_bias_level = wm8993_set_bias_level, |
e5eec34c | 1603 | .reg_cache_size = ARRAY_SIZE(wm8993_reg_defaults), |
f0fba2ad LG |
1604 | .reg_word_size = sizeof(u16), |
1605 | .reg_cache_default = wm8993_reg_defaults, | |
1606 | .volatile_register = wm8993_volatile, | |
942c435b | 1607 | }; |
942c435b | 1608 | |
f0fba2ad LG |
1609 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
1610 | static __devinit int wm8993_i2c_probe(struct i2c_client *i2c, | |
1611 | const struct i2c_device_id *id) | |
942c435b MB |
1612 | { |
1613 | struct wm8993_priv *wm8993; | |
942c435b | 1614 | int ret; |
942c435b MB |
1615 | |
1616 | wm8993 = kzalloc(sizeof(struct wm8993_priv), GFP_KERNEL); | |
1617 | if (wm8993 == NULL) | |
1618 | return -ENOMEM; | |
1619 | ||
942c435b | 1620 | i2c_set_clientdata(i2c, wm8993); |
942c435b | 1621 | |
f0fba2ad LG |
1622 | ret = snd_soc_register_codec(&i2c->dev, |
1623 | &soc_codec_dev_wm8993, &wm8993_dai, 1); | |
1624 | if (ret < 0) | |
1625 | kfree(wm8993); | |
942c435b MB |
1626 | return ret; |
1627 | } | |
1628 | ||
f0fba2ad | 1629 | static __devexit int wm8993_i2c_remove(struct i2c_client *client) |
942c435b | 1630 | { |
f0fba2ad LG |
1631 | snd_soc_unregister_codec(&client->dev); |
1632 | kfree(i2c_get_clientdata(client)); | |
942c435b MB |
1633 | return 0; |
1634 | } | |
1635 | ||
1636 | static const struct i2c_device_id wm8993_i2c_id[] = { | |
1637 | { "wm8993", 0 }, | |
1638 | { } | |
1639 | }; | |
1640 | MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id); | |
1641 | ||
1642 | static struct i2c_driver wm8993_i2c_driver = { | |
1643 | .driver = { | |
f0fba2ad | 1644 | .name = "wm8993-codec", |
942c435b MB |
1645 | .owner = THIS_MODULE, |
1646 | }, | |
f0fba2ad LG |
1647 | .probe = wm8993_i2c_probe, |
1648 | .remove = __devexit_p(wm8993_i2c_remove), | |
942c435b MB |
1649 | .id_table = wm8993_i2c_id, |
1650 | }; | |
f0fba2ad | 1651 | #endif |
942c435b MB |
1652 | |
1653 | static int __init wm8993_modinit(void) | |
1654 | { | |
f0fba2ad LG |
1655 | int ret = 0; |
1656 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
942c435b | 1657 | ret = i2c_add_driver(&wm8993_i2c_driver); |
f0fba2ad LG |
1658 | if (ret != 0) { |
1659 | pr_err("WM8993: Unable to register I2C driver: %d\n", | |
1660 | ret); | |
1661 | } | |
1662 | #endif | |
942c435b MB |
1663 | return ret; |
1664 | } | |
1665 | module_init(wm8993_modinit); | |
1666 | ||
1667 | static void __exit wm8993_exit(void) | |
1668 | { | |
f0fba2ad | 1669 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
942c435b | 1670 | i2c_del_driver(&wm8993_i2c_driver); |
f0fba2ad | 1671 | #endif |
942c435b MB |
1672 | } |
1673 | module_exit(wm8993_exit); | |
1674 | ||
1675 | ||
1676 | MODULE_DESCRIPTION("ASoC WM8993 driver"); | |
1677 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
1678 | MODULE_LICENSE("GPL"); |