Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f2644a2c MB |
2 | /* |
3 | * wm8960.c -- WM8960 ALSA SoC Audio driver | |
4 | * | |
656baaeb MB |
5 | * Copyright 2007-11 Wolfson Microelectronics, plc |
6 | * | |
f2644a2c | 7 | * Author: Liam Girdwood |
f2644a2c MB |
8 | */ |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/moduleparam.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/pm.h> | |
75aa8868 | 15 | #include <linux/clk.h> |
f2644a2c | 16 | #include <linux/i2c.h> |
5a0e3ad6 | 17 | #include <linux/slab.h> |
f2644a2c MB |
18 | #include <sound/core.h> |
19 | #include <sound/pcm.h> | |
20 | #include <sound/pcm_params.h> | |
21 | #include <sound/soc.h> | |
f2644a2c MB |
22 | #include <sound/initval.h> |
23 | #include <sound/tlv.h> | |
b6877a47 | 24 | #include <sound/wm8960.h> |
f2644a2c MB |
25 | |
26 | #include "wm8960.h" | |
27 | ||
f2644a2c | 28 | /* R25 - Power 1 */ |
913d7b4c | 29 | #define WM8960_VMID_MASK 0x180 |
f2644a2c MB |
30 | #define WM8960_VREF 0x40 |
31 | ||
913d7b4c MB |
32 | /* R26 - Power 2 */ |
33 | #define WM8960_PWR2_LOUT1 0x40 | |
34 | #define WM8960_PWR2_ROUT1 0x20 | |
35 | #define WM8960_PWR2_OUT3 0x02 | |
36 | ||
f2644a2c MB |
37 | /* R28 - Anti-pop 1 */ |
38 | #define WM8960_POBCTRL 0x80 | |
39 | #define WM8960_BUFDCOPEN 0x10 | |
40 | #define WM8960_BUFIOEN 0x08 | |
41 | #define WM8960_SOFT_ST 0x04 | |
42 | #define WM8960_HPSTBY 0x01 | |
43 | ||
44 | /* R29 - Anti-pop 2 */ | |
45 | #define WM8960_DISOP 0x40 | |
913d7b4c | 46 | #define WM8960_DRES_MASK 0x30 |
f2644a2c | 47 | |
3176bf2d | 48 | static bool is_pll_freq_available(unsigned int source, unsigned int target); |
e075fc17 | 49 | static int wm8960_set_pll(struct snd_soc_component *component, |
3176bf2d | 50 | unsigned int freq_in, unsigned int freq_out); |
f2644a2c MB |
51 | /* |
52 | * wm8960 register cache | |
53 | * We can't read the WM8960 register space when we are | |
54 | * using 2 wire for device control, so we cache them instead. | |
55 | */ | |
0ebe36c6 | 56 | static const struct reg_default wm8960_reg_defaults[] = { |
b3df026e MB |
57 | { 0x0, 0x00a7 }, |
58 | { 0x1, 0x00a7 }, | |
0ebe36c6 MB |
59 | { 0x2, 0x0000 }, |
60 | { 0x3, 0x0000 }, | |
61 | { 0x4, 0x0000 }, | |
62 | { 0x5, 0x0008 }, | |
63 | { 0x6, 0x0000 }, | |
64 | { 0x7, 0x000a }, | |
65 | { 0x8, 0x01c0 }, | |
66 | { 0x9, 0x0000 }, | |
67 | { 0xa, 0x00ff }, | |
68 | { 0xb, 0x00ff }, | |
69 | ||
70 | { 0x10, 0x0000 }, | |
71 | { 0x11, 0x007b }, | |
72 | { 0x12, 0x0100 }, | |
73 | { 0x13, 0x0032 }, | |
74 | { 0x14, 0x0000 }, | |
75 | { 0x15, 0x00c3 }, | |
76 | { 0x16, 0x00c3 }, | |
77 | { 0x17, 0x01c0 }, | |
78 | { 0x18, 0x0000 }, | |
79 | { 0x19, 0x0000 }, | |
80 | { 0x1a, 0x0000 }, | |
81 | { 0x1b, 0x0000 }, | |
82 | { 0x1c, 0x0000 }, | |
83 | { 0x1d, 0x0000 }, | |
84 | ||
85 | { 0x20, 0x0100 }, | |
86 | { 0x21, 0x0100 }, | |
87 | { 0x22, 0x0050 }, | |
88 | ||
89 | { 0x25, 0x0050 }, | |
90 | { 0x26, 0x0000 }, | |
91 | { 0x27, 0x0000 }, | |
92 | { 0x28, 0x0000 }, | |
93 | { 0x29, 0x0000 }, | |
94 | { 0x2a, 0x0040 }, | |
95 | { 0x2b, 0x0000 }, | |
96 | { 0x2c, 0x0000 }, | |
97 | { 0x2d, 0x0050 }, | |
98 | { 0x2e, 0x0050 }, | |
99 | { 0x2f, 0x0000 }, | |
100 | { 0x30, 0x0002 }, | |
101 | { 0x31, 0x0037 }, | |
102 | ||
103 | { 0x33, 0x0080 }, | |
104 | { 0x34, 0x0008 }, | |
105 | { 0x35, 0x0031 }, | |
106 | { 0x36, 0x0026 }, | |
107 | { 0x37, 0x00e9 }, | |
f2644a2c MB |
108 | }; |
109 | ||
0ebe36c6 MB |
110 | static bool wm8960_volatile(struct device *dev, unsigned int reg) |
111 | { | |
112 | switch (reg) { | |
113 | case WM8960_RESET: | |
114 | return true; | |
115 | default: | |
116 | return false; | |
117 | } | |
118 | } | |
119 | ||
f2644a2c | 120 | struct wm8960_priv { |
75aa8868 | 121 | struct clk *mclk; |
0ebe36c6 | 122 | struct regmap *regmap; |
e075fc17 | 123 | int (*set_bias_level)(struct snd_soc_component *, |
f0fba2ad | 124 | enum snd_soc_bias_level level); |
913d7b4c MB |
125 | struct snd_soc_dapm_widget *lout1; |
126 | struct snd_soc_dapm_widget *rout1; | |
127 | struct snd_soc_dapm_widget *out3; | |
afd6d36a | 128 | bool deemph; |
3176bf2d | 129 | int lrclk; |
0e50b51a ZW |
130 | int bclk; |
131 | int sysclk; | |
3176bf2d ZW |
132 | int clk_id; |
133 | int freq_in; | |
134 | bool is_stream_in_use[2]; | |
e2280c90 | 135 | struct wm8960_data pdata; |
f2644a2c MB |
136 | }; |
137 | ||
3ad5e861 | 138 | #define wm8960_reset(c) regmap_write(c, WM8960_RESET, 0) |
f2644a2c MB |
139 | |
140 | /* enumerated controls */ | |
f2644a2c MB |
141 | static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted", |
142 | "Right Inverted", "Stereo Inversion"}; | |
143 | static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"}; | |
144 | static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"}; | |
145 | static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"}; | |
146 | static const char *wm8960_alcmode[] = {"ALC", "Limiter"}; | |
4a5893cf ZW |
147 | static const char *wm8960_adc_data_output_sel[] = { |
148 | "Left Data = Left ADC; Right Data = Right ADC", | |
149 | "Left Data = Left ADC; Right Data = Left ADC", | |
150 | "Left Data = Right ADC; Right Data = Right ADC", | |
151 | "Left Data = Right ADC; Right Data = Left ADC", | |
152 | }; | |
defbf708 | 153 | static const char *wm8960_dmonomix[] = {"Stereo", "Mono"}; |
f2644a2c MB |
154 | |
155 | static const struct soc_enum wm8960_enum[] = { | |
f2644a2c MB |
156 | SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity), |
157 | SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity), | |
158 | SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff), | |
159 | SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff), | |
160 | SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc), | |
161 | SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode), | |
4a5893cf | 162 | SOC_ENUM_SINGLE(WM8960_ADDCTL1, 2, 4, wm8960_adc_data_output_sel), |
defbf708 | 163 | SOC_ENUM_SINGLE(WM8960_ADDCTL1, 4, 2, wm8960_dmonomix), |
f2644a2c MB |
164 | }; |
165 | ||
afd6d36a MB |
166 | static const int deemph_settings[] = { 0, 32000, 44100, 48000 }; |
167 | ||
e075fc17 | 168 | static int wm8960_set_deemph(struct snd_soc_component *component) |
afd6d36a | 169 | { |
e075fc17 | 170 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); |
afd6d36a MB |
171 | int val, i, best; |
172 | ||
173 | /* If we're using deemphasis select the nearest available sample | |
174 | * rate. | |
175 | */ | |
176 | if (wm8960->deemph) { | |
177 | best = 1; | |
178 | for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { | |
3176bf2d ZW |
179 | if (abs(deemph_settings[i] - wm8960->lrclk) < |
180 | abs(deemph_settings[best] - wm8960->lrclk)) | |
afd6d36a MB |
181 | best = i; |
182 | } | |
183 | ||
184 | val = best << 1; | |
185 | } else { | |
186 | val = 0; | |
187 | } | |
188 | ||
e075fc17 | 189 | dev_dbg(component->dev, "Set deemphasis %d\n", val); |
afd6d36a | 190 | |
e075fc17 | 191 | return snd_soc_component_update_bits(component, WM8960_DACCTL1, |
afd6d36a MB |
192 | 0x6, val); |
193 | } | |
194 | ||
195 | static int wm8960_get_deemph(struct snd_kcontrol *kcontrol, | |
196 | struct snd_ctl_elem_value *ucontrol) | |
197 | { | |
e075fc17 KM |
198 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
199 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); | |
afd6d36a | 200 | |
b4a18c8b | 201 | ucontrol->value.integer.value[0] = wm8960->deemph; |
3f343f85 | 202 | return 0; |
afd6d36a MB |
203 | } |
204 | ||
205 | static int wm8960_put_deemph(struct snd_kcontrol *kcontrol, | |
206 | struct snd_ctl_elem_value *ucontrol) | |
207 | { | |
e075fc17 KM |
208 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
209 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); | |
c1fe81f2 | 210 | unsigned int deemph = ucontrol->value.integer.value[0]; |
afd6d36a MB |
211 | |
212 | if (deemph > 1) | |
213 | return -EINVAL; | |
214 | ||
215 | wm8960->deemph = deemph; | |
216 | ||
e075fc17 | 217 | return wm8960_set_deemph(component); |
afd6d36a MB |
218 | } |
219 | ||
3758ff5f | 220 | static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1); |
7e90f9b2 | 221 | static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1725, 75, 0); |
3758ff5f | 222 | static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); |
f2644a2c MB |
223 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0); |
224 | static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); | |
7e90f9b2 | 225 | static const DECLARE_TLV_DB_SCALE(lineinboost_tlv, -1500, 300, 1); |
b269cebf | 226 | static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(micboost_tlv, |
7e90f9b2 ZW |
227 | 0, 1, TLV_DB_SCALE_ITEM(0, 1300, 0), |
228 | 2, 3, TLV_DB_SCALE_ITEM(2000, 900, 0), | |
b269cebf | 229 | ); |
f2644a2c MB |
230 | |
231 | static const struct snd_kcontrol_new wm8960_snd_controls[] = { | |
232 | SOC_DOUBLE_R_TLV("Capture Volume", WM8960_LINVOL, WM8960_RINVOL, | |
7e90f9b2 | 233 | 0, 63, 0, inpga_tlv), |
f2644a2c MB |
234 | SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL, |
235 | 6, 1, 0), | |
236 | SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL, | |
41a59cae | 237 | 7, 1, 1), |
f2644a2c | 238 | |
95826a37 | 239 | SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT3 Volume", |
7e90f9b2 | 240 | WM8960_INBMIX1, 4, 7, 0, lineinboost_tlv), |
95826a37 | 241 | SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT2 Volume", |
7e90f9b2 | 242 | WM8960_INBMIX1, 1, 7, 0, lineinboost_tlv), |
95826a37 | 243 | SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT3 Volume", |
7e90f9b2 | 244 | WM8960_INBMIX2, 4, 7, 0, lineinboost_tlv), |
95826a37 | 245 | SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT2 Volume", |
7e90f9b2 ZW |
246 | WM8960_INBMIX2, 1, 7, 0, lineinboost_tlv), |
247 | SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT1 Volume", | |
8524bb0c | 248 | WM8960_RINPATH, 4, 3, 0, micboost_tlv), |
7e90f9b2 | 249 | SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT1 Volume", |
8524bb0c | 250 | WM8960_LINPATH, 4, 3, 0, micboost_tlv), |
21eb2693 | 251 | |
f2644a2c MB |
252 | SOC_DOUBLE_R_TLV("Playback Volume", WM8960_LDAC, WM8960_RDAC, |
253 | 0, 255, 0, dac_tlv), | |
254 | ||
255 | SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1, | |
256 | 0, 127, 0, out_tlv), | |
257 | SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1, | |
258 | 7, 1, 0), | |
259 | ||
260 | SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8960_LOUT2, WM8960_ROUT2, | |
261 | 0, 127, 0, out_tlv), | |
262 | SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8960_LOUT2, WM8960_ROUT2, | |
263 | 7, 1, 0), | |
264 | SOC_SINGLE("Speaker DC Volume", WM8960_CLASSD3, 3, 5, 0), | |
265 | SOC_SINGLE("Speaker AC Volume", WM8960_CLASSD3, 0, 5, 0), | |
266 | ||
267 | SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0), | |
4faaa8d9 | 268 | SOC_ENUM("ADC Polarity", wm8960_enum[0]), |
f2644a2c MB |
269 | SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0), |
270 | ||
a077e81e | 271 | SOC_ENUM("DAC Polarity", wm8960_enum[1]), |
afd6d36a MB |
272 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, |
273 | wm8960_get_deemph, wm8960_put_deemph), | |
f2644a2c | 274 | |
4faaa8d9 MB |
275 | SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[2]), |
276 | SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[3]), | |
f2644a2c MB |
277 | SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0), |
278 | SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0), | |
279 | ||
4faaa8d9 | 280 | SOC_ENUM("ALC Function", wm8960_enum[4]), |
f2644a2c MB |
281 | SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0), |
282 | SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1), | |
283 | SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0), | |
284 | SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0), | |
4faaa8d9 | 285 | SOC_ENUM("ALC Mode", wm8960_enum[5]), |
f2644a2c MB |
286 | SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0), |
287 | SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0), | |
288 | ||
289 | SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0), | |
290 | SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0), | |
291 | ||
c324aac0 MH |
292 | SOC_DOUBLE_R_TLV("ADC PCM Capture Volume", WM8960_LADC, WM8960_RADC, |
293 | 0, 255, 0, adc_tlv), | |
f2644a2c MB |
294 | |
295 | SOC_SINGLE_TLV("Left Output Mixer Boost Bypass Volume", | |
296 | WM8960_BYPASS1, 4, 7, 1, bypass_tlv), | |
297 | SOC_SINGLE_TLV("Left Output Mixer LINPUT3 Volume", | |
298 | WM8960_LOUTMIX, 4, 7, 1, bypass_tlv), | |
299 | SOC_SINGLE_TLV("Right Output Mixer Boost Bypass Volume", | |
300 | WM8960_BYPASS2, 4, 7, 1, bypass_tlv), | |
301 | SOC_SINGLE_TLV("Right Output Mixer RINPUT3 Volume", | |
302 | WM8960_ROUTMIX, 4, 7, 1, bypass_tlv), | |
4a5893cf ZW |
303 | |
304 | SOC_ENUM("ADC Data Output Select", wm8960_enum[6]), | |
defbf708 | 305 | SOC_ENUM("DAC Mono Mix", wm8960_enum[7]), |
f2644a2c MB |
306 | }; |
307 | ||
308 | static const struct snd_kcontrol_new wm8960_lin_boost[] = { | |
309 | SOC_DAPM_SINGLE("LINPUT2 Switch", WM8960_LINPATH, 6, 1, 0), | |
310 | SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LINPATH, 7, 1, 0), | |
311 | SOC_DAPM_SINGLE("LINPUT1 Switch", WM8960_LINPATH, 8, 1, 0), | |
312 | }; | |
313 | ||
314 | static const struct snd_kcontrol_new wm8960_lin[] = { | |
315 | SOC_DAPM_SINGLE("Boost Switch", WM8960_LINPATH, 3, 1, 0), | |
316 | }; | |
317 | ||
318 | static const struct snd_kcontrol_new wm8960_rin_boost[] = { | |
319 | SOC_DAPM_SINGLE("RINPUT2 Switch", WM8960_RINPATH, 6, 1, 0), | |
320 | SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_RINPATH, 7, 1, 0), | |
321 | SOC_DAPM_SINGLE("RINPUT1 Switch", WM8960_RINPATH, 8, 1, 0), | |
322 | }; | |
323 | ||
324 | static const struct snd_kcontrol_new wm8960_rin[] = { | |
325 | SOC_DAPM_SINGLE("Boost Switch", WM8960_RINPATH, 3, 1, 0), | |
326 | }; | |
327 | ||
328 | static const struct snd_kcontrol_new wm8960_loutput_mixer[] = { | |
329 | SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_LOUTMIX, 8, 1, 0), | |
330 | SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LOUTMIX, 7, 1, 0), | |
331 | SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS1, 7, 1, 0), | |
332 | }; | |
333 | ||
334 | static const struct snd_kcontrol_new wm8960_routput_mixer[] = { | |
335 | SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_ROUTMIX, 8, 1, 0), | |
336 | SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_ROUTMIX, 7, 1, 0), | |
337 | SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS2, 7, 1, 0), | |
338 | }; | |
339 | ||
340 | static const struct snd_kcontrol_new wm8960_mono_out[] = { | |
341 | SOC_DAPM_SINGLE("Left Switch", WM8960_MONOMIX1, 7, 1, 0), | |
342 | SOC_DAPM_SINGLE("Right Switch", WM8960_MONOMIX2, 7, 1, 0), | |
343 | }; | |
344 | ||
345 | static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = { | |
346 | SND_SOC_DAPM_INPUT("LINPUT1"), | |
347 | SND_SOC_DAPM_INPUT("RINPUT1"), | |
348 | SND_SOC_DAPM_INPUT("LINPUT2"), | |
349 | SND_SOC_DAPM_INPUT("RINPUT2"), | |
350 | SND_SOC_DAPM_INPUT("LINPUT3"), | |
351 | SND_SOC_DAPM_INPUT("RINPUT3"), | |
352 | ||
187774cb | 353 | SND_SOC_DAPM_SUPPLY("MICB", WM8960_POWER1, 1, 0, NULL, 0), |
f2644a2c MB |
354 | |
355 | SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8960_POWER1, 5, 0, | |
356 | wm8960_lin_boost, ARRAY_SIZE(wm8960_lin_boost)), | |
357 | SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8960_POWER1, 4, 0, | |
358 | wm8960_rin_boost, ARRAY_SIZE(wm8960_rin_boost)), | |
359 | ||
360 | SND_SOC_DAPM_MIXER("Left Input Mixer", WM8960_POWER3, 5, 0, | |
361 | wm8960_lin, ARRAY_SIZE(wm8960_lin)), | |
362 | SND_SOC_DAPM_MIXER("Right Input Mixer", WM8960_POWER3, 4, 0, | |
363 | wm8960_rin, ARRAY_SIZE(wm8960_rin)), | |
364 | ||
44426de4 MB |
365 | SND_SOC_DAPM_ADC("Left ADC", "Capture", WM8960_POWER1, 3, 0), |
366 | SND_SOC_DAPM_ADC("Right ADC", "Capture", WM8960_POWER1, 2, 0), | |
f2644a2c MB |
367 | |
368 | SND_SOC_DAPM_DAC("Left DAC", "Playback", WM8960_POWER2, 8, 0), | |
369 | SND_SOC_DAPM_DAC("Right DAC", "Playback", WM8960_POWER2, 7, 0), | |
370 | ||
371 | SND_SOC_DAPM_MIXER("Left Output Mixer", WM8960_POWER3, 3, 0, | |
372 | &wm8960_loutput_mixer[0], | |
373 | ARRAY_SIZE(wm8960_loutput_mixer)), | |
374 | SND_SOC_DAPM_MIXER("Right Output Mixer", WM8960_POWER3, 2, 0, | |
375 | &wm8960_routput_mixer[0], | |
376 | ARRAY_SIZE(wm8960_routput_mixer)), | |
377 | ||
f2644a2c MB |
378 | SND_SOC_DAPM_PGA("LOUT1 PGA", WM8960_POWER2, 6, 0, NULL, 0), |
379 | SND_SOC_DAPM_PGA("ROUT1 PGA", WM8960_POWER2, 5, 0, NULL, 0), | |
380 | ||
381 | SND_SOC_DAPM_PGA("Left Speaker PGA", WM8960_POWER2, 4, 0, NULL, 0), | |
382 | SND_SOC_DAPM_PGA("Right Speaker PGA", WM8960_POWER2, 3, 0, NULL, 0), | |
383 | ||
384 | SND_SOC_DAPM_PGA("Right Speaker Output", WM8960_CLASSD1, 7, 0, NULL, 0), | |
385 | SND_SOC_DAPM_PGA("Left Speaker Output", WM8960_CLASSD1, 6, 0, NULL, 0), | |
386 | ||
387 | SND_SOC_DAPM_OUTPUT("SPK_LP"), | |
388 | SND_SOC_DAPM_OUTPUT("SPK_LN"), | |
389 | SND_SOC_DAPM_OUTPUT("HP_L"), | |
390 | SND_SOC_DAPM_OUTPUT("HP_R"), | |
391 | SND_SOC_DAPM_OUTPUT("SPK_RP"), | |
392 | SND_SOC_DAPM_OUTPUT("SPK_RN"), | |
393 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
394 | }; | |
395 | ||
913d7b4c MB |
396 | static const struct snd_soc_dapm_widget wm8960_dapm_widgets_out3[] = { |
397 | SND_SOC_DAPM_MIXER("Mono Output Mixer", WM8960_POWER2, 1, 0, | |
398 | &wm8960_mono_out[0], | |
399 | ARRAY_SIZE(wm8960_mono_out)), | |
400 | }; | |
401 | ||
402 | /* Represent OUT3 as a PGA so that it gets turned on with LOUT1/ROUT1 */ | |
403 | static const struct snd_soc_dapm_widget wm8960_dapm_widgets_capless[] = { | |
404 | SND_SOC_DAPM_PGA("OUT3 VMID", WM8960_POWER2, 1, 0, NULL, 0), | |
405 | }; | |
406 | ||
f2644a2c MB |
407 | static const struct snd_soc_dapm_route audio_paths[] = { |
408 | { "Left Boost Mixer", "LINPUT1 Switch", "LINPUT1" }, | |
409 | { "Left Boost Mixer", "LINPUT2 Switch", "LINPUT2" }, | |
410 | { "Left Boost Mixer", "LINPUT3 Switch", "LINPUT3" }, | |
411 | ||
2d4a3260 ZW |
412 | { "Left Input Mixer", "Boost Switch", "Left Boost Mixer" }, |
413 | { "Left Input Mixer", "Boost Switch", "LINPUT1" }, /* Really Boost Switch */ | |
f2644a2c MB |
414 | { "Left Input Mixer", NULL, "LINPUT2" }, |
415 | { "Left Input Mixer", NULL, "LINPUT3" }, | |
416 | ||
417 | { "Right Boost Mixer", "RINPUT1 Switch", "RINPUT1" }, | |
418 | { "Right Boost Mixer", "RINPUT2 Switch", "RINPUT2" }, | |
419 | { "Right Boost Mixer", "RINPUT3 Switch", "RINPUT3" }, | |
420 | ||
2d4a3260 ZW |
421 | { "Right Input Mixer", "Boost Switch", "Right Boost Mixer" }, |
422 | { "Right Input Mixer", "Boost Switch", "RINPUT1" }, /* Really Boost Switch */ | |
f2644a2c | 423 | { "Right Input Mixer", NULL, "RINPUT2" }, |
85e36a1f | 424 | { "Right Input Mixer", NULL, "RINPUT3" }, |
f2644a2c MB |
425 | |
426 | { "Left ADC", NULL, "Left Input Mixer" }, | |
427 | { "Right ADC", NULL, "Right Input Mixer" }, | |
428 | ||
429 | { "Left Output Mixer", "LINPUT3 Switch", "LINPUT3" }, | |
2d4a3260 | 430 | { "Left Output Mixer", "Boost Bypass Switch", "Left Boost Mixer" }, |
f2644a2c MB |
431 | { "Left Output Mixer", "PCM Playback Switch", "Left DAC" }, |
432 | ||
433 | { "Right Output Mixer", "RINPUT3 Switch", "RINPUT3" }, | |
2d4a3260 | 434 | { "Right Output Mixer", "Boost Bypass Switch", "Right Boost Mixer" }, |
f2644a2c MB |
435 | { "Right Output Mixer", "PCM Playback Switch", "Right DAC" }, |
436 | ||
f2644a2c MB |
437 | { "LOUT1 PGA", NULL, "Left Output Mixer" }, |
438 | { "ROUT1 PGA", NULL, "Right Output Mixer" }, | |
439 | ||
440 | { "HP_L", NULL, "LOUT1 PGA" }, | |
441 | { "HP_R", NULL, "ROUT1 PGA" }, | |
442 | ||
443 | { "Left Speaker PGA", NULL, "Left Output Mixer" }, | |
444 | { "Right Speaker PGA", NULL, "Right Output Mixer" }, | |
445 | ||
446 | { "Left Speaker Output", NULL, "Left Speaker PGA" }, | |
447 | { "Right Speaker Output", NULL, "Right Speaker PGA" }, | |
448 | ||
449 | { "SPK_LN", NULL, "Left Speaker Output" }, | |
450 | { "SPK_LP", NULL, "Left Speaker Output" }, | |
451 | { "SPK_RN", NULL, "Right Speaker Output" }, | |
452 | { "SPK_RP", NULL, "Right Speaker Output" }, | |
913d7b4c MB |
453 | }; |
454 | ||
455 | static const struct snd_soc_dapm_route audio_paths_out3[] = { | |
456 | { "Mono Output Mixer", "Left Switch", "Left Output Mixer" }, | |
457 | { "Mono Output Mixer", "Right Switch", "Right Output Mixer" }, | |
f2644a2c MB |
458 | |
459 | { "OUT3", NULL, "Mono Output Mixer", } | |
460 | }; | |
461 | ||
913d7b4c MB |
462 | static const struct snd_soc_dapm_route audio_paths_capless[] = { |
463 | { "HP_L", NULL, "OUT3 VMID" }, | |
464 | { "HP_R", NULL, "OUT3 VMID" }, | |
465 | ||
466 | { "OUT3 VMID", NULL, "Left Output Mixer" }, | |
467 | { "OUT3 VMID", NULL, "Right Output Mixer" }, | |
468 | }; | |
469 | ||
e075fc17 | 470 | static int wm8960_add_widgets(struct snd_soc_component *component) |
f2644a2c | 471 | { |
e075fc17 | 472 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); |
e2280c90 | 473 | struct wm8960_data *pdata = &wm8960->pdata; |
e075fc17 | 474 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); |
913d7b4c MB |
475 | struct snd_soc_dapm_widget *w; |
476 | ||
ce6120cc | 477 | snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets, |
f2644a2c MB |
478 | ARRAY_SIZE(wm8960_dapm_widgets)); |
479 | ||
ce6120cc | 480 | snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths)); |
f2644a2c | 481 | |
913d7b4c MB |
482 | /* In capless mode OUT3 is used to provide VMID for the |
483 | * headphone outputs, otherwise it is used as a mono mixer. | |
484 | */ | |
485 | if (pdata && pdata->capless) { | |
ce6120cc | 486 | snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless, |
913d7b4c MB |
487 | ARRAY_SIZE(wm8960_dapm_widgets_capless)); |
488 | ||
ce6120cc | 489 | snd_soc_dapm_add_routes(dapm, audio_paths_capless, |
913d7b4c MB |
490 | ARRAY_SIZE(audio_paths_capless)); |
491 | } else { | |
ce6120cc | 492 | snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3, |
913d7b4c MB |
493 | ARRAY_SIZE(wm8960_dapm_widgets_out3)); |
494 | ||
ce6120cc | 495 | snd_soc_dapm_add_routes(dapm, audio_paths_out3, |
913d7b4c MB |
496 | ARRAY_SIZE(audio_paths_out3)); |
497 | } | |
498 | ||
499 | /* We need to power up the headphone output stage out of | |
500 | * sequence for capless mode. To save scanning the widget | |
501 | * list each time to find the desired power state do so now | |
502 | * and save the result. | |
503 | */ | |
e075fc17 | 504 | list_for_each_entry(w, &component->card->widgets, list) { |
93f32f53 | 505 | if (w->dapm != dapm) |
97c866de | 506 | continue; |
913d7b4c MB |
507 | if (strcmp(w->name, "LOUT1 PGA") == 0) |
508 | wm8960->lout1 = w; | |
509 | if (strcmp(w->name, "ROUT1 PGA") == 0) | |
510 | wm8960->rout1 = w; | |
511 | if (strcmp(w->name, "OUT3 VMID") == 0) | |
512 | wm8960->out3 = w; | |
513 | } | |
514 | ||
f2644a2c MB |
515 | return 0; |
516 | } | |
517 | ||
518 | static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
519 | unsigned int fmt) | |
520 | { | |
e075fc17 | 521 | struct snd_soc_component *component = codec_dai->component; |
f2644a2c MB |
522 | u16 iface = 0; |
523 | ||
524 | /* set master/slave audio interface */ | |
525 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
526 | case SND_SOC_DAIFMT_CBM_CFM: | |
527 | iface |= 0x0040; | |
528 | break; | |
529 | case SND_SOC_DAIFMT_CBS_CFS: | |
530 | break; | |
531 | default: | |
532 | return -EINVAL; | |
533 | } | |
534 | ||
535 | /* interface format */ | |
536 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
537 | case SND_SOC_DAIFMT_I2S: | |
538 | iface |= 0x0002; | |
539 | break; | |
540 | case SND_SOC_DAIFMT_RIGHT_J: | |
541 | break; | |
542 | case SND_SOC_DAIFMT_LEFT_J: | |
543 | iface |= 0x0001; | |
544 | break; | |
545 | case SND_SOC_DAIFMT_DSP_A: | |
546 | iface |= 0x0003; | |
547 | break; | |
548 | case SND_SOC_DAIFMT_DSP_B: | |
549 | iface |= 0x0013; | |
550 | break; | |
551 | default: | |
552 | return -EINVAL; | |
553 | } | |
554 | ||
555 | /* clock inversion */ | |
556 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
557 | case SND_SOC_DAIFMT_NB_NF: | |
558 | break; | |
559 | case SND_SOC_DAIFMT_IB_IF: | |
560 | iface |= 0x0090; | |
561 | break; | |
562 | case SND_SOC_DAIFMT_IB_NF: | |
563 | iface |= 0x0080; | |
564 | break; | |
565 | case SND_SOC_DAIFMT_NB_IF: | |
566 | iface |= 0x0010; | |
567 | break; | |
568 | default: | |
569 | return -EINVAL; | |
570 | } | |
571 | ||
572 | /* set iface */ | |
e075fc17 | 573 | snd_soc_component_write(component, WM8960_IFACE1, iface); |
f2644a2c MB |
574 | return 0; |
575 | } | |
576 | ||
db059c0f MB |
577 | static struct { |
578 | int rate; | |
579 | unsigned int val; | |
580 | } alc_rates[] = { | |
581 | { 48000, 0 }, | |
582 | { 44100, 0 }, | |
583 | { 32000, 1 }, | |
584 | { 22050, 2 }, | |
585 | { 24000, 2 }, | |
586 | { 16000, 3 }, | |
22ee76da | 587 | { 11025, 4 }, |
db059c0f MB |
588 | { 12000, 4 }, |
589 | { 8000, 5 }, | |
590 | }; | |
591 | ||
3176bf2d ZW |
592 | /* -1 for reserved value */ |
593 | static const int sysclk_divs[] = { 1, -1, 2, -1 }; | |
594 | ||
0e50b51a ZW |
595 | /* Multiply 256 for internal 256 div */ |
596 | static const int dac_divs[] = { 256, 384, 512, 768, 1024, 1408, 1536 }; | |
597 | ||
598 | /* Multiply 10 to eliminate decimials */ | |
599 | static const int bclk_divs[] = { | |
600 | 10, 15, 20, 30, 40, 55, 60, 80, 110, | |
601 | 120, 160, 220, 240, 320, 320, 320 | |
602 | }; | |
603 | ||
3ddc9721 DB |
604 | /** |
605 | * wm8960_configure_sysclk - checks if there is a sysclk frequency available | |
606 | * The sysclk must be chosen such that: | |
607 | * - sysclk = MCLK / sysclk_divs | |
608 | * - lrclk = sysclk / dac_divs | |
609 | * - 10 * bclk = sysclk / bclk_divs | |
610 | * | |
419eac3c | 611 | * @wm8960: codec private data |
3ddc9721 DB |
612 | * @mclk: MCLK used to derive sysclk |
613 | * @sysclk_idx: sysclk_divs index for found sysclk | |
614 | * @dac_idx: dac_divs index for found lrclk | |
615 | * @bclk_idx: bclk_divs index for found bclk | |
616 | * | |
617 | * Returns: | |
3c01b9ee DB |
618 | * -1, in case no sysclk frequency available found |
619 | * >=0, in case we could derive bclk and lrclk from sysclk using | |
620 | * (@sysclk_idx, @dac_idx, @bclk_idx) dividers | |
3ddc9721 DB |
621 | */ |
622 | static | |
623 | int wm8960_configure_sysclk(struct wm8960_priv *wm8960, int mclk, | |
624 | int *sysclk_idx, int *dac_idx, int *bclk_idx) | |
625 | { | |
626 | int sysclk, bclk, lrclk; | |
627 | int i, j, k; | |
99067c07 | 628 | int diff; |
3c01b9ee DB |
629 | |
630 | /* marker for no match */ | |
631 | *bclk_idx = -1; | |
3ddc9721 DB |
632 | |
633 | bclk = wm8960->bclk; | |
634 | lrclk = wm8960->lrclk; | |
635 | ||
636 | /* check if the sysclk frequency is available. */ | |
637 | for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) { | |
638 | if (sysclk_divs[i] == -1) | |
639 | continue; | |
640 | sysclk = mclk / sysclk_divs[i]; | |
641 | for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) { | |
642 | if (sysclk != dac_divs[j] * lrclk) | |
643 | continue; | |
644 | for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) { | |
645 | diff = sysclk - bclk * bclk_divs[k] / 10; | |
646 | if (diff == 0) { | |
647 | *sysclk_idx = i; | |
648 | *dac_idx = j; | |
649 | *bclk_idx = k; | |
650 | break; | |
651 | } | |
652 | } | |
653 | if (k != ARRAY_SIZE(bclk_divs)) | |
654 | break; | |
655 | } | |
656 | if (j != ARRAY_SIZE(dac_divs)) | |
657 | break; | |
658 | } | |
3c01b9ee | 659 | return *bclk_idx; |
3ddc9721 DB |
660 | } |
661 | ||
84fdc00d DB |
662 | /** |
663 | * wm8960_configure_pll - checks if there is a PLL out frequency available | |
664 | * The PLL out frequency must be chosen such that: | |
665 | * - sysclk = lrclk * dac_divs | |
666 | * - freq_out = sysclk * sysclk_divs | |
667 | * - 10 * sysclk = bclk * bclk_divs | |
668 | * | |
82bab889 DB |
669 | * If we cannot find an exact match for (sysclk, lrclk, bclk) |
670 | * triplet, we relax the bclk such that bclk is chosen as the | |
671 | * closest available frequency greater than expected bclk. | |
672 | * | |
e075fc17 | 673 | * @component: component structure |
84fdc00d DB |
674 | * @freq_in: input frequency used to derive freq out via PLL |
675 | * @sysclk_idx: sysclk_divs index for found sysclk | |
676 | * @dac_idx: dac_divs index for found lrclk | |
677 | * @bclk_idx: bclk_divs index for found bclk | |
678 | * | |
679 | * Returns: | |
66772eda | 680 | * < 0, in case no PLL frequency out available was found |
84fdc00d DB |
681 | * >=0, in case we could derive bclk, lrclk, sysclk from PLL out using |
682 | * (@sysclk_idx, @dac_idx, @bclk_idx) dividers | |
683 | */ | |
684 | static | |
e075fc17 | 685 | int wm8960_configure_pll(struct snd_soc_component *component, int freq_in, |
84fdc00d DB |
686 | int *sysclk_idx, int *dac_idx, int *bclk_idx) |
687 | { | |
e075fc17 | 688 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); |
84fdc00d | 689 | int sysclk, bclk, lrclk, freq_out; |
82bab889 | 690 | int diff, closest, best_freq_out; |
84fdc00d DB |
691 | int i, j, k; |
692 | ||
693 | bclk = wm8960->bclk; | |
694 | lrclk = wm8960->lrclk; | |
82bab889 | 695 | closest = freq_in; |
84fdc00d | 696 | |
82bab889 | 697 | best_freq_out = -EINVAL; |
66772eda | 698 | *sysclk_idx = *dac_idx = *bclk_idx = -1; |
84fdc00d | 699 | |
16b82e75 SW |
700 | /* |
701 | * From Datasheet, the PLL performs best when f2 is between | |
702 | * 90MHz and 100MHz, the desired sysclk output is 11.2896MHz | |
703 | * or 12.288MHz, then sysclkdiv = 2 is the best choice. | |
704 | * So search sysclk_divs from 2 to 1 other than from 1 to 2. | |
705 | */ | |
706 | for (i = ARRAY_SIZE(sysclk_divs) - 1; i >= 0; --i) { | |
84fdc00d DB |
707 | if (sysclk_divs[i] == -1) |
708 | continue; | |
709 | for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) { | |
710 | sysclk = lrclk * dac_divs[j]; | |
711 | freq_out = sysclk * sysclk_divs[i]; | |
712 | ||
713 | for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) { | |
714 | if (!is_pll_freq_available(freq_in, freq_out)) | |
715 | continue; | |
716 | ||
717 | diff = sysclk - bclk * bclk_divs[k] / 10; | |
718 | if (diff == 0) { | |
719 | *sysclk_idx = i; | |
720 | *dac_idx = j; | |
721 | *bclk_idx = k; | |
66772eda | 722 | return freq_out; |
84fdc00d | 723 | } |
82bab889 DB |
724 | if (diff > 0 && closest > diff) { |
725 | *sysclk_idx = i; | |
726 | *dac_idx = j; | |
727 | *bclk_idx = k; | |
728 | closest = diff; | |
729 | best_freq_out = freq_out; | |
730 | } | |
84fdc00d DB |
731 | } |
732 | } | |
733 | } | |
82bab889 DB |
734 | |
735 | return best_freq_out; | |
84fdc00d | 736 | } |
e075fc17 | 737 | static int wm8960_configure_clocking(struct snd_soc_component *component) |
0e50b51a | 738 | { |
e075fc17 | 739 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); |
84fdc00d | 740 | int freq_out, freq_in; |
6d75dfc3 | 741 | u16 iface1 = snd_soc_component_read(component, WM8960_IFACE1); |
3176bf2d | 742 | int i, j, k; |
3ddc9721 | 743 | int ret; |
0e50b51a | 744 | |
6b9b546d SW |
745 | /* |
746 | * For Slave mode clocking should still be configured, | |
747 | * so this if statement should be removed, but some platform | |
748 | * may not work if the sysclk is not configured, to avoid such | |
749 | * compatible issue, just add '!wm8960->sysclk' condition in | |
750 | * this if statement. | |
751 | */ | |
752 | if (!(iface1 & (1 << 6)) && !wm8960->sysclk) { | |
753 | dev_warn(component->dev, | |
754 | "slave mode, but proceeding with no clock configuration\n"); | |
3176bf2d ZW |
755 | return 0; |
756 | } | |
757 | ||
758 | if (wm8960->clk_id != WM8960_SYSCLK_MCLK && !wm8960->freq_in) { | |
e075fc17 | 759 | dev_err(component->dev, "No MCLK configured\n"); |
3176bf2d | 760 | return -EINVAL; |
0e50b51a ZW |
761 | } |
762 | ||
3176bf2d | 763 | freq_in = wm8960->freq_in; |
3176bf2d ZW |
764 | /* |
765 | * If it's sysclk auto mode, check if the MCLK can provide sysclk or | |
766 | * not. If MCLK can provide sysclk, using MCLK to provide sysclk | |
767 | * directly. Otherwise, auto select a available pll out frequency | |
768 | * and set PLL. | |
769 | */ | |
770 | if (wm8960->clk_id == WM8960_SYSCLK_AUTO) { | |
771 | /* disable the PLL and using MCLK to provide sysclk */ | |
e075fc17 | 772 | wm8960_set_pll(component, 0, 0); |
3176bf2d ZW |
773 | freq_out = freq_in; |
774 | } else if (wm8960->sysclk) { | |
775 | freq_out = wm8960->sysclk; | |
776 | } else { | |
e075fc17 | 777 | dev_err(component->dev, "No SYSCLK configured\n"); |
3176bf2d | 778 | return -EINVAL; |
0e50b51a ZW |
779 | } |
780 | ||
6bb74514 | 781 | if (wm8960->clk_id != WM8960_SYSCLK_PLL) { |
3ddc9721 | 782 | ret = wm8960_configure_sysclk(wm8960, freq_out, &i, &j, &k); |
3c01b9ee | 783 | if (ret >= 0) { |
6bb74514 SH |
784 | goto configure_clock; |
785 | } else if (wm8960->clk_id != WM8960_SYSCLK_AUTO) { | |
e075fc17 | 786 | dev_err(component->dev, "failed to configure clock\n"); |
6bb74514 SH |
787 | return -EINVAL; |
788 | } | |
3176bf2d | 789 | } |
0e50b51a | 790 | |
e075fc17 | 791 | freq_out = wm8960_configure_pll(component, freq_in, &i, &j, &k); |
66772eda | 792 | if (freq_out < 0) { |
e075fc17 | 793 | dev_err(component->dev, "failed to configure clock via PLL\n"); |
66772eda | 794 | return freq_out; |
0e50b51a | 795 | } |
e075fc17 | 796 | wm8960_set_pll(component, freq_in, freq_out); |
0e50b51a | 797 | |
3176bf2d ZW |
798 | configure_clock: |
799 | /* configure sysclk clock */ | |
e075fc17 | 800 | snd_soc_component_update_bits(component, WM8960_CLOCK1, 3 << 1, i << 1); |
3176bf2d ZW |
801 | |
802 | /* configure frame clock */ | |
e075fc17 KM |
803 | snd_soc_component_update_bits(component, WM8960_CLOCK1, 0x7 << 3, j << 3); |
804 | snd_soc_component_update_bits(component, WM8960_CLOCK1, 0x7 << 6, j << 6); | |
0e50b51a ZW |
805 | |
806 | /* configure bit clock */ | |
e075fc17 | 807 | snd_soc_component_update_bits(component, WM8960_CLOCK2, 0xf, k); |
3176bf2d ZW |
808 | |
809 | return 0; | |
0e50b51a ZW |
810 | } |
811 | ||
f2644a2c MB |
812 | static int wm8960_hw_params(struct snd_pcm_substream *substream, |
813 | struct snd_pcm_hw_params *params, | |
814 | struct snd_soc_dai *dai) | |
815 | { | |
e075fc17 KM |
816 | struct snd_soc_component *component = dai->component; |
817 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); | |
6d75dfc3 | 818 | u16 iface = snd_soc_component_read(component, WM8960_IFACE1) & 0xfff3; |
0e50b51a | 819 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
db059c0f | 820 | int i; |
f2644a2c | 821 | |
0e50b51a ZW |
822 | wm8960->bclk = snd_soc_params_to_bclk(params); |
823 | if (params_channels(params) == 1) | |
824 | wm8960->bclk *= 2; | |
825 | ||
f2644a2c | 826 | /* bit size */ |
39e9cc46 MB |
827 | switch (params_width(params)) { |
828 | case 16: | |
f2644a2c | 829 | break; |
39e9cc46 | 830 | case 20: |
f2644a2c MB |
831 | iface |= 0x0004; |
832 | break; | |
39e9cc46 | 833 | case 24: |
f2644a2c MB |
834 | iface |= 0x0008; |
835 | break; | |
7a8c7867 ZW |
836 | case 32: |
837 | /* right justify mode does not support 32 word length */ | |
838 | if ((iface & 0x3) != 0) { | |
839 | iface |= 0x000c; | |
840 | break; | |
841 | } | |
3e146b55 | 842 | fallthrough; |
4c2474c0 | 843 | default: |
e075fc17 | 844 | dev_err(component->dev, "unsupported width %d\n", |
39e9cc46 | 845 | params_width(params)); |
4c2474c0 | 846 | return -EINVAL; |
f2644a2c MB |
847 | } |
848 | ||
3176bf2d | 849 | wm8960->lrclk = params_rate(params); |
afd6d36a | 850 | /* Update filters for the new rate */ |
3176bf2d | 851 | if (tx) { |
e075fc17 | 852 | wm8960_set_deemph(component); |
db059c0f MB |
853 | } else { |
854 | for (i = 0; i < ARRAY_SIZE(alc_rates); i++) | |
855 | if (alc_rates[i].rate == params_rate(params)) | |
e075fc17 | 856 | snd_soc_component_update_bits(component, |
db059c0f MB |
857 | WM8960_ADDCTL3, 0x7, |
858 | alc_rates[i].val); | |
afd6d36a MB |
859 | } |
860 | ||
f2644a2c | 861 | /* set iface */ |
e075fc17 | 862 | snd_soc_component_write(component, WM8960_IFACE1, iface); |
0e50b51a | 863 | |
3176bf2d ZW |
864 | wm8960->is_stream_in_use[tx] = true; |
865 | ||
1e060a45 | 866 | if (!wm8960->is_stream_in_use[!tx]) |
e075fc17 | 867 | return wm8960_configure_clocking(component); |
3176bf2d ZW |
868 | |
869 | return 0; | |
870 | } | |
871 | ||
872 | static int wm8960_hw_free(struct snd_pcm_substream *substream, | |
873 | struct snd_soc_dai *dai) | |
874 | { | |
e075fc17 KM |
875 | struct snd_soc_component *component = dai->component; |
876 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); | |
3176bf2d ZW |
877 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
878 | ||
879 | wm8960->is_stream_in_use[tx] = false; | |
0e50b51a | 880 | |
f2644a2c MB |
881 | return 0; |
882 | } | |
883 | ||
26d3c16e | 884 | static int wm8960_mute(struct snd_soc_dai *dai, int mute, int direction) |
f2644a2c | 885 | { |
e075fc17 | 886 | struct snd_soc_component *component = dai->component; |
f2644a2c MB |
887 | |
888 | if (mute) | |
e075fc17 | 889 | snd_soc_component_update_bits(component, WM8960_DACCTL1, 0x8, 0x8); |
f2644a2c | 890 | else |
e075fc17 | 891 | snd_soc_component_update_bits(component, WM8960_DACCTL1, 0x8, 0); |
f2644a2c MB |
892 | return 0; |
893 | } | |
894 | ||
e075fc17 | 895 | static int wm8960_set_bias_level_out3(struct snd_soc_component *component, |
913d7b4c | 896 | enum snd_soc_bias_level level) |
f2644a2c | 897 | { |
e075fc17 | 898 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); |
6d75dfc3 | 899 | u16 pm2 = snd_soc_component_read(component, WM8960_POWER2); |
75aa8868 | 900 | int ret; |
0ebe36c6 | 901 | |
f2644a2c MB |
902 | switch (level) { |
903 | case SND_SOC_BIAS_ON: | |
904 | break; | |
905 | ||
906 | case SND_SOC_BIAS_PREPARE: | |
e075fc17 | 907 | switch (snd_soc_component_get_bias_level(component)) { |
75aa8868 ZW |
908 | case SND_SOC_BIAS_STANDBY: |
909 | if (!IS_ERR(wm8960->mclk)) { | |
910 | ret = clk_prepare_enable(wm8960->mclk); | |
911 | if (ret) { | |
e075fc17 | 912 | dev_err(component->dev, |
75aa8868 ZW |
913 | "Failed to enable MCLK: %d\n", |
914 | ret); | |
915 | return ret; | |
916 | } | |
917 | } | |
918 | ||
e075fc17 | 919 | ret = wm8960_configure_clocking(component); |
3176bf2d ZW |
920 | if (ret) |
921 | return ret; | |
922 | ||
75aa8868 | 923 | /* Set VMID to 2x50k */ |
e075fc17 | 924 | snd_soc_component_update_bits(component, WM8960_POWER1, 0x180, 0x80); |
75aa8868 ZW |
925 | break; |
926 | ||
927 | case SND_SOC_BIAS_ON: | |
3176bf2d ZW |
928 | /* |
929 | * If it's sysclk auto mode, and the pll is enabled, | |
930 | * disable the pll | |
931 | */ | |
932 | if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1)) | |
e075fc17 | 933 | wm8960_set_pll(component, 0, 0); |
3176bf2d | 934 | |
75aa8868 ZW |
935 | if (!IS_ERR(wm8960->mclk)) |
936 | clk_disable_unprepare(wm8960->mclk); | |
937 | break; | |
938 | ||
939 | default: | |
940 | break; | |
941 | } | |
942 | ||
f2644a2c MB |
943 | break; |
944 | ||
945 | case SND_SOC_BIAS_STANDBY: | |
e075fc17 | 946 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
0ebe36c6 | 947 | regcache_sync(wm8960->regmap); |
bc45df2d | 948 | |
f2644a2c | 949 | /* Enable anti-pop features */ |
e075fc17 | 950 | snd_soc_component_write(component, WM8960_APOP1, |
913d7b4c MB |
951 | WM8960_POBCTRL | WM8960_SOFT_ST | |
952 | WM8960_BUFDCOPEN | WM8960_BUFIOEN); | |
f2644a2c MB |
953 | |
954 | /* Enable & ramp VMID at 2x50k */ | |
e075fc17 | 955 | snd_soc_component_update_bits(component, WM8960_POWER1, 0x80, 0x80); |
f2644a2c MB |
956 | msleep(100); |
957 | ||
958 | /* Enable VREF */ | |
e075fc17 | 959 | snd_soc_component_update_bits(component, WM8960_POWER1, WM8960_VREF, |
16b24881 | 960 | WM8960_VREF); |
f2644a2c MB |
961 | |
962 | /* Disable anti-pop features */ | |
e075fc17 | 963 | snd_soc_component_write(component, WM8960_APOP1, WM8960_BUFIOEN); |
f2644a2c MB |
964 | } |
965 | ||
966 | /* Set VMID to 2x250k */ | |
e075fc17 | 967 | snd_soc_component_update_bits(component, WM8960_POWER1, 0x180, 0x100); |
f2644a2c MB |
968 | break; |
969 | ||
970 | case SND_SOC_BIAS_OFF: | |
971 | /* Enable anti-pop features */ | |
e075fc17 | 972 | snd_soc_component_write(component, WM8960_APOP1, |
f2644a2c MB |
973 | WM8960_POBCTRL | WM8960_SOFT_ST | |
974 | WM8960_BUFDCOPEN | WM8960_BUFIOEN); | |
975 | ||
976 | /* Disable VMID and VREF, let them discharge */ | |
e075fc17 | 977 | snd_soc_component_write(component, WM8960_POWER1, 0); |
f2644a2c | 978 | msleep(600); |
913d7b4c MB |
979 | break; |
980 | } | |
981 | ||
913d7b4c MB |
982 | return 0; |
983 | } | |
984 | ||
e075fc17 | 985 | static int wm8960_set_bias_level_capless(struct snd_soc_component *component, |
913d7b4c MB |
986 | enum snd_soc_bias_level level) |
987 | { | |
e075fc17 | 988 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); |
6d75dfc3 | 989 | u16 pm2 = snd_soc_component_read(component, WM8960_POWER2); |
75aa8868 | 990 | int reg, ret; |
913d7b4c MB |
991 | |
992 | switch (level) { | |
993 | case SND_SOC_BIAS_ON: | |
994 | break; | |
995 | ||
996 | case SND_SOC_BIAS_PREPARE: | |
e075fc17 | 997 | switch (snd_soc_component_get_bias_level(component)) { |
913d7b4c MB |
998 | case SND_SOC_BIAS_STANDBY: |
999 | /* Enable anti pop mode */ | |
e075fc17 | 1000 | snd_soc_component_update_bits(component, WM8960_APOP1, |
913d7b4c MB |
1001 | WM8960_POBCTRL | WM8960_SOFT_ST | |
1002 | WM8960_BUFDCOPEN, | |
1003 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
1004 | WM8960_BUFDCOPEN); | |
1005 | ||
1006 | /* Enable LOUT1, ROUT1 and OUT3 if they're enabled */ | |
1007 | reg = 0; | |
1008 | if (wm8960->lout1 && wm8960->lout1->power) | |
1009 | reg |= WM8960_PWR2_LOUT1; | |
1010 | if (wm8960->rout1 && wm8960->rout1->power) | |
1011 | reg |= WM8960_PWR2_ROUT1; | |
1012 | if (wm8960->out3 && wm8960->out3->power) | |
1013 | reg |= WM8960_PWR2_OUT3; | |
e075fc17 | 1014 | snd_soc_component_update_bits(component, WM8960_POWER2, |
913d7b4c MB |
1015 | WM8960_PWR2_LOUT1 | |
1016 | WM8960_PWR2_ROUT1 | | |
1017 | WM8960_PWR2_OUT3, reg); | |
1018 | ||
1019 | /* Enable VMID at 2*50k */ | |
e075fc17 | 1020 | snd_soc_component_update_bits(component, WM8960_POWER1, |
913d7b4c MB |
1021 | WM8960_VMID_MASK, 0x80); |
1022 | ||
1023 | /* Ramp */ | |
1024 | msleep(100); | |
1025 | ||
1026 | /* Enable VREF */ | |
e075fc17 | 1027 | snd_soc_component_update_bits(component, WM8960_POWER1, |
913d7b4c MB |
1028 | WM8960_VREF, WM8960_VREF); |
1029 | ||
1030 | msleep(100); | |
75aa8868 ZW |
1031 | |
1032 | if (!IS_ERR(wm8960->mclk)) { | |
1033 | ret = clk_prepare_enable(wm8960->mclk); | |
1034 | if (ret) { | |
e075fc17 | 1035 | dev_err(component->dev, |
75aa8868 ZW |
1036 | "Failed to enable MCLK: %d\n", |
1037 | ret); | |
1038 | return ret; | |
1039 | } | |
1040 | } | |
3176bf2d | 1041 | |
e075fc17 | 1042 | ret = wm8960_configure_clocking(component); |
3176bf2d ZW |
1043 | if (ret) |
1044 | return ret; | |
1045 | ||
913d7b4c MB |
1046 | break; |
1047 | ||
1048 | case SND_SOC_BIAS_ON: | |
3176bf2d ZW |
1049 | /* |
1050 | * If it's sysclk auto mode, and the pll is enabled, | |
1051 | * disable the pll | |
1052 | */ | |
1053 | if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1)) | |
e075fc17 | 1054 | wm8960_set_pll(component, 0, 0); |
3176bf2d | 1055 | |
75aa8868 ZW |
1056 | if (!IS_ERR(wm8960->mclk)) |
1057 | clk_disable_unprepare(wm8960->mclk); | |
1058 | ||
913d7b4c | 1059 | /* Enable anti-pop mode */ |
e075fc17 | 1060 | snd_soc_component_update_bits(component, WM8960_APOP1, |
913d7b4c MB |
1061 | WM8960_POBCTRL | WM8960_SOFT_ST | |
1062 | WM8960_BUFDCOPEN, | |
1063 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
1064 | WM8960_BUFDCOPEN); | |
1065 | ||
1066 | /* Disable VMID and VREF */ | |
e075fc17 | 1067 | snd_soc_component_update_bits(component, WM8960_POWER1, |
913d7b4c MB |
1068 | WM8960_VREF | WM8960_VMID_MASK, 0); |
1069 | break; | |
1070 | ||
bc45df2d | 1071 | case SND_SOC_BIAS_OFF: |
0ebe36c6 | 1072 | regcache_sync(wm8960->regmap); |
bc45df2d | 1073 | break; |
913d7b4c MB |
1074 | default: |
1075 | break; | |
1076 | } | |
1077 | break; | |
f2644a2c | 1078 | |
913d7b4c | 1079 | case SND_SOC_BIAS_STANDBY: |
e075fc17 | 1080 | switch (snd_soc_component_get_bias_level(component)) { |
913d7b4c MB |
1081 | case SND_SOC_BIAS_PREPARE: |
1082 | /* Disable HP discharge */ | |
e075fc17 | 1083 | snd_soc_component_update_bits(component, WM8960_APOP2, |
913d7b4c MB |
1084 | WM8960_DISOP | WM8960_DRES_MASK, |
1085 | 0); | |
1086 | ||
1087 | /* Disable anti-pop features */ | |
e075fc17 | 1088 | snd_soc_component_update_bits(component, WM8960_APOP1, |
913d7b4c MB |
1089 | WM8960_POBCTRL | WM8960_SOFT_ST | |
1090 | WM8960_BUFDCOPEN, | |
1091 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
1092 | WM8960_BUFDCOPEN); | |
1093 | break; | |
1094 | ||
1095 | default: | |
1096 | break; | |
1097 | } | |
1098 | break; | |
f2644a2c | 1099 | |
913d7b4c | 1100 | case SND_SOC_BIAS_OFF: |
f2644a2c MB |
1101 | break; |
1102 | } | |
1103 | ||
f2644a2c MB |
1104 | return 0; |
1105 | } | |
1106 | ||
1107 | /* PLL divisors */ | |
1108 | struct _pll_div { | |
1109 | u32 pre_div:1; | |
1110 | u32 n:4; | |
1111 | u32 k:24; | |
1112 | }; | |
1113 | ||
3176bf2d ZW |
1114 | static bool is_pll_freq_available(unsigned int source, unsigned int target) |
1115 | { | |
1116 | unsigned int Ndiv; | |
1117 | ||
1118 | if (source == 0 || target == 0) | |
1119 | return false; | |
1120 | ||
1121 | /* Scale up target to PLL operating frequency */ | |
1122 | target *= 4; | |
1123 | Ndiv = target / source; | |
1124 | ||
1125 | if (Ndiv < 6) { | |
1126 | source >>= 1; | |
1127 | Ndiv = target / source; | |
1128 | } | |
1129 | ||
1130 | if ((Ndiv < 6) || (Ndiv > 12)) | |
1131 | return false; | |
1132 | ||
1133 | return true; | |
1134 | } | |
1135 | ||
f2644a2c MB |
1136 | /* The size in bits of the pll divide multiplied by 10 |
1137 | * to allow rounding later */ | |
1138 | #define FIXED_PLL_SIZE ((1 << 24) * 10) | |
1139 | ||
1140 | static int pll_factors(unsigned int source, unsigned int target, | |
1141 | struct _pll_div *pll_div) | |
1142 | { | |
1143 | unsigned long long Kpart; | |
1144 | unsigned int K, Ndiv, Nmod; | |
1145 | ||
1146 | pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target); | |
1147 | ||
1148 | /* Scale up target to PLL operating frequency */ | |
1149 | target *= 4; | |
1150 | ||
1151 | Ndiv = target / source; | |
1152 | if (Ndiv < 6) { | |
1153 | source >>= 1; | |
1154 | pll_div->pre_div = 1; | |
1155 | Ndiv = target / source; | |
1156 | } else | |
1157 | pll_div->pre_div = 0; | |
1158 | ||
1159 | if ((Ndiv < 6) || (Ndiv > 12)) { | |
1160 | pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv); | |
1161 | return -EINVAL; | |
1162 | } | |
1163 | ||
1164 | pll_div->n = Ndiv; | |
1165 | Nmod = target % source; | |
1166 | Kpart = FIXED_PLL_SIZE * (long long)Nmod; | |
1167 | ||
1168 | do_div(Kpart, source); | |
1169 | ||
1170 | K = Kpart & 0xFFFFFFFF; | |
1171 | ||
1172 | /* Check if we need to round */ | |
1173 | if ((K % 10) >= 5) | |
1174 | K += 5; | |
1175 | ||
1176 | /* Move down to proper range now rounding is done */ | |
1177 | K /= 10; | |
1178 | ||
1179 | pll_div->k = K; | |
1180 | ||
1181 | pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n", | |
1182 | pll_div->n, pll_div->k, pll_div->pre_div); | |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
e075fc17 | 1187 | static int wm8960_set_pll(struct snd_soc_component *component, |
3176bf2d | 1188 | unsigned int freq_in, unsigned int freq_out) |
f2644a2c | 1189 | { |
f2644a2c MB |
1190 | u16 reg; |
1191 | static struct _pll_div pll_div; | |
1192 | int ret; | |
1193 | ||
1194 | if (freq_in && freq_out) { | |
1195 | ret = pll_factors(freq_in, freq_out, &pll_div); | |
1196 | if (ret != 0) | |
1197 | return ret; | |
1198 | } | |
1199 | ||
1200 | /* Disable the PLL: even if we are changing the frequency the | |
1201 | * PLL needs to be disabled while we do so. */ | |
e075fc17 KM |
1202 | snd_soc_component_update_bits(component, WM8960_CLOCK1, 0x1, 0); |
1203 | snd_soc_component_update_bits(component, WM8960_POWER2, 0x1, 0); | |
f2644a2c MB |
1204 | |
1205 | if (!freq_in || !freq_out) | |
1206 | return 0; | |
1207 | ||
6d75dfc3 | 1208 | reg = snd_soc_component_read(component, WM8960_PLL1) & ~0x3f; |
f2644a2c MB |
1209 | reg |= pll_div.pre_div << 4; |
1210 | reg |= pll_div.n; | |
1211 | ||
1212 | if (pll_div.k) { | |
1213 | reg |= 0x20; | |
1214 | ||
e075fc17 KM |
1215 | snd_soc_component_write(component, WM8960_PLL2, (pll_div.k >> 16) & 0xff); |
1216 | snd_soc_component_write(component, WM8960_PLL3, (pll_div.k >> 8) & 0xff); | |
1217 | snd_soc_component_write(component, WM8960_PLL4, pll_div.k & 0xff); | |
f2644a2c | 1218 | } |
e075fc17 | 1219 | snd_soc_component_write(component, WM8960_PLL1, reg); |
f2644a2c MB |
1220 | |
1221 | /* Turn it on */ | |
e075fc17 | 1222 | snd_soc_component_update_bits(component, WM8960_POWER2, 0x1, 0x1); |
f2644a2c | 1223 | msleep(250); |
e075fc17 | 1224 | snd_soc_component_update_bits(component, WM8960_CLOCK1, 0x1, 0x1); |
f2644a2c MB |
1225 | |
1226 | return 0; | |
1227 | } | |
1228 | ||
3176bf2d ZW |
1229 | static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, |
1230 | int source, unsigned int freq_in, unsigned int freq_out) | |
1231 | { | |
e075fc17 KM |
1232 | struct snd_soc_component *component = codec_dai->component; |
1233 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); | |
3176bf2d ZW |
1234 | |
1235 | wm8960->freq_in = freq_in; | |
1236 | ||
1237 | if (pll_id == WM8960_SYSCLK_AUTO) | |
1238 | return 0; | |
1239 | ||
e075fc17 | 1240 | return wm8960_set_pll(component, freq_in, freq_out); |
3176bf2d ZW |
1241 | } |
1242 | ||
f2644a2c MB |
1243 | static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai, |
1244 | int div_id, int div) | |
1245 | { | |
e075fc17 | 1246 | struct snd_soc_component *component = codec_dai->component; |
f2644a2c MB |
1247 | u16 reg; |
1248 | ||
1249 | switch (div_id) { | |
f2644a2c | 1250 | case WM8960_SYSCLKDIV: |
6d75dfc3 | 1251 | reg = snd_soc_component_read(component, WM8960_CLOCK1) & 0x1f9; |
e075fc17 | 1252 | snd_soc_component_write(component, WM8960_CLOCK1, reg | div); |
f2644a2c MB |
1253 | break; |
1254 | case WM8960_DACDIV: | |
6d75dfc3 | 1255 | reg = snd_soc_component_read(component, WM8960_CLOCK1) & 0x1c7; |
e075fc17 | 1256 | snd_soc_component_write(component, WM8960_CLOCK1, reg | div); |
f2644a2c MB |
1257 | break; |
1258 | case WM8960_OPCLKDIV: | |
6d75dfc3 | 1259 | reg = snd_soc_component_read(component, WM8960_PLL1) & 0x03f; |
e075fc17 | 1260 | snd_soc_component_write(component, WM8960_PLL1, reg | div); |
f2644a2c MB |
1261 | break; |
1262 | case WM8960_DCLKDIV: | |
6d75dfc3 | 1263 | reg = snd_soc_component_read(component, WM8960_CLOCK2) & 0x03f; |
e075fc17 | 1264 | snd_soc_component_write(component, WM8960_CLOCK2, reg | div); |
f2644a2c MB |
1265 | break; |
1266 | case WM8960_TOCLKSEL: | |
6d75dfc3 | 1267 | reg = snd_soc_component_read(component, WM8960_ADDCTL1) & 0x1fd; |
e075fc17 | 1268 | snd_soc_component_write(component, WM8960_ADDCTL1, reg | div); |
f2644a2c MB |
1269 | break; |
1270 | default: | |
1271 | return -EINVAL; | |
1272 | } | |
1273 | ||
1274 | return 0; | |
1275 | } | |
1276 | ||
e075fc17 | 1277 | static int wm8960_set_bias_level(struct snd_soc_component *component, |
f0fba2ad LG |
1278 | enum snd_soc_bias_level level) |
1279 | { | |
e075fc17 | 1280 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); |
f0fba2ad | 1281 | |
e075fc17 | 1282 | return wm8960->set_bias_level(component, level); |
f0fba2ad LG |
1283 | } |
1284 | ||
0e50b51a ZW |
1285 | static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, |
1286 | unsigned int freq, int dir) | |
1287 | { | |
e075fc17 KM |
1288 | struct snd_soc_component *component = dai->component; |
1289 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); | |
0e50b51a ZW |
1290 | |
1291 | switch (clk_id) { | |
1292 | case WM8960_SYSCLK_MCLK: | |
e075fc17 | 1293 | snd_soc_component_update_bits(component, WM8960_CLOCK1, |
0e50b51a ZW |
1294 | 0x1, WM8960_SYSCLK_MCLK); |
1295 | break; | |
1296 | case WM8960_SYSCLK_PLL: | |
e075fc17 | 1297 | snd_soc_component_update_bits(component, WM8960_CLOCK1, |
0e50b51a ZW |
1298 | 0x1, WM8960_SYSCLK_PLL); |
1299 | break; | |
3176bf2d ZW |
1300 | case WM8960_SYSCLK_AUTO: |
1301 | break; | |
0e50b51a ZW |
1302 | default: |
1303 | return -EINVAL; | |
1304 | } | |
1305 | ||
1306 | wm8960->sysclk = freq; | |
3176bf2d | 1307 | wm8960->clk_id = clk_id; |
0e50b51a ZW |
1308 | |
1309 | return 0; | |
1310 | } | |
1311 | ||
f2644a2c MB |
1312 | #define WM8960_RATES SNDRV_PCM_RATE_8000_48000 |
1313 | ||
1314 | #define WM8960_FORMATS \ | |
1315 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
7a8c7867 | 1316 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
f2644a2c | 1317 | |
85e7652d | 1318 | static const struct snd_soc_dai_ops wm8960_dai_ops = { |
f2644a2c | 1319 | .hw_params = wm8960_hw_params, |
3176bf2d | 1320 | .hw_free = wm8960_hw_free, |
26d3c16e | 1321 | .mute_stream = wm8960_mute, |
f2644a2c MB |
1322 | .set_fmt = wm8960_set_dai_fmt, |
1323 | .set_clkdiv = wm8960_set_dai_clkdiv, | |
1324 | .set_pll = wm8960_set_dai_pll, | |
0e50b51a | 1325 | .set_sysclk = wm8960_set_dai_sysclk, |
26d3c16e | 1326 | .no_capture_mute = 1, |
f2644a2c MB |
1327 | }; |
1328 | ||
f0fba2ad LG |
1329 | static struct snd_soc_dai_driver wm8960_dai = { |
1330 | .name = "wm8960-hifi", | |
f2644a2c MB |
1331 | .playback = { |
1332 | .stream_name = "Playback", | |
1333 | .channels_min = 1, | |
1334 | .channels_max = 2, | |
1335 | .rates = WM8960_RATES, | |
1336 | .formats = WM8960_FORMATS,}, | |
1337 | .capture = { | |
1338 | .stream_name = "Capture", | |
1339 | .channels_min = 1, | |
1340 | .channels_max = 2, | |
1341 | .rates = WM8960_RATES, | |
1342 | .formats = WM8960_FORMATS,}, | |
1343 | .ops = &wm8960_dai_ops, | |
07695752 | 1344 | .symmetric_rate = 1, |
f2644a2c | 1345 | }; |
f2644a2c | 1346 | |
e075fc17 | 1347 | static int wm8960_probe(struct snd_soc_component *component) |
f2644a2c | 1348 | { |
e075fc17 | 1349 | struct wm8960_priv *wm8960 = snd_soc_component_get_drvdata(component); |
e2280c90 | 1350 | struct wm8960_data *pdata = &wm8960->pdata; |
f2644a2c | 1351 | |
e2280c90 ZW |
1352 | if (pdata->capless) |
1353 | wm8960->set_bias_level = wm8960_set_bias_level_capless; | |
1354 | else | |
1355 | wm8960->set_bias_level = wm8960_set_bias_level_out3; | |
f2644a2c | 1356 | |
e075fc17 | 1357 | snd_soc_add_component_controls(component, wm8960_snd_controls, |
f0fba2ad | 1358 | ARRAY_SIZE(wm8960_snd_controls)); |
e075fc17 | 1359 | wm8960_add_widgets(component); |
f2644a2c MB |
1360 | |
1361 | return 0; | |
1362 | } | |
1363 | ||
e075fc17 KM |
1364 | static const struct snd_soc_component_driver soc_component_dev_wm8960 = { |
1365 | .probe = wm8960_probe, | |
1366 | .set_bias_level = wm8960_set_bias_level, | |
1367 | .suspend_bias_off = 1, | |
1368 | .idle_bias_on = 1, | |
1369 | .use_pmdown_time = 1, | |
1370 | .endianness = 1, | |
1371 | .non_legacy_dai_naming = 1, | |
0ebe36c6 MB |
1372 | }; |
1373 | ||
1374 | static const struct regmap_config wm8960_regmap = { | |
1375 | .reg_bits = 7, | |
1376 | .val_bits = 9, | |
1377 | .max_register = WM8960_PLL4, | |
1378 | ||
1379 | .reg_defaults = wm8960_reg_defaults, | |
1380 | .num_reg_defaults = ARRAY_SIZE(wm8960_reg_defaults), | |
1381 | .cache_type = REGCACHE_RBTREE, | |
1382 | ||
1383 | .volatile_reg = wm8960_volatile, | |
f0fba2ad LG |
1384 | }; |
1385 | ||
e2280c90 ZW |
1386 | static void wm8960_set_pdata_from_of(struct i2c_client *i2c, |
1387 | struct wm8960_data *pdata) | |
1388 | { | |
1389 | const struct device_node *np = i2c->dev.of_node; | |
1390 | ||
1391 | if (of_property_read_bool(np, "wlf,capless")) | |
1392 | pdata->capless = true; | |
1393 | ||
1394 | if (of_property_read_bool(np, "wlf,shared-lrclk")) | |
1395 | pdata->shared_lrclk = true; | |
c9015a17 SW |
1396 | |
1397 | of_property_read_u32_array(np, "wlf,gpio-cfg", pdata->gpio_cfg, | |
1398 | ARRAY_SIZE(pdata->gpio_cfg)); | |
1399 | ||
1400 | of_property_read_u32_array(np, "wlf,hp-cfg", pdata->hp_cfg, | |
1401 | ARRAY_SIZE(pdata->hp_cfg)); | |
e2280c90 ZW |
1402 | } |
1403 | ||
7a79e94e BP |
1404 | static int wm8960_i2c_probe(struct i2c_client *i2c, |
1405 | const struct i2c_device_id *id) | |
f2644a2c | 1406 | { |
37061631 | 1407 | struct wm8960_data *pdata = dev_get_platdata(&i2c->dev); |
f2644a2c | 1408 | struct wm8960_priv *wm8960; |
f0fba2ad | 1409 | int ret; |
f2644a2c | 1410 | |
b9791c01 MB |
1411 | wm8960 = devm_kzalloc(&i2c->dev, sizeof(struct wm8960_priv), |
1412 | GFP_KERNEL); | |
f2644a2c MB |
1413 | if (wm8960 == NULL) |
1414 | return -ENOMEM; | |
1415 | ||
75aa8868 ZW |
1416 | wm8960->mclk = devm_clk_get(&i2c->dev, "mclk"); |
1417 | if (IS_ERR(wm8960->mclk)) { | |
1418 | if (PTR_ERR(wm8960->mclk) == -EPROBE_DEFER) | |
1419 | return -EPROBE_DEFER; | |
1420 | } | |
1421 | ||
c5e6f5fa | 1422 | wm8960->regmap = devm_regmap_init_i2c(i2c, &wm8960_regmap); |
0ebe36c6 MB |
1423 | if (IS_ERR(wm8960->regmap)) |
1424 | return PTR_ERR(wm8960->regmap); | |
1425 | ||
e2280c90 ZW |
1426 | if (pdata) |
1427 | memcpy(&wm8960->pdata, pdata, sizeof(struct wm8960_data)); | |
1428 | else if (i2c->dev.of_node) | |
1429 | wm8960_set_pdata_from_of(i2c, &wm8960->pdata); | |
1430 | ||
3ad5e861 ZW |
1431 | ret = wm8960_reset(wm8960->regmap); |
1432 | if (ret != 0) { | |
1433 | dev_err(&i2c->dev, "Failed to issue reset\n"); | |
1434 | return ret; | |
1435 | } | |
1436 | ||
1437 | if (wm8960->pdata.shared_lrclk) { | |
37061631 MB |
1438 | ret = regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2, |
1439 | 0x4, 0x4); | |
1440 | if (ret != 0) { | |
1441 | dev_err(&i2c->dev, "Failed to enable LRCM: %d\n", | |
1442 | ret); | |
1443 | return ret; | |
1444 | } | |
1445 | } | |
1446 | ||
3ad5e861 ZW |
1447 | /* Latch the update bits */ |
1448 | regmap_update_bits(wm8960->regmap, WM8960_LINVOL, 0x100, 0x100); | |
1449 | regmap_update_bits(wm8960->regmap, WM8960_RINVOL, 0x100, 0x100); | |
1450 | regmap_update_bits(wm8960->regmap, WM8960_LADC, 0x100, 0x100); | |
1451 | regmap_update_bits(wm8960->regmap, WM8960_RADC, 0x100, 0x100); | |
1452 | regmap_update_bits(wm8960->regmap, WM8960_LDAC, 0x100, 0x100); | |
1453 | regmap_update_bits(wm8960->regmap, WM8960_RDAC, 0x100, 0x100); | |
1454 | regmap_update_bits(wm8960->regmap, WM8960_LOUT1, 0x100, 0x100); | |
1455 | regmap_update_bits(wm8960->regmap, WM8960_ROUT1, 0x100, 0x100); | |
1456 | regmap_update_bits(wm8960->regmap, WM8960_LOUT2, 0x100, 0x100); | |
1457 | regmap_update_bits(wm8960->regmap, WM8960_ROUT2, 0x100, 0x100); | |
1458 | ||
c9015a17 SW |
1459 | /* ADCLRC pin configured as GPIO. */ |
1460 | regmap_update_bits(wm8960->regmap, WM8960_IFACE2, 1 << 6, | |
1461 | wm8960->pdata.gpio_cfg[0] << 6); | |
1462 | regmap_update_bits(wm8960->regmap, WM8960_ADDCTL4, 0xF << 4, | |
1463 | wm8960->pdata.gpio_cfg[1] << 4); | |
1464 | ||
1465 | /* Enable headphone jack detect */ | |
1466 | regmap_update_bits(wm8960->regmap, WM8960_ADDCTL4, 3 << 2, | |
1467 | wm8960->pdata.hp_cfg[0] << 2); | |
1468 | regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2, 3 << 5, | |
1469 | wm8960->pdata.hp_cfg[1] << 5); | |
1470 | regmap_update_bits(wm8960->regmap, WM8960_ADDCTL1, 3, | |
1471 | wm8960->pdata.hp_cfg[2]); | |
1472 | ||
f2644a2c | 1473 | i2c_set_clientdata(i2c, wm8960); |
f2644a2c | 1474 | |
e075fc17 KM |
1475 | ret = devm_snd_soc_register_component(&i2c->dev, |
1476 | &soc_component_dev_wm8960, &wm8960_dai, 1); | |
b9791c01 | 1477 | |
f0fba2ad | 1478 | return ret; |
f2644a2c MB |
1479 | } |
1480 | ||
7a79e94e | 1481 | static int wm8960_i2c_remove(struct i2c_client *client) |
f2644a2c | 1482 | { |
f2644a2c MB |
1483 | return 0; |
1484 | } | |
1485 | ||
1486 | static const struct i2c_device_id wm8960_i2c_id[] = { | |
1487 | { "wm8960", 0 }, | |
1488 | { } | |
1489 | }; | |
1490 | MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id); | |
1491 | ||
e2280c90 ZW |
1492 | static const struct of_device_id wm8960_of_match[] = { |
1493 | { .compatible = "wlf,wm8960", }, | |
1494 | { } | |
1495 | }; | |
1496 | MODULE_DEVICE_TABLE(of, wm8960_of_match); | |
1497 | ||
f2644a2c MB |
1498 | static struct i2c_driver wm8960_i2c_driver = { |
1499 | .driver = { | |
091edccf | 1500 | .name = "wm8960", |
e2280c90 | 1501 | .of_match_table = wm8960_of_match, |
f2644a2c MB |
1502 | }, |
1503 | .probe = wm8960_i2c_probe, | |
7a79e94e | 1504 | .remove = wm8960_i2c_remove, |
f2644a2c MB |
1505 | .id_table = wm8960_i2c_id, |
1506 | }; | |
1507 | ||
3c010e60 | 1508 | module_i2c_driver(wm8960_i2c_driver); |
f2644a2c | 1509 | |
f2644a2c MB |
1510 | MODULE_DESCRIPTION("ASoC WM8960 driver"); |
1511 | MODULE_AUTHOR("Liam Girdwood"); | |
1512 | MODULE_LICENSE("GPL"); |