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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b35a28af MB |
2 | /* |
3 | * wm8955.c -- WM8955 ALSA SoC Audio driver | |
4 | * | |
5 | * Copyright 2009 Wolfson Microelectronics plc | |
6 | * | |
7 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
b35a28af MB |
8 | */ |
9 | ||
10 | #include <linux/module.h> | |
11 | #include <linux/moduleparam.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/delay.h> | |
14 | #include <linux/pm.h> | |
15 | #include <linux/i2c.h> | |
95860fdf | 16 | #include <linux/regmap.h> |
b35a28af | 17 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
b35a28af MB |
19 | #include <sound/core.h> |
20 | #include <sound/pcm.h> | |
21 | #include <sound/pcm_params.h> | |
22 | #include <sound/soc.h> | |
b35a28af MB |
23 | #include <sound/initval.h> |
24 | #include <sound/tlv.h> | |
25 | #include <sound/wm8955.h> | |
26 | ||
27 | #include "wm8955.h" | |
28 | ||
b35a28af MB |
29 | #define WM8955_NUM_SUPPLIES 4 |
30 | static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = { | |
31 | "DCVDD", | |
32 | "DBVDD", | |
33 | "HPVDD", | |
34 | "AVDD", | |
35 | }; | |
36 | ||
37 | /* codec private data */ | |
38 | struct wm8955_priv { | |
95860fdf | 39 | struct regmap *regmap; |
f0fba2ad | 40 | |
b35a28af MB |
41 | unsigned int mclk_rate; |
42 | ||
43 | int deemph; | |
44 | int fs; | |
45 | ||
46 | struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES]; | |
b35a28af MB |
47 | }; |
48 | ||
95860fdf MB |
49 | static const struct reg_default wm8955_reg_defaults[] = { |
50 | { 2, 0x0079 }, /* R2 - LOUT1 volume */ | |
51 | { 3, 0x0079 }, /* R3 - ROUT1 volume */ | |
52 | { 5, 0x0008 }, /* R5 - DAC Control */ | |
53 | { 7, 0x000A }, /* R7 - Audio Interface */ | |
54 | { 8, 0x0000 }, /* R8 - Sample Rate */ | |
55 | { 10, 0x00FF }, /* R10 - Left DAC volume */ | |
56 | { 11, 0x00FF }, /* R11 - Right DAC volume */ | |
57 | { 12, 0x000F }, /* R12 - Bass control */ | |
58 | { 13, 0x000F }, /* R13 - Treble control */ | |
59 | { 23, 0x00C1 }, /* R23 - Additional control (1) */ | |
60 | { 24, 0x0000 }, /* R24 - Additional control (2) */ | |
61 | { 25, 0x0000 }, /* R25 - Power Management (1) */ | |
62 | { 26, 0x0000 }, /* R26 - Power Management (2) */ | |
63 | { 27, 0x0000 }, /* R27 - Additional Control (3) */ | |
64 | { 34, 0x0050 }, /* R34 - Left out Mix (1) */ | |
65 | { 35, 0x0050 }, /* R35 - Left out Mix (2) */ | |
66 | { 36, 0x0050 }, /* R36 - Right out Mix (1) */ | |
67 | { 37, 0x0050 }, /* R37 - Right Out Mix (2) */ | |
68 | { 38, 0x0050 }, /* R38 - Mono out Mix (1) */ | |
69 | { 39, 0x0050 }, /* R39 - Mono out Mix (2) */ | |
70 | { 40, 0x0079 }, /* R40 - LOUT2 volume */ | |
71 | { 41, 0x0079 }, /* R41 - ROUT2 volume */ | |
72 | { 42, 0x0079 }, /* R42 - MONOOUT volume */ | |
73 | { 43, 0x0000 }, /* R43 - Clocking / PLL */ | |
74 | { 44, 0x0103 }, /* R44 - PLL Control 1 */ | |
75 | { 45, 0x0024 }, /* R45 - PLL Control 2 */ | |
76 | { 46, 0x01BA }, /* R46 - PLL Control 3 */ | |
77 | { 59, 0x0000 }, /* R59 - PLL Control 4 */ | |
b35a28af MB |
78 | }; |
79 | ||
95860fdf MB |
80 | static bool wm8955_writeable(struct device *dev, unsigned int reg) |
81 | { | |
82 | switch (reg) { | |
83 | case WM8955_LOUT1_VOLUME: | |
84 | case WM8955_ROUT1_VOLUME: | |
85 | case WM8955_DAC_CONTROL: | |
86 | case WM8955_AUDIO_INTERFACE: | |
87 | case WM8955_SAMPLE_RATE: | |
88 | case WM8955_LEFT_DAC_VOLUME: | |
89 | case WM8955_RIGHT_DAC_VOLUME: | |
90 | case WM8955_BASS_CONTROL: | |
91 | case WM8955_TREBLE_CONTROL: | |
92 | case WM8955_RESET: | |
93 | case WM8955_ADDITIONAL_CONTROL_1: | |
94 | case WM8955_ADDITIONAL_CONTROL_2: | |
95 | case WM8955_POWER_MANAGEMENT_1: | |
96 | case WM8955_POWER_MANAGEMENT_2: | |
97 | case WM8955_ADDITIONAL_CONTROL_3: | |
98 | case WM8955_LEFT_OUT_MIX_1: | |
99 | case WM8955_LEFT_OUT_MIX_2: | |
100 | case WM8955_RIGHT_OUT_MIX_1: | |
101 | case WM8955_RIGHT_OUT_MIX_2: | |
102 | case WM8955_MONO_OUT_MIX_1: | |
103 | case WM8955_MONO_OUT_MIX_2: | |
104 | case WM8955_LOUT2_VOLUME: | |
105 | case WM8955_ROUT2_VOLUME: | |
106 | case WM8955_MONOOUT_VOLUME: | |
107 | case WM8955_CLOCKING_PLL: | |
108 | case WM8955_PLL_CONTROL_1: | |
109 | case WM8955_PLL_CONTROL_2: | |
110 | case WM8955_PLL_CONTROL_3: | |
111 | case WM8955_PLL_CONTROL_4: | |
112 | return true; | |
113 | default: | |
114 | return false; | |
115 | } | |
116 | } | |
117 | ||
118 | static bool wm8955_volatile(struct device *dev, unsigned int reg) | |
119 | { | |
120 | switch (reg) { | |
121 | case WM8955_RESET: | |
122 | return true; | |
123 | default: | |
124 | return false; | |
125 | } | |
126 | } | |
127 | ||
69b626e6 | 128 | static int wm8955_reset(struct snd_soc_component *component) |
b35a28af | 129 | { |
69b626e6 | 130 | return snd_soc_component_write(component, WM8955_RESET, 0); |
b35a28af MB |
131 | } |
132 | ||
133 | struct pll_factors { | |
134 | int n; | |
135 | int k; | |
136 | int outdiv; | |
137 | }; | |
138 | ||
139 | /* The size in bits of the FLL divide multiplied by 10 | |
140 | * to allow rounding later */ | |
141 | #define FIXED_FLL_SIZE ((1 << 22) * 10) | |
142 | ||
e8758a5e | 143 | static int wm8955_pll_factors(struct device *dev, |
b35a28af MB |
144 | int Fref, int Fout, struct pll_factors *pll) |
145 | { | |
146 | u64 Kpart; | |
147 | unsigned int K, Ndiv, Nmod, target; | |
148 | ||
149 | dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout); | |
150 | ||
151 | /* The oscilator should run at should be 90-100MHz, and | |
152 | * there's a divide by 4 plus an optional divide by 2 in the | |
153 | * output path to generate the system clock. The clock table | |
154 | * is sortd so we should always generate a suitable target. */ | |
155 | target = Fout * 4; | |
156 | if (target < 90000000) { | |
157 | pll->outdiv = 1; | |
158 | target *= 2; | |
159 | } else { | |
160 | pll->outdiv = 0; | |
161 | } | |
162 | ||
163 | WARN_ON(target < 90000000 || target > 100000000); | |
164 | ||
165 | dev_dbg(dev, "Fvco=%dHz\n", target); | |
166 | ||
167 | /* Now, calculate N.K */ | |
168 | Ndiv = target / Fref; | |
169 | ||
170 | pll->n = Ndiv; | |
171 | Nmod = target % Fref; | |
172 | dev_dbg(dev, "Nmod=%d\n", Nmod); | |
173 | ||
174 | /* Calculate fractional part - scale up so we can round. */ | |
175 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
176 | ||
177 | do_div(Kpart, Fref); | |
178 | ||
179 | K = Kpart & 0xFFFFFFFF; | |
180 | ||
181 | if ((K % 10) >= 5) | |
182 | K += 5; | |
183 | ||
184 | /* Move down to proper range now rounding is done */ | |
185 | pll->k = K / 10; | |
186 | ||
187 | dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv); | |
188 | ||
189 | return 0; | |
190 | } | |
191 | ||
25985edc | 192 | /* Lookup table specifying SRATE (table 25 in datasheet); some of the |
b35a28af MB |
193 | * output frequencies have been rounded to the standard frequencies |
194 | * they are intended to match where the error is slight. */ | |
195 | static struct { | |
196 | int mclk; | |
197 | int fs; | |
198 | int usb; | |
199 | int sr; | |
200 | } clock_cfgs[] = { | |
201 | { 18432000, 8000, 0, 3, }, | |
202 | { 18432000, 12000, 0, 9, }, | |
203 | { 18432000, 16000, 0, 11, }, | |
204 | { 18432000, 24000, 0, 29, }, | |
205 | { 18432000, 32000, 0, 13, }, | |
206 | { 18432000, 48000, 0, 1, }, | |
207 | { 18432000, 96000, 0, 15, }, | |
208 | ||
209 | { 16934400, 8018, 0, 19, }, | |
210 | { 16934400, 11025, 0, 25, }, | |
211 | { 16934400, 22050, 0, 27, }, | |
212 | { 16934400, 44100, 0, 17, }, | |
213 | { 16934400, 88200, 0, 31, }, | |
214 | ||
215 | { 12000000, 8000, 1, 2, }, | |
216 | { 12000000, 11025, 1, 25, }, | |
217 | { 12000000, 12000, 1, 8, }, | |
218 | { 12000000, 16000, 1, 10, }, | |
219 | { 12000000, 22050, 1, 27, }, | |
220 | { 12000000, 24000, 1, 28, }, | |
221 | { 12000000, 32000, 1, 12, }, | |
222 | { 12000000, 44100, 1, 17, }, | |
223 | { 12000000, 48000, 1, 0, }, | |
224 | { 12000000, 88200, 1, 31, }, | |
225 | { 12000000, 96000, 1, 14, }, | |
226 | ||
227 | { 12288000, 8000, 0, 2, }, | |
228 | { 12288000, 12000, 0, 8, }, | |
229 | { 12288000, 16000, 0, 10, }, | |
230 | { 12288000, 24000, 0, 28, }, | |
231 | { 12288000, 32000, 0, 12, }, | |
232 | { 12288000, 48000, 0, 0, }, | |
233 | { 12288000, 96000, 0, 14, }, | |
234 | ||
235 | { 12289600, 8018, 0, 18, }, | |
236 | { 12289600, 11025, 0, 24, }, | |
237 | { 12289600, 22050, 0, 26, }, | |
238 | { 11289600, 44100, 0, 16, }, | |
239 | { 11289600, 88200, 0, 31, }, | |
240 | }; | |
241 | ||
69b626e6 | 242 | static int wm8955_configure_clocking(struct snd_soc_component *component) |
b35a28af | 243 | { |
69b626e6 | 244 | struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); |
b35a28af MB |
245 | int i, ret, val; |
246 | int clocking = 0; | |
247 | int srate = 0; | |
248 | int sr = -1; | |
249 | struct pll_factors pll; | |
250 | ||
251 | /* If we're not running a sample rate currently just pick one */ | |
252 | if (wm8955->fs == 0) | |
253 | wm8955->fs = 8000; | |
254 | ||
255 | /* Can we generate an exact output? */ | |
256 | for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) { | |
257 | if (wm8955->fs != clock_cfgs[i].fs) | |
258 | continue; | |
259 | sr = i; | |
260 | ||
261 | if (wm8955->mclk_rate == clock_cfgs[i].mclk) | |
262 | break; | |
263 | } | |
264 | ||
265 | /* We should never get here with an unsupported sample rate */ | |
266 | if (sr == -1) { | |
69b626e6 | 267 | dev_err(component->dev, "Sample rate %dHz unsupported\n", |
b35a28af MB |
268 | wm8955->fs); |
269 | WARN_ON(sr == -1); | |
270 | return -EINVAL; | |
271 | } | |
272 | ||
273 | if (i == ARRAY_SIZE(clock_cfgs)) { | |
274 | /* If we can't generate the right clock from MCLK then | |
275 | * we should configure the PLL to supply us with an | |
276 | * appropriate clock. | |
277 | */ | |
278 | clocking |= WM8955_MCLKSEL; | |
279 | ||
280 | /* Use the last divider configuration we saw for the | |
281 | * sample rate. */ | |
e8758a5e | 282 | ret = wm8955_pll_factors(component->dev, wm8955->mclk_rate, |
b35a28af MB |
283 | clock_cfgs[sr].mclk, &pll); |
284 | if (ret != 0) { | |
69b626e6 | 285 | dev_err(component->dev, |
b35a28af MB |
286 | "Unable to generate %dHz from %dHz MCLK\n", |
287 | wm8955->fs, wm8955->mclk_rate); | |
288 | return -EINVAL; | |
289 | } | |
290 | ||
69b626e6 | 291 | snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_1, |
b35a28af MB |
292 | WM8955_N_MASK | WM8955_K_21_18_MASK, |
293 | (pll.n << WM8955_N_SHIFT) | | |
294 | pll.k >> 18); | |
69b626e6 | 295 | snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_2, |
b35a28af MB |
296 | WM8955_K_17_9_MASK, |
297 | (pll.k >> 9) & WM8955_K_17_9_MASK); | |
69b626e6 | 298 | snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_3, |
b35a28af MB |
299 | WM8955_K_8_0_MASK, |
300 | pll.k & WM8955_K_8_0_MASK); | |
301 | if (pll.k) | |
69b626e6 | 302 | snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_4, |
b35a28af MB |
303 | WM8955_KEN, WM8955_KEN); |
304 | else | |
69b626e6 | 305 | snd_soc_component_update_bits(component, WM8955_PLL_CONTROL_4, |
b35a28af MB |
306 | WM8955_KEN, 0); |
307 | ||
308 | if (pll.outdiv) | |
309 | val = WM8955_PLL_RB | WM8955_PLLOUTDIV2; | |
310 | else | |
311 | val = WM8955_PLL_RB; | |
312 | ||
313 | /* Now start the PLL running */ | |
69b626e6 | 314 | snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL, |
b35a28af | 315 | WM8955_PLL_RB | WM8955_PLLOUTDIV2, val); |
69b626e6 | 316 | snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL, |
b35a28af MB |
317 | WM8955_PLLEN, WM8955_PLLEN); |
318 | } | |
319 | ||
320 | srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT); | |
321 | ||
69b626e6 | 322 | snd_soc_component_update_bits(component, WM8955_SAMPLE_RATE, |
b35a28af | 323 | WM8955_USB | WM8955_SR_MASK, srate); |
69b626e6 | 324 | snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL, |
b35a28af MB |
325 | WM8955_MCLKSEL, clocking); |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
330 | static int wm8955_sysclk(struct snd_soc_dapm_widget *w, | |
331 | struct snd_kcontrol *kcontrol, int event) | |
332 | { | |
69b626e6 | 333 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
b35a28af MB |
334 | int ret = 0; |
335 | ||
336 | /* Always disable the clocks - if we're doing reconfiguration this | |
337 | * avoids misclocking. | |
338 | */ | |
69b626e6 | 339 | snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1, |
b35a28af | 340 | WM8955_DIGENB, 0); |
69b626e6 | 341 | snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL, |
b35a28af MB |
342 | WM8955_PLL_RB | WM8955_PLLEN, 0); |
343 | ||
344 | switch (event) { | |
345 | case SND_SOC_DAPM_POST_PMD: | |
346 | break; | |
347 | case SND_SOC_DAPM_PRE_PMU: | |
69b626e6 | 348 | ret = wm8955_configure_clocking(component); |
b35a28af MB |
349 | break; |
350 | default: | |
351 | ret = -EINVAL; | |
352 | break; | |
353 | } | |
354 | ||
355 | return ret; | |
356 | } | |
357 | ||
358 | static int deemph_settings[] = { 0, 32000, 44100, 48000 }; | |
359 | ||
69b626e6 | 360 | static int wm8955_set_deemph(struct snd_soc_component *component) |
b35a28af | 361 | { |
69b626e6 | 362 | struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); |
b35a28af MB |
363 | int val, i, best; |
364 | ||
365 | /* If we're using deemphasis select the nearest available sample | |
366 | * rate. | |
367 | */ | |
368 | if (wm8955->deemph) { | |
369 | best = 1; | |
370 | for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { | |
371 | if (abs(deemph_settings[i] - wm8955->fs) < | |
372 | abs(deemph_settings[best] - wm8955->fs)) | |
373 | best = i; | |
374 | } | |
375 | ||
376 | val = best << WM8955_DEEMPH_SHIFT; | |
377 | } else { | |
378 | val = 0; | |
379 | } | |
380 | ||
69b626e6 | 381 | dev_dbg(component->dev, "Set deemphasis %d\n", val); |
b35a28af | 382 | |
69b626e6 | 383 | return snd_soc_component_update_bits(component, WM8955_DAC_CONTROL, |
b35a28af MB |
384 | WM8955_DEEMPH_MASK, val); |
385 | } | |
386 | ||
387 | static int wm8955_get_deemph(struct snd_kcontrol *kcontrol, | |
388 | struct snd_ctl_elem_value *ucontrol) | |
389 | { | |
69b626e6 KM |
390 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
391 | struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); | |
b35a28af | 392 | |
07892b10 | 393 | ucontrol->value.integer.value[0] = wm8955->deemph; |
3f343f85 | 394 | return 0; |
b35a28af MB |
395 | } |
396 | ||
397 | static int wm8955_put_deemph(struct snd_kcontrol *kcontrol, | |
398 | struct snd_ctl_elem_value *ucontrol) | |
399 | { | |
69b626e6 KM |
400 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
401 | struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); | |
3e2a71b2 | 402 | unsigned int deemph = ucontrol->value.integer.value[0]; |
b35a28af MB |
403 | |
404 | if (deemph > 1) | |
405 | return -EINVAL; | |
406 | ||
407 | wm8955->deemph = deemph; | |
408 | ||
69b626e6 | 409 | return wm8955_set_deemph(component); |
b35a28af MB |
410 | } |
411 | ||
412 | static const char *bass_mode_text[] = { | |
413 | "Linear", "Adaptive", | |
414 | }; | |
415 | ||
54db41c1 | 416 | static SOC_ENUM_SINGLE_DECL(bass_mode, WM8955_BASS_CONTROL, 7, bass_mode_text); |
b35a28af MB |
417 | |
418 | static const char *bass_cutoff_text[] = { | |
419 | "Low", "High" | |
420 | }; | |
421 | ||
54db41c1 TI |
422 | static SOC_ENUM_SINGLE_DECL(bass_cutoff, WM8955_BASS_CONTROL, 6, |
423 | bass_cutoff_text); | |
b35a28af MB |
424 | |
425 | static const char *treble_cutoff_text[] = { | |
426 | "High", "Low" | |
427 | }; | |
428 | ||
54db41c1 TI |
429 | static SOC_ENUM_SINGLE_DECL(treble_cutoff, WM8955_TREBLE_CONTROL, 2, |
430 | treble_cutoff_text); | |
b35a28af MB |
431 | |
432 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); | |
433 | static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0); | |
434 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); | |
435 | static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0); | |
436 | static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); | |
437 | static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1); | |
438 | ||
439 | static const struct snd_kcontrol_new wm8955_snd_controls[] = { | |
440 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME, | |
441 | WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv), | |
442 | SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1, | |
443 | atten_tlv), | |
444 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, | |
445 | wm8955_get_deemph, wm8955_put_deemph), | |
446 | ||
447 | SOC_ENUM("Bass Mode", bass_mode), | |
448 | SOC_ENUM("Bass Cutoff", bass_cutoff), | |
449 | SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1), | |
450 | ||
451 | SOC_ENUM("Treble Cutoff", treble_cutoff), | |
452 | SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv), | |
453 | ||
454 | SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1, | |
455 | bypass_tlv), | |
456 | SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1, | |
457 | bypass_tlv), | |
458 | ||
459 | SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1, | |
460 | bypass_tlv), | |
461 | SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1, | |
462 | bypass_tlv), | |
463 | ||
464 | /* Not a stereo pair so they line up with the DAPM switches */ | |
465 | SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1, | |
466 | mono_tlv), | |
467 | SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1, | |
468 | mono_tlv), | |
469 | ||
470 | SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME, | |
471 | WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv), | |
472 | SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME, | |
473 | WM8955_ROUT1_VOLUME, 7, 1, 0), | |
474 | ||
475 | SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME, | |
476 | WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv), | |
477 | SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME, | |
478 | WM8955_ROUT2_VOLUME, 7, 1, 0), | |
479 | ||
480 | SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv), | |
481 | SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0), | |
482 | }; | |
483 | ||
484 | static const struct snd_kcontrol_new lmixer[] = { | |
485 | SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0), | |
486 | SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0), | |
487 | SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0), | |
488 | SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0), | |
489 | }; | |
490 | ||
491 | static const struct snd_kcontrol_new rmixer[] = { | |
492 | SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0), | |
493 | SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0), | |
494 | SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0), | |
495 | SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0), | |
496 | }; | |
497 | ||
498 | static const struct snd_kcontrol_new mmixer[] = { | |
499 | SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0), | |
500 | SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0), | |
501 | SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0), | |
502 | SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0), | |
503 | }; | |
504 | ||
505 | static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = { | |
506 | SND_SOC_DAPM_INPUT("MONOIN-"), | |
507 | SND_SOC_DAPM_INPUT("MONOIN+"), | |
508 | SND_SOC_DAPM_INPUT("LINEINR"), | |
509 | SND_SOC_DAPM_INPUT("LINEINL"), | |
510 | ||
511 | SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0), | |
512 | ||
513 | SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk, | |
514 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
515 | SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0), | |
516 | ||
517 | SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0), | |
518 | SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0), | |
519 | ||
520 | SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0), | |
521 | SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0), | |
522 | SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0), | |
523 | SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0), | |
524 | SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0), | |
525 | SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0), | |
526 | ||
527 | /* The names are chosen to make the control names nice */ | |
528 | SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0, | |
529 | lmixer, ARRAY_SIZE(lmixer)), | |
530 | SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0, | |
531 | rmixer, ARRAY_SIZE(rmixer)), | |
532 | SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0, | |
533 | mmixer, ARRAY_SIZE(mmixer)), | |
534 | ||
535 | SND_SOC_DAPM_OUTPUT("LOUT1"), | |
536 | SND_SOC_DAPM_OUTPUT("ROUT1"), | |
537 | SND_SOC_DAPM_OUTPUT("LOUT2"), | |
538 | SND_SOC_DAPM_OUTPUT("ROUT2"), | |
539 | SND_SOC_DAPM_OUTPUT("MONOOUT"), | |
540 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
541 | }; | |
542 | ||
3294c4c6 | 543 | static const struct snd_soc_dapm_route wm8955_dapm_routes[] = { |
b35a28af MB |
544 | { "DACL", NULL, "SYSCLK" }, |
545 | { "DACR", NULL, "SYSCLK" }, | |
546 | ||
547 | { "Mono Input", NULL, "MONOIN-" }, | |
548 | { "Mono Input", NULL, "MONOIN+" }, | |
549 | ||
550 | { "Left", "Playback Switch", "DACL" }, | |
551 | { "Left", "Right Playback Switch", "DACR" }, | |
552 | { "Left", "Bypass Switch", "LINEINL" }, | |
553 | { "Left", "Mono Switch", "Mono Input" }, | |
554 | ||
555 | { "Right", "Playback Switch", "DACR" }, | |
556 | { "Right", "Left Playback Switch", "DACL" }, | |
557 | { "Right", "Bypass Switch", "LINEINR" }, | |
558 | { "Right", "Mono Switch", "Mono Input" }, | |
559 | ||
560 | { "Mono", "Left Playback Switch", "DACL" }, | |
561 | { "Mono", "Right Playback Switch", "DACR" }, | |
562 | { "Mono", "Left Bypass Switch", "LINEINL" }, | |
563 | { "Mono", "Right Bypass Switch", "LINEINR" }, | |
564 | ||
565 | { "LOUT1 PGA", NULL, "Left" }, | |
566 | { "LOUT1", NULL, "TSDEN" }, | |
567 | { "LOUT1", NULL, "LOUT1 PGA" }, | |
568 | ||
569 | { "ROUT1 PGA", NULL, "Right" }, | |
570 | { "ROUT1", NULL, "TSDEN" }, | |
571 | { "ROUT1", NULL, "ROUT1 PGA" }, | |
572 | ||
573 | { "LOUT2 PGA", NULL, "Left" }, | |
574 | { "LOUT2", NULL, "TSDEN" }, | |
575 | { "LOUT2", NULL, "LOUT2 PGA" }, | |
576 | ||
577 | { "ROUT2 PGA", NULL, "Right" }, | |
578 | { "ROUT2", NULL, "TSDEN" }, | |
579 | { "ROUT2", NULL, "ROUT2 PGA" }, | |
580 | ||
581 | { "MOUT PGA", NULL, "Mono" }, | |
582 | { "MONOOUT", NULL, "MOUT PGA" }, | |
583 | ||
584 | /* OUT3 not currently implemented */ | |
585 | { "OUT3", NULL, "OUT3 PGA" }, | |
586 | }; | |
587 | ||
b35a28af MB |
588 | static int wm8955_hw_params(struct snd_pcm_substream *substream, |
589 | struct snd_pcm_hw_params *params, | |
590 | struct snd_soc_dai *dai) | |
591 | { | |
69b626e6 KM |
592 | struct snd_soc_component *component = dai->component; |
593 | struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); | |
b35a28af MB |
594 | int ret; |
595 | int wl; | |
596 | ||
1df93ca3 MB |
597 | switch (params_width(params)) { |
598 | case 16: | |
b35a28af MB |
599 | wl = 0; |
600 | break; | |
1df93ca3 | 601 | case 20: |
b35a28af MB |
602 | wl = 0x4; |
603 | break; | |
1df93ca3 | 604 | case 24: |
b35a28af MB |
605 | wl = 0x8; |
606 | break; | |
1df93ca3 | 607 | case 32: |
b35a28af MB |
608 | wl = 0xc; |
609 | break; | |
610 | default: | |
611 | return -EINVAL; | |
612 | } | |
69b626e6 | 613 | snd_soc_component_update_bits(component, WM8955_AUDIO_INTERFACE, |
b35a28af MB |
614 | WM8955_WL_MASK, wl); |
615 | ||
616 | wm8955->fs = params_rate(params); | |
69b626e6 | 617 | wm8955_set_deemph(component); |
b35a28af MB |
618 | |
619 | /* If the chip is clocked then disable the clocks and force a | |
620 | * reconfiguration, otherwise DAPM will power up the | |
621 | * clocks for us later. */ | |
6d75dfc3 | 622 | ret = snd_soc_component_read(component, WM8955_POWER_MANAGEMENT_1); |
b35a28af MB |
623 | if (ret < 0) |
624 | return ret; | |
625 | if (ret & WM8955_DIGENB) { | |
69b626e6 | 626 | snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1, |
b35a28af | 627 | WM8955_DIGENB, 0); |
69b626e6 | 628 | snd_soc_component_update_bits(component, WM8955_CLOCKING_PLL, |
b35a28af MB |
629 | WM8955_PLL_RB | WM8955_PLLEN, 0); |
630 | ||
69b626e6 | 631 | wm8955_configure_clocking(component); |
b35a28af MB |
632 | } |
633 | ||
634 | return 0; | |
635 | } | |
636 | ||
637 | ||
638 | static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id, | |
639 | unsigned int freq, int dir) | |
640 | { | |
69b626e6 KM |
641 | struct snd_soc_component *component = dai->component; |
642 | struct wm8955_priv *priv = snd_soc_component_get_drvdata(component); | |
b35a28af MB |
643 | int div; |
644 | ||
645 | switch (clk_id) { | |
646 | case WM8955_CLK_MCLK: | |
647 | if (freq > 15000000) { | |
648 | priv->mclk_rate = freq /= 2; | |
649 | div = WM8955_MCLKDIV2; | |
650 | } else { | |
651 | priv->mclk_rate = freq; | |
652 | div = 0; | |
653 | } | |
654 | ||
69b626e6 | 655 | snd_soc_component_update_bits(component, WM8955_SAMPLE_RATE, |
b35a28af MB |
656 | WM8955_MCLKDIV2, div); |
657 | break; | |
658 | ||
659 | default: | |
660 | return -EINVAL; | |
661 | } | |
662 | ||
663 | dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
668 | static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
669 | { | |
69b626e6 | 670 | struct snd_soc_component *component = dai->component; |
b35a28af MB |
671 | u16 aif = 0; |
672 | ||
673 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
674 | case SND_SOC_DAIFMT_CBS_CFS: | |
675 | break; | |
676 | case SND_SOC_DAIFMT_CBM_CFM: | |
677 | aif |= WM8955_MS; | |
678 | break; | |
679 | default: | |
680 | return -EINVAL; | |
681 | } | |
682 | ||
683 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
684 | case SND_SOC_DAIFMT_DSP_B: | |
685 | aif |= WM8955_LRP; | |
3e146b55 | 686 | fallthrough; |
b35a28af MB |
687 | case SND_SOC_DAIFMT_DSP_A: |
688 | aif |= 0x3; | |
689 | break; | |
690 | case SND_SOC_DAIFMT_I2S: | |
691 | aif |= 0x2; | |
692 | break; | |
693 | case SND_SOC_DAIFMT_RIGHT_J: | |
694 | break; | |
695 | case SND_SOC_DAIFMT_LEFT_J: | |
696 | aif |= 0x1; | |
697 | break; | |
698 | default: | |
699 | return -EINVAL; | |
700 | } | |
701 | ||
702 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
703 | case SND_SOC_DAIFMT_DSP_A: | |
704 | case SND_SOC_DAIFMT_DSP_B: | |
705 | /* frame inversion not valid for DSP modes */ | |
706 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
707 | case SND_SOC_DAIFMT_NB_NF: | |
708 | break; | |
709 | case SND_SOC_DAIFMT_IB_NF: | |
710 | aif |= WM8955_BCLKINV; | |
711 | break; | |
712 | default: | |
713 | return -EINVAL; | |
714 | } | |
715 | break; | |
716 | ||
717 | case SND_SOC_DAIFMT_I2S: | |
718 | case SND_SOC_DAIFMT_RIGHT_J: | |
719 | case SND_SOC_DAIFMT_LEFT_J: | |
720 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
721 | case SND_SOC_DAIFMT_NB_NF: | |
722 | break; | |
723 | case SND_SOC_DAIFMT_IB_IF: | |
724 | aif |= WM8955_BCLKINV | WM8955_LRP; | |
725 | break; | |
726 | case SND_SOC_DAIFMT_IB_NF: | |
727 | aif |= WM8955_BCLKINV; | |
728 | break; | |
729 | case SND_SOC_DAIFMT_NB_IF: | |
730 | aif |= WM8955_LRP; | |
731 | break; | |
732 | default: | |
733 | return -EINVAL; | |
734 | } | |
735 | break; | |
736 | default: | |
737 | return -EINVAL; | |
738 | } | |
739 | ||
69b626e6 | 740 | snd_soc_component_update_bits(component, WM8955_AUDIO_INTERFACE, |
b35a28af MB |
741 | WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV | |
742 | WM8955_LRP, aif); | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
747 | ||
26d3c16e | 748 | static int wm8955_mute(struct snd_soc_dai *codec_dai, int mute, int direction) |
b35a28af | 749 | { |
69b626e6 | 750 | struct snd_soc_component *component = codec_dai->component; |
b35a28af MB |
751 | int val; |
752 | ||
753 | if (mute) | |
754 | val = WM8955_DACMU; | |
755 | else | |
756 | val = 0; | |
757 | ||
69b626e6 | 758 | snd_soc_component_update_bits(component, WM8955_DAC_CONTROL, WM8955_DACMU, val); |
b35a28af MB |
759 | |
760 | return 0; | |
761 | } | |
762 | ||
69b626e6 | 763 | static int wm8955_set_bias_level(struct snd_soc_component *component, |
b35a28af MB |
764 | enum snd_soc_bias_level level) |
765 | { | |
69b626e6 | 766 | struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); |
95860fdf | 767 | int ret; |
b35a28af MB |
768 | |
769 | switch (level) { | |
770 | case SND_SOC_BIAS_ON: | |
771 | break; | |
772 | ||
773 | case SND_SOC_BIAS_PREPARE: | |
774 | /* VMID resistance 2*50k */ | |
69b626e6 | 775 | snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1, |
b35a28af MB |
776 | WM8955_VMIDSEL_MASK, |
777 | 0x1 << WM8955_VMIDSEL_SHIFT); | |
778 | ||
779 | /* Default bias current */ | |
69b626e6 | 780 | snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_1, |
b35a28af MB |
781 | WM8955_VSEL_MASK, |
782 | 0x2 << WM8955_VSEL_SHIFT); | |
783 | break; | |
784 | ||
785 | case SND_SOC_BIAS_STANDBY: | |
69b626e6 | 786 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
b35a28af MB |
787 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies), |
788 | wm8955->supplies); | |
789 | if (ret != 0) { | |
69b626e6 | 790 | dev_err(component->dev, |
b35a28af MB |
791 | "Failed to enable supplies: %d\n", |
792 | ret); | |
793 | return ret; | |
794 | } | |
795 | ||
95860fdf | 796 | regcache_sync(wm8955->regmap); |
b35a28af MB |
797 | |
798 | /* Enable VREF and VMID */ | |
69b626e6 | 799 | snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1, |
b35a28af MB |
800 | WM8955_VREF | |
801 | WM8955_VMIDSEL_MASK, | |
802 | WM8955_VREF | | |
803 | 0x3 << WM8955_VREF_SHIFT); | |
804 | ||
805 | /* Let VMID ramp */ | |
806 | msleep(500); | |
807 | ||
808 | /* High resistance VROI to maintain outputs */ | |
69b626e6 | 809 | snd_soc_component_update_bits(component, |
b35a28af MB |
810 | WM8955_ADDITIONAL_CONTROL_3, |
811 | WM8955_VROI, WM8955_VROI); | |
812 | } | |
813 | ||
814 | /* Maintain VMID with 2*250k */ | |
69b626e6 | 815 | snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1, |
b35a28af MB |
816 | WM8955_VMIDSEL_MASK, |
817 | 0x2 << WM8955_VMIDSEL_SHIFT); | |
818 | ||
819 | /* Minimum bias current */ | |
69b626e6 | 820 | snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_1, |
b35a28af MB |
821 | WM8955_VSEL_MASK, 0); |
822 | break; | |
823 | ||
824 | case SND_SOC_BIAS_OFF: | |
825 | /* Low resistance VROI to help discharge */ | |
69b626e6 | 826 | snd_soc_component_update_bits(component, |
b35a28af MB |
827 | WM8955_ADDITIONAL_CONTROL_3, |
828 | WM8955_VROI, 0); | |
829 | ||
830 | /* Turn off VMID and VREF */ | |
69b626e6 | 831 | snd_soc_component_update_bits(component, WM8955_POWER_MANAGEMENT_1, |
b35a28af MB |
832 | WM8955_VREF | |
833 | WM8955_VMIDSEL_MASK, 0); | |
834 | ||
835 | regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), | |
836 | wm8955->supplies); | |
837 | break; | |
838 | } | |
b35a28af MB |
839 | return 0; |
840 | } | |
841 | ||
842 | #define WM8955_RATES SNDRV_PCM_RATE_8000_96000 | |
843 | ||
844 | #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
845 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
846 | ||
85e7652d | 847 | static const struct snd_soc_dai_ops wm8955_dai_ops = { |
b35a28af MB |
848 | .set_sysclk = wm8955_set_sysclk, |
849 | .set_fmt = wm8955_set_fmt, | |
850 | .hw_params = wm8955_hw_params, | |
26d3c16e KM |
851 | .mute_stream = wm8955_mute, |
852 | .no_capture_mute = 1, | |
b35a28af MB |
853 | }; |
854 | ||
f0fba2ad LG |
855 | static struct snd_soc_dai_driver wm8955_dai = { |
856 | .name = "wm8955-hifi", | |
b35a28af MB |
857 | .playback = { |
858 | .stream_name = "Playback", | |
859 | .channels_min = 2, | |
860 | .channels_max = 2, | |
861 | .rates = WM8955_RATES, | |
862 | .formats = WM8955_FORMATS, | |
863 | }, | |
864 | .ops = &wm8955_dai_ops, | |
865 | }; | |
b35a28af | 866 | |
69b626e6 | 867 | static int wm8955_probe(struct snd_soc_component *component) |
b35a28af | 868 | { |
69b626e6 KM |
869 | struct wm8955_priv *wm8955 = snd_soc_component_get_drvdata(component); |
870 | struct wm8955_pdata *pdata = dev_get_platdata(component->dev); | |
f0fba2ad | 871 | int ret, i; |
b35a28af | 872 | |
b35a28af MB |
873 | for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++) |
874 | wm8955->supplies[i].supply = wm8955_supply_names[i]; | |
875 | ||
69b626e6 | 876 | ret = devm_regulator_bulk_get(component->dev, ARRAY_SIZE(wm8955->supplies), |
b35a28af MB |
877 | wm8955->supplies); |
878 | if (ret != 0) { | |
69b626e6 | 879 | dev_err(component->dev, "Failed to request supplies: %d\n", ret); |
f0fba2ad | 880 | return ret; |
b35a28af MB |
881 | } |
882 | ||
883 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies), | |
884 | wm8955->supplies); | |
885 | if (ret != 0) { | |
69b626e6 | 886 | dev_err(component->dev, "Failed to enable supplies: %d\n", ret); |
e90c7b45 | 887 | return ret; |
b35a28af MB |
888 | } |
889 | ||
69b626e6 | 890 | ret = wm8955_reset(component); |
b35a28af | 891 | if (ret < 0) { |
69b626e6 | 892 | dev_err(component->dev, "Failed to issue reset: %d\n", ret); |
b35a28af MB |
893 | goto err_enable; |
894 | } | |
895 | ||
b35a28af | 896 | /* Change some default settings - latch VU and enable ZC */ |
69b626e6 | 897 | snd_soc_component_update_bits(component, WM8955_LEFT_DAC_VOLUME, |
a1b3b5ee | 898 | WM8955_LDVU, WM8955_LDVU); |
69b626e6 | 899 | snd_soc_component_update_bits(component, WM8955_RIGHT_DAC_VOLUME, |
a1b3b5ee | 900 | WM8955_RDVU, WM8955_RDVU); |
69b626e6 | 901 | snd_soc_component_update_bits(component, WM8955_LOUT1_VOLUME, |
a1b3b5ee MB |
902 | WM8955_LO1VU | WM8955_LO1ZC, |
903 | WM8955_LO1VU | WM8955_LO1ZC); | |
69b626e6 | 904 | snd_soc_component_update_bits(component, WM8955_ROUT1_VOLUME, |
a1b3b5ee MB |
905 | WM8955_RO1VU | WM8955_RO1ZC, |
906 | WM8955_RO1VU | WM8955_RO1ZC); | |
69b626e6 | 907 | snd_soc_component_update_bits(component, WM8955_LOUT2_VOLUME, |
a1b3b5ee MB |
908 | WM8955_LO2VU | WM8955_LO2ZC, |
909 | WM8955_LO2VU | WM8955_LO2ZC); | |
69b626e6 | 910 | snd_soc_component_update_bits(component, WM8955_ROUT2_VOLUME, |
a1b3b5ee MB |
911 | WM8955_RO2VU | WM8955_RO2ZC, |
912 | WM8955_RO2VU | WM8955_RO2ZC); | |
69b626e6 | 913 | snd_soc_component_update_bits(component, WM8955_MONOOUT_VOLUME, |
a1b3b5ee | 914 | WM8955_MOZC, WM8955_MOZC); |
b35a28af MB |
915 | |
916 | /* Also enable adaptive bass boost by default */ | |
69b626e6 | 917 | snd_soc_component_update_bits(component, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB); |
b35a28af MB |
918 | |
919 | /* Set platform data values */ | |
f0fba2ad LG |
920 | if (pdata) { |
921 | if (pdata->out2_speaker) | |
69b626e6 | 922 | snd_soc_component_update_bits(component, WM8955_ADDITIONAL_CONTROL_2, |
95860fdf | 923 | WM8955_ROUT2INV, WM8955_ROUT2INV); |
b35a28af | 924 | |
f0fba2ad | 925 | if (pdata->monoin_diff) |
69b626e6 | 926 | snd_soc_component_update_bits(component, WM8955_MONO_OUT_MIX_1, |
95860fdf | 927 | WM8955_DMEN, WM8955_DMEN); |
b35a28af MB |
928 | } |
929 | ||
69b626e6 | 930 | snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY); |
b35a28af MB |
931 | |
932 | /* Bias level configuration will have done an extra enable */ | |
933 | regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); | |
934 | ||
b35a28af MB |
935 | return 0; |
936 | ||
937 | err_enable: | |
938 | regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); | |
b35a28af MB |
939 | return ret; |
940 | } | |
941 | ||
69b626e6 KM |
942 | static const struct snd_soc_component_driver soc_component_dev_wm8955 = { |
943 | .probe = wm8955_probe, | |
944 | .set_bias_level = wm8955_set_bias_level, | |
945 | .controls = wm8955_snd_controls, | |
946 | .num_controls = ARRAY_SIZE(wm8955_snd_controls), | |
947 | .dapm_widgets = wm8955_dapm_widgets, | |
948 | .num_dapm_widgets = ARRAY_SIZE(wm8955_dapm_widgets), | |
949 | .dapm_routes = wm8955_dapm_routes, | |
950 | .num_dapm_routes = ARRAY_SIZE(wm8955_dapm_routes), | |
951 | .suspend_bias_off = 1, | |
952 | .idle_bias_on = 1, | |
953 | .use_pmdown_time = 1, | |
954 | .endianness = 1, | |
95860fdf MB |
955 | }; |
956 | ||
957 | static const struct regmap_config wm8955_regmap = { | |
958 | .reg_bits = 7, | |
959 | .val_bits = 9, | |
960 | ||
961 | .max_register = WM8955_MAX_REGISTER, | |
962 | .volatile_reg = wm8955_volatile, | |
963 | .writeable_reg = wm8955_writeable, | |
964 | ||
6066d156 | 965 | .cache_type = REGCACHE_MAPLE, |
95860fdf MB |
966 | .reg_defaults = wm8955_reg_defaults, |
967 | .num_reg_defaults = ARRAY_SIZE(wm8955_reg_defaults), | |
f0fba2ad LG |
968 | }; |
969 | ||
97b0b6e3 | 970 | static int wm8955_i2c_probe(struct i2c_client *i2c) |
b35a28af MB |
971 | { |
972 | struct wm8955_priv *wm8955; | |
f0fba2ad | 973 | int ret; |
b35a28af | 974 | |
ba5c88d0 MB |
975 | wm8955 = devm_kzalloc(&i2c->dev, sizeof(struct wm8955_priv), |
976 | GFP_KERNEL); | |
b35a28af MB |
977 | if (wm8955 == NULL) |
978 | return -ENOMEM; | |
979 | ||
385b27f5 | 980 | wm8955->regmap = devm_regmap_init_i2c(i2c, &wm8955_regmap); |
95860fdf MB |
981 | if (IS_ERR(wm8955->regmap)) { |
982 | ret = PTR_ERR(wm8955->regmap); | |
983 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
984 | ret); | |
985 | return ret; | |
986 | } | |
987 | ||
b35a28af | 988 | i2c_set_clientdata(i2c, wm8955); |
b35a28af | 989 | |
69b626e6 KM |
990 | ret = devm_snd_soc_register_component(&i2c->dev, |
991 | &soc_component_dev_wm8955, &wm8955_dai, 1); | |
95860fdf MB |
992 | |
993 | return ret; | |
b35a28af MB |
994 | } |
995 | ||
b35a28af | 996 | static const struct i2c_device_id wm8955_i2c_id[] = { |
ba2a2c37 | 997 | { "wm8955" }, |
b35a28af MB |
998 | { } |
999 | }; | |
1000 | MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id); | |
1001 | ||
1002 | static struct i2c_driver wm8955_i2c_driver = { | |
1003 | .driver = { | |
091edccf | 1004 | .name = "wm8955", |
b35a28af | 1005 | }, |
9abcd240 | 1006 | .probe = wm8955_i2c_probe, |
b35a28af MB |
1007 | .id_table = wm8955_i2c_id, |
1008 | }; | |
b35a28af | 1009 | |
07c9c32b | 1010 | module_i2c_driver(wm8955_i2c_driver); |
b35a28af MB |
1011 | |
1012 | MODULE_DESCRIPTION("ASoC WM8955 driver"); | |
1013 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
1014 | MODULE_LICENSE("GPL"); |