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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a91eb199 MB |
2 | /* |
3 | * wm8904.c -- WM8904 ALSA SoC Audio driver | |
4 | * | |
656baaeb | 5 | * Copyright 2009-12 Wolfson Microelectronics plc |
a91eb199 MB |
6 | * |
7 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
a91eb199 MB |
8 | */ |
9 | ||
8b9920e3 | 10 | #include <linux/clk.h> |
a91eb199 | 11 | #include <linux/module.h> |
a91eb199 MB |
12 | #include <linux/init.h> |
13 | #include <linux/delay.h> | |
14 | #include <linux/pm.h> | |
15 | #include <linux/i2c.h> | |
84d0d831 | 16 | #include <linux/regmap.h> |
a91eb199 | 17 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
a91eb199 MB |
19 | #include <sound/core.h> |
20 | #include <sound/pcm.h> | |
21 | #include <sound/pcm_params.h> | |
22 | #include <sound/soc.h> | |
a91eb199 MB |
23 | #include <sound/initval.h> |
24 | #include <sound/tlv.h> | |
25 | #include <sound/wm8904.h> | |
26 | ||
27 | #include "wm8904.h" | |
28 | ||
8c126474 MB |
29 | enum wm8904_type { |
30 | WM8904, | |
31 | WM8912, | |
32 | }; | |
33 | ||
a91eb199 MB |
34 | #define WM8904_NUM_DCS_CHANNELS 4 |
35 | ||
36 | #define WM8904_NUM_SUPPLIES 5 | |
37 | static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { | |
38 | "DCVDD", | |
39 | "DBVDD", | |
40 | "AVDD", | |
41 | "CPVDD", | |
42 | "MICVDD", | |
43 | }; | |
44 | ||
45 | /* codec private data */ | |
46 | struct wm8904_priv { | |
84d0d831 | 47 | struct regmap *regmap; |
8b9920e3 | 48 | struct clk *mclk; |
f0fba2ad | 49 | |
8c126474 MB |
50 | enum wm8904_type devtype; |
51 | ||
a91eb199 MB |
52 | struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES]; |
53 | ||
54 | struct wm8904_pdata *pdata; | |
55 | ||
56 | int deemph; | |
57 | ||
58 | /* Platform provided DRC configuration */ | |
59 | const char **drc_texts; | |
60 | int drc_cfg; | |
61 | struct soc_enum drc_enum; | |
62 | ||
63 | /* Platform provided ReTune mobile configuration */ | |
64 | int num_retune_mobile_texts; | |
65 | const char **retune_mobile_texts; | |
66 | int retune_mobile_cfg; | |
67 | struct soc_enum retune_mobile_enum; | |
68 | ||
69 | /* FLL setup */ | |
70 | int fll_src; | |
71 | int fll_fref; | |
72 | int fll_fout; | |
73 | ||
74 | /* Clocking configuration */ | |
75 | unsigned int mclk_rate; | |
76 | int sysclk_src; | |
77 | unsigned int sysclk_rate; | |
78 | ||
79 | int tdm_width; | |
80 | int tdm_slots; | |
81 | int bclk; | |
82 | int fs; | |
83 | ||
84 | /* DC servo configuration - cached offset values */ | |
85 | int dcs_state[WM8904_NUM_DCS_CHANNELS]; | |
86 | }; | |
87 | ||
84d0d831 MB |
88 | static const struct reg_default wm8904_reg_defaults[] = { |
89 | { 4, 0x0018 }, /* R4 - Bias Control 0 */ | |
90 | { 5, 0x0000 }, /* R5 - VMID Control 0 */ | |
91 | { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */ | |
92 | { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */ | |
93 | { 8, 0x0001 }, /* R8 - Analogue DAC 0 */ | |
94 | { 9, 0x9696 }, /* R9 - mic Filter Control */ | |
95 | { 10, 0x0001 }, /* R10 - Analogue ADC 0 */ | |
96 | { 12, 0x0000 }, /* R12 - Power Management 0 */ | |
97 | { 14, 0x0000 }, /* R14 - Power Management 2 */ | |
98 | { 15, 0x0000 }, /* R15 - Power Management 3 */ | |
99 | { 18, 0x0000 }, /* R18 - Power Management 6 */ | |
985b11fa | 100 | { 20, 0x945E }, /* R20 - Clock Rates 0 */ |
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101 | { 21, 0x0C05 }, /* R21 - Clock Rates 1 */ |
102 | { 22, 0x0006 }, /* R22 - Clock Rates 2 */ | |
103 | { 24, 0x0050 }, /* R24 - Audio Interface 0 */ | |
104 | { 25, 0x000A }, /* R25 - Audio Interface 1 */ | |
105 | { 26, 0x00E4 }, /* R26 - Audio Interface 2 */ | |
106 | { 27, 0x0040 }, /* R27 - Audio Interface 3 */ | |
107 | { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */ | |
108 | { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */ | |
109 | { 32, 0x0000 }, /* R32 - DAC Digital 0 */ | |
110 | { 33, 0x0008 }, /* R33 - DAC Digital 1 */ | |
111 | { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */ | |
112 | { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */ | |
113 | { 38, 0x0010 }, /* R38 - ADC Digital 0 */ | |
114 | { 39, 0x0000 }, /* R39 - Digital Microphone 0 */ | |
115 | { 40, 0x01AF }, /* R40 - DRC 0 */ | |
116 | { 41, 0x3248 }, /* R41 - DRC 1 */ | |
117 | { 42, 0x0000 }, /* R42 - DRC 2 */ | |
118 | { 43, 0x0000 }, /* R43 - DRC 3 */ | |
119 | { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */ | |
120 | { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */ | |
121 | { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */ | |
122 | { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */ | |
123 | { 57, 0x002D }, /* R57 - Analogue OUT1 Left */ | |
124 | { 58, 0x002D }, /* R58 - Analogue OUT1 Right */ | |
125 | { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */ | |
126 | { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */ | |
127 | { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */ | |
128 | { 67, 0x0000 }, /* R67 - DC Servo 0 */ | |
129 | { 69, 0xAAAA }, /* R69 - DC Servo 2 */ | |
130 | { 71, 0xAAAA }, /* R71 - DC Servo 4 */ | |
131 | { 72, 0xAAAA }, /* R72 - DC Servo 5 */ | |
132 | { 90, 0x0000 }, /* R90 - Analogue HP 0 */ | |
133 | { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */ | |
134 | { 98, 0x0000 }, /* R98 - Charge Pump 0 */ | |
135 | { 104, 0x0004 }, /* R104 - Class W 0 */ | |
136 | { 108, 0x0000 }, /* R108 - Write Sequencer 0 */ | |
137 | { 109, 0x0000 }, /* R109 - Write Sequencer 1 */ | |
138 | { 110, 0x0000 }, /* R110 - Write Sequencer 2 */ | |
139 | { 111, 0x0000 }, /* R111 - Write Sequencer 3 */ | |
140 | { 112, 0x0000 }, /* R112 - Write Sequencer 4 */ | |
141 | { 116, 0x0000 }, /* R116 - FLL Control 1 */ | |
142 | { 117, 0x0007 }, /* R117 - FLL Control 2 */ | |
143 | { 118, 0x0000 }, /* R118 - FLL Control 3 */ | |
144 | { 119, 0x2EE0 }, /* R119 - FLL Control 4 */ | |
145 | { 120, 0x0004 }, /* R120 - FLL Control 5 */ | |
146 | { 121, 0x0014 }, /* R121 - GPIO Control 1 */ | |
147 | { 122, 0x0010 }, /* R122 - GPIO Control 2 */ | |
148 | { 123, 0x0010 }, /* R123 - GPIO Control 3 */ | |
149 | { 124, 0x0000 }, /* R124 - GPIO Control 4 */ | |
150 | { 126, 0x0000 }, /* R126 - Digital Pulls */ | |
151 | { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */ | |
152 | { 129, 0x0000 }, /* R129 - Interrupt Polarity */ | |
153 | { 130, 0x0000 }, /* R130 - Interrupt Debounce */ | |
154 | { 134, 0x0000 }, /* R134 - EQ1 */ | |
155 | { 135, 0x000C }, /* R135 - EQ2 */ | |
156 | { 136, 0x000C }, /* R136 - EQ3 */ | |
157 | { 137, 0x000C }, /* R137 - EQ4 */ | |
158 | { 138, 0x000C }, /* R138 - EQ5 */ | |
159 | { 139, 0x000C }, /* R139 - EQ6 */ | |
160 | { 140, 0x0FCA }, /* R140 - EQ7 */ | |
161 | { 141, 0x0400 }, /* R141 - EQ8 */ | |
162 | { 142, 0x00D8 }, /* R142 - EQ9 */ | |
163 | { 143, 0x1EB5 }, /* R143 - EQ10 */ | |
164 | { 144, 0xF145 }, /* R144 - EQ11 */ | |
165 | { 145, 0x0B75 }, /* R145 - EQ12 */ | |
166 | { 146, 0x01C5 }, /* R146 - EQ13 */ | |
167 | { 147, 0x1C58 }, /* R147 - EQ14 */ | |
168 | { 148, 0xF373 }, /* R148 - EQ15 */ | |
169 | { 149, 0x0A54 }, /* R149 - EQ16 */ | |
170 | { 150, 0x0558 }, /* R150 - EQ17 */ | |
171 | { 151, 0x168E }, /* R151 - EQ18 */ | |
172 | { 152, 0xF829 }, /* R152 - EQ19 */ | |
173 | { 153, 0x07AD }, /* R153 - EQ20 */ | |
174 | { 154, 0x1103 }, /* R154 - EQ21 */ | |
175 | { 155, 0x0564 }, /* R155 - EQ22 */ | |
176 | { 156, 0x0559 }, /* R156 - EQ23 */ | |
177 | { 157, 0x4000 }, /* R157 - EQ24 */ | |
178 | { 161, 0x0000 }, /* R161 - Control Interface Test 1 */ | |
179 | { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */ | |
180 | { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */ | |
181 | { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */ | |
a91eb199 MB |
182 | }; |
183 | ||
84d0d831 MB |
184 | static bool wm8904_volatile_register(struct device *dev, unsigned int reg) |
185 | { | |
186 | switch (reg) { | |
187 | case WM8904_SW_RESET_AND_ID: | |
188 | case WM8904_REVISION: | |
189 | case WM8904_DC_SERVO_1: | |
190 | case WM8904_DC_SERVO_6: | |
191 | case WM8904_DC_SERVO_7: | |
192 | case WM8904_DC_SERVO_8: | |
193 | case WM8904_DC_SERVO_9: | |
194 | case WM8904_DC_SERVO_READBACK_0: | |
195 | case WM8904_INTERRUPT_STATUS: | |
196 | return true; | |
197 | default: | |
198 | return false; | |
199 | } | |
200 | } | |
a91eb199 | 201 | |
84d0d831 | 202 | static bool wm8904_readable_register(struct device *dev, unsigned int reg) |
a91eb199 | 203 | { |
84d0d831 MB |
204 | switch (reg) { |
205 | case WM8904_SW_RESET_AND_ID: | |
206 | case WM8904_REVISION: | |
207 | case WM8904_BIAS_CONTROL_0: | |
208 | case WM8904_VMID_CONTROL_0: | |
209 | case WM8904_MIC_BIAS_CONTROL_0: | |
210 | case WM8904_MIC_BIAS_CONTROL_1: | |
211 | case WM8904_ANALOGUE_DAC_0: | |
212 | case WM8904_MIC_FILTER_CONTROL: | |
213 | case WM8904_ANALOGUE_ADC_0: | |
214 | case WM8904_POWER_MANAGEMENT_0: | |
215 | case WM8904_POWER_MANAGEMENT_2: | |
216 | case WM8904_POWER_MANAGEMENT_3: | |
217 | case WM8904_POWER_MANAGEMENT_6: | |
218 | case WM8904_CLOCK_RATES_0: | |
219 | case WM8904_CLOCK_RATES_1: | |
220 | case WM8904_CLOCK_RATES_2: | |
221 | case WM8904_AUDIO_INTERFACE_0: | |
222 | case WM8904_AUDIO_INTERFACE_1: | |
223 | case WM8904_AUDIO_INTERFACE_2: | |
224 | case WM8904_AUDIO_INTERFACE_3: | |
225 | case WM8904_DAC_DIGITAL_VOLUME_LEFT: | |
226 | case WM8904_DAC_DIGITAL_VOLUME_RIGHT: | |
227 | case WM8904_DAC_DIGITAL_0: | |
228 | case WM8904_DAC_DIGITAL_1: | |
229 | case WM8904_ADC_DIGITAL_VOLUME_LEFT: | |
230 | case WM8904_ADC_DIGITAL_VOLUME_RIGHT: | |
231 | case WM8904_ADC_DIGITAL_0: | |
232 | case WM8904_DIGITAL_MICROPHONE_0: | |
233 | case WM8904_DRC_0: | |
234 | case WM8904_DRC_1: | |
235 | case WM8904_DRC_2: | |
236 | case WM8904_DRC_3: | |
237 | case WM8904_ANALOGUE_LEFT_INPUT_0: | |
238 | case WM8904_ANALOGUE_RIGHT_INPUT_0: | |
239 | case WM8904_ANALOGUE_LEFT_INPUT_1: | |
240 | case WM8904_ANALOGUE_RIGHT_INPUT_1: | |
241 | case WM8904_ANALOGUE_OUT1_LEFT: | |
242 | case WM8904_ANALOGUE_OUT1_RIGHT: | |
243 | case WM8904_ANALOGUE_OUT2_LEFT: | |
244 | case WM8904_ANALOGUE_OUT2_RIGHT: | |
245 | case WM8904_ANALOGUE_OUT12_ZC: | |
246 | case WM8904_DC_SERVO_0: | |
247 | case WM8904_DC_SERVO_1: | |
248 | case WM8904_DC_SERVO_2: | |
249 | case WM8904_DC_SERVO_4: | |
250 | case WM8904_DC_SERVO_5: | |
251 | case WM8904_DC_SERVO_6: | |
252 | case WM8904_DC_SERVO_7: | |
253 | case WM8904_DC_SERVO_8: | |
254 | case WM8904_DC_SERVO_9: | |
255 | case WM8904_DC_SERVO_READBACK_0: | |
256 | case WM8904_ANALOGUE_HP_0: | |
257 | case WM8904_ANALOGUE_LINEOUT_0: | |
258 | case WM8904_CHARGE_PUMP_0: | |
259 | case WM8904_CLASS_W_0: | |
260 | case WM8904_WRITE_SEQUENCER_0: | |
261 | case WM8904_WRITE_SEQUENCER_1: | |
262 | case WM8904_WRITE_SEQUENCER_2: | |
263 | case WM8904_WRITE_SEQUENCER_3: | |
264 | case WM8904_WRITE_SEQUENCER_4: | |
265 | case WM8904_FLL_CONTROL_1: | |
266 | case WM8904_FLL_CONTROL_2: | |
267 | case WM8904_FLL_CONTROL_3: | |
268 | case WM8904_FLL_CONTROL_4: | |
269 | case WM8904_FLL_CONTROL_5: | |
270 | case WM8904_GPIO_CONTROL_1: | |
271 | case WM8904_GPIO_CONTROL_2: | |
272 | case WM8904_GPIO_CONTROL_3: | |
273 | case WM8904_GPIO_CONTROL_4: | |
274 | case WM8904_DIGITAL_PULLS: | |
275 | case WM8904_INTERRUPT_STATUS: | |
276 | case WM8904_INTERRUPT_STATUS_MASK: | |
277 | case WM8904_INTERRUPT_POLARITY: | |
278 | case WM8904_INTERRUPT_DEBOUNCE: | |
279 | case WM8904_EQ1: | |
280 | case WM8904_EQ2: | |
281 | case WM8904_EQ3: | |
282 | case WM8904_EQ4: | |
283 | case WM8904_EQ5: | |
284 | case WM8904_EQ6: | |
285 | case WM8904_EQ7: | |
286 | case WM8904_EQ8: | |
287 | case WM8904_EQ9: | |
288 | case WM8904_EQ10: | |
289 | case WM8904_EQ11: | |
290 | case WM8904_EQ12: | |
291 | case WM8904_EQ13: | |
292 | case WM8904_EQ14: | |
293 | case WM8904_EQ15: | |
294 | case WM8904_EQ16: | |
295 | case WM8904_EQ17: | |
296 | case WM8904_EQ18: | |
297 | case WM8904_EQ19: | |
298 | case WM8904_EQ20: | |
299 | case WM8904_EQ21: | |
300 | case WM8904_EQ22: | |
301 | case WM8904_EQ23: | |
302 | case WM8904_EQ24: | |
303 | case WM8904_CONTROL_INTERFACE_TEST_1: | |
9b85fc90 | 304 | case WM8904_ADC_TEST_0: |
84d0d831 MB |
305 | case WM8904_ANALOGUE_OUTPUT_BIAS_0: |
306 | case WM8904_FLL_NCO_TEST_0: | |
307 | case WM8904_FLL_NCO_TEST_1: | |
308 | return true; | |
309 | default: | |
28b5df18 | 310 | return false; |
84d0d831 | 311 | } |
a91eb199 MB |
312 | } |
313 | ||
46a9100c | 314 | static int wm8904_configure_clocking(struct snd_soc_component *component) |
a91eb199 | 315 | { |
46a9100c | 316 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); |
a91eb199 MB |
317 | unsigned int clock0, clock2, rate; |
318 | ||
319 | /* Gate the clock while we're updating to avoid misclocking */ | |
6d75dfc3 | 320 | clock2 = snd_soc_component_read(component, WM8904_CLOCK_RATES_2); |
46a9100c | 321 | snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, |
a91eb199 MB |
322 | WM8904_SYSCLK_SRC, 0); |
323 | ||
324 | /* This should be done on init() for bypass paths */ | |
325 | switch (wm8904->sysclk_src) { | |
326 | case WM8904_CLK_MCLK: | |
46a9100c | 327 | dev_dbg(component->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); |
a91eb199 MB |
328 | |
329 | clock2 &= ~WM8904_SYSCLK_SRC; | |
330 | rate = wm8904->mclk_rate; | |
331 | ||
332 | /* Ensure the FLL is stopped */ | |
46a9100c | 333 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, |
a91eb199 MB |
334 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); |
335 | break; | |
336 | ||
337 | case WM8904_CLK_FLL: | |
46a9100c | 338 | dev_dbg(component->dev, "Using %dHz FLL clock\n", |
a91eb199 MB |
339 | wm8904->fll_fout); |
340 | ||
341 | clock2 |= WM8904_SYSCLK_SRC; | |
342 | rate = wm8904->fll_fout; | |
343 | break; | |
344 | ||
345 | default: | |
46a9100c | 346 | dev_err(component->dev, "System clock not configured\n"); |
a91eb199 MB |
347 | return -EINVAL; |
348 | } | |
349 | ||
350 | /* SYSCLK shouldn't be over 13.5MHz */ | |
351 | if (rate > 13500000) { | |
352 | clock0 = WM8904_MCLK_DIV; | |
353 | wm8904->sysclk_rate = rate / 2; | |
354 | } else { | |
355 | clock0 = 0; | |
356 | wm8904->sysclk_rate = rate; | |
357 | } | |
358 | ||
46a9100c | 359 | snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV, |
a91eb199 MB |
360 | clock0); |
361 | ||
46a9100c | 362 | snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, |
a91eb199 MB |
363 | WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2); |
364 | ||
46a9100c | 365 | dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); |
a91eb199 MB |
366 | |
367 | return 0; | |
368 | } | |
369 | ||
46a9100c | 370 | static void wm8904_set_drc(struct snd_soc_component *component) |
a91eb199 | 371 | { |
46a9100c | 372 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); |
a91eb199 MB |
373 | struct wm8904_pdata *pdata = wm8904->pdata; |
374 | int save, i; | |
375 | ||
376 | /* Save any enables; the configuration should clear them. */ | |
6d75dfc3 | 377 | save = snd_soc_component_read(component, WM8904_DRC_0); |
a91eb199 MB |
378 | |
379 | for (i = 0; i < WM8904_DRC_REGS; i++) | |
46a9100c | 380 | snd_soc_component_update_bits(component, WM8904_DRC_0 + i, 0xffff, |
a91eb199 MB |
381 | pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); |
382 | ||
383 | /* Reenable the DRC */ | |
46a9100c | 384 | snd_soc_component_update_bits(component, WM8904_DRC_0, |
a91eb199 MB |
385 | WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save); |
386 | } | |
387 | ||
388 | static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, | |
389 | struct snd_ctl_elem_value *ucontrol) | |
390 | { | |
46a9100c KM |
391 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
392 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); | |
a91eb199 | 393 | struct wm8904_pdata *pdata = wm8904->pdata; |
c41a024c | 394 | int value = ucontrol->value.enumerated.item[0]; |
a91eb199 MB |
395 | |
396 | if (value >= pdata->num_drc_cfgs) | |
397 | return -EINVAL; | |
398 | ||
399 | wm8904->drc_cfg = value; | |
400 | ||
46a9100c | 401 | wm8904_set_drc(component); |
a91eb199 MB |
402 | |
403 | return 0; | |
404 | } | |
405 | ||
406 | static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, | |
407 | struct snd_ctl_elem_value *ucontrol) | |
408 | { | |
46a9100c KM |
409 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
410 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); | |
a91eb199 MB |
411 | |
412 | ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
46a9100c | 417 | static void wm8904_set_retune_mobile(struct snd_soc_component *component) |
a91eb199 | 418 | { |
46a9100c | 419 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); |
a91eb199 MB |
420 | struct wm8904_pdata *pdata = wm8904->pdata; |
421 | int best, best_val, save, i, cfg; | |
422 | ||
423 | if (!pdata || !wm8904->num_retune_mobile_texts) | |
424 | return; | |
425 | ||
426 | /* Find the version of the currently selected configuration | |
427 | * with the nearest sample rate. */ | |
428 | cfg = wm8904->retune_mobile_cfg; | |
429 | best = 0; | |
430 | best_val = INT_MAX; | |
431 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
432 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
433 | wm8904->retune_mobile_texts[cfg]) == 0 && | |
434 | abs(pdata->retune_mobile_cfgs[i].rate | |
435 | - wm8904->fs) < best_val) { | |
436 | best = i; | |
437 | best_val = abs(pdata->retune_mobile_cfgs[i].rate | |
438 | - wm8904->fs); | |
439 | } | |
440 | } | |
441 | ||
46a9100c | 442 | dev_dbg(component->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", |
a91eb199 MB |
443 | pdata->retune_mobile_cfgs[best].name, |
444 | pdata->retune_mobile_cfgs[best].rate, | |
445 | wm8904->fs); | |
446 | ||
447 | /* The EQ will be disabled while reconfiguring it, remember the | |
448 | * current configuration. | |
449 | */ | |
6d75dfc3 | 450 | save = snd_soc_component_read(component, WM8904_EQ1); |
a91eb199 MB |
451 | |
452 | for (i = 0; i < WM8904_EQ_REGS; i++) | |
46a9100c | 453 | snd_soc_component_update_bits(component, WM8904_EQ1 + i, 0xffff, |
a91eb199 MB |
454 | pdata->retune_mobile_cfgs[best].regs[i]); |
455 | ||
46a9100c | 456 | snd_soc_component_update_bits(component, WM8904_EQ1, WM8904_EQ_ENA, save); |
a91eb199 MB |
457 | } |
458 | ||
459 | static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
460 | struct snd_ctl_elem_value *ucontrol) | |
461 | { | |
46a9100c KM |
462 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
463 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); | |
a91eb199 | 464 | struct wm8904_pdata *pdata = wm8904->pdata; |
c41a024c | 465 | int value = ucontrol->value.enumerated.item[0]; |
a91eb199 MB |
466 | |
467 | if (value >= pdata->num_retune_mobile_cfgs) | |
468 | return -EINVAL; | |
469 | ||
470 | wm8904->retune_mobile_cfg = value; | |
471 | ||
46a9100c | 472 | wm8904_set_retune_mobile(component); |
a91eb199 MB |
473 | |
474 | return 0; | |
475 | } | |
476 | ||
477 | static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
478 | struct snd_ctl_elem_value *ucontrol) | |
479 | { | |
46a9100c KM |
480 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
481 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); | |
a91eb199 MB |
482 | |
483 | ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | static int deemph_settings[] = { 0, 32000, 44100, 48000 }; | |
489 | ||
46a9100c | 490 | static int wm8904_set_deemph(struct snd_soc_component *component) |
a91eb199 | 491 | { |
46a9100c | 492 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); |
a91eb199 MB |
493 | int val, i, best; |
494 | ||
495 | /* If we're using deemphasis select the nearest available sample | |
496 | * rate. | |
497 | */ | |
498 | if (wm8904->deemph) { | |
499 | best = 1; | |
500 | for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { | |
501 | if (abs(deemph_settings[i] - wm8904->fs) < | |
502 | abs(deemph_settings[best] - wm8904->fs)) | |
503 | best = i; | |
504 | } | |
505 | ||
506 | val = best << WM8904_DEEMPH_SHIFT; | |
507 | } else { | |
508 | val = 0; | |
509 | } | |
510 | ||
46a9100c | 511 | dev_dbg(component->dev, "Set deemphasis %d\n", val); |
a91eb199 | 512 | |
46a9100c | 513 | return snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, |
a91eb199 MB |
514 | WM8904_DEEMPH_MASK, val); |
515 | } | |
516 | ||
517 | static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, | |
518 | struct snd_ctl_elem_value *ucontrol) | |
519 | { | |
46a9100c KM |
520 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
521 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); | |
a91eb199 | 522 | |
eaddf6fd | 523 | ucontrol->value.integer.value[0] = wm8904->deemph; |
3f343f85 | 524 | return 0; |
a91eb199 MB |
525 | } |
526 | ||
527 | static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, | |
528 | struct snd_ctl_elem_value *ucontrol) | |
529 | { | |
46a9100c KM |
530 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
531 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); | |
931dfa69 | 532 | unsigned int deemph = ucontrol->value.integer.value[0]; |
a91eb199 MB |
533 | |
534 | if (deemph > 1) | |
535 | return -EINVAL; | |
536 | ||
537 | wm8904->deemph = deemph; | |
538 | ||
46a9100c | 539 | return wm8904_set_deemph(component); |
a91eb199 MB |
540 | } |
541 | ||
542 | static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); | |
543 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
544 | static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); | |
545 | static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); | |
546 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
547 | ||
a91eb199 MB |
548 | static const char *hpf_mode_text[] = { |
549 | "Hi-fi", "Voice 1", "Voice 2", "Voice 3" | |
550 | }; | |
551 | ||
d12bfd62 TI |
552 | static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5, |
553 | hpf_mode_text); | |
a91eb199 | 554 | |
9b85fc90 MB |
555 | static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol, |
556 | struct snd_ctl_elem_value *ucontrol) | |
557 | { | |
46a9100c | 558 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
9b85fc90 MB |
559 | unsigned int val; |
560 | int ret; | |
561 | ||
562 | ret = snd_soc_put_volsw(kcontrol, ucontrol); | |
563 | if (ret < 0) | |
564 | return ret; | |
565 | ||
566 | if (ucontrol->value.integer.value[0]) | |
567 | val = 0; | |
568 | else | |
569 | val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5; | |
570 | ||
46a9100c | 571 | snd_soc_component_update_bits(component, WM8904_ADC_TEST_0, |
9b85fc90 MB |
572 | WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5, |
573 | val); | |
574 | ||
575 | return ret; | |
576 | } | |
577 | ||
a91eb199 MB |
578 | static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { |
579 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, | |
580 | WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), | |
581 | ||
a91eb199 MB |
582 | /* No TLV since it depends on mode */ |
583 | SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0, | |
584 | WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0), | |
585 | SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0, | |
5a7c5f26 | 586 | WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1), |
a91eb199 MB |
587 | |
588 | SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0), | |
589 | SOC_ENUM("High Pass Filter Mode", hpf_mode), | |
5a68bae2 LPC |
590 | SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0, |
591 | snd_soc_get_volsw, wm8904_adc_osr_put), | |
a91eb199 MB |
592 | }; |
593 | ||
594 | static const char *drc_path_text[] = { | |
595 | "ADC", "DAC" | |
596 | }; | |
597 | ||
d12bfd62 | 598 | static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text); |
a91eb199 MB |
599 | |
600 | static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = { | |
601 | SOC_SINGLE_TLV("Digital Playback Boost Volume", | |
602 | WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv), | |
603 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT, | |
604 | WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), | |
605 | ||
606 | SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT, | |
607 | WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv), | |
608 | SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT, | |
609 | WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1), | |
610 | SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT, | |
611 | WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0), | |
612 | ||
613 | SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT, | |
614 | WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv), | |
615 | SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT, | |
616 | WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1), | |
617 | SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT, | |
618 | WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0), | |
619 | ||
620 | SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0), | |
621 | SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0), | |
622 | SOC_ENUM("DRC Path", drc_path), | |
623 | SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0), | |
624 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, | |
625 | wm8904_get_deemph, wm8904_put_deemph), | |
626 | }; | |
627 | ||
628 | static const struct snd_kcontrol_new wm8904_snd_controls[] = { | |
629 | SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0, | |
630 | sidetone_tlv), | |
631 | }; | |
632 | ||
633 | static const struct snd_kcontrol_new wm8904_eq_controls[] = { | |
634 | SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv), | |
635 | SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv), | |
636 | SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv), | |
637 | SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv), | |
638 | SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv), | |
639 | }; | |
640 | ||
641 | static int cp_event(struct snd_soc_dapm_widget *w, | |
642 | struct snd_kcontrol *kcontrol, int event) | |
643 | { | |
4c8d620a TI |
644 | if (WARN_ON(event != SND_SOC_DAPM_POST_PMU)) |
645 | return -EINVAL; | |
a91eb199 MB |
646 | |
647 | /* Maximum startup time */ | |
648 | udelay(500); | |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
653 | static int sysclk_event(struct snd_soc_dapm_widget *w, | |
654 | struct snd_kcontrol *kcontrol, int event) | |
655 | { | |
46a9100c KM |
656 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
657 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); | |
a91eb199 MB |
658 | |
659 | switch (event) { | |
660 | case SND_SOC_DAPM_PRE_PMU: | |
661 | /* If we're using the FLL then we only start it when | |
662 | * required; we assume that the configuration has been | |
663 | * done previously and all we need to do is kick it | |
664 | * off. | |
665 | */ | |
666 | switch (wm8904->sysclk_src) { | |
667 | case WM8904_CLK_FLL: | |
46a9100c | 668 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, |
a91eb199 MB |
669 | WM8904_FLL_OSC_ENA, |
670 | WM8904_FLL_OSC_ENA); | |
671 | ||
46a9100c | 672 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, |
a91eb199 MB |
673 | WM8904_FLL_ENA, |
674 | WM8904_FLL_ENA); | |
675 | break; | |
676 | ||
677 | default: | |
678 | break; | |
679 | } | |
680 | break; | |
681 | ||
682 | case SND_SOC_DAPM_POST_PMD: | |
46a9100c | 683 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, |
a91eb199 MB |
684 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); |
685 | break; | |
686 | } | |
687 | ||
688 | return 0; | |
689 | } | |
690 | ||
691 | static int out_pga_event(struct snd_soc_dapm_widget *w, | |
692 | struct snd_kcontrol *kcontrol, int event) | |
693 | { | |
46a9100c KM |
694 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
695 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); | |
a91eb199 MB |
696 | int reg, val; |
697 | int dcs_mask; | |
698 | int dcs_l, dcs_r; | |
699 | int dcs_l_reg, dcs_r_reg; | |
472a6309 | 700 | int an_out_reg; |
a91eb199 | 701 | int timeout; |
e4bc6696 | 702 | int pwr_reg; |
a91eb199 MB |
703 | |
704 | /* This code is shared between HP and LINEOUT; we do all our | |
705 | * power management in stereo pairs to avoid latency issues so | |
706 | * we reuse shift to identify which rather than strcmp() the | |
707 | * name. */ | |
708 | reg = w->shift; | |
709 | ||
710 | switch (reg) { | |
711 | case WM8904_ANALOGUE_HP_0: | |
e4bc6696 | 712 | pwr_reg = WM8904_POWER_MANAGEMENT_2; |
a91eb199 MB |
713 | dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; |
714 | dcs_r_reg = WM8904_DC_SERVO_8; | |
715 | dcs_l_reg = WM8904_DC_SERVO_9; | |
472a6309 | 716 | an_out_reg = WM8904_ANALOGUE_OUT1_LEFT; |
a91eb199 MB |
717 | dcs_l = 0; |
718 | dcs_r = 1; | |
719 | break; | |
720 | case WM8904_ANALOGUE_LINEOUT_0: | |
e4bc6696 | 721 | pwr_reg = WM8904_POWER_MANAGEMENT_3; |
a91eb199 MB |
722 | dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; |
723 | dcs_r_reg = WM8904_DC_SERVO_6; | |
724 | dcs_l_reg = WM8904_DC_SERVO_7; | |
472a6309 | 725 | an_out_reg = WM8904_ANALOGUE_OUT2_LEFT; |
a91eb199 MB |
726 | dcs_l = 2; |
727 | dcs_r = 3; | |
728 | break; | |
729 | default: | |
8d8bb1ad | 730 | WARN(1, "Invalid reg %d\n", reg); |
a91eb199 MB |
731 | return -EINVAL; |
732 | } | |
733 | ||
734 | switch (event) { | |
e4bc6696 MB |
735 | case SND_SOC_DAPM_PRE_PMU: |
736 | /* Power on the PGAs */ | |
46a9100c | 737 | snd_soc_component_update_bits(component, pwr_reg, |
e4bc6696 MB |
738 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, |
739 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA); | |
740 | ||
a91eb199 | 741 | /* Power on the amplifier */ |
46a9100c | 742 | snd_soc_component_update_bits(component, reg, |
a91eb199 MB |
743 | WM8904_HPL_ENA | WM8904_HPR_ENA, |
744 | WM8904_HPL_ENA | WM8904_HPR_ENA); | |
745 | ||
e4bc6696 | 746 | |
a91eb199 | 747 | /* Enable the first stage */ |
46a9100c | 748 | snd_soc_component_update_bits(component, reg, |
a91eb199 MB |
749 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, |
750 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY); | |
751 | ||
752 | /* Power up the DC servo */ | |
46a9100c | 753 | snd_soc_component_update_bits(component, WM8904_DC_SERVO_0, |
a91eb199 MB |
754 | dcs_mask, dcs_mask); |
755 | ||
756 | /* Either calibrate the DC servo or restore cached state | |
757 | * if we have that. | |
758 | */ | |
759 | if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { | |
46a9100c | 760 | dev_dbg(component->dev, "Restoring DC servo state\n"); |
a91eb199 | 761 | |
46a9100c | 762 | snd_soc_component_write(component, dcs_l_reg, |
a91eb199 | 763 | wm8904->dcs_state[dcs_l]); |
46a9100c | 764 | snd_soc_component_write(component, dcs_r_reg, |
a91eb199 MB |
765 | wm8904->dcs_state[dcs_r]); |
766 | ||
46a9100c | 767 | snd_soc_component_write(component, WM8904_DC_SERVO_1, dcs_mask); |
a91eb199 MB |
768 | |
769 | timeout = 20; | |
770 | } else { | |
46a9100c | 771 | dev_dbg(component->dev, "Calibrating DC servo\n"); |
a91eb199 | 772 | |
46a9100c | 773 | snd_soc_component_write(component, WM8904_DC_SERVO_1, |
a91eb199 MB |
774 | dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT); |
775 | ||
776 | timeout = 500; | |
777 | } | |
778 | ||
779 | /* Wait for DC servo to complete */ | |
780 | dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT; | |
781 | do { | |
6d75dfc3 | 782 | val = snd_soc_component_read(component, WM8904_DC_SERVO_READBACK_0); |
a91eb199 MB |
783 | if ((val & dcs_mask) == dcs_mask) |
784 | break; | |
785 | ||
786 | msleep(1); | |
787 | } while (--timeout); | |
788 | ||
789 | if ((val & dcs_mask) != dcs_mask) | |
46a9100c | 790 | dev_warn(component->dev, "DC servo timed out\n"); |
a91eb199 | 791 | else |
46a9100c | 792 | dev_dbg(component->dev, "DC servo ready\n"); |
a91eb199 MB |
793 | |
794 | /* Enable the output stage */ | |
46a9100c | 795 | snd_soc_component_update_bits(component, reg, |
a91eb199 MB |
796 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, |
797 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); | |
472a6309 EG |
798 | |
799 | /* Update volume, requires PGA to be powered */ | |
800 | val = snd_soc_component_read(component, an_out_reg); | |
801 | snd_soc_component_write(component, an_out_reg, val); | |
e4bc6696 | 802 | break; |
a91eb199 | 803 | |
e4bc6696 | 804 | case SND_SOC_DAPM_POST_PMU: |
a91eb199 | 805 | /* Unshort the output itself */ |
46a9100c | 806 | snd_soc_component_update_bits(component, reg, |
a91eb199 MB |
807 | WM8904_HPL_RMV_SHORT | |
808 | WM8904_HPR_RMV_SHORT, | |
809 | WM8904_HPL_RMV_SHORT | | |
810 | WM8904_HPR_RMV_SHORT); | |
811 | ||
812 | break; | |
813 | ||
814 | case SND_SOC_DAPM_PRE_PMD: | |
815 | /* Short the output */ | |
46a9100c | 816 | snd_soc_component_update_bits(component, reg, |
a91eb199 MB |
817 | WM8904_HPL_RMV_SHORT | |
818 | WM8904_HPR_RMV_SHORT, 0); | |
e4bc6696 | 819 | break; |
a91eb199 | 820 | |
e4bc6696 | 821 | case SND_SOC_DAPM_POST_PMD: |
a91eb199 MB |
822 | /* Cache the DC servo configuration; this will be |
823 | * invalidated if we change the configuration. */ | |
6d75dfc3 KM |
824 | wm8904->dcs_state[dcs_l] = snd_soc_component_read(component, dcs_l_reg); |
825 | wm8904->dcs_state[dcs_r] = snd_soc_component_read(component, dcs_r_reg); | |
a91eb199 | 826 | |
46a9100c | 827 | snd_soc_component_update_bits(component, WM8904_DC_SERVO_0, |
a91eb199 MB |
828 | dcs_mask, 0); |
829 | ||
830 | /* Disable the amplifier input and output stages */ | |
46a9100c | 831 | snd_soc_component_update_bits(component, reg, |
a91eb199 MB |
832 | WM8904_HPL_ENA | WM8904_HPR_ENA | |
833 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY | | |
834 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, | |
835 | 0); | |
e4bc6696 MB |
836 | |
837 | /* PGAs too */ | |
46a9100c | 838 | snd_soc_component_update_bits(component, pwr_reg, |
e4bc6696 MB |
839 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, |
840 | 0); | |
a91eb199 MB |
841 | break; |
842 | } | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
0a05f2e8 MM |
847 | static const char *input_mode_text[] = { |
848 | "Single-Ended", "Differential Line", "Differential Mic" | |
849 | }; | |
850 | ||
a91eb199 MB |
851 | static const char *lin_text[] = { |
852 | "IN1L", "IN2L", "IN3L" | |
853 | }; | |
854 | ||
d12bfd62 TI |
855 | static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2, |
856 | lin_text); | |
a91eb199 MB |
857 | |
858 | static const struct snd_kcontrol_new lin_mux = | |
859 | SOC_DAPM_ENUM("Left Capture Mux", lin_enum); | |
860 | ||
d12bfd62 TI |
861 | static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4, |
862 | lin_text); | |
a91eb199 MB |
863 | |
864 | static const struct snd_kcontrol_new lin_inv_mux = | |
22afe624 | 865 | SOC_DAPM_ENUM("Left Capture Inverting Mux", lin_inv_enum); |
a91eb199 | 866 | |
0a05f2e8 MM |
867 | static SOC_ENUM_SINGLE_DECL(lin_mode_enum, |
868 | WM8904_ANALOGUE_LEFT_INPUT_1, 0, | |
869 | input_mode_text); | |
870 | ||
871 | static const struct snd_kcontrol_new lin_mode = | |
872 | SOC_DAPM_ENUM("Left Capture Mode", lin_mode_enum); | |
873 | ||
a91eb199 MB |
874 | static const char *rin_text[] = { |
875 | "IN1R", "IN2R", "IN3R" | |
876 | }; | |
877 | ||
d12bfd62 TI |
878 | static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2, |
879 | rin_text); | |
a91eb199 MB |
880 | |
881 | static const struct snd_kcontrol_new rin_mux = | |
882 | SOC_DAPM_ENUM("Right Capture Mux", rin_enum); | |
883 | ||
d12bfd62 TI |
884 | static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4, |
885 | rin_text); | |
a91eb199 MB |
886 | |
887 | static const struct snd_kcontrol_new rin_inv_mux = | |
22afe624 | 888 | SOC_DAPM_ENUM("Right Capture Inverting Mux", rin_inv_enum); |
a91eb199 | 889 | |
0a05f2e8 MM |
890 | static SOC_ENUM_SINGLE_DECL(rin_mode_enum, |
891 | WM8904_ANALOGUE_RIGHT_INPUT_1, 0, | |
892 | input_mode_text); | |
893 | ||
894 | static const struct snd_kcontrol_new rin_mode = | |
895 | SOC_DAPM_ENUM("Right Capture Mode", rin_mode_enum); | |
896 | ||
a91eb199 MB |
897 | static const char *aif_text[] = { |
898 | "Left", "Right" | |
899 | }; | |
900 | ||
d12bfd62 TI |
901 | static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7, |
902 | aif_text); | |
a91eb199 MB |
903 | |
904 | static const struct snd_kcontrol_new aifoutl_mux = | |
905 | SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); | |
906 | ||
d12bfd62 TI |
907 | static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6, |
908 | aif_text); | |
a91eb199 MB |
909 | |
910 | static const struct snd_kcontrol_new aifoutr_mux = | |
911 | SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); | |
912 | ||
d12bfd62 TI |
913 | static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5, |
914 | aif_text); | |
a91eb199 MB |
915 | |
916 | static const struct snd_kcontrol_new aifinl_mux = | |
917 | SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); | |
918 | ||
d12bfd62 TI |
919 | static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4, |
920 | aif_text); | |
a91eb199 MB |
921 | |
922 | static const struct snd_kcontrol_new aifinr_mux = | |
923 | SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); | |
924 | ||
925 | static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = { | |
926 | SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event, | |
927 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
928 | SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0), | |
929 | SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0), | |
930 | }; | |
931 | ||
932 | static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = { | |
933 | SND_SOC_DAPM_INPUT("IN1L"), | |
934 | SND_SOC_DAPM_INPUT("IN1R"), | |
935 | SND_SOC_DAPM_INPUT("IN2L"), | |
936 | SND_SOC_DAPM_INPUT("IN2R"), | |
937 | SND_SOC_DAPM_INPUT("IN3L"), | |
938 | SND_SOC_DAPM_INPUT("IN3R"), | |
939 | ||
dcd658c5 | 940 | SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0), |
a91eb199 MB |
941 | |
942 | SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux), | |
943 | SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0, | |
944 | &lin_inv_mux), | |
0a05f2e8 | 945 | SND_SOC_DAPM_MUX("Left Capture Mode", SND_SOC_NOPM, 0, 0, &lin_mode), |
a91eb199 MB |
946 | SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux), |
947 | SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0, | |
948 | &rin_inv_mux), | |
0a05f2e8 | 949 | SND_SOC_DAPM_MUX("Right Capture Mode", SND_SOC_NOPM, 0, 0, &rin_mode), |
a91eb199 MB |
950 | |
951 | SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0, | |
952 | NULL, 0), | |
953 | SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0, | |
954 | NULL, 0), | |
955 | ||
956 | SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0), | |
957 | SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0), | |
958 | ||
959 | SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), | |
960 | SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), | |
961 | ||
962 | SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), | |
963 | SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), | |
964 | }; | |
965 | ||
966 | static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = { | |
967 | SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), | |
968 | SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), | |
969 | ||
970 | SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), | |
971 | SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), | |
972 | ||
973 | SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0), | |
974 | SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0), | |
975 | ||
976 | SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event, | |
977 | SND_SOC_DAPM_POST_PMU), | |
978 | ||
e4bc6696 MB |
979 | SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), |
980 | SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
a91eb199 | 981 | |
e4bc6696 MB |
982 | SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), |
983 | SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
a91eb199 MB |
984 | |
985 | SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0, | |
986 | 0, NULL, 0, out_pga_event, | |
e4bc6696 MB |
987 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
988 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
a91eb199 MB |
989 | SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0, |
990 | 0, NULL, 0, out_pga_event, | |
e4bc6696 MB |
991 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
992 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
a91eb199 MB |
993 | |
994 | SND_SOC_DAPM_OUTPUT("HPOUTL"), | |
995 | SND_SOC_DAPM_OUTPUT("HPOUTR"), | |
996 | SND_SOC_DAPM_OUTPUT("LINEOUTL"), | |
997 | SND_SOC_DAPM_OUTPUT("LINEOUTR"), | |
998 | }; | |
999 | ||
1000 | static const char *out_mux_text[] = { | |
1001 | "DAC", "Bypass" | |
1002 | }; | |
1003 | ||
d12bfd62 TI |
1004 | static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3, |
1005 | out_mux_text); | |
a91eb199 MB |
1006 | |
1007 | static const struct snd_kcontrol_new hpl_mux = | |
1008 | SOC_DAPM_ENUM("HPL Mux", hpl_enum); | |
1009 | ||
d12bfd62 TI |
1010 | static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2, |
1011 | out_mux_text); | |
a91eb199 MB |
1012 | |
1013 | static const struct snd_kcontrol_new hpr_mux = | |
1014 | SOC_DAPM_ENUM("HPR Mux", hpr_enum); | |
1015 | ||
d12bfd62 TI |
1016 | static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1, |
1017 | out_mux_text); | |
a91eb199 MB |
1018 | |
1019 | static const struct snd_kcontrol_new linel_mux = | |
1020 | SOC_DAPM_ENUM("LINEL Mux", linel_enum); | |
1021 | ||
d12bfd62 TI |
1022 | static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0, |
1023 | out_mux_text); | |
a91eb199 MB |
1024 | |
1025 | static const struct snd_kcontrol_new liner_mux = | |
e94a093c | 1026 | SOC_DAPM_ENUM("LINER Mux", liner_enum); |
a91eb199 MB |
1027 | |
1028 | static const char *sidetone_text[] = { | |
1029 | "None", "Left", "Right" | |
1030 | }; | |
1031 | ||
d12bfd62 TI |
1032 | static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2, |
1033 | sidetone_text); | |
a91eb199 MB |
1034 | |
1035 | static const struct snd_kcontrol_new dacl_sidetone_mux = | |
1036 | SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum); | |
1037 | ||
d12bfd62 TI |
1038 | static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0, |
1039 | sidetone_text); | |
a91eb199 MB |
1040 | |
1041 | static const struct snd_kcontrol_new dacr_sidetone_mux = | |
1042 | SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum); | |
1043 | ||
1044 | static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = { | |
1045 | SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0), | |
1046 | SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1047 | SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1048 | ||
1049 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux), | |
1050 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux), | |
1051 | ||
1052 | SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), | |
1053 | SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), | |
1054 | SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux), | |
1055 | SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux), | |
1056 | }; | |
1057 | ||
1058 | static const struct snd_soc_dapm_route core_intercon[] = { | |
1059 | { "CLK_DSP", NULL, "SYSCLK" }, | |
1060 | { "TOCLK", NULL, "SYSCLK" }, | |
1061 | }; | |
1062 | ||
1063 | static const struct snd_soc_dapm_route adc_intercon[] = { | |
1064 | { "Left Capture Mux", "IN1L", "IN1L" }, | |
1065 | { "Left Capture Mux", "IN2L", "IN2L" }, | |
1066 | { "Left Capture Mux", "IN3L", "IN3L" }, | |
1067 | ||
1068 | { "Left Capture Inverting Mux", "IN1L", "IN1L" }, | |
1069 | { "Left Capture Inverting Mux", "IN2L", "IN2L" }, | |
1070 | { "Left Capture Inverting Mux", "IN3L", "IN3L" }, | |
1071 | ||
0a05f2e8 MM |
1072 | { "Left Capture Mode", "Single-Ended", "Left Capture Inverting Mux" }, |
1073 | { "Left Capture Mode", "Differential Line", "Left Capture Mux" }, | |
1074 | { "Left Capture Mode", "Differential Line", "Left Capture Inverting Mux" }, | |
1075 | { "Left Capture Mode", "Differential Mic", "Left Capture Mux" }, | |
1076 | { "Left Capture Mode", "Differential Mic", "Left Capture Inverting Mux" }, | |
1077 | ||
a91eb199 MB |
1078 | { "Right Capture Mux", "IN1R", "IN1R" }, |
1079 | { "Right Capture Mux", "IN2R", "IN2R" }, | |
1080 | { "Right Capture Mux", "IN3R", "IN3R" }, | |
1081 | ||
1082 | { "Right Capture Inverting Mux", "IN1R", "IN1R" }, | |
1083 | { "Right Capture Inverting Mux", "IN2R", "IN2R" }, | |
1084 | { "Right Capture Inverting Mux", "IN3R", "IN3R" }, | |
1085 | ||
0a05f2e8 MM |
1086 | { "Right Capture Mode", "Single-Ended", "Right Capture Inverting Mux" }, |
1087 | { "Right Capture Mode", "Differential Line", "Right Capture Mux" }, | |
1088 | { "Right Capture Mode", "Differential Line", "Right Capture Inverting Mux" }, | |
1089 | { "Right Capture Mode", "Differential Mic", "Right Capture Mux" }, | |
1090 | { "Right Capture Mode", "Differential Mic", "Right Capture Inverting Mux" }, | |
a91eb199 | 1091 | |
0a05f2e8 MM |
1092 | { "Left Capture PGA", NULL, "Left Capture Mode" }, |
1093 | { "Right Capture PGA", NULL, "Right Capture Mode" }, | |
a91eb199 | 1094 | |
a30c188b BS |
1095 | { "AIFOUTL Mux", "Left", "ADCL" }, |
1096 | { "AIFOUTL Mux", "Right", "ADCR" }, | |
1097 | { "AIFOUTR Mux", "Left", "ADCL" }, | |
1098 | { "AIFOUTR Mux", "Right", "ADCR" }, | |
1099 | ||
1100 | { "AIFOUTL", NULL, "AIFOUTL Mux" }, | |
1101 | { "AIFOUTR", NULL, "AIFOUTR Mux" }, | |
a91eb199 MB |
1102 | |
1103 | { "ADCL", NULL, "CLK_DSP" }, | |
1104 | { "ADCL", NULL, "Left Capture PGA" }, | |
1105 | ||
1106 | { "ADCR", NULL, "CLK_DSP" }, | |
1107 | { "ADCR", NULL, "Right Capture PGA" }, | |
1108 | }; | |
1109 | ||
1110 | static const struct snd_soc_dapm_route dac_intercon[] = { | |
a30c188b BS |
1111 | { "DACL Mux", "Left", "AIFINL" }, |
1112 | { "DACL Mux", "Right", "AIFINR" }, | |
1113 | ||
1114 | { "DACR Mux", "Left", "AIFINL" }, | |
1115 | { "DACR Mux", "Right", "AIFINR" }, | |
1116 | ||
1117 | { "DACL", NULL, "DACL Mux" }, | |
a91eb199 MB |
1118 | { "DACL", NULL, "CLK_DSP" }, |
1119 | ||
a30c188b | 1120 | { "DACR", NULL, "DACR Mux" }, |
a91eb199 MB |
1121 | { "DACR", NULL, "CLK_DSP" }, |
1122 | ||
1123 | { "Charge pump", NULL, "SYSCLK" }, | |
1124 | ||
1125 | { "Headphone Output", NULL, "HPL PGA" }, | |
1126 | { "Headphone Output", NULL, "HPR PGA" }, | |
1127 | { "Headphone Output", NULL, "Charge pump" }, | |
1128 | { "Headphone Output", NULL, "TOCLK" }, | |
1129 | ||
1130 | { "Line Output", NULL, "LINEL PGA" }, | |
1131 | { "Line Output", NULL, "LINER PGA" }, | |
1132 | { "Line Output", NULL, "Charge pump" }, | |
1133 | { "Line Output", NULL, "TOCLK" }, | |
1134 | ||
1135 | { "HPOUTL", NULL, "Headphone Output" }, | |
1136 | { "HPOUTR", NULL, "Headphone Output" }, | |
1137 | ||
1138 | { "LINEOUTL", NULL, "Line Output" }, | |
1139 | { "LINEOUTR", NULL, "Line Output" }, | |
1140 | }; | |
1141 | ||
1142 | static const struct snd_soc_dapm_route wm8904_intercon[] = { | |
1143 | { "Left Sidetone", "Left", "ADCL" }, | |
1144 | { "Left Sidetone", "Right", "ADCR" }, | |
1145 | { "DACL", NULL, "Left Sidetone" }, | |
1146 | ||
1147 | { "Right Sidetone", "Left", "ADCL" }, | |
1148 | { "Right Sidetone", "Right", "ADCR" }, | |
1149 | { "DACR", NULL, "Right Sidetone" }, | |
1150 | ||
1151 | { "Left Bypass", NULL, "Class G" }, | |
1152 | { "Left Bypass", NULL, "Left Capture PGA" }, | |
1153 | ||
1154 | { "Right Bypass", NULL, "Class G" }, | |
1155 | { "Right Bypass", NULL, "Right Capture PGA" }, | |
1156 | ||
1157 | { "HPL Mux", "DAC", "DACL" }, | |
1158 | { "HPL Mux", "Bypass", "Left Bypass" }, | |
1159 | ||
1160 | { "HPR Mux", "DAC", "DACR" }, | |
1161 | { "HPR Mux", "Bypass", "Right Bypass" }, | |
1162 | ||
1163 | { "LINEL Mux", "DAC", "DACL" }, | |
1164 | { "LINEL Mux", "Bypass", "Left Bypass" }, | |
1165 | ||
1166 | { "LINER Mux", "DAC", "DACR" }, | |
1167 | { "LINER Mux", "Bypass", "Right Bypass" }, | |
1168 | ||
1169 | { "HPL PGA", NULL, "HPL Mux" }, | |
1170 | { "HPR PGA", NULL, "HPR Mux" }, | |
1171 | ||
1172 | { "LINEL PGA", NULL, "LINEL Mux" }, | |
1173 | { "LINER PGA", NULL, "LINER Mux" }, | |
1174 | }; | |
1175 | ||
8c126474 MB |
1176 | static const struct snd_soc_dapm_route wm8912_intercon[] = { |
1177 | { "HPL PGA", NULL, "DACL" }, | |
1178 | { "HPR PGA", NULL, "DACR" }, | |
1179 | ||
1180 | { "LINEL PGA", NULL, "DACL" }, | |
1181 | { "LINER PGA", NULL, "DACR" }, | |
1182 | }; | |
1183 | ||
46a9100c | 1184 | static int wm8904_add_widgets(struct snd_soc_component *component) |
a91eb199 | 1185 | { |
46a9100c KM |
1186 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); |
1187 | struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); | |
a91eb199 | 1188 | |
ce6120cc | 1189 | snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets, |
a91eb199 | 1190 | ARRAY_SIZE(wm8904_core_dapm_widgets)); |
ce6120cc | 1191 | snd_soc_dapm_add_routes(dapm, core_intercon, |
a91eb199 | 1192 | ARRAY_SIZE(core_intercon)); |
8c126474 MB |
1193 | |
1194 | switch (wm8904->devtype) { | |
1195 | case WM8904: | |
46a9100c | 1196 | snd_soc_add_component_controls(component, wm8904_adc_snd_controls, |
8c126474 | 1197 | ARRAY_SIZE(wm8904_adc_snd_controls)); |
46a9100c | 1198 | snd_soc_add_component_controls(component, wm8904_dac_snd_controls, |
8c126474 | 1199 | ARRAY_SIZE(wm8904_dac_snd_controls)); |
46a9100c | 1200 | snd_soc_add_component_controls(component, wm8904_snd_controls, |
8c126474 MB |
1201 | ARRAY_SIZE(wm8904_snd_controls)); |
1202 | ||
ce6120cc | 1203 | snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets, |
8c126474 | 1204 | ARRAY_SIZE(wm8904_adc_dapm_widgets)); |
ce6120cc | 1205 | snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, |
8c126474 | 1206 | ARRAY_SIZE(wm8904_dac_dapm_widgets)); |
ce6120cc | 1207 | snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets, |
8c126474 MB |
1208 | ARRAY_SIZE(wm8904_dapm_widgets)); |
1209 | ||
ce6120cc | 1210 | snd_soc_dapm_add_routes(dapm, adc_intercon, |
8c126474 | 1211 | ARRAY_SIZE(adc_intercon)); |
ce6120cc | 1212 | snd_soc_dapm_add_routes(dapm, dac_intercon, |
8c126474 | 1213 | ARRAY_SIZE(dac_intercon)); |
ce6120cc | 1214 | snd_soc_dapm_add_routes(dapm, wm8904_intercon, |
8c126474 MB |
1215 | ARRAY_SIZE(wm8904_intercon)); |
1216 | break; | |
1217 | ||
1218 | case WM8912: | |
46a9100c | 1219 | snd_soc_add_component_controls(component, wm8904_dac_snd_controls, |
8c126474 MB |
1220 | ARRAY_SIZE(wm8904_dac_snd_controls)); |
1221 | ||
ce6120cc | 1222 | snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, |
8c126474 MB |
1223 | ARRAY_SIZE(wm8904_dac_dapm_widgets)); |
1224 | ||
ce6120cc | 1225 | snd_soc_dapm_add_routes(dapm, dac_intercon, |
8c126474 | 1226 | ARRAY_SIZE(dac_intercon)); |
ce6120cc | 1227 | snd_soc_dapm_add_routes(dapm, wm8912_intercon, |
8c126474 MB |
1228 | ARRAY_SIZE(wm8912_intercon)); |
1229 | break; | |
1230 | } | |
a91eb199 | 1231 | |
a91eb199 MB |
1232 | return 0; |
1233 | } | |
1234 | ||
1235 | static struct { | |
1236 | int ratio; | |
1237 | unsigned int clk_sys_rate; | |
1238 | } clk_sys_rates[] = { | |
1239 | { 64, 0 }, | |
1240 | { 128, 1 }, | |
1241 | { 192, 2 }, | |
1242 | { 256, 3 }, | |
1243 | { 384, 4 }, | |
1244 | { 512, 5 }, | |
1245 | { 786, 6 }, | |
1246 | { 1024, 7 }, | |
1247 | { 1408, 8 }, | |
1248 | { 1536, 9 }, | |
1249 | }; | |
1250 | ||
1251 | static struct { | |
1252 | int rate; | |
1253 | int sample_rate; | |
1254 | } sample_rates[] = { | |
1255 | { 8000, 0 }, | |
1256 | { 11025, 1 }, | |
1257 | { 12000, 1 }, | |
1258 | { 16000, 2 }, | |
1259 | { 22050, 3 }, | |
1260 | { 24000, 3 }, | |
1261 | { 32000, 4 }, | |
1262 | { 44100, 5 }, | |
1263 | { 48000, 5 }, | |
1264 | }; | |
1265 | ||
1266 | static struct { | |
1267 | int div; /* *10 due to .5s */ | |
1268 | int bclk_div; | |
1269 | } bclk_divs[] = { | |
1270 | { 10, 0 }, | |
1271 | { 15, 1 }, | |
1272 | { 20, 2 }, | |
1273 | { 30, 3 }, | |
1274 | { 40, 4 }, | |
1275 | { 50, 5 }, | |
1276 | { 55, 6 }, | |
1277 | { 60, 7 }, | |
1278 | { 80, 8 }, | |
1279 | { 100, 9 }, | |
1280 | { 110, 10 }, | |
1281 | { 120, 11 }, | |
1282 | { 160, 12 }, | |
1283 | { 200, 13 }, | |
1284 | { 220, 14 }, | |
1285 | { 240, 16 }, | |
1286 | { 200, 17 }, | |
1287 | { 320, 18 }, | |
1288 | { 440, 19 }, | |
1289 | { 480, 20 }, | |
1290 | }; | |
1291 | ||
1292 | ||
1293 | static int wm8904_hw_params(struct snd_pcm_substream *substream, | |
1294 | struct snd_pcm_hw_params *params, | |
1295 | struct snd_soc_dai *dai) | |
1296 | { | |
46a9100c KM |
1297 | struct snd_soc_component *component = dai->component; |
1298 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); | |
a91eb199 MB |
1299 | int ret, i, best, best_val, cur_val; |
1300 | unsigned int aif1 = 0; | |
1301 | unsigned int aif2 = 0; | |
1302 | unsigned int aif3 = 0; | |
1303 | unsigned int clock1 = 0; | |
1304 | unsigned int dac_digital1 = 0; | |
1305 | ||
1306 | /* What BCLK do we need? */ | |
1307 | wm8904->fs = params_rate(params); | |
1308 | if (wm8904->tdm_slots) { | |
46a9100c | 1309 | dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n", |
a91eb199 MB |
1310 | wm8904->tdm_slots, wm8904->tdm_width); |
1311 | wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, | |
1312 | wm8904->tdm_width, 2, | |
1313 | wm8904->tdm_slots); | |
1314 | } else { | |
1315 | wm8904->bclk = snd_soc_params_to_bclk(params); | |
1316 | } | |
1317 | ||
2f44b043 MB |
1318 | switch (params_width(params)) { |
1319 | case 16: | |
56927eb0 | 1320 | break; |
2f44b043 | 1321 | case 20: |
56927eb0 MB |
1322 | aif1 |= 0x40; |
1323 | break; | |
2f44b043 | 1324 | case 24: |
56927eb0 MB |
1325 | aif1 |= 0x80; |
1326 | break; | |
2f44b043 | 1327 | case 32: |
56927eb0 MB |
1328 | aif1 |= 0xc0; |
1329 | break; | |
1330 | default: | |
1331 | return -EINVAL; | |
1332 | } | |
1333 | ||
1334 | ||
46a9100c | 1335 | dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8904->bclk); |
a91eb199 | 1336 | |
46a9100c | 1337 | ret = wm8904_configure_clocking(component); |
a91eb199 MB |
1338 | if (ret != 0) |
1339 | return ret; | |
1340 | ||
1341 | /* Select nearest CLK_SYS_RATE */ | |
1342 | best = 0; | |
1343 | best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) | |
1344 | - wm8904->fs); | |
1345 | for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { | |
1346 | cur_val = abs((wm8904->sysclk_rate / | |
ef995e3a | 1347 | clk_sys_rates[i].ratio) - wm8904->fs); |
a91eb199 MB |
1348 | if (cur_val < best_val) { |
1349 | best = i; | |
1350 | best_val = cur_val; | |
1351 | } | |
1352 | } | |
46a9100c | 1353 | dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n", |
a91eb199 MB |
1354 | clk_sys_rates[best].ratio); |
1355 | clock1 |= (clk_sys_rates[best].clk_sys_rate | |
1356 | << WM8904_CLK_SYS_RATE_SHIFT); | |
1357 | ||
1358 | /* SAMPLE_RATE */ | |
1359 | best = 0; | |
1360 | best_val = abs(wm8904->fs - sample_rates[0].rate); | |
1361 | for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { | |
1362 | /* Closest match */ | |
1363 | cur_val = abs(wm8904->fs - sample_rates[i].rate); | |
1364 | if (cur_val < best_val) { | |
1365 | best = i; | |
1366 | best_val = cur_val; | |
1367 | } | |
1368 | } | |
46a9100c | 1369 | dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n", |
a91eb199 MB |
1370 | sample_rates[best].rate); |
1371 | clock1 |= (sample_rates[best].sample_rate | |
1372 | << WM8904_SAMPLE_RATE_SHIFT); | |
1373 | ||
1374 | /* Enable sloping stopband filter for low sample rates */ | |
1375 | if (wm8904->fs <= 24000) | |
1376 | dac_digital1 |= WM8904_DAC_SB_FILT; | |
1377 | ||
1378 | /* BCLK_DIV */ | |
1379 | best = 0; | |
1380 | best_val = INT_MAX; | |
1381 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
1382 | cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) | |
1383 | - wm8904->bclk; | |
1384 | if (cur_val < 0) /* Table is sorted */ | |
1385 | break; | |
1386 | if (cur_val < best_val) { | |
1387 | best = i; | |
1388 | best_val = cur_val; | |
1389 | } | |
1390 | } | |
1391 | wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; | |
46a9100c | 1392 | dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", |
a91eb199 MB |
1393 | bclk_divs[best].div, wm8904->bclk); |
1394 | aif2 |= bclk_divs[best].bclk_div; | |
1395 | ||
1396 | /* LRCLK is a simple fraction of BCLK */ | |
46a9100c | 1397 | dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); |
a91eb199 MB |
1398 | aif3 |= wm8904->bclk / wm8904->fs; |
1399 | ||
1400 | /* Apply the settings */ | |
46a9100c | 1401 | snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, |
a91eb199 | 1402 | WM8904_DAC_SB_FILT, dac_digital1); |
46a9100c | 1403 | snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1, |
a91eb199 | 1404 | WM8904_AIF_WL_MASK, aif1); |
46a9100c | 1405 | snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_2, |
a91eb199 | 1406 | WM8904_BCLK_DIV_MASK, aif2); |
46a9100c | 1407 | snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3, |
a91eb199 | 1408 | WM8904_LRCLK_RATE_MASK, aif3); |
46a9100c | 1409 | snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_1, |
a91eb199 MB |
1410 | WM8904_SAMPLE_RATE_MASK | |
1411 | WM8904_CLK_SYS_RATE_MASK, clock1); | |
1412 | ||
1413 | /* Update filters for the new settings */ | |
46a9100c KM |
1414 | wm8904_set_retune_mobile(component); |
1415 | wm8904_set_deemph(component); | |
a91eb199 MB |
1416 | |
1417 | return 0; | |
1418 | } | |
1419 | ||
a91eb199 MB |
1420 | static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) |
1421 | { | |
46a9100c | 1422 | struct snd_soc_component *component = dai->component; |
a91eb199 MB |
1423 | unsigned int aif1 = 0; |
1424 | unsigned int aif3 = 0; | |
1425 | ||
1426 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1427 | case SND_SOC_DAIFMT_CBS_CFS: | |
1428 | break; | |
1429 | case SND_SOC_DAIFMT_CBS_CFM: | |
1430 | aif3 |= WM8904_LRCLK_DIR; | |
1431 | break; | |
1432 | case SND_SOC_DAIFMT_CBM_CFS: | |
1433 | aif1 |= WM8904_BCLK_DIR; | |
1434 | break; | |
1435 | case SND_SOC_DAIFMT_CBM_CFM: | |
1436 | aif1 |= WM8904_BCLK_DIR; | |
1437 | aif3 |= WM8904_LRCLK_DIR; | |
1438 | break; | |
1439 | default: | |
1440 | return -EINVAL; | |
1441 | } | |
1442 | ||
1443 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1444 | case SND_SOC_DAIFMT_DSP_B: | |
f0199bc5 | 1445 | aif1 |= 0x3 | WM8904_AIF_LRCLK_INV; |
3e146b55 | 1446 | fallthrough; |
a91eb199 MB |
1447 | case SND_SOC_DAIFMT_DSP_A: |
1448 | aif1 |= 0x3; | |
1449 | break; | |
1450 | case SND_SOC_DAIFMT_I2S: | |
1451 | aif1 |= 0x2; | |
1452 | break; | |
1453 | case SND_SOC_DAIFMT_RIGHT_J: | |
1454 | break; | |
1455 | case SND_SOC_DAIFMT_LEFT_J: | |
1456 | aif1 |= 0x1; | |
1457 | break; | |
1458 | default: | |
1459 | return -EINVAL; | |
1460 | } | |
1461 | ||
1462 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1463 | case SND_SOC_DAIFMT_DSP_A: | |
1464 | case SND_SOC_DAIFMT_DSP_B: | |
1465 | /* frame inversion not valid for DSP modes */ | |
1466 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1467 | case SND_SOC_DAIFMT_NB_NF: | |
1468 | break; | |
1469 | case SND_SOC_DAIFMT_IB_NF: | |
1470 | aif1 |= WM8904_AIF_BCLK_INV; | |
1471 | break; | |
1472 | default: | |
1473 | return -EINVAL; | |
1474 | } | |
1475 | break; | |
1476 | ||
1477 | case SND_SOC_DAIFMT_I2S: | |
1478 | case SND_SOC_DAIFMT_RIGHT_J: | |
1479 | case SND_SOC_DAIFMT_LEFT_J: | |
1480 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1481 | case SND_SOC_DAIFMT_NB_NF: | |
1482 | break; | |
1483 | case SND_SOC_DAIFMT_IB_IF: | |
1484 | aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; | |
1485 | break; | |
1486 | case SND_SOC_DAIFMT_IB_NF: | |
1487 | aif1 |= WM8904_AIF_BCLK_INV; | |
1488 | break; | |
1489 | case SND_SOC_DAIFMT_NB_IF: | |
1490 | aif1 |= WM8904_AIF_LRCLK_INV; | |
1491 | break; | |
1492 | default: | |
1493 | return -EINVAL; | |
1494 | } | |
1495 | break; | |
1496 | default: | |
1497 | return -EINVAL; | |
1498 | } | |
1499 | ||
46a9100c | 1500 | snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1, |
a91eb199 MB |
1501 | WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV | |
1502 | WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); | |
46a9100c | 1503 | snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_3, |
a91eb199 MB |
1504 | WM8904_LRCLK_DIR, aif3); |
1505 | ||
1506 | return 0; | |
1507 | } | |
1508 | ||
1509 | ||
1510 | static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, | |
1511 | unsigned int rx_mask, int slots, int slot_width) | |
1512 | { | |
46a9100c KM |
1513 | struct snd_soc_component *component = dai->component; |
1514 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); | |
a91eb199 MB |
1515 | int aif1 = 0; |
1516 | ||
1517 | /* Don't need to validate anything if we're turning off TDM */ | |
1518 | if (slots == 0) | |
1519 | goto out; | |
1520 | ||
1521 | /* Note that we allow configurations we can't handle ourselves - | |
1522 | * for example, we can generate clocks for slots 2 and up even if | |
1523 | * we can't use those slots ourselves. | |
1524 | */ | |
1525 | aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; | |
1526 | ||
1527 | switch (rx_mask) { | |
1528 | case 3: | |
1529 | break; | |
1530 | case 0xc: | |
1531 | aif1 |= WM8904_AIFADC_TDM_CHAN; | |
1532 | break; | |
1533 | default: | |
1534 | return -EINVAL; | |
1535 | } | |
1536 | ||
1537 | ||
1538 | switch (tx_mask) { | |
1539 | case 3: | |
1540 | break; | |
1541 | case 0xc: | |
1542 | aif1 |= WM8904_AIFDAC_TDM_CHAN; | |
1543 | break; | |
1544 | default: | |
1545 | return -EINVAL; | |
1546 | } | |
1547 | ||
1548 | out: | |
1549 | wm8904->tdm_width = slot_width; | |
1550 | wm8904->tdm_slots = slots / 2; | |
1551 | ||
46a9100c | 1552 | snd_soc_component_update_bits(component, WM8904_AUDIO_INTERFACE_1, |
a91eb199 MB |
1553 | WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN | |
1554 | WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); | |
1555 | ||
1556 | return 0; | |
1557 | } | |
1558 | ||
1559 | struct _fll_div { | |
1560 | u16 fll_fratio; | |
1561 | u16 fll_outdiv; | |
1562 | u16 fll_clk_ref_div; | |
1563 | u16 n; | |
1564 | u16 k; | |
1565 | }; | |
1566 | ||
1567 | /* The size in bits of the FLL divide multiplied by 10 | |
1568 | * to allow rounding later */ | |
1569 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
1570 | ||
1571 | static struct { | |
1572 | unsigned int min; | |
1573 | unsigned int max; | |
1574 | u16 fll_fratio; | |
1575 | int ratio; | |
1576 | } fll_fratios[] = { | |
1577 | { 0, 64000, 4, 16 }, | |
1578 | { 64000, 128000, 3, 8 }, | |
1579 | { 128000, 256000, 2, 4 }, | |
1580 | { 256000, 1000000, 1, 2 }, | |
1581 | { 1000000, 13500000, 0, 1 }, | |
1582 | }; | |
1583 | ||
1584 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | |
1585 | unsigned int Fout) | |
1586 | { | |
1587 | u64 Kpart; | |
1588 | unsigned int K, Ndiv, Nmod, target; | |
1589 | unsigned int div; | |
1590 | int i; | |
1591 | ||
1592 | /* Fref must be <=13.5MHz */ | |
1593 | div = 1; | |
1594 | fll_div->fll_clk_ref_div = 0; | |
1595 | while ((Fref / div) > 13500000) { | |
1596 | div *= 2; | |
1597 | fll_div->fll_clk_ref_div++; | |
1598 | ||
1599 | if (div > 8) { | |
1600 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", | |
1601 | Fref); | |
1602 | return -EINVAL; | |
1603 | } | |
1604 | } | |
1605 | ||
1606 | pr_debug("Fref=%u Fout=%u\n", Fref, Fout); | |
1607 | ||
1608 | /* Apply the division for our remaining calculations */ | |
1609 | Fref /= div; | |
1610 | ||
1611 | /* Fvco should be 90-100MHz; don't check the upper bound */ | |
1612 | div = 4; | |
1613 | while (Fout * div < 90000000) { | |
1614 | div++; | |
1615 | if (div > 64) { | |
1616 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", | |
1617 | Fout); | |
1618 | return -EINVAL; | |
1619 | } | |
1620 | } | |
1621 | target = Fout * div; | |
1622 | fll_div->fll_outdiv = div - 1; | |
1623 | ||
1624 | pr_debug("Fvco=%dHz\n", target); | |
1625 | ||
25985edc | 1626 | /* Find an appropriate FLL_FRATIO and factor it out of the target */ |
a91eb199 MB |
1627 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { |
1628 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { | |
1629 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; | |
1630 | target /= fll_fratios[i].ratio; | |
1631 | break; | |
1632 | } | |
1633 | } | |
1634 | if (i == ARRAY_SIZE(fll_fratios)) { | |
1635 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); | |
1636 | return -EINVAL; | |
1637 | } | |
1638 | ||
1639 | /* Now, calculate N.K */ | |
1640 | Ndiv = target / Fref; | |
1641 | ||
1642 | fll_div->n = Ndiv; | |
1643 | Nmod = target % Fref; | |
1644 | pr_debug("Nmod=%d\n", Nmod); | |
1645 | ||
1646 | /* Calculate fractional part - scale up so we can round. */ | |
1647 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
1648 | ||
1649 | do_div(Kpart, Fref); | |
1650 | ||
1651 | K = Kpart & 0xFFFFFFFF; | |
1652 | ||
1653 | if ((K % 10) >= 5) | |
1654 | K += 5; | |
1655 | ||
1656 | /* Move down to proper range now rounding is done */ | |
1657 | fll_div->k = K / 10; | |
1658 | ||
1659 | pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", | |
1660 | fll_div->n, fll_div->k, | |
1661 | fll_div->fll_fratio, fll_div->fll_outdiv, | |
1662 | fll_div->fll_clk_ref_div); | |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
1667 | static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, | |
1668 | unsigned int Fref, unsigned int Fout) | |
1669 | { | |
46a9100c KM |
1670 | struct snd_soc_component *component = dai->component; |
1671 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); | |
a91eb199 MB |
1672 | struct _fll_div fll_div; |
1673 | int ret, val; | |
1674 | int clock2, fll1; | |
1675 | ||
1676 | /* Any change? */ | |
1677 | if (source == wm8904->fll_src && Fref == wm8904->fll_fref && | |
1678 | Fout == wm8904->fll_fout) | |
1679 | return 0; | |
1680 | ||
6d75dfc3 | 1681 | clock2 = snd_soc_component_read(component, WM8904_CLOCK_RATES_2); |
18240b67 | 1682 | |
a91eb199 | 1683 | if (Fout == 0) { |
46a9100c | 1684 | dev_dbg(component->dev, "FLL disabled\n"); |
a91eb199 MB |
1685 | |
1686 | wm8904->fll_fref = 0; | |
1687 | wm8904->fll_fout = 0; | |
1688 | ||
1689 | /* Gate SYSCLK to avoid glitches */ | |
46a9100c | 1690 | snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, |
a91eb199 MB |
1691 | WM8904_CLK_SYS_ENA, 0); |
1692 | ||
46a9100c | 1693 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, |
a91eb199 MB |
1694 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); |
1695 | ||
1696 | goto out; | |
1697 | } | |
1698 | ||
1699 | /* Validate the FLL ID */ | |
1700 | switch (source) { | |
1701 | case WM8904_FLL_MCLK: | |
1702 | case WM8904_FLL_LRCLK: | |
1703 | case WM8904_FLL_BCLK: | |
1704 | ret = fll_factors(&fll_div, Fref, Fout); | |
1705 | if (ret != 0) | |
1706 | return ret; | |
1707 | break; | |
1708 | ||
1709 | case WM8904_FLL_FREE_RUNNING: | |
46a9100c | 1710 | dev_dbg(component->dev, "Using free running FLL\n"); |
a91eb199 MB |
1711 | /* Force 12MHz and output/4 for now */ |
1712 | Fout = 12000000; | |
1713 | Fref = 12000000; | |
1714 | ||
1715 | memset(&fll_div, 0, sizeof(fll_div)); | |
1716 | fll_div.fll_outdiv = 3; | |
1717 | break; | |
1718 | ||
1719 | default: | |
46a9100c | 1720 | dev_err(component->dev, "Unknown FLL ID %d\n", fll_id); |
a91eb199 MB |
1721 | return -EINVAL; |
1722 | } | |
1723 | ||
1724 | /* Save current state then disable the FLL and SYSCLK to avoid | |
1725 | * misclocking */ | |
6d75dfc3 | 1726 | fll1 = snd_soc_component_read(component, WM8904_FLL_CONTROL_1); |
46a9100c | 1727 | snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, |
a91eb199 | 1728 | WM8904_CLK_SYS_ENA, 0); |
46a9100c | 1729 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, |
a91eb199 MB |
1730 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); |
1731 | ||
1732 | /* Unlock forced oscilator control to switch it on/off */ | |
46a9100c | 1733 | snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1, |
a91eb199 MB |
1734 | WM8904_USER_KEY, WM8904_USER_KEY); |
1735 | ||
1736 | if (fll_id == WM8904_FLL_FREE_RUNNING) { | |
1737 | val = WM8904_FLL_FRC_NCO; | |
1738 | } else { | |
1739 | val = 0; | |
1740 | } | |
1741 | ||
46a9100c | 1742 | snd_soc_component_update_bits(component, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO, |
a91eb199 | 1743 | val); |
46a9100c | 1744 | snd_soc_component_update_bits(component, WM8904_CONTROL_INTERFACE_TEST_1, |
a91eb199 MB |
1745 | WM8904_USER_KEY, 0); |
1746 | ||
1747 | switch (fll_id) { | |
1748 | case WM8904_FLL_MCLK: | |
46a9100c | 1749 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, |
a91eb199 MB |
1750 | WM8904_FLL_CLK_REF_SRC_MASK, 0); |
1751 | break; | |
1752 | ||
1753 | case WM8904_FLL_LRCLK: | |
46a9100c | 1754 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, |
a91eb199 MB |
1755 | WM8904_FLL_CLK_REF_SRC_MASK, 1); |
1756 | break; | |
1757 | ||
1758 | case WM8904_FLL_BCLK: | |
46a9100c | 1759 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, |
a91eb199 MB |
1760 | WM8904_FLL_CLK_REF_SRC_MASK, 2); |
1761 | break; | |
1762 | } | |
1763 | ||
1764 | if (fll_div.k) | |
1765 | val = WM8904_FLL_FRACN_ENA; | |
1766 | else | |
1767 | val = 0; | |
46a9100c | 1768 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, |
a91eb199 MB |
1769 | WM8904_FLL_FRACN_ENA, val); |
1770 | ||
46a9100c | 1771 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_2, |
a91eb199 MB |
1772 | WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK, |
1773 | (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) | | |
1774 | (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT)); | |
1775 | ||
46a9100c | 1776 | snd_soc_component_write(component, WM8904_FLL_CONTROL_3, fll_div.k); |
a91eb199 | 1777 | |
46a9100c | 1778 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK, |
a91eb199 MB |
1779 | fll_div.n << WM8904_FLL_N_SHIFT); |
1780 | ||
46a9100c | 1781 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_5, |
a91eb199 MB |
1782 | WM8904_FLL_CLK_REF_DIV_MASK, |
1783 | fll_div.fll_clk_ref_div | |
1784 | << WM8904_FLL_CLK_REF_DIV_SHIFT); | |
1785 | ||
46a9100c | 1786 | dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); |
a91eb199 MB |
1787 | |
1788 | wm8904->fll_fref = Fref; | |
1789 | wm8904->fll_fout = Fout; | |
1790 | wm8904->fll_src = source; | |
1791 | ||
1792 | /* Enable the FLL if it was previously active */ | |
46a9100c | 1793 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, |
a91eb199 | 1794 | WM8904_FLL_OSC_ENA, fll1); |
46a9100c | 1795 | snd_soc_component_update_bits(component, WM8904_FLL_CONTROL_1, |
a91eb199 MB |
1796 | WM8904_FLL_ENA, fll1); |
1797 | ||
1798 | out: | |
1799 | /* Reenable SYSCLK if it was previously active */ | |
46a9100c | 1800 | snd_soc_component_update_bits(component, WM8904_CLOCK_RATES_2, |
a91eb199 MB |
1801 | WM8904_CLK_SYS_ENA, clock2); |
1802 | ||
1803 | return 0; | |
1804 | } | |
1805 | ||
13409d27 MW |
1806 | static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
1807 | unsigned int freq, int dir) | |
1808 | { | |
1809 | struct snd_soc_component *component = dai->component; | |
1810 | struct wm8904_priv *priv = snd_soc_component_get_drvdata(component); | |
1811 | unsigned long mclk_freq; | |
1812 | int ret; | |
1813 | ||
1814 | switch (clk_id) { | |
1815 | case WM8904_CLK_AUTO: | |
2a0bda27 MW |
1816 | /* We don't have any rate constraints, so just ignore the |
1817 | * request to disable constraining. | |
1818 | */ | |
1819 | if (!freq) | |
1820 | return 0; | |
1821 | ||
13409d27 MW |
1822 | mclk_freq = clk_get_rate(priv->mclk); |
1823 | /* enable FLL if a different sysclk is desired */ | |
1824 | if (mclk_freq != freq) { | |
1825 | priv->sysclk_src = WM8904_CLK_FLL; | |
1826 | ret = wm8904_set_fll(dai, WM8904_FLL_MCLK, | |
1827 | WM8904_FLL_MCLK, | |
1828 | mclk_freq, freq); | |
1829 | if (ret) | |
1830 | return ret; | |
1831 | break; | |
1832 | } | |
1833 | clk_id = WM8904_CLK_MCLK; | |
3e146b55 | 1834 | fallthrough; |
13409d27 MW |
1835 | |
1836 | case WM8904_CLK_MCLK: | |
1837 | priv->sysclk_src = clk_id; | |
1838 | priv->mclk_rate = freq; | |
1839 | break; | |
1840 | ||
1841 | case WM8904_CLK_FLL: | |
1842 | priv->sysclk_src = clk_id; | |
1843 | break; | |
1844 | ||
1845 | default: | |
1846 | return -EINVAL; | |
1847 | } | |
1848 | ||
1849 | dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); | |
1850 | ||
1851 | wm8904_configure_clocking(component); | |
1852 | ||
1853 | return 0; | |
1854 | } | |
1855 | ||
26d3c16e | 1856 | static int wm8904_mute(struct snd_soc_dai *codec_dai, int mute, int direction) |
a91eb199 | 1857 | { |
46a9100c | 1858 | struct snd_soc_component *component = codec_dai->component; |
a91eb199 MB |
1859 | int val; |
1860 | ||
1861 | if (mute) | |
1862 | val = WM8904_DAC_MUTE; | |
1863 | else | |
1864 | val = 0; | |
1865 | ||
46a9100c | 1866 | snd_soc_component_update_bits(component, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); |
a91eb199 MB |
1867 | |
1868 | return 0; | |
1869 | } | |
1870 | ||
46a9100c | 1871 | static int wm8904_set_bias_level(struct snd_soc_component *component, |
a91eb199 MB |
1872 | enum snd_soc_bias_level level) |
1873 | { | |
46a9100c | 1874 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); |
c1334218 | 1875 | int ret; |
a91eb199 MB |
1876 | |
1877 | switch (level) { | |
1878 | case SND_SOC_BIAS_ON: | |
1879 | break; | |
1880 | ||
1881 | case SND_SOC_BIAS_PREPARE: | |
1882 | /* VMID resistance 2*50k */ | |
46a9100c | 1883 | snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, |
a91eb199 MB |
1884 | WM8904_VMID_RES_MASK, |
1885 | 0x1 << WM8904_VMID_RES_SHIFT); | |
1886 | ||
1887 | /* Normal bias current */ | |
46a9100c | 1888 | snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, |
a91eb199 MB |
1889 | WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT); |
1890 | break; | |
1891 | ||
1892 | case SND_SOC_BIAS_STANDBY: | |
46a9100c | 1893 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
a91eb199 MB |
1894 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), |
1895 | wm8904->supplies); | |
1896 | if (ret != 0) { | |
46a9100c | 1897 | dev_err(component->dev, |
a91eb199 MB |
1898 | "Failed to enable supplies: %d\n", |
1899 | ret); | |
1900 | return ret; | |
1901 | } | |
1902 | ||
5489e81f MM |
1903 | ret = clk_prepare_enable(wm8904->mclk); |
1904 | if (ret) { | |
1905 | dev_err(component->dev, | |
1906 | "Failed to enable MCLK: %d\n", ret); | |
1907 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), | |
1908 | wm8904->supplies); | |
1909 | return ret; | |
1910 | } | |
1911 | ||
c1b88ee2 | 1912 | regcache_cache_only(wm8904->regmap, false); |
84d0d831 | 1913 | regcache_sync(wm8904->regmap); |
a91eb199 MB |
1914 | |
1915 | /* Enable bias */ | |
46a9100c | 1916 | snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, |
a91eb199 MB |
1917 | WM8904_BIAS_ENA, WM8904_BIAS_ENA); |
1918 | ||
1919 | /* Enable VMID, VMID buffering, 2*5k resistance */ | |
46a9100c | 1920 | snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, |
a91eb199 MB |
1921 | WM8904_VMID_ENA | |
1922 | WM8904_VMID_RES_MASK, | |
1923 | WM8904_VMID_ENA | | |
1924 | 0x3 << WM8904_VMID_RES_SHIFT); | |
1925 | ||
1926 | /* Let VMID ramp */ | |
1927 | msleep(1); | |
1928 | } | |
1929 | ||
1930 | /* Maintain VMID with 2*250k */ | |
46a9100c | 1931 | snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, |
a91eb199 MB |
1932 | WM8904_VMID_RES_MASK, |
1933 | 0x2 << WM8904_VMID_RES_SHIFT); | |
1934 | ||
1935 | /* Bias current *0.5 */ | |
46a9100c | 1936 | snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, |
a91eb199 MB |
1937 | WM8904_ISEL_MASK, 0); |
1938 | break; | |
1939 | ||
1940 | case SND_SOC_BIAS_OFF: | |
1941 | /* Turn off VMID */ | |
46a9100c | 1942 | snd_soc_component_update_bits(component, WM8904_VMID_CONTROL_0, |
a91eb199 MB |
1943 | WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0); |
1944 | ||
1945 | /* Stop bias generation */ | |
46a9100c | 1946 | snd_soc_component_update_bits(component, WM8904_BIAS_CONTROL_0, |
a91eb199 MB |
1947 | WM8904_BIAS_ENA, 0); |
1948 | ||
e9149b8c | 1949 | snd_soc_component_write(component, WM8904_SW_RESET_AND_ID, 0); |
c1b88ee2 MB |
1950 | regcache_cache_only(wm8904->regmap, true); |
1951 | regcache_mark_dirty(wm8904->regmap); | |
c1334218 | 1952 | |
a91eb199 MB |
1953 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), |
1954 | wm8904->supplies); | |
8b9920e3 | 1955 | clk_disable_unprepare(wm8904->mclk); |
a91eb199 MB |
1956 | break; |
1957 | } | |
a91eb199 MB |
1958 | return 0; |
1959 | } | |
1960 | ||
1961 | #define WM8904_RATES SNDRV_PCM_RATE_8000_96000 | |
1962 | ||
1963 | #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
1964 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
1965 | ||
85e7652d | 1966 | static const struct snd_soc_dai_ops wm8904_dai_ops = { |
a91eb199 MB |
1967 | .set_sysclk = wm8904_set_sysclk, |
1968 | .set_fmt = wm8904_set_fmt, | |
1969 | .set_tdm_slot = wm8904_set_tdm_slot, | |
1970 | .set_pll = wm8904_set_fll, | |
1971 | .hw_params = wm8904_hw_params, | |
26d3c16e KM |
1972 | .mute_stream = wm8904_mute, |
1973 | .no_capture_mute = 1, | |
a91eb199 MB |
1974 | }; |
1975 | ||
f0fba2ad LG |
1976 | static struct snd_soc_dai_driver wm8904_dai = { |
1977 | .name = "wm8904-hifi", | |
a91eb199 MB |
1978 | .playback = { |
1979 | .stream_name = "Playback", | |
1980 | .channels_min = 2, | |
1981 | .channels_max = 2, | |
1982 | .rates = WM8904_RATES, | |
1983 | .formats = WM8904_FORMATS, | |
1984 | }, | |
1985 | .capture = { | |
1986 | .stream_name = "Capture", | |
1987 | .channels_min = 2, | |
1988 | .channels_max = 2, | |
1989 | .rates = WM8904_RATES, | |
1990 | .formats = WM8904_FORMATS, | |
1991 | }, | |
1992 | .ops = &wm8904_dai_ops, | |
07695752 | 1993 | .symmetric_rate = 1, |
a91eb199 | 1994 | }; |
a91eb199 | 1995 | |
46a9100c | 1996 | static void wm8904_handle_retune_mobile_pdata(struct snd_soc_component *component) |
a91eb199 | 1997 | { |
46a9100c | 1998 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); |
a91eb199 MB |
1999 | struct wm8904_pdata *pdata = wm8904->pdata; |
2000 | struct snd_kcontrol_new control = | |
2001 | SOC_ENUM_EXT("EQ Mode", | |
2002 | wm8904->retune_mobile_enum, | |
2003 | wm8904_get_retune_mobile_enum, | |
2004 | wm8904_put_retune_mobile_enum); | |
2005 | int ret, i, j; | |
2006 | const char **t; | |
2007 | ||
2008 | /* We need an array of texts for the enum API but the number | |
2009 | * of texts is likely to be less than the number of | |
2010 | * configurations due to the sample rate dependency of the | |
2011 | * configurations. */ | |
2012 | wm8904->num_retune_mobile_texts = 0; | |
2013 | wm8904->retune_mobile_texts = NULL; | |
2014 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
2015 | for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { | |
2016 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
2017 | wm8904->retune_mobile_texts[j]) == 0) | |
2018 | break; | |
2019 | } | |
2020 | ||
2021 | if (j != wm8904->num_retune_mobile_texts) | |
2022 | continue; | |
2023 | ||
2024 | /* Expand the array... */ | |
2025 | t = krealloc(wm8904->retune_mobile_texts, | |
2026 | sizeof(char *) * | |
2027 | (wm8904->num_retune_mobile_texts + 1), | |
2028 | GFP_KERNEL); | |
2029 | if (t == NULL) | |
2030 | continue; | |
2031 | ||
2032 | /* ...store the new entry... */ | |
2033 | t[wm8904->num_retune_mobile_texts] = | |
2034 | pdata->retune_mobile_cfgs[i].name; | |
2035 | ||
2036 | /* ...and remember the new version. */ | |
2037 | wm8904->num_retune_mobile_texts++; | |
2038 | wm8904->retune_mobile_texts = t; | |
2039 | } | |
2040 | ||
46a9100c | 2041 | dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n", |
a91eb199 MB |
2042 | wm8904->num_retune_mobile_texts); |
2043 | ||
9a8d38db | 2044 | wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts; |
a91eb199 MB |
2045 | wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; |
2046 | ||
46a9100c | 2047 | ret = snd_soc_add_component_controls(component, &control, 1); |
a91eb199 | 2048 | if (ret != 0) |
46a9100c | 2049 | dev_err(component->dev, |
a91eb199 MB |
2050 | "Failed to add ReTune Mobile control: %d\n", ret); |
2051 | } | |
2052 | ||
46a9100c | 2053 | static void wm8904_handle_pdata(struct snd_soc_component *component) |
a91eb199 | 2054 | { |
46a9100c | 2055 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); |
a91eb199 MB |
2056 | struct wm8904_pdata *pdata = wm8904->pdata; |
2057 | int ret, i; | |
2058 | ||
2059 | if (!pdata) { | |
46a9100c | 2060 | snd_soc_add_component_controls(component, wm8904_eq_controls, |
a91eb199 MB |
2061 | ARRAY_SIZE(wm8904_eq_controls)); |
2062 | return; | |
2063 | } | |
2064 | ||
46a9100c | 2065 | dev_dbg(component->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); |
a91eb199 MB |
2066 | |
2067 | if (pdata->num_drc_cfgs) { | |
2068 | struct snd_kcontrol_new control = | |
2069 | SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, | |
2070 | wm8904_get_drc_enum, wm8904_put_drc_enum); | |
2071 | ||
2072 | /* We need an array of texts for the enum API */ | |
6da2ec56 KC |
2073 | wm8904->drc_texts = kmalloc_array(pdata->num_drc_cfgs, |
2074 | sizeof(char *), | |
2075 | GFP_KERNEL); | |
d931099b | 2076 | if (!wm8904->drc_texts) |
a91eb199 | 2077 | return; |
a91eb199 MB |
2078 | |
2079 | for (i = 0; i < pdata->num_drc_cfgs; i++) | |
2080 | wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; | |
2081 | ||
9a8d38db | 2082 | wm8904->drc_enum.items = pdata->num_drc_cfgs; |
a91eb199 MB |
2083 | wm8904->drc_enum.texts = wm8904->drc_texts; |
2084 | ||
46a9100c | 2085 | ret = snd_soc_add_component_controls(component, &control, 1); |
a91eb199 | 2086 | if (ret != 0) |
46a9100c | 2087 | dev_err(component->dev, |
a91eb199 MB |
2088 | "Failed to add DRC mode control: %d\n", ret); |
2089 | ||
46a9100c | 2090 | wm8904_set_drc(component); |
a91eb199 MB |
2091 | } |
2092 | ||
46a9100c | 2093 | dev_dbg(component->dev, "%d ReTune Mobile configurations\n", |
a91eb199 MB |
2094 | pdata->num_retune_mobile_cfgs); |
2095 | ||
2096 | if (pdata->num_retune_mobile_cfgs) | |
46a9100c | 2097 | wm8904_handle_retune_mobile_pdata(component); |
a91eb199 | 2098 | else |
46a9100c | 2099 | snd_soc_add_component_controls(component, wm8904_eq_controls, |
a91eb199 MB |
2100 | ARRAY_SIZE(wm8904_eq_controls)); |
2101 | } | |
2102 | ||
a91eb199 | 2103 | |
46a9100c | 2104 | static int wm8904_probe(struct snd_soc_component *component) |
a91eb199 | 2105 | { |
46a9100c | 2106 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); |
a91eb199 | 2107 | |
8c126474 MB |
2108 | switch (wm8904->devtype) { |
2109 | case WM8904: | |
2110 | break; | |
2111 | case WM8912: | |
2112 | memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture)); | |
2113 | break; | |
2114 | default: | |
46a9100c | 2115 | dev_err(component->dev, "Unknown device type %d\n", |
8c126474 | 2116 | wm8904->devtype); |
f0fba2ad | 2117 | return -EINVAL; |
8c126474 MB |
2118 | } |
2119 | ||
46a9100c | 2120 | wm8904_handle_pdata(component); |
a91eb199 | 2121 | |
46a9100c | 2122 | wm8904_add_widgets(component); |
a91eb199 MB |
2123 | |
2124 | return 0; | |
a91eb199 MB |
2125 | } |
2126 | ||
46a9100c | 2127 | static void wm8904_remove(struct snd_soc_component *component) |
a91eb199 | 2128 | { |
46a9100c | 2129 | struct wm8904_priv *wm8904 = snd_soc_component_get_drvdata(component); |
f0fba2ad | 2130 | |
cd70978c AL |
2131 | kfree(wm8904->retune_mobile_texts); |
2132 | kfree(wm8904->drc_texts); | |
a91eb199 MB |
2133 | } |
2134 | ||
46a9100c KM |
2135 | static const struct snd_soc_component_driver soc_component_dev_wm8904 = { |
2136 | .probe = wm8904_probe, | |
2137 | .remove = wm8904_remove, | |
2138 | .set_bias_level = wm8904_set_bias_level, | |
2139 | .use_pmdown_time = 1, | |
2140 | .endianness = 1, | |
84d0d831 MB |
2141 | }; |
2142 | ||
2143 | static const struct regmap_config wm8904_regmap = { | |
2144 | .reg_bits = 8, | |
2145 | .val_bits = 16, | |
2146 | ||
2147 | .max_register = WM8904_MAX_REGISTER, | |
2148 | .volatile_reg = wm8904_volatile_register, | |
2149 | .readable_reg = wm8904_readable_register, | |
2150 | ||
9bd4bc4c | 2151 | .cache_type = REGCACHE_MAPLE, |
84d0d831 MB |
2152 | .reg_defaults = wm8904_reg_defaults, |
2153 | .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults), | |
f0fba2ad LG |
2154 | }; |
2155 | ||
b1a5fad5 | 2156 | #ifdef CONFIG_OF |
b1a5fad5 AM |
2157 | static const struct of_device_id wm8904_of_match[] = { |
2158 | { | |
2159 | .compatible = "wlf,wm8904", | |
fb82c6ed | 2160 | .data = (void *)WM8904, |
b1a5fad5 AM |
2161 | }, { |
2162 | .compatible = "wlf,wm8912", | |
fb82c6ed | 2163 | .data = (void *)WM8912, |
b1a5fad5 AM |
2164 | }, { |
2165 | /* sentinel */ | |
2166 | } | |
2167 | }; | |
2168 | MODULE_DEVICE_TABLE(of, wm8904_of_match); | |
2169 | #endif | |
2170 | ||
6d8f318b SK |
2171 | static const struct i2c_device_id wm8904_i2c_id[]; |
2172 | ||
2173 | static int wm8904_i2c_probe(struct i2c_client *i2c) | |
a91eb199 MB |
2174 | { |
2175 | struct wm8904_priv *wm8904; | |
03862cf6 MB |
2176 | unsigned int val; |
2177 | int ret, i; | |
a91eb199 | 2178 | |
93e26d4e MB |
2179 | wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv), |
2180 | GFP_KERNEL); | |
a91eb199 MB |
2181 | if (wm8904 == NULL) |
2182 | return -ENOMEM; | |
2183 | ||
8b9920e3 BS |
2184 | wm8904->mclk = devm_clk_get(&i2c->dev, "mclk"); |
2185 | if (IS_ERR(wm8904->mclk)) { | |
2186 | ret = PTR_ERR(wm8904->mclk); | |
2187 | dev_err(&i2c->dev, "Failed to get MCLK\n"); | |
2188 | return ret; | |
2189 | } | |
2190 | ||
d633edd9 | 2191 | wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap); |
84d0d831 MB |
2192 | if (IS_ERR(wm8904->regmap)) { |
2193 | ret = PTR_ERR(wm8904->regmap); | |
2194 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
2195 | ret); | |
2196 | return ret; | |
2197 | } | |
2198 | ||
b1a5fad5 AM |
2199 | if (i2c->dev.of_node) { |
2200 | const struct of_device_id *match; | |
2201 | ||
2202 | match = of_match_node(wm8904_of_match, i2c->dev.of_node); | |
2203 | if (match == NULL) | |
2204 | return -EINVAL; | |
5a180332 | 2205 | wm8904->devtype = (uintptr_t)match->data; |
b1a5fad5 | 2206 | } else { |
6d8f318b SK |
2207 | const struct i2c_device_id *id = |
2208 | i2c_match_id(wm8904_i2c_id, i2c); | |
b1a5fad5 AM |
2209 | wm8904->devtype = id->driver_data; |
2210 | } | |
2211 | ||
a91eb199 | 2212 | i2c_set_clientdata(i2c, wm8904); |
a91eb199 MB |
2213 | wm8904->pdata = i2c->dev.platform_data; |
2214 | ||
03862cf6 MB |
2215 | for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) |
2216 | wm8904->supplies[i].supply = wm8904_supply_names[i]; | |
2217 | ||
2218 | ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies), | |
2219 | wm8904->supplies); | |
2220 | if (ret != 0) { | |
2221 | dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); | |
2222 | return ret; | |
2223 | } | |
2224 | ||
2225 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), | |
2226 | wm8904->supplies); | |
2227 | if (ret != 0) { | |
2228 | dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); | |
2229 | return ret; | |
2230 | } | |
2231 | ||
2232 | ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val); | |
2233 | if (ret < 0) { | |
2234 | dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); | |
2235 | goto err_enable; | |
2236 | } | |
2237 | if (val != 0x8904) { | |
2238 | dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val); | |
2239 | ret = -EINVAL; | |
2240 | goto err_enable; | |
2241 | } | |
2242 | ||
2243 | ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val); | |
2244 | if (ret < 0) { | |
2245 | dev_err(&i2c->dev, "Failed to read device revision: %d\n", | |
2246 | ret); | |
2247 | goto err_enable; | |
2248 | } | |
2249 | dev_info(&i2c->dev, "revision %c\n", val + 'A'); | |
2250 | ||
2251 | ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0); | |
2252 | if (ret < 0) { | |
2253 | dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); | |
2254 | goto err_enable; | |
2255 | } | |
2256 | ||
725e7a7b MB |
2257 | /* Change some default settings - latch VU and enable ZC */ |
2258 | regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT, | |
2259 | WM8904_ADC_VU, WM8904_ADC_VU); | |
2260 | regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT, | |
2261 | WM8904_ADC_VU, WM8904_ADC_VU); | |
2262 | regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT, | |
2263 | WM8904_DAC_VU, WM8904_DAC_VU); | |
2264 | regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT, | |
2265 | WM8904_DAC_VU, WM8904_DAC_VU); | |
2266 | regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT, | |
2267 | WM8904_HPOUT_VU | WM8904_HPOUTLZC, | |
2268 | WM8904_HPOUT_VU | WM8904_HPOUTLZC); | |
2269 | regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT, | |
2270 | WM8904_HPOUT_VU | WM8904_HPOUTRZC, | |
2271 | WM8904_HPOUT_VU | WM8904_HPOUTRZC); | |
2272 | regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT, | |
2273 | WM8904_LINEOUT_VU | WM8904_LINEOUTLZC, | |
2274 | WM8904_LINEOUT_VU | WM8904_LINEOUTLZC); | |
2275 | regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT, | |
2276 | WM8904_LINEOUT_VU | WM8904_LINEOUTRZC, | |
2277 | WM8904_LINEOUT_VU | WM8904_LINEOUTRZC); | |
2278 | regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0, | |
2279 | WM8904_SR_MODE, 0); | |
2280 | ||
2281 | /* Apply configuration from the platform data. */ | |
2282 | if (wm8904->pdata) { | |
2283 | for (i = 0; i < WM8904_GPIO_REGS; i++) { | |
2284 | if (!wm8904->pdata->gpio_cfg[i]) | |
2285 | continue; | |
2286 | ||
2287 | regmap_update_bits(wm8904->regmap, | |
2288 | WM8904_GPIO_CONTROL_1 + i, | |
2289 | 0xffff, | |
2290 | wm8904->pdata->gpio_cfg[i]); | |
2291 | } | |
2292 | ||
2293 | /* Zero is the default value for these anyway */ | |
2294 | for (i = 0; i < WM8904_MIC_REGS; i++) | |
2295 | regmap_update_bits(wm8904->regmap, | |
2296 | WM8904_MIC_BIAS_CONTROL_0 + i, | |
2297 | 0xffff, | |
2298 | wm8904->pdata->mic_cfg[i]); | |
2299 | } | |
2300 | ||
2301 | /* Set Class W by default - this will be managed by the Class | |
2302 | * G widget at runtime where bypass paths are available. | |
2303 | */ | |
2304 | regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0, | |
2305 | WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR); | |
2306 | ||
2307 | /* Use normal bias source */ | |
2308 | regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0, | |
2309 | WM8904_POBCTRL, 0); | |
2310 | ||
f061e2be MB |
2311 | /* Fill the cache for the ADC test register */ |
2312 | regmap_read(wm8904->regmap, WM8904_ADC_TEST_0, &val); | |
2313 | ||
03862cf6 MB |
2314 | /* Can leave the device powered off until we need it */ |
2315 | regcache_cache_only(wm8904->regmap, true); | |
2316 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
2317 | ||
46a9100c KM |
2318 | ret = devm_snd_soc_register_component(&i2c->dev, |
2319 | &soc_component_dev_wm8904, &wm8904_dai, 1); | |
84d0d831 | 2320 | if (ret != 0) |
03862cf6 | 2321 | return ret; |
84d0d831 MB |
2322 | |
2323 | return 0; | |
93e26d4e | 2324 | |
03862cf6 MB |
2325 | err_enable: |
2326 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
f0fba2ad | 2327 | return ret; |
a91eb199 MB |
2328 | } |
2329 | ||
a91eb199 | 2330 | static const struct i2c_device_id wm8904_i2c_id[] = { |
8c126474 MB |
2331 | { "wm8904", WM8904 }, |
2332 | { "wm8912", WM8912 }, | |
df1553c8 | 2333 | { "wm8918", WM8904 }, /* Actually a subset, updates to follow */ |
a91eb199 MB |
2334 | { } |
2335 | }; | |
2336 | MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id); | |
2337 | ||
2338 | static struct i2c_driver wm8904_i2c_driver = { | |
2339 | .driver = { | |
091edccf | 2340 | .name = "wm8904", |
b1a5fad5 | 2341 | .of_match_table = of_match_ptr(wm8904_of_match), |
a91eb199 | 2342 | }, |
9abcd240 | 2343 | .probe = wm8904_i2c_probe, |
a91eb199 MB |
2344 | .id_table = wm8904_i2c_id, |
2345 | }; | |
a91eb199 | 2346 | |
8cb28fd6 | 2347 | module_i2c_driver(wm8904_i2c_driver); |
a91eb199 MB |
2348 | |
2349 | MODULE_DESCRIPTION("ASoC WM8904 driver"); | |
2350 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
2351 | MODULE_LICENSE("GPL"); |