Commit | Line | Data |
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f1c0a02f MB |
1 | /* |
2 | * wm8903.c -- WM8903 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2008 Wolfson Microelectronics | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * TODO: | |
13 | * - TDM mode configuration. | |
f1c0a02f | 14 | * - Digital microphone support. |
f1c0a02f MB |
15 | */ |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/moduleparam.h> | |
19 | #include <linux/init.h> | |
8abd16a6 | 20 | #include <linux/completion.h> |
f1c0a02f MB |
21 | #include <linux/delay.h> |
22 | #include <linux/pm.h> | |
23 | #include <linux/i2c.h> | |
24 | #include <linux/platform_device.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
f1c0a02f | 26 | #include <sound/core.h> |
7245387e | 27 | #include <sound/jack.h> |
f1c0a02f MB |
28 | #include <sound/pcm.h> |
29 | #include <sound/pcm_params.h> | |
30 | #include <sound/tlv.h> | |
31 | #include <sound/soc.h> | |
32 | #include <sound/soc-dapm.h> | |
33 | #include <sound/initval.h> | |
8abd16a6 | 34 | #include <sound/wm8903.h> |
f1c0a02f MB |
35 | |
36 | #include "wm8903.h" | |
37 | ||
f1c0a02f MB |
38 | /* Register defaults at reset */ |
39 | static u16 wm8903_reg_defaults[] = { | |
40 | 0x8903, /* R0 - SW Reset and ID */ | |
41 | 0x0000, /* R1 - Revision Number */ | |
42 | 0x0000, /* R2 */ | |
43 | 0x0000, /* R3 */ | |
44 | 0x0018, /* R4 - Bias Control 0 */ | |
45 | 0x0000, /* R5 - VMID Control 0 */ | |
46 | 0x0000, /* R6 - Mic Bias Control 0 */ | |
47 | 0x0000, /* R7 */ | |
48 | 0x0001, /* R8 - Analogue DAC 0 */ | |
49 | 0x0000, /* R9 */ | |
50 | 0x0001, /* R10 - Analogue ADC 0 */ | |
51 | 0x0000, /* R11 */ | |
52 | 0x0000, /* R12 - Power Management 0 */ | |
53 | 0x0000, /* R13 - Power Management 1 */ | |
54 | 0x0000, /* R14 - Power Management 2 */ | |
55 | 0x0000, /* R15 - Power Management 3 */ | |
56 | 0x0000, /* R16 - Power Management 4 */ | |
57 | 0x0000, /* R17 - Power Management 5 */ | |
58 | 0x0000, /* R18 - Power Management 6 */ | |
59 | 0x0000, /* R19 */ | |
60 | 0x0400, /* R20 - Clock Rates 0 */ | |
61 | 0x0D07, /* R21 - Clock Rates 1 */ | |
62 | 0x0000, /* R22 - Clock Rates 2 */ | |
63 | 0x0000, /* R23 */ | |
64 | 0x0050, /* R24 - Audio Interface 0 */ | |
65 | 0x0242, /* R25 - Audio Interface 1 */ | |
66 | 0x0008, /* R26 - Audio Interface 2 */ | |
67 | 0x0022, /* R27 - Audio Interface 3 */ | |
68 | 0x0000, /* R28 */ | |
69 | 0x0000, /* R29 */ | |
70 | 0x00C0, /* R30 - DAC Digital Volume Left */ | |
71 | 0x00C0, /* R31 - DAC Digital Volume Right */ | |
72 | 0x0000, /* R32 - DAC Digital 0 */ | |
73 | 0x0000, /* R33 - DAC Digital 1 */ | |
74 | 0x0000, /* R34 */ | |
75 | 0x0000, /* R35 */ | |
76 | 0x00C0, /* R36 - ADC Digital Volume Left */ | |
77 | 0x00C0, /* R37 - ADC Digital Volume Right */ | |
78 | 0x0000, /* R38 - ADC Digital 0 */ | |
79 | 0x0073, /* R39 - Digital Microphone 0 */ | |
80 | 0x09BF, /* R40 - DRC 0 */ | |
81 | 0x3241, /* R41 - DRC 1 */ | |
82 | 0x0020, /* R42 - DRC 2 */ | |
83 | 0x0000, /* R43 - DRC 3 */ | |
84 | 0x0085, /* R44 - Analogue Left Input 0 */ | |
85 | 0x0085, /* R45 - Analogue Right Input 0 */ | |
86 | 0x0044, /* R46 - Analogue Left Input 1 */ | |
87 | 0x0044, /* R47 - Analogue Right Input 1 */ | |
88 | 0x0000, /* R48 */ | |
89 | 0x0000, /* R49 */ | |
90 | 0x0008, /* R50 - Analogue Left Mix 0 */ | |
91 | 0x0004, /* R51 - Analogue Right Mix 0 */ | |
92 | 0x0000, /* R52 - Analogue Spk Mix Left 0 */ | |
93 | 0x0000, /* R53 - Analogue Spk Mix Left 1 */ | |
94 | 0x0000, /* R54 - Analogue Spk Mix Right 0 */ | |
95 | 0x0000, /* R55 - Analogue Spk Mix Right 1 */ | |
96 | 0x0000, /* R56 */ | |
97 | 0x002D, /* R57 - Analogue OUT1 Left */ | |
98 | 0x002D, /* R58 - Analogue OUT1 Right */ | |
99 | 0x0039, /* R59 - Analogue OUT2 Left */ | |
100 | 0x0039, /* R60 - Analogue OUT2 Right */ | |
101 | 0x0100, /* R61 */ | |
102 | 0x0139, /* R62 - Analogue OUT3 Left */ | |
103 | 0x0139, /* R63 - Analogue OUT3 Right */ | |
104 | 0x0000, /* R64 */ | |
105 | 0x0000, /* R65 - Analogue SPK Output Control 0 */ | |
106 | 0x0000, /* R66 */ | |
107 | 0x0010, /* R67 - DC Servo 0 */ | |
108 | 0x0100, /* R68 */ | |
109 | 0x00A4, /* R69 - DC Servo 2 */ | |
110 | 0x0807, /* R70 */ | |
111 | 0x0000, /* R71 */ | |
112 | 0x0000, /* R72 */ | |
113 | 0x0000, /* R73 */ | |
114 | 0x0000, /* R74 */ | |
115 | 0x0000, /* R75 */ | |
116 | 0x0000, /* R76 */ | |
117 | 0x0000, /* R77 */ | |
118 | 0x0000, /* R78 */ | |
119 | 0x000E, /* R79 */ | |
120 | 0x0000, /* R80 */ | |
121 | 0x0000, /* R81 */ | |
122 | 0x0000, /* R82 */ | |
123 | 0x0000, /* R83 */ | |
124 | 0x0000, /* R84 */ | |
125 | 0x0000, /* R85 */ | |
126 | 0x0000, /* R86 */ | |
127 | 0x0006, /* R87 */ | |
128 | 0x0000, /* R88 */ | |
129 | 0x0000, /* R89 */ | |
130 | 0x0000, /* R90 - Analogue HP 0 */ | |
131 | 0x0060, /* R91 */ | |
132 | 0x0000, /* R92 */ | |
133 | 0x0000, /* R93 */ | |
134 | 0x0000, /* R94 - Analogue Lineout 0 */ | |
135 | 0x0060, /* R95 */ | |
136 | 0x0000, /* R96 */ | |
137 | 0x0000, /* R97 */ | |
138 | 0x0000, /* R98 - Charge Pump 0 */ | |
139 | 0x1F25, /* R99 */ | |
140 | 0x2B19, /* R100 */ | |
141 | 0x01C0, /* R101 */ | |
142 | 0x01EF, /* R102 */ | |
143 | 0x2B00, /* R103 */ | |
144 | 0x0000, /* R104 - Class W 0 */ | |
145 | 0x01C0, /* R105 */ | |
146 | 0x1C10, /* R106 */ | |
147 | 0x0000, /* R107 */ | |
148 | 0x0000, /* R108 - Write Sequencer 0 */ | |
149 | 0x0000, /* R109 - Write Sequencer 1 */ | |
150 | 0x0000, /* R110 - Write Sequencer 2 */ | |
151 | 0x0000, /* R111 - Write Sequencer 3 */ | |
152 | 0x0000, /* R112 - Write Sequencer 4 */ | |
153 | 0x0000, /* R113 */ | |
154 | 0x0000, /* R114 - Control Interface */ | |
155 | 0x0000, /* R115 */ | |
156 | 0x00A8, /* R116 - GPIO Control 1 */ | |
157 | 0x00A8, /* R117 - GPIO Control 2 */ | |
158 | 0x00A8, /* R118 - GPIO Control 3 */ | |
159 | 0x0220, /* R119 - GPIO Control 4 */ | |
160 | 0x01A0, /* R120 - GPIO Control 5 */ | |
161 | 0x0000, /* R121 - Interrupt Status 1 */ | |
162 | 0xFFFF, /* R122 - Interrupt Status 1 Mask */ | |
163 | 0x0000, /* R123 - Interrupt Polarity 1 */ | |
164 | 0x0000, /* R124 */ | |
165 | 0x0003, /* R125 */ | |
166 | 0x0000, /* R126 - Interrupt Control */ | |
167 | 0x0000, /* R127 */ | |
168 | 0x0005, /* R128 */ | |
169 | 0x0000, /* R129 - Control Interface Test 1 */ | |
170 | 0x0000, /* R130 */ | |
171 | 0x0000, /* R131 */ | |
172 | 0x0000, /* R132 */ | |
173 | 0x0000, /* R133 */ | |
174 | 0x0000, /* R134 */ | |
175 | 0x03FF, /* R135 */ | |
176 | 0x0007, /* R136 */ | |
177 | 0x0040, /* R137 */ | |
178 | 0x0000, /* R138 */ | |
179 | 0x0000, /* R139 */ | |
180 | 0x0000, /* R140 */ | |
181 | 0x0000, /* R141 */ | |
182 | 0x0000, /* R142 */ | |
183 | 0x0000, /* R143 */ | |
184 | 0x0000, /* R144 */ | |
185 | 0x0000, /* R145 */ | |
186 | 0x0000, /* R146 */ | |
187 | 0x0000, /* R147 */ | |
188 | 0x4000, /* R148 */ | |
189 | 0x6810, /* R149 - Charge Pump Test 1 */ | |
190 | 0x0004, /* R150 */ | |
191 | 0x0000, /* R151 */ | |
192 | 0x0000, /* R152 */ | |
193 | 0x0000, /* R153 */ | |
194 | 0x0000, /* R154 */ | |
195 | 0x0000, /* R155 */ | |
196 | 0x0000, /* R156 */ | |
197 | 0x0000, /* R157 */ | |
198 | 0x0000, /* R158 */ | |
199 | 0x0000, /* R159 */ | |
200 | 0x0000, /* R160 */ | |
201 | 0x0000, /* R161 */ | |
202 | 0x0000, /* R162 */ | |
203 | 0x0000, /* R163 */ | |
204 | 0x0028, /* R164 - Clock Rate Test 4 */ | |
205 | 0x0004, /* R165 */ | |
206 | 0x0000, /* R166 */ | |
207 | 0x0060, /* R167 */ | |
208 | 0x0000, /* R168 */ | |
209 | 0x0000, /* R169 */ | |
210 | 0x0000, /* R170 */ | |
211 | 0x0000, /* R171 */ | |
212 | 0x0000, /* R172 - Analogue Output Bias 0 */ | |
213 | }; | |
214 | ||
d58d5d55 | 215 | struct wm8903_priv { |
f0fba2ad | 216 | |
d58d5d55 MB |
217 | u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)]; |
218 | ||
219 | int sysclk; | |
f0fba2ad | 220 | int irq; |
d58d5d55 MB |
221 | |
222 | /* Reference counts */ | |
d58d5d55 MB |
223 | int class_w_users; |
224 | int playback_active; | |
225 | int capture_active; | |
226 | ||
8abd16a6 MB |
227 | struct completion wseq; |
228 | ||
7245387e MB |
229 | struct snd_soc_jack *mic_jack; |
230 | int mic_det; | |
231 | int mic_short; | |
232 | int mic_last_report; | |
233 | int mic_delay; | |
234 | ||
d58d5d55 MB |
235 | struct snd_pcm_substream *master_substream; |
236 | struct snd_pcm_substream *slave_substream; | |
237 | }; | |
238 | ||
8d50e447 | 239 | static int wm8903_volatile_register(unsigned int reg) |
f1c0a02f MB |
240 | { |
241 | switch (reg) { | |
242 | case WM8903_SW_RESET_AND_ID: | |
243 | case WM8903_REVISION_NUMBER: | |
244 | case WM8903_INTERRUPT_STATUS_1: | |
245 | case WM8903_WRITE_SEQUENCER_4: | |
8d50e447 | 246 | return 1; |
f1c0a02f MB |
247 | |
248 | default: | |
f1c0a02f | 249 | return 0; |
8d50e447 | 250 | } |
f1c0a02f MB |
251 | } |
252 | ||
253 | static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start) | |
254 | { | |
255 | u16 reg[5]; | |
b2c812e2 | 256 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); |
f1c0a02f MB |
257 | |
258 | BUG_ON(start > 48); | |
259 | ||
37f88e84 | 260 | /* Enable the sequencer if it's not already on */ |
8d50e447 | 261 | reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0); |
37f88e84 MB |
262 | snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, |
263 | reg[0] | WM8903_WSEQ_ENA); | |
f1c0a02f | 264 | |
f0fba2ad | 265 | dev_dbg(codec->dev, "Starting sequence at %d\n", start); |
f1c0a02f | 266 | |
8d50e447 | 267 | snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3, |
f1c0a02f MB |
268 | start | WM8903_WSEQ_START); |
269 | ||
270 | /* Wait for it to complete. If we have the interrupt wired up then | |
8abd16a6 | 271 | * that will break us out of the poll early. |
f1c0a02f MB |
272 | */ |
273 | do { | |
8abd16a6 MB |
274 | wait_for_completion_timeout(&wm8903->wseq, |
275 | msecs_to_jiffies(10)); | |
f1c0a02f | 276 | |
8d50e447 | 277 | reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4); |
f1c0a02f MB |
278 | } while (reg[4] & WM8903_WSEQ_BUSY); |
279 | ||
f0fba2ad | 280 | dev_dbg(codec->dev, "Sequence complete\n"); |
f1c0a02f | 281 | |
37f88e84 MB |
282 | /* Disable the sequencer again if we enabled it */ |
283 | snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]); | |
f1c0a02f MB |
284 | |
285 | return 0; | |
286 | } | |
287 | ||
288 | static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache) | |
289 | { | |
290 | int i; | |
291 | ||
292 | /* There really ought to be something better we can do here :/ */ | |
293 | for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++) | |
8d50e447 | 294 | cache[i] = codec->hw_read(codec, i); |
f1c0a02f MB |
295 | } |
296 | ||
297 | static void wm8903_reset(struct snd_soc_codec *codec) | |
298 | { | |
8d50e447 | 299 | snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0); |
d58d5d55 MB |
300 | memcpy(codec->reg_cache, wm8903_reg_defaults, |
301 | sizeof(wm8903_reg_defaults)); | |
f1c0a02f MB |
302 | } |
303 | ||
304 | #define WM8903_OUTPUT_SHORT 0x8 | |
305 | #define WM8903_OUTPUT_OUT 0x4 | |
306 | #define WM8903_OUTPUT_INT 0x2 | |
307 | #define WM8903_OUTPUT_IN 0x1 | |
308 | ||
42768a12 MB |
309 | static int wm8903_cp_event(struct snd_soc_dapm_widget *w, |
310 | struct snd_kcontrol *kcontrol, int event) | |
311 | { | |
312 | WARN_ON(event != SND_SOC_DAPM_POST_PMU); | |
313 | mdelay(4); | |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
f1c0a02f MB |
318 | /* |
319 | * Event for headphone and line out amplifier power changes. Special | |
320 | * power up/down sequences are required in order to maximise pop/click | |
321 | * performance. | |
322 | */ | |
323 | static int wm8903_output_event(struct snd_soc_dapm_widget *w, | |
324 | struct snd_kcontrol *kcontrol, int event) | |
325 | { | |
326 | struct snd_soc_codec *codec = w->codec; | |
f1c0a02f | 327 | u16 val; |
0bc286e2 | 328 | u16 reg; |
d7d5c547 MB |
329 | u16 dcs_reg; |
330 | u16 dcs_bit; | |
0bc286e2 | 331 | int shift; |
f1c0a02f MB |
332 | |
333 | switch (w->reg) { | |
334 | case WM8903_POWER_MANAGEMENT_2: | |
335 | reg = WM8903_ANALOGUE_HP_0; | |
d7d5c547 | 336 | dcs_bit = 0 + w->shift; |
f1c0a02f MB |
337 | break; |
338 | case WM8903_POWER_MANAGEMENT_3: | |
339 | reg = WM8903_ANALOGUE_LINEOUT_0; | |
d7d5c547 | 340 | dcs_bit = 2 + w->shift; |
f1c0a02f MB |
341 | break; |
342 | default: | |
343 | BUG(); | |
1e297a19 | 344 | return -EINVAL; /* Spurious warning from some compilers */ |
f1c0a02f MB |
345 | } |
346 | ||
347 | switch (w->shift) { | |
348 | case 0: | |
349 | shift = 0; | |
350 | break; | |
351 | case 1: | |
352 | shift = 4; | |
353 | break; | |
354 | default: | |
355 | BUG(); | |
1e297a19 | 356 | return -EINVAL; /* Spurious warning from some compilers */ |
f1c0a02f MB |
357 | } |
358 | ||
359 | if (event & SND_SOC_DAPM_PRE_PMU) { | |
8d50e447 | 360 | val = snd_soc_read(codec, reg); |
f1c0a02f MB |
361 | |
362 | /* Short the output */ | |
363 | val &= ~(WM8903_OUTPUT_SHORT << shift); | |
8d50e447 | 364 | snd_soc_write(codec, reg, val); |
f1c0a02f MB |
365 | } |
366 | ||
367 | if (event & SND_SOC_DAPM_POST_PMU) { | |
8d50e447 | 368 | val = snd_soc_read(codec, reg); |
f1c0a02f MB |
369 | |
370 | val |= (WM8903_OUTPUT_IN << shift); | |
8d50e447 | 371 | snd_soc_write(codec, reg, val); |
f1c0a02f MB |
372 | |
373 | val |= (WM8903_OUTPUT_INT << shift); | |
8d50e447 | 374 | snd_soc_write(codec, reg, val); |
f1c0a02f MB |
375 | |
376 | /* Turn on the output ENA_OUTP */ | |
377 | val |= (WM8903_OUTPUT_OUT << shift); | |
8d50e447 | 378 | snd_soc_write(codec, reg, val); |
f1c0a02f | 379 | |
d7d5c547 | 380 | /* Enable the DC servo */ |
8d50e447 | 381 | dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0); |
d7d5c547 | 382 | dcs_reg |= dcs_bit; |
8d50e447 | 383 | snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg); |
d7d5c547 | 384 | |
f1c0a02f MB |
385 | /* Remove the short */ |
386 | val |= (WM8903_OUTPUT_SHORT << shift); | |
8d50e447 | 387 | snd_soc_write(codec, reg, val); |
f1c0a02f MB |
388 | } |
389 | ||
390 | if (event & SND_SOC_DAPM_PRE_PMD) { | |
8d50e447 | 391 | val = snd_soc_read(codec, reg); |
f1c0a02f MB |
392 | |
393 | /* Short the output */ | |
394 | val &= ~(WM8903_OUTPUT_SHORT << shift); | |
8d50e447 | 395 | snd_soc_write(codec, reg, val); |
f1c0a02f | 396 | |
d7d5c547 | 397 | /* Disable the DC servo */ |
8d50e447 | 398 | dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0); |
d7d5c547 | 399 | dcs_reg &= ~dcs_bit; |
8d50e447 | 400 | snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg); |
d7d5c547 | 401 | |
f1c0a02f MB |
402 | /* Then disable the intermediate and output stages */ |
403 | val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT | | |
404 | WM8903_OUTPUT_IN) << shift); | |
8d50e447 | 405 | snd_soc_write(codec, reg, val); |
f1c0a02f MB |
406 | } |
407 | ||
f1c0a02f MB |
408 | return 0; |
409 | } | |
410 | ||
411 | /* | |
412 | * When used with DAC outputs only the WM8903 charge pump supports | |
413 | * operation in class W mode, providing very low power consumption | |
414 | * when used with digital sources. Enable and disable this mode | |
415 | * automatically depending on the mixer configuration. | |
416 | * | |
417 | * All the relevant controls are simple switches. | |
418 | */ | |
419 | static int wm8903_class_w_put(struct snd_kcontrol *kcontrol, | |
420 | struct snd_ctl_elem_value *ucontrol) | |
421 | { | |
422 | struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol); | |
423 | struct snd_soc_codec *codec = widget->codec; | |
b2c812e2 | 424 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); |
f1c0a02f MB |
425 | u16 reg; |
426 | int ret; | |
427 | ||
8d50e447 | 428 | reg = snd_soc_read(codec, WM8903_CLASS_W_0); |
f1c0a02f MB |
429 | |
430 | /* Turn it off if we're about to enable bypass */ | |
431 | if (ucontrol->value.integer.value[0]) { | |
432 | if (wm8903->class_w_users == 0) { | |
f0fba2ad | 433 | dev_dbg(codec->dev, "Disabling Class W\n"); |
8d50e447 | 434 | snd_soc_write(codec, WM8903_CLASS_W_0, reg & |
f1c0a02f MB |
435 | ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V)); |
436 | } | |
437 | wm8903->class_w_users++; | |
438 | } | |
439 | ||
440 | /* Implement the change */ | |
441 | ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); | |
442 | ||
443 | /* If we've just disabled the last bypass path turn Class W on */ | |
444 | if (!ucontrol->value.integer.value[0]) { | |
445 | if (wm8903->class_w_users == 1) { | |
f0fba2ad | 446 | dev_dbg(codec->dev, "Enabling Class W\n"); |
8d50e447 | 447 | snd_soc_write(codec, WM8903_CLASS_W_0, reg | |
f1c0a02f MB |
448 | WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); |
449 | } | |
450 | wm8903->class_w_users--; | |
451 | } | |
452 | ||
f0fba2ad | 453 | dev_dbg(codec->dev, "Bypass use count now %d\n", |
f1c0a02f MB |
454 | wm8903->class_w_users); |
455 | ||
456 | return ret; | |
457 | } | |
458 | ||
459 | #define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \ | |
460 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
461 | .info = snd_soc_info_volsw, \ | |
462 | .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \ | |
463 | .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } | |
464 | ||
465 | ||
466 | /* ALSA can only do steps of .01dB */ | |
467 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
468 | ||
291ce18c | 469 | static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0); |
f1c0a02f MB |
470 | static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); |
471 | ||
472 | static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0); | |
473 | static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0); | |
474 | static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0); | |
475 | static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0); | |
476 | static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0); | |
477 | ||
478 | static const char *drc_slope_text[] = { | |
479 | "1", "1/2", "1/4", "1/8", "1/16", "0" | |
480 | }; | |
481 | ||
482 | static const struct soc_enum drc_slope_r0 = | |
483 | SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text); | |
484 | ||
485 | static const struct soc_enum drc_slope_r1 = | |
486 | SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text); | |
487 | ||
488 | static const char *drc_attack_text[] = { | |
489 | "instantaneous", | |
490 | "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms", | |
491 | "46.4ms", "92.8ms", "185.6ms" | |
492 | }; | |
493 | ||
494 | static const struct soc_enum drc_attack = | |
495 | SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text); | |
496 | ||
497 | static const char *drc_decay_text[] = { | |
498 | "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s", | |
499 | "23.87s", "47.56s" | |
500 | }; | |
501 | ||
502 | static const struct soc_enum drc_decay = | |
503 | SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text); | |
504 | ||
505 | static const char *drc_ff_delay_text[] = { | |
506 | "5 samples", "9 samples" | |
507 | }; | |
508 | ||
509 | static const struct soc_enum drc_ff_delay = | |
510 | SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text); | |
511 | ||
512 | static const char *drc_qr_decay_text[] = { | |
513 | "0.725ms", "1.45ms", "5.8ms" | |
514 | }; | |
515 | ||
516 | static const struct soc_enum drc_qr_decay = | |
517 | SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text); | |
518 | ||
519 | static const char *drc_smoothing_text[] = { | |
520 | "Low", "Medium", "High" | |
521 | }; | |
522 | ||
523 | static const struct soc_enum drc_smoothing = | |
524 | SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text); | |
525 | ||
526 | static const char *soft_mute_text[] = { | |
527 | "Fast (fs/2)", "Slow (fs/32)" | |
528 | }; | |
529 | ||
530 | static const struct soc_enum soft_mute = | |
531 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text); | |
532 | ||
533 | static const char *mute_mode_text[] = { | |
534 | "Hard", "Soft" | |
535 | }; | |
536 | ||
537 | static const struct soc_enum mute_mode = | |
538 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text); | |
539 | ||
540 | static const char *dac_deemphasis_text[] = { | |
541 | "Disabled", "32kHz", "44.1kHz", "48kHz" | |
542 | }; | |
543 | ||
544 | static const struct soc_enum dac_deemphasis = | |
545 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text); | |
546 | ||
547 | static const char *companding_text[] = { | |
548 | "ulaw", "alaw" | |
549 | }; | |
550 | ||
551 | static const struct soc_enum dac_companding = | |
552 | SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text); | |
553 | ||
554 | static const struct soc_enum adc_companding = | |
555 | SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text); | |
556 | ||
557 | static const char *input_mode_text[] = { | |
558 | "Single-Ended", "Differential Line", "Differential Mic" | |
559 | }; | |
560 | ||
561 | static const struct soc_enum linput_mode_enum = | |
562 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); | |
563 | ||
564 | static const struct soc_enum rinput_mode_enum = | |
565 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); | |
566 | ||
567 | static const char *linput_mux_text[] = { | |
568 | "IN1L", "IN2L", "IN3L" | |
569 | }; | |
570 | ||
571 | static const struct soc_enum linput_enum = | |
572 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text); | |
573 | ||
574 | static const struct soc_enum linput_inv_enum = | |
575 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text); | |
576 | ||
577 | static const char *rinput_mux_text[] = { | |
578 | "IN1R", "IN2R", "IN3R" | |
579 | }; | |
580 | ||
581 | static const struct soc_enum rinput_enum = | |
582 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text); | |
583 | ||
584 | static const struct soc_enum rinput_inv_enum = | |
585 | SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text); | |
586 | ||
587 | ||
291ce18c MB |
588 | static const char *sidetone_text[] = { |
589 | "None", "Left", "Right" | |
590 | }; | |
591 | ||
592 | static const struct soc_enum lsidetone_enum = | |
593 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text); | |
594 | ||
595 | static const struct soc_enum rsidetone_enum = | |
596 | SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text); | |
597 | ||
f1c0a02f MB |
598 | static const struct snd_kcontrol_new wm8903_snd_controls[] = { |
599 | ||
600 | /* Input PGAs - No TLV since the scale depends on PGA mode */ | |
601 | SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0, | |
5715952b | 602 | 7, 1, 1), |
f1c0a02f MB |
603 | SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0, |
604 | 0, 31, 0), | |
605 | SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1, | |
606 | 6, 1, 0), | |
607 | ||
608 | SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0, | |
5715952b | 609 | 7, 1, 1), |
f1c0a02f MB |
610 | SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0, |
611 | 0, 31, 0), | |
612 | SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1, | |
613 | 6, 1, 0), | |
614 | ||
615 | /* ADCs */ | |
616 | SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0), | |
617 | SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0), | |
618 | SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1), | |
af901ca1 | 619 | SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1, |
f1c0a02f MB |
620 | drc_tlv_thresh), |
621 | SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp), | |
622 | SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min), | |
623 | SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max), | |
624 | SOC_ENUM("DRC Attack Rate", drc_attack), | |
625 | SOC_ENUM("DRC Decay Rate", drc_decay), | |
626 | SOC_ENUM("DRC FF Delay", drc_ff_delay), | |
627 | SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0), | |
628 | SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0), | |
af901ca1 | 629 | SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max), |
f1c0a02f MB |
630 | SOC_ENUM("DRC QR Decay Rate", drc_qr_decay), |
631 | SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0), | |
632 | SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0), | |
af901ca1 | 633 | SOC_ENUM("DRC Smoothing Threshold", drc_smoothing), |
f1c0a02f MB |
634 | SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup), |
635 | ||
636 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT, | |
637 | WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), | |
638 | SOC_ENUM("ADC Companding Mode", adc_companding), | |
639 | SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0), | |
640 | ||
291ce18c MB |
641 | SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8, |
642 | 12, 0, digital_sidetone_tlv), | |
643 | ||
f1c0a02f MB |
644 | /* DAC */ |
645 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT, | |
646 | WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv), | |
647 | SOC_ENUM("DAC Soft Mute Rate", soft_mute), | |
648 | SOC_ENUM("DAC Mute Mode", mute_mode), | |
649 | SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0), | |
650 | SOC_ENUM("DAC De-emphasis", dac_deemphasis), | |
f1c0a02f MB |
651 | SOC_ENUM("DAC Companding Mode", dac_companding), |
652 | SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0), | |
653 | ||
654 | /* Headphones */ | |
655 | SOC_DOUBLE_R("Headphone Switch", | |
656 | WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, | |
657 | 8, 1, 1), | |
658 | SOC_DOUBLE_R("Headphone ZC Switch", | |
659 | WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, | |
660 | 6, 1, 0), | |
661 | SOC_DOUBLE_R_TLV("Headphone Volume", | |
662 | WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT, | |
663 | 0, 63, 0, out_tlv), | |
664 | ||
665 | /* Line out */ | |
666 | SOC_DOUBLE_R("Line Out Switch", | |
667 | WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, | |
668 | 8, 1, 1), | |
669 | SOC_DOUBLE_R("Line Out ZC Switch", | |
670 | WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, | |
671 | 6, 1, 0), | |
672 | SOC_DOUBLE_R_TLV("Line Out Volume", | |
673 | WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT, | |
674 | 0, 63, 0, out_tlv), | |
675 | ||
676 | /* Speaker */ | |
677 | SOC_DOUBLE_R("Speaker Switch", | |
678 | WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1), | |
679 | SOC_DOUBLE_R("Speaker ZC Switch", | |
680 | WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0), | |
681 | SOC_DOUBLE_R_TLV("Speaker Volume", | |
682 | WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, | |
683 | 0, 63, 0, out_tlv), | |
684 | }; | |
685 | ||
f1c0a02f MB |
686 | static const struct snd_kcontrol_new linput_mode_mux = |
687 | SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum); | |
688 | ||
689 | static const struct snd_kcontrol_new rinput_mode_mux = | |
690 | SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum); | |
691 | ||
692 | static const struct snd_kcontrol_new linput_mux = | |
693 | SOC_DAPM_ENUM("Left Input Mux", linput_enum); | |
694 | ||
695 | static const struct snd_kcontrol_new linput_inv_mux = | |
696 | SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum); | |
697 | ||
698 | static const struct snd_kcontrol_new rinput_mux = | |
699 | SOC_DAPM_ENUM("Right Input Mux", rinput_enum); | |
700 | ||
701 | static const struct snd_kcontrol_new rinput_inv_mux = | |
702 | SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum); | |
703 | ||
291ce18c MB |
704 | static const struct snd_kcontrol_new lsidetone_mux = |
705 | SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum); | |
706 | ||
707 | static const struct snd_kcontrol_new rsidetone_mux = | |
708 | SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum); | |
709 | ||
f1c0a02f MB |
710 | static const struct snd_kcontrol_new left_output_mixer[] = { |
711 | SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0), | |
712 | SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0), | |
713 | SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0), | |
4b4fffdd | 714 | SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0), |
f1c0a02f MB |
715 | }; |
716 | ||
717 | static const struct snd_kcontrol_new right_output_mixer[] = { | |
718 | SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0), | |
719 | SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0), | |
720 | SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0), | |
4b4fffdd | 721 | SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0), |
f1c0a02f MB |
722 | }; |
723 | ||
724 | static const struct snd_kcontrol_new left_speaker_mixer[] = { | |
725 | SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0), | |
726 | SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0), | |
727 | SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0), | |
728 | SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, | |
4b4fffdd | 729 | 0, 1, 0), |
f1c0a02f MB |
730 | }; |
731 | ||
732 | static const struct snd_kcontrol_new right_speaker_mixer[] = { | |
733 | SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0), | |
734 | SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0), | |
735 | SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, | |
736 | 1, 1, 0), | |
737 | SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, | |
4b4fffdd | 738 | 0, 1, 0), |
f1c0a02f MB |
739 | }; |
740 | ||
741 | static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = { | |
742 | SND_SOC_DAPM_INPUT("IN1L"), | |
743 | SND_SOC_DAPM_INPUT("IN1R"), | |
744 | SND_SOC_DAPM_INPUT("IN2L"), | |
745 | SND_SOC_DAPM_INPUT("IN2R"), | |
746 | SND_SOC_DAPM_INPUT("IN3L"), | |
747 | SND_SOC_DAPM_INPUT("IN3R"), | |
748 | ||
749 | SND_SOC_DAPM_OUTPUT("HPOUTL"), | |
750 | SND_SOC_DAPM_OUTPUT("HPOUTR"), | |
751 | SND_SOC_DAPM_OUTPUT("LINEOUTL"), | |
752 | SND_SOC_DAPM_OUTPUT("LINEOUTR"), | |
753 | SND_SOC_DAPM_OUTPUT("LOP"), | |
754 | SND_SOC_DAPM_OUTPUT("LON"), | |
755 | SND_SOC_DAPM_OUTPUT("ROP"), | |
756 | SND_SOC_DAPM_OUTPUT("RON"), | |
757 | ||
758 | SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0), | |
759 | ||
760 | SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux), | |
761 | SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0, | |
762 | &linput_inv_mux), | |
763 | SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux), | |
764 | ||
765 | SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux), | |
766 | SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0, | |
767 | &rinput_inv_mux), | |
768 | SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux), | |
769 | ||
770 | SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0), | |
771 | SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0), | |
772 | ||
773 | SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0), | |
774 | SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0), | |
775 | ||
291ce18c MB |
776 | SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux), |
777 | SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux), | |
778 | ||
f1c0a02f MB |
779 | SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0), |
780 | SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0), | |
781 | ||
782 | SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0, | |
783 | left_output_mixer, ARRAY_SIZE(left_output_mixer)), | |
784 | SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0, | |
785 | right_output_mixer, ARRAY_SIZE(right_output_mixer)), | |
786 | ||
787 | SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0, | |
788 | left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), | |
789 | SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0, | |
790 | right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), | |
791 | ||
792 | SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2, | |
793 | 1, 0, NULL, 0, wm8903_output_event, | |
794 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
42768a12 | 795 | SND_SOC_DAPM_PRE_PMD), |
f1c0a02f MB |
796 | SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2, |
797 | 0, 0, NULL, 0, wm8903_output_event, | |
798 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
42768a12 | 799 | SND_SOC_DAPM_PRE_PMD), |
f1c0a02f MB |
800 | |
801 | SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0, | |
802 | NULL, 0, wm8903_output_event, | |
803 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
42768a12 | 804 | SND_SOC_DAPM_PRE_PMD), |
f1c0a02f MB |
805 | SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0, |
806 | NULL, 0, wm8903_output_event, | |
807 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | | |
42768a12 | 808 | SND_SOC_DAPM_PRE_PMD), |
f1c0a02f MB |
809 | |
810 | SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0, | |
811 | NULL, 0), | |
812 | SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0, | |
813 | NULL, 0), | |
814 | ||
42768a12 MB |
815 | SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0, |
816 | wm8903_cp_event, SND_SOC_DAPM_POST_PMU), | |
c2aef4ff | 817 | SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0), |
f1c0a02f MB |
818 | }; |
819 | ||
820 | static const struct snd_soc_dapm_route intercon[] = { | |
821 | ||
822 | { "Left Input Mux", "IN1L", "IN1L" }, | |
823 | { "Left Input Mux", "IN2L", "IN2L" }, | |
824 | { "Left Input Mux", "IN3L", "IN3L" }, | |
825 | ||
826 | { "Left Input Inverting Mux", "IN1L", "IN1L" }, | |
827 | { "Left Input Inverting Mux", "IN2L", "IN2L" }, | |
828 | { "Left Input Inverting Mux", "IN3L", "IN3L" }, | |
829 | ||
830 | { "Right Input Mux", "IN1R", "IN1R" }, | |
831 | { "Right Input Mux", "IN2R", "IN2R" }, | |
832 | { "Right Input Mux", "IN3R", "IN3R" }, | |
833 | ||
834 | { "Right Input Inverting Mux", "IN1R", "IN1R" }, | |
835 | { "Right Input Inverting Mux", "IN2R", "IN2R" }, | |
836 | { "Right Input Inverting Mux", "IN3R", "IN3R" }, | |
837 | ||
838 | { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" }, | |
839 | { "Left Input Mode Mux", "Differential Line", | |
840 | "Left Input Mux" }, | |
841 | { "Left Input Mode Mux", "Differential Line", | |
842 | "Left Input Inverting Mux" }, | |
843 | { "Left Input Mode Mux", "Differential Mic", | |
844 | "Left Input Mux" }, | |
845 | { "Left Input Mode Mux", "Differential Mic", | |
846 | "Left Input Inverting Mux" }, | |
847 | ||
848 | { "Right Input Mode Mux", "Single-Ended", | |
849 | "Right Input Inverting Mux" }, | |
850 | { "Right Input Mode Mux", "Differential Line", | |
851 | "Right Input Mux" }, | |
852 | { "Right Input Mode Mux", "Differential Line", | |
853 | "Right Input Inverting Mux" }, | |
854 | { "Right Input Mode Mux", "Differential Mic", | |
855 | "Right Input Mux" }, | |
856 | { "Right Input Mode Mux", "Differential Mic", | |
857 | "Right Input Inverting Mux" }, | |
858 | ||
859 | { "Left Input PGA", NULL, "Left Input Mode Mux" }, | |
860 | { "Right Input PGA", NULL, "Right Input Mode Mux" }, | |
861 | ||
862 | { "ADCL", NULL, "Left Input PGA" }, | |
c2aef4ff | 863 | { "ADCL", NULL, "CLK_DSP" }, |
f1c0a02f | 864 | { "ADCR", NULL, "Right Input PGA" }, |
c2aef4ff MB |
865 | { "ADCR", NULL, "CLK_DSP" }, |
866 | ||
291ce18c MB |
867 | { "DACL Sidetone", "Left", "ADCL" }, |
868 | { "DACL Sidetone", "Right", "ADCR" }, | |
869 | { "DACR Sidetone", "Left", "ADCL" }, | |
870 | { "DACR Sidetone", "Right", "ADCR" }, | |
871 | ||
872 | { "DACL", NULL, "DACL Sidetone" }, | |
c2aef4ff | 873 | { "DACL", NULL, "CLK_DSP" }, |
291ce18c | 874 | { "DACR", NULL, "DACR Sidetone" }, |
c2aef4ff | 875 | { "DACR", NULL, "CLK_DSP" }, |
f1c0a02f MB |
876 | |
877 | { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" }, | |
878 | { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" }, | |
879 | { "Left Output Mixer", "DACL Switch", "DACL" }, | |
880 | { "Left Output Mixer", "DACR Switch", "DACR" }, | |
881 | ||
882 | { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" }, | |
883 | { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" }, | |
884 | { "Right Output Mixer", "DACL Switch", "DACL" }, | |
885 | { "Right Output Mixer", "DACR Switch", "DACR" }, | |
886 | ||
887 | { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, | |
888 | { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, | |
889 | { "Left Speaker Mixer", "DACL Switch", "DACL" }, | |
890 | { "Left Speaker Mixer", "DACR Switch", "DACR" }, | |
891 | ||
892 | { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" }, | |
893 | { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" }, | |
894 | { "Right Speaker Mixer", "DACL Switch", "DACL" }, | |
895 | { "Right Speaker Mixer", "DACR Switch", "DACR" }, | |
896 | ||
897 | { "Left Line Output PGA", NULL, "Left Output Mixer" }, | |
898 | { "Right Line Output PGA", NULL, "Right Output Mixer" }, | |
899 | ||
900 | { "Left Headphone Output PGA", NULL, "Left Output Mixer" }, | |
901 | { "Right Headphone Output PGA", NULL, "Right Output Mixer" }, | |
902 | ||
903 | { "Left Speaker PGA", NULL, "Left Speaker Mixer" }, | |
904 | { "Right Speaker PGA", NULL, "Right Speaker Mixer" }, | |
905 | ||
906 | { "HPOUTL", NULL, "Left Headphone Output PGA" }, | |
907 | { "HPOUTR", NULL, "Right Headphone Output PGA" }, | |
908 | ||
909 | { "LINEOUTL", NULL, "Left Line Output PGA" }, | |
910 | { "LINEOUTR", NULL, "Right Line Output PGA" }, | |
911 | ||
912 | { "LOP", NULL, "Left Speaker PGA" }, | |
913 | { "LON", NULL, "Left Speaker PGA" }, | |
914 | ||
915 | { "ROP", NULL, "Right Speaker PGA" }, | |
916 | { "RON", NULL, "Right Speaker PGA" }, | |
42768a12 MB |
917 | |
918 | { "Left Headphone Output PGA", NULL, "Charge Pump" }, | |
919 | { "Right Headphone Output PGA", NULL, "Charge Pump" }, | |
920 | { "Left Line Output PGA", NULL, "Charge Pump" }, | |
921 | { "Right Line Output PGA", NULL, "Charge Pump" }, | |
f1c0a02f MB |
922 | }; |
923 | ||
924 | static int wm8903_add_widgets(struct snd_soc_codec *codec) | |
925 | { | |
ce6120cc | 926 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
f1c0a02f | 927 | |
ce6120cc LG |
928 | snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets, |
929 | ARRAY_SIZE(wm8903_dapm_widgets)); | |
930 | snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); | |
f1c0a02f | 931 | |
f1c0a02f MB |
932 | return 0; |
933 | } | |
934 | ||
935 | static int wm8903_set_bias_level(struct snd_soc_codec *codec, | |
936 | enum snd_soc_bias_level level) | |
937 | { | |
f1c0a02f MB |
938 | u16 reg, reg2; |
939 | ||
940 | switch (level) { | |
941 | case SND_SOC_BIAS_ON: | |
942 | case SND_SOC_BIAS_PREPARE: | |
8d50e447 | 943 | reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0); |
f1c0a02f MB |
944 | reg &= ~(WM8903_VMID_RES_MASK); |
945 | reg |= WM8903_VMID_RES_50K; | |
8d50e447 | 946 | snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg); |
f1c0a02f MB |
947 | break; |
948 | ||
949 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 950 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
8d50e447 | 951 | snd_soc_write(codec, WM8903_CLOCK_RATES_2, |
3b1228ab MB |
952 | WM8903_CLK_SYS_ENA); |
953 | ||
4dbfe809 | 954 | /* Change DC servo dither level in startup sequence */ |
8d50e447 MB |
955 | snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11); |
956 | snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257); | |
957 | snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2); | |
4dbfe809 | 958 | |
f1c0a02f MB |
959 | wm8903_run_sequence(codec, 0); |
960 | wm8903_sync_reg_cache(codec, codec->reg_cache); | |
961 | ||
962 | /* Enable low impedence charge pump output */ | |
8d50e447 | 963 | reg = snd_soc_read(codec, |
f1c0a02f | 964 | WM8903_CONTROL_INTERFACE_TEST_1); |
8d50e447 | 965 | snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, |
f1c0a02f | 966 | reg | WM8903_TEST_KEY); |
8d50e447 MB |
967 | reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1); |
968 | snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1, | |
f1c0a02f | 969 | reg2 | WM8903_CP_SW_KELVIN_MODE_MASK); |
8d50e447 | 970 | snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1, |
f1c0a02f MB |
971 | reg); |
972 | ||
973 | /* By default no bypass paths are enabled so | |
974 | * enable Class W support. | |
975 | */ | |
f0fba2ad | 976 | dev_dbg(codec->dev, "Enabling Class W\n"); |
8d50e447 | 977 | snd_soc_write(codec, WM8903_CLASS_W_0, reg | |
f1c0a02f MB |
978 | WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V); |
979 | } | |
980 | ||
8d50e447 | 981 | reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0); |
f1c0a02f MB |
982 | reg &= ~(WM8903_VMID_RES_MASK); |
983 | reg |= WM8903_VMID_RES_250K; | |
8d50e447 | 984 | snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg); |
f1c0a02f MB |
985 | break; |
986 | ||
987 | case SND_SOC_BIAS_OFF: | |
988 | wm8903_run_sequence(codec, 32); | |
8d50e447 | 989 | reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2); |
3b1228ab | 990 | reg &= ~WM8903_CLK_SYS_ENA; |
8d50e447 | 991 | snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg); |
f1c0a02f MB |
992 | break; |
993 | } | |
994 | ||
ce6120cc | 995 | codec->dapm.bias_level = level; |
f1c0a02f MB |
996 | |
997 | return 0; | |
998 | } | |
999 | ||
1000 | static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
1001 | int clk_id, unsigned int freq, int dir) | |
1002 | { | |
1003 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1004 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); |
f1c0a02f MB |
1005 | |
1006 | wm8903->sysclk = freq; | |
1007 | ||
1008 | return 0; | |
1009 | } | |
1010 | ||
1011 | static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1012 | unsigned int fmt) | |
1013 | { | |
1014 | struct snd_soc_codec *codec = codec_dai->codec; | |
8d50e447 | 1015 | u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); |
f1c0a02f MB |
1016 | |
1017 | aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK | | |
1018 | WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV); | |
1019 | ||
1020 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1021 | case SND_SOC_DAIFMT_CBS_CFS: | |
1022 | break; | |
1023 | case SND_SOC_DAIFMT_CBS_CFM: | |
1024 | aif1 |= WM8903_LRCLK_DIR; | |
1025 | break; | |
1026 | case SND_SOC_DAIFMT_CBM_CFM: | |
1027 | aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR; | |
1028 | break; | |
1029 | case SND_SOC_DAIFMT_CBM_CFS: | |
1030 | aif1 |= WM8903_BCLK_DIR; | |
1031 | break; | |
1032 | default: | |
1033 | return -EINVAL; | |
1034 | } | |
1035 | ||
1036 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1037 | case SND_SOC_DAIFMT_DSP_A: | |
1038 | aif1 |= 0x3; | |
1039 | break; | |
1040 | case SND_SOC_DAIFMT_DSP_B: | |
1041 | aif1 |= 0x3 | WM8903_AIF_LRCLK_INV; | |
1042 | break; | |
1043 | case SND_SOC_DAIFMT_I2S: | |
1044 | aif1 |= 0x2; | |
1045 | break; | |
1046 | case SND_SOC_DAIFMT_RIGHT_J: | |
1047 | aif1 |= 0x1; | |
1048 | break; | |
1049 | case SND_SOC_DAIFMT_LEFT_J: | |
1050 | break; | |
1051 | default: | |
1052 | return -EINVAL; | |
1053 | } | |
1054 | ||
1055 | /* Clock inversion */ | |
1056 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1057 | case SND_SOC_DAIFMT_DSP_A: | |
1058 | case SND_SOC_DAIFMT_DSP_B: | |
1059 | /* frame inversion not valid for DSP modes */ | |
1060 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1061 | case SND_SOC_DAIFMT_NB_NF: | |
1062 | break; | |
1063 | case SND_SOC_DAIFMT_IB_NF: | |
1064 | aif1 |= WM8903_AIF_BCLK_INV; | |
1065 | break; | |
1066 | default: | |
1067 | return -EINVAL; | |
1068 | } | |
1069 | break; | |
1070 | case SND_SOC_DAIFMT_I2S: | |
1071 | case SND_SOC_DAIFMT_RIGHT_J: | |
1072 | case SND_SOC_DAIFMT_LEFT_J: | |
1073 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1074 | case SND_SOC_DAIFMT_NB_NF: | |
1075 | break; | |
1076 | case SND_SOC_DAIFMT_IB_IF: | |
1077 | aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV; | |
1078 | break; | |
1079 | case SND_SOC_DAIFMT_IB_NF: | |
1080 | aif1 |= WM8903_AIF_BCLK_INV; | |
1081 | break; | |
1082 | case SND_SOC_DAIFMT_NB_IF: | |
1083 | aif1 |= WM8903_AIF_LRCLK_INV; | |
1084 | break; | |
1085 | default: | |
1086 | return -EINVAL; | |
1087 | } | |
1088 | break; | |
1089 | default: | |
1090 | return -EINVAL; | |
1091 | } | |
1092 | ||
8d50e447 | 1093 | snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); |
f1c0a02f MB |
1094 | |
1095 | return 0; | |
1096 | } | |
1097 | ||
1098 | static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
1099 | { | |
1100 | struct snd_soc_codec *codec = codec_dai->codec; | |
1101 | u16 reg; | |
1102 | ||
8d50e447 | 1103 | reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); |
f1c0a02f MB |
1104 | |
1105 | if (mute) | |
1106 | reg |= WM8903_DAC_MUTE; | |
1107 | else | |
1108 | reg &= ~WM8903_DAC_MUTE; | |
1109 | ||
8d50e447 | 1110 | snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg); |
f1c0a02f MB |
1111 | |
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | /* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended | |
1116 | * for optimal performance so we list the lower rates first and match | |
1117 | * on the last match we find. */ | |
1118 | static struct { | |
1119 | int div; | |
1120 | int rate; | |
1121 | int mode; | |
1122 | int mclk_div; | |
1123 | } clk_sys_ratios[] = { | |
1124 | { 64, 0x0, 0x0, 1 }, | |
1125 | { 68, 0x0, 0x1, 1 }, | |
1126 | { 125, 0x0, 0x2, 1 }, | |
1127 | { 128, 0x1, 0x0, 1 }, | |
1128 | { 136, 0x1, 0x1, 1 }, | |
1129 | { 192, 0x2, 0x0, 1 }, | |
1130 | { 204, 0x2, 0x1, 1 }, | |
1131 | ||
1132 | { 64, 0x0, 0x0, 2 }, | |
1133 | { 68, 0x0, 0x1, 2 }, | |
1134 | { 125, 0x0, 0x2, 2 }, | |
1135 | { 128, 0x1, 0x0, 2 }, | |
1136 | { 136, 0x1, 0x1, 2 }, | |
1137 | { 192, 0x2, 0x0, 2 }, | |
1138 | { 204, 0x2, 0x1, 2 }, | |
1139 | ||
1140 | { 250, 0x2, 0x2, 1 }, | |
1141 | { 256, 0x3, 0x0, 1 }, | |
1142 | { 272, 0x3, 0x1, 1 }, | |
1143 | { 384, 0x4, 0x0, 1 }, | |
1144 | { 408, 0x4, 0x1, 1 }, | |
1145 | { 375, 0x4, 0x2, 1 }, | |
1146 | { 512, 0x5, 0x0, 1 }, | |
1147 | { 544, 0x5, 0x1, 1 }, | |
1148 | { 500, 0x5, 0x2, 1 }, | |
1149 | { 768, 0x6, 0x0, 1 }, | |
1150 | { 816, 0x6, 0x1, 1 }, | |
1151 | { 750, 0x6, 0x2, 1 }, | |
1152 | { 1024, 0x7, 0x0, 1 }, | |
1153 | { 1088, 0x7, 0x1, 1 }, | |
1154 | { 1000, 0x7, 0x2, 1 }, | |
1155 | { 1408, 0x8, 0x0, 1 }, | |
1156 | { 1496, 0x8, 0x1, 1 }, | |
1157 | { 1536, 0x9, 0x0, 1 }, | |
1158 | { 1632, 0x9, 0x1, 1 }, | |
1159 | { 1500, 0x9, 0x2, 1 }, | |
1160 | ||
1161 | { 250, 0x2, 0x2, 2 }, | |
1162 | { 256, 0x3, 0x0, 2 }, | |
1163 | { 272, 0x3, 0x1, 2 }, | |
1164 | { 384, 0x4, 0x0, 2 }, | |
1165 | { 408, 0x4, 0x1, 2 }, | |
1166 | { 375, 0x4, 0x2, 2 }, | |
1167 | { 512, 0x5, 0x0, 2 }, | |
1168 | { 544, 0x5, 0x1, 2 }, | |
1169 | { 500, 0x5, 0x2, 2 }, | |
1170 | { 768, 0x6, 0x0, 2 }, | |
1171 | { 816, 0x6, 0x1, 2 }, | |
1172 | { 750, 0x6, 0x2, 2 }, | |
1173 | { 1024, 0x7, 0x0, 2 }, | |
1174 | { 1088, 0x7, 0x1, 2 }, | |
1175 | { 1000, 0x7, 0x2, 2 }, | |
1176 | { 1408, 0x8, 0x0, 2 }, | |
1177 | { 1496, 0x8, 0x1, 2 }, | |
1178 | { 1536, 0x9, 0x0, 2 }, | |
1179 | { 1632, 0x9, 0x1, 2 }, | |
1180 | { 1500, 0x9, 0x2, 2 }, | |
1181 | }; | |
1182 | ||
1183 | /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ | |
1184 | static struct { | |
1185 | int ratio; | |
1186 | int div; | |
1187 | } bclk_divs[] = { | |
1188 | { 10, 0 }, | |
f1c0a02f MB |
1189 | { 20, 2 }, |
1190 | { 30, 3 }, | |
1191 | { 40, 4 }, | |
1192 | { 50, 5 }, | |
f1c0a02f MB |
1193 | { 60, 7 }, |
1194 | { 80, 8 }, | |
1195 | { 100, 9 }, | |
f1c0a02f MB |
1196 | { 120, 11 }, |
1197 | { 160, 12 }, | |
1198 | { 200, 13 }, | |
1199 | { 220, 14 }, | |
1200 | { 240, 15 }, | |
f1c0a02f MB |
1201 | { 300, 17 }, |
1202 | { 320, 18 }, | |
1203 | { 440, 19 }, | |
1204 | { 480, 20 }, | |
1205 | }; | |
1206 | ||
1207 | /* Sample rates for DSP */ | |
1208 | static struct { | |
1209 | int rate; | |
1210 | int value; | |
1211 | } sample_rates[] = { | |
1212 | { 8000, 0 }, | |
1213 | { 11025, 1 }, | |
1214 | { 12000, 2 }, | |
1215 | { 16000, 3 }, | |
1216 | { 22050, 4 }, | |
1217 | { 24000, 5 }, | |
1218 | { 32000, 6 }, | |
1219 | { 44100, 7 }, | |
1220 | { 48000, 8 }, | |
1221 | { 88200, 9 }, | |
1222 | { 96000, 10 }, | |
1223 | { 0, 0 }, | |
1224 | }; | |
1225 | ||
dee89c4d MB |
1226 | static int wm8903_startup(struct snd_pcm_substream *substream, |
1227 | struct snd_soc_dai *dai) | |
f1c0a02f MB |
1228 | { |
1229 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 1230 | struct snd_soc_codec *codec = rtd->codec; |
b2c812e2 | 1231 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); |
f1c0a02f MB |
1232 | struct snd_pcm_runtime *master_runtime; |
1233 | ||
1234 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1235 | wm8903->playback_active++; | |
1236 | else | |
1237 | wm8903->capture_active++; | |
1238 | ||
1239 | /* The DAI has shared clocks so if we already have a playback or | |
1240 | * capture going then constrain this substream to match it. | |
1241 | */ | |
1242 | if (wm8903->master_substream) { | |
1243 | master_runtime = wm8903->master_substream->runtime; | |
1244 | ||
f0fba2ad | 1245 | dev_dbg(codec->dev, "Constraining to %d bits\n", |
727fb909 | 1246 | master_runtime->sample_bits); |
f1c0a02f MB |
1247 | |
1248 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1249 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
1250 | master_runtime->sample_bits, | |
1251 | master_runtime->sample_bits); | |
1252 | ||
1253 | wm8903->slave_substream = substream; | |
1254 | } else | |
1255 | wm8903->master_substream = substream; | |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
dee89c4d MB |
1260 | static void wm8903_shutdown(struct snd_pcm_substream *substream, |
1261 | struct snd_soc_dai *dai) | |
f1c0a02f MB |
1262 | { |
1263 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 1264 | struct snd_soc_codec *codec = rtd->codec; |
b2c812e2 | 1265 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); |
f1c0a02f MB |
1266 | |
1267 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1268 | wm8903->playback_active--; | |
1269 | else | |
1270 | wm8903->capture_active--; | |
1271 | ||
1272 | if (wm8903->master_substream == substream) | |
1273 | wm8903->master_substream = wm8903->slave_substream; | |
1274 | ||
1275 | wm8903->slave_substream = NULL; | |
1276 | } | |
1277 | ||
1278 | static int wm8903_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
1279 | struct snd_pcm_hw_params *params, |
1280 | struct snd_soc_dai *dai) | |
f1c0a02f MB |
1281 | { |
1282 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 1283 | struct snd_soc_codec *codec =rtd->codec; |
b2c812e2 | 1284 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); |
f1c0a02f MB |
1285 | int fs = params_rate(params); |
1286 | int bclk; | |
1287 | int bclk_div; | |
1288 | int i; | |
1289 | int dsp_config; | |
1290 | int clk_config; | |
1291 | int best_val; | |
1292 | int cur_val; | |
1293 | int clk_sys; | |
1294 | ||
8d50e447 MB |
1295 | u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1); |
1296 | u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2); | |
1297 | u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3); | |
1298 | u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0); | |
1299 | u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1); | |
1300 | u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); | |
f1c0a02f MB |
1301 | |
1302 | if (substream == wm8903->slave_substream) { | |
f0fba2ad | 1303 | dev_dbg(codec->dev, "Ignoring hw_params for slave substream\n"); |
f1c0a02f MB |
1304 | return 0; |
1305 | } | |
1306 | ||
9e79261f MB |
1307 | /* Enable sloping stopband filter for low sample rates */ |
1308 | if (fs <= 24000) | |
1309 | dac_digital1 |= WM8903_DAC_SB_FILT; | |
1310 | else | |
1311 | dac_digital1 &= ~WM8903_DAC_SB_FILT; | |
1312 | ||
f1c0a02f MB |
1313 | /* Configure sample rate logic for DSP - choose nearest rate */ |
1314 | dsp_config = 0; | |
1315 | best_val = abs(sample_rates[dsp_config].rate - fs); | |
1316 | for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { | |
1317 | cur_val = abs(sample_rates[i].rate - fs); | |
1318 | if (cur_val <= best_val) { | |
1319 | dsp_config = i; | |
1320 | best_val = cur_val; | |
1321 | } | |
1322 | } | |
1323 | ||
1324 | /* Constraints should stop us hitting this but let's make sure */ | |
1325 | if (wm8903->capture_active) | |
1326 | switch (sample_rates[dsp_config].rate) { | |
1327 | case 88200: | |
1328 | case 96000: | |
f0fba2ad | 1329 | dev_err(codec->dev, "%dHz unsupported by ADC\n", |
f1c0a02f MB |
1330 | fs); |
1331 | return -EINVAL; | |
1332 | ||
1333 | default: | |
1334 | break; | |
1335 | } | |
1336 | ||
f0fba2ad | 1337 | dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate); |
f1c0a02f MB |
1338 | clock1 &= ~WM8903_SAMPLE_RATE_MASK; |
1339 | clock1 |= sample_rates[dsp_config].value; | |
1340 | ||
1341 | aif1 &= ~WM8903_AIF_WL_MASK; | |
1342 | bclk = 2 * fs; | |
1343 | switch (params_format(params)) { | |
1344 | case SNDRV_PCM_FORMAT_S16_LE: | |
1345 | bclk *= 16; | |
1346 | break; | |
1347 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1348 | bclk *= 20; | |
1349 | aif1 |= 0x4; | |
1350 | break; | |
1351 | case SNDRV_PCM_FORMAT_S24_LE: | |
1352 | bclk *= 24; | |
1353 | aif1 |= 0x8; | |
1354 | break; | |
1355 | case SNDRV_PCM_FORMAT_S32_LE: | |
1356 | bclk *= 32; | |
1357 | aif1 |= 0xc; | |
1358 | break; | |
1359 | default: | |
1360 | return -EINVAL; | |
1361 | } | |
1362 | ||
f0fba2ad | 1363 | dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n", |
f1c0a02f MB |
1364 | wm8903->sysclk, fs); |
1365 | ||
1366 | /* We may not have an MCLK which allows us to generate exactly | |
1367 | * the clock we want, particularly with USB derived inputs, so | |
1368 | * approximate. | |
1369 | */ | |
1370 | clk_config = 0; | |
1371 | best_val = abs((wm8903->sysclk / | |
1372 | (clk_sys_ratios[0].mclk_div * | |
1373 | clk_sys_ratios[0].div)) - fs); | |
1374 | for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) { | |
1375 | cur_val = abs((wm8903->sysclk / | |
1376 | (clk_sys_ratios[i].mclk_div * | |
1377 | clk_sys_ratios[i].div)) - fs); | |
1378 | ||
1379 | if (cur_val <= best_val) { | |
1380 | clk_config = i; | |
1381 | best_val = cur_val; | |
1382 | } | |
1383 | } | |
1384 | ||
1385 | if (clk_sys_ratios[clk_config].mclk_div == 2) { | |
1386 | clock0 |= WM8903_MCLKDIV2; | |
1387 | clk_sys = wm8903->sysclk / 2; | |
1388 | } else { | |
1389 | clock0 &= ~WM8903_MCLKDIV2; | |
1390 | clk_sys = wm8903->sysclk; | |
1391 | } | |
1392 | ||
1393 | clock1 &= ~(WM8903_CLK_SYS_RATE_MASK | | |
1394 | WM8903_CLK_SYS_MODE_MASK); | |
1395 | clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT; | |
1396 | clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT; | |
1397 | ||
f0fba2ad | 1398 | dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n", |
f1c0a02f MB |
1399 | clk_sys_ratios[clk_config].rate, |
1400 | clk_sys_ratios[clk_config].mode, | |
1401 | clk_sys_ratios[clk_config].div); | |
1402 | ||
f0fba2ad | 1403 | dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys); |
f1c0a02f MB |
1404 | |
1405 | /* We may not get quite the right frequency if using | |
1406 | * approximate clocks so look for the closest match that is | |
1407 | * higher than the target (we need to ensure that there enough | |
1408 | * BCLKs to clock out the samples). | |
1409 | */ | |
1410 | bclk_div = 0; | |
1411 | best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk; | |
1412 | i = 1; | |
1413 | while (i < ARRAY_SIZE(bclk_divs)) { | |
1414 | cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk; | |
1415 | if (cur_val < 0) /* BCLK table is sorted */ | |
1416 | break; | |
1417 | bclk_div = i; | |
1418 | best_val = cur_val; | |
1419 | i++; | |
1420 | } | |
1421 | ||
1422 | aif2 &= ~WM8903_BCLK_DIV_MASK; | |
1423 | aif3 &= ~WM8903_LRCLK_RATE_MASK; | |
1424 | ||
f0fba2ad | 1425 | dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", |
f1c0a02f MB |
1426 | bclk_divs[bclk_div].ratio / 10, bclk, |
1427 | (clk_sys * 10) / bclk_divs[bclk_div].ratio); | |
1428 | ||
1429 | aif2 |= bclk_divs[bclk_div].div; | |
1430 | aif3 |= bclk / fs; | |
1431 | ||
8d50e447 MB |
1432 | snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0); |
1433 | snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1); | |
1434 | snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1); | |
1435 | snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2); | |
1436 | snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3); | |
1437 | snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1); | |
f1c0a02f MB |
1438 | |
1439 | return 0; | |
1440 | } | |
1441 | ||
7245387e MB |
1442 | /** |
1443 | * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ | |
1444 | * | |
1445 | * @codec: WM8903 codec | |
1446 | * @jack: jack to report detection events on | |
1447 | * @det: value to report for presence detection | |
1448 | * @shrt: value to report for short detection | |
1449 | * | |
1450 | * Enable microphone detection via IRQ on the WM8903. If GPIOs are | |
1451 | * being used to bring out signals to the processor then only platform | |
1452 | * data configuration is needed for WM8903 and processor GPIOs should | |
1453 | * be configured using snd_soc_jack_add_gpios() instead. | |
1454 | * | |
1455 | * The current threasholds for detection should be configured using | |
1456 | * micdet_cfg in the platform data. Using this function will force on | |
1457 | * the microphone bias for the device. | |
1458 | */ | |
1459 | int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, | |
1460 | int det, int shrt) | |
1461 | { | |
b2c812e2 | 1462 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); |
69266866 | 1463 | int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT; |
7245387e MB |
1464 | |
1465 | dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n", | |
1466 | det, shrt); | |
1467 | ||
1468 | /* Store the configuration */ | |
1469 | wm8903->mic_jack = jack; | |
1470 | wm8903->mic_det = det; | |
1471 | wm8903->mic_short = shrt; | |
1472 | ||
1473 | /* Enable interrupts we've got a report configured for */ | |
1474 | if (det) | |
1475 | irq_mask &= ~WM8903_MICDET_EINT; | |
1476 | if (shrt) | |
1477 | irq_mask &= ~WM8903_MICSHRT_EINT; | |
1478 | ||
1479 | snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, | |
1480 | WM8903_MICDET_EINT | WM8903_MICSHRT_EINT, | |
1481 | irq_mask); | |
1482 | ||
69266866 MB |
1483 | if (det && shrt) { |
1484 | /* Enable mic detection, this may not have been set through | |
1485 | * platform data (eg, if the defaults are OK). */ | |
1486 | snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, | |
1487 | WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); | |
1488 | snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, | |
1489 | WM8903_MICDET_ENA, WM8903_MICDET_ENA); | |
1490 | } else { | |
1491 | snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0, | |
1492 | WM8903_MICDET_ENA, 0); | |
1493 | } | |
7245387e MB |
1494 | |
1495 | return 0; | |
1496 | } | |
1497 | EXPORT_SYMBOL_GPL(wm8903_mic_detect); | |
1498 | ||
8abd16a6 MB |
1499 | static irqreturn_t wm8903_irq(int irq, void *data) |
1500 | { | |
f0fba2ad LG |
1501 | struct snd_soc_codec *codec = data; |
1502 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); | |
7245387e MB |
1503 | int mic_report; |
1504 | int int_pol; | |
1505 | int int_val = 0; | |
1506 | int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK); | |
8abd16a6 | 1507 | |
7245387e | 1508 | int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask; |
8abd16a6 | 1509 | |
7245387e | 1510 | if (int_val & WM8903_WSEQ_BUSY_EINT) { |
8abd16a6 MB |
1511 | dev_dbg(codec->dev, "Write sequencer done\n"); |
1512 | complete(&wm8903->wseq); | |
1513 | } | |
1514 | ||
7245387e MB |
1515 | /* |
1516 | * The rest is microphone jack detection. We need to manually | |
1517 | * invert the polarity of the interrupt after each event - to | |
1518 | * simplify the code keep track of the last state we reported | |
1519 | * and just invert the relevant bits in both the report and | |
1520 | * the polarity register. | |
1521 | */ | |
1522 | mic_report = wm8903->mic_last_report; | |
1523 | int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1); | |
1524 | ||
1525 | if (int_val & WM8903_MICSHRT_EINT) { | |
1526 | dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol); | |
1527 | ||
1528 | mic_report ^= wm8903->mic_short; | |
1529 | int_pol ^= WM8903_MICSHRT_INV; | |
1530 | } | |
1531 | ||
1532 | if (int_val & WM8903_MICDET_EINT) { | |
1533 | dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol); | |
1534 | ||
1535 | mic_report ^= wm8903->mic_det; | |
1536 | int_pol ^= WM8903_MICDET_INV; | |
1537 | ||
1538 | msleep(wm8903->mic_delay); | |
1539 | } | |
1540 | ||
1541 | snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1, | |
1542 | WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol); | |
1543 | ||
1544 | snd_soc_jack_report(wm8903->mic_jack, mic_report, | |
1545 | wm8903->mic_short | wm8903->mic_det); | |
1546 | ||
1547 | wm8903->mic_last_report = mic_report; | |
1548 | ||
8abd16a6 MB |
1549 | return IRQ_HANDLED; |
1550 | } | |
1551 | ||
f1c0a02f MB |
1552 | #define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\ |
1553 | SNDRV_PCM_RATE_11025 | \ | |
1554 | SNDRV_PCM_RATE_16000 | \ | |
1555 | SNDRV_PCM_RATE_22050 | \ | |
1556 | SNDRV_PCM_RATE_32000 | \ | |
1557 | SNDRV_PCM_RATE_44100 | \ | |
1558 | SNDRV_PCM_RATE_48000 | \ | |
1559 | SNDRV_PCM_RATE_88200 | \ | |
1560 | SNDRV_PCM_RATE_96000) | |
1561 | ||
1562 | #define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ | |
1563 | SNDRV_PCM_RATE_11025 | \ | |
1564 | SNDRV_PCM_RATE_16000 | \ | |
1565 | SNDRV_PCM_RATE_22050 | \ | |
1566 | SNDRV_PCM_RATE_32000 | \ | |
1567 | SNDRV_PCM_RATE_44100 | \ | |
1568 | SNDRV_PCM_RATE_48000) | |
1569 | ||
1570 | #define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
1571 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
1572 | SNDRV_PCM_FMTBIT_S24_LE) | |
1573 | ||
6335d055 EM |
1574 | static struct snd_soc_dai_ops wm8903_dai_ops = { |
1575 | .startup = wm8903_startup, | |
1576 | .shutdown = wm8903_shutdown, | |
1577 | .hw_params = wm8903_hw_params, | |
1578 | .digital_mute = wm8903_digital_mute, | |
1579 | .set_fmt = wm8903_set_dai_fmt, | |
1580 | .set_sysclk = wm8903_set_dai_sysclk, | |
1581 | }; | |
1582 | ||
f0fba2ad LG |
1583 | static struct snd_soc_dai_driver wm8903_dai = { |
1584 | .name = "wm8903-hifi", | |
f1c0a02f MB |
1585 | .playback = { |
1586 | .stream_name = "Playback", | |
1587 | .channels_min = 2, | |
1588 | .channels_max = 2, | |
1589 | .rates = WM8903_PLAYBACK_RATES, | |
1590 | .formats = WM8903_FORMATS, | |
1591 | }, | |
1592 | .capture = { | |
1593 | .stream_name = "Capture", | |
1594 | .channels_min = 2, | |
1595 | .channels_max = 2, | |
1596 | .rates = WM8903_CAPTURE_RATES, | |
1597 | .formats = WM8903_FORMATS, | |
1598 | }, | |
6335d055 | 1599 | .ops = &wm8903_dai_ops, |
0d960e88 | 1600 | .symmetric_rates = 1, |
f1c0a02f | 1601 | }; |
f1c0a02f | 1602 | |
f0fba2ad | 1603 | static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state) |
f1c0a02f | 1604 | { |
f1c0a02f MB |
1605 | wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); |
1606 | ||
1607 | return 0; | |
1608 | } | |
1609 | ||
f0fba2ad | 1610 | static int wm8903_resume(struct snd_soc_codec *codec) |
f1c0a02f | 1611 | { |
f1c0a02f MB |
1612 | int i; |
1613 | u16 *reg_cache = codec->reg_cache; | |
40aa7030 | 1614 | u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults), |
f1c0a02f MB |
1615 | GFP_KERNEL); |
1616 | ||
1617 | /* Bring the codec back up to standby first to minimise pop/clicks */ | |
1618 | wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
f1c0a02f MB |
1619 | |
1620 | /* Sync back everything else */ | |
1621 | if (tmp_cache) { | |
1622 | for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++) | |
1623 | if (tmp_cache[i] != reg_cache[i]) | |
8d50e447 | 1624 | snd_soc_write(codec, i, tmp_cache[i]); |
40aa7030 | 1625 | kfree(tmp_cache); |
f1c0a02f | 1626 | } else { |
f0fba2ad | 1627 | dev_err(codec->dev, "Failed to allocate temporary cache\n"); |
f1c0a02f MB |
1628 | } |
1629 | ||
1630 | return 0; | |
1631 | } | |
1632 | ||
f0fba2ad | 1633 | static int wm8903_probe(struct snd_soc_codec *codec) |
f1c0a02f | 1634 | { |
f0fba2ad LG |
1635 | struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev); |
1636 | struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec); | |
73b34ead | 1637 | int ret, i; |
8abd16a6 | 1638 | int trigger, irq_pol; |
f1c0a02f MB |
1639 | u16 val; |
1640 | ||
8abd16a6 | 1641 | init_completion(&wm8903->wseq); |
d58d5d55 | 1642 | |
8d50e447 MB |
1643 | ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C); |
1644 | if (ret != 0) { | |
f0fba2ad LG |
1645 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); |
1646 | return ret; | |
8d50e447 MB |
1647 | } |
1648 | ||
1649 | val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID); | |
d58d5d55 | 1650 | if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) { |
f0fba2ad | 1651 | dev_err(codec->dev, |
d58d5d55 MB |
1652 | "Device with ID register %x is not a WM8903\n", val); |
1653 | return -ENODEV; | |
f1c0a02f MB |
1654 | } |
1655 | ||
8d50e447 | 1656 | val = snd_soc_read(codec, WM8903_REVISION_NUMBER); |
f0fba2ad | 1657 | dev_info(codec->dev, "WM8903 revision %d\n", |
f1c0a02f MB |
1658 | val & WM8903_CHIP_REV_MASK); |
1659 | ||
1660 | wm8903_reset(codec); | |
1661 | ||
37f88e84 | 1662 | /* Set up GPIOs and microphone detection */ |
73b34ead MB |
1663 | if (pdata) { |
1664 | for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) { | |
1665 | if (!pdata->gpio_cfg[i]) | |
1666 | continue; | |
1667 | ||
1668 | snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i, | |
1669 | pdata->gpio_cfg[i] & 0xffff); | |
1670 | } | |
37f88e84 MB |
1671 | |
1672 | snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, | |
1673 | pdata->micdet_cfg); | |
1674 | ||
1675 | /* Microphone detection needs the WSEQ clock */ | |
1676 | if (pdata->micdet_cfg) | |
1677 | snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0, | |
1678 | WM8903_WSEQ_ENA, WM8903_WSEQ_ENA); | |
1679 | ||
1680 | wm8903->mic_delay = pdata->micdet_delay; | |
73b34ead | 1681 | } |
8abd16a6 | 1682 | |
f0fba2ad | 1683 | if (wm8903->irq) { |
8abd16a6 MB |
1684 | if (pdata && pdata->irq_active_low) { |
1685 | trigger = IRQF_TRIGGER_LOW; | |
1686 | irq_pol = WM8903_IRQ_POL; | |
1687 | } else { | |
1688 | trigger = IRQF_TRIGGER_HIGH; | |
1689 | irq_pol = 0; | |
1690 | } | |
1691 | ||
1692 | snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL, | |
1693 | WM8903_IRQ_POL, irq_pol); | |
1694 | ||
f0fba2ad | 1695 | ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq, |
8abd16a6 | 1696 | trigger | IRQF_ONESHOT, |
f0fba2ad | 1697 | "wm8903", codec); |
8abd16a6 | 1698 | if (ret != 0) { |
f0fba2ad | 1699 | dev_err(codec->dev, "Failed to request IRQ: %d\n", |
8abd16a6 | 1700 | ret); |
f0fba2ad | 1701 | return ret; |
8abd16a6 MB |
1702 | } |
1703 | ||
1704 | /* Enable write sequencer interrupts */ | |
1705 | snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK, | |
1706 | WM8903_IM_WSEQ_BUSY_EINT, 0); | |
1707 | } | |
73b34ead | 1708 | |
f1c0a02f MB |
1709 | /* power on device */ |
1710 | wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1711 | ||
1712 | /* Latch volume update bits */ | |
8d50e447 | 1713 | val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT); |
f1c0a02f | 1714 | val |= WM8903_ADCVU; |
8d50e447 MB |
1715 | snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val); |
1716 | snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val); | |
f1c0a02f | 1717 | |
8d50e447 | 1718 | val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT); |
f1c0a02f | 1719 | val |= WM8903_DACVU; |
8d50e447 MB |
1720 | snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val); |
1721 | snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val); | |
f1c0a02f | 1722 | |
8d50e447 | 1723 | val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT); |
f1c0a02f | 1724 | val |= WM8903_HPOUTVU; |
8d50e447 MB |
1725 | snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val); |
1726 | snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val); | |
f1c0a02f | 1727 | |
8d50e447 | 1728 | val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT); |
f1c0a02f | 1729 | val |= WM8903_LINEOUTVU; |
8d50e447 MB |
1730 | snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val); |
1731 | snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val); | |
f1c0a02f | 1732 | |
8d50e447 | 1733 | val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT); |
f1c0a02f | 1734 | val |= WM8903_SPKVU; |
8d50e447 MB |
1735 | snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val); |
1736 | snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val); | |
f1c0a02f MB |
1737 | |
1738 | /* Enable DAC soft mute by default */ | |
8d50e447 | 1739 | val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1); |
f1c0a02f | 1740 | val |= WM8903_DAC_MUTEMODE; |
8d50e447 | 1741 | snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val); |
f1c0a02f | 1742 | |
f0fba2ad LG |
1743 | snd_soc_add_controls(codec, wm8903_snd_controls, |
1744 | ARRAY_SIZE(wm8903_snd_controls)); | |
1745 | wm8903_add_widgets(codec); | |
f1c0a02f | 1746 | |
f1c0a02f MB |
1747 | return ret; |
1748 | } | |
1749 | ||
f0fba2ad LG |
1750 | /* power down chip */ |
1751 | static int wm8903_remove(struct snd_soc_codec *codec) | |
f1c0a02f | 1752 | { |
f0fba2ad LG |
1753 | wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF); |
1754 | return 0; | |
1755 | } | |
f1c0a02f | 1756 | |
f0fba2ad LG |
1757 | static struct snd_soc_codec_driver soc_codec_dev_wm8903 = { |
1758 | .probe = wm8903_probe, | |
1759 | .remove = wm8903_remove, | |
1760 | .suspend = wm8903_suspend, | |
1761 | .resume = wm8903_resume, | |
1762 | .set_bias_level = wm8903_set_bias_level, | |
1763 | .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults), | |
1764 | .reg_word_size = sizeof(u16), | |
1765 | .reg_cache_default = wm8903_reg_defaults, | |
1766 | .volatile_register = wm8903_volatile_register, | |
1767 | }; | |
f1c0a02f | 1768 | |
f0fba2ad LG |
1769 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
1770 | static __devinit int wm8903_i2c_probe(struct i2c_client *i2c, | |
1771 | const struct i2c_device_id *id) | |
1772 | { | |
1773 | struct wm8903_priv *wm8903; | |
1774 | int ret; | |
f1c0a02f | 1775 | |
f0fba2ad LG |
1776 | wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL); |
1777 | if (wm8903 == NULL) | |
1778 | return -ENOMEM; | |
8abd16a6 | 1779 | |
f0fba2ad | 1780 | i2c_set_clientdata(i2c, wm8903); |
f0fba2ad | 1781 | wm8903->irq = i2c->irq; |
d58d5d55 | 1782 | |
f0fba2ad LG |
1783 | ret = snd_soc_register_codec(&i2c->dev, |
1784 | &soc_codec_dev_wm8903, &wm8903_dai, 1); | |
1785 | if (ret < 0) | |
1786 | kfree(wm8903); | |
1787 | return ret; | |
1788 | } | |
f1c0a02f | 1789 | |
f0fba2ad LG |
1790 | static __devexit int wm8903_i2c_remove(struct i2c_client *client) |
1791 | { | |
1792 | snd_soc_unregister_codec(&client->dev); | |
1793 | kfree(i2c_get_clientdata(client)); | |
f1c0a02f MB |
1794 | return 0; |
1795 | } | |
1796 | ||
f1c0a02f | 1797 | static const struct i2c_device_id wm8903_i2c_id[] = { |
f0fba2ad LG |
1798 | { "wm8903", 0 }, |
1799 | { } | |
f1c0a02f MB |
1800 | }; |
1801 | MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id); | |
1802 | ||
1803 | static struct i2c_driver wm8903_i2c_driver = { | |
1804 | .driver = { | |
f0fba2ad | 1805 | .name = "wm8903-codec", |
f1c0a02f MB |
1806 | .owner = THIS_MODULE, |
1807 | }, | |
f0fba2ad LG |
1808 | .probe = wm8903_i2c_probe, |
1809 | .remove = __devexit_p(wm8903_i2c_remove), | |
f1c0a02f MB |
1810 | .id_table = wm8903_i2c_id, |
1811 | }; | |
f0fba2ad | 1812 | #endif |
f1c0a02f | 1813 | |
f0fba2ad | 1814 | static int __init wm8903_modinit(void) |
f1c0a02f | 1815 | { |
f1c0a02f | 1816 | int ret = 0; |
f0fba2ad LG |
1817 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
1818 | ret = i2c_add_driver(&wm8903_i2c_driver); | |
1819 | if (ret != 0) { | |
1820 | printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n", | |
1821 | ret); | |
f1c0a02f | 1822 | } |
f0fba2ad | 1823 | #endif |
f1c0a02f | 1824 | return ret; |
64089b84 MB |
1825 | } |
1826 | module_init(wm8903_modinit); | |
1827 | ||
1828 | static void __exit wm8903_exit(void) | |
1829 | { | |
f0fba2ad | 1830 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
d58d5d55 | 1831 | i2c_del_driver(&wm8903_i2c_driver); |
f0fba2ad | 1832 | #endif |
64089b84 MB |
1833 | } |
1834 | module_exit(wm8903_exit); | |
1835 | ||
f1c0a02f MB |
1836 | MODULE_DESCRIPTION("ASoC WM8903 driver"); |
1837 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>"); | |
1838 | MODULE_LICENSE("GPL"); |