projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-2.6-block.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
14 * - Mic detect.
15 * - Digital microphone support.
16 * - Interrupt support (mic detect and sequencer).
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/pm.h>
24#include <linux/i2c.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
f1c0a02f
MB		 27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/tlv.h>
31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33#include <sound/initval.h>
34
35#include "wm8903.h"
36
f1c0a02f
MB		 37/* Register defaults at reset */
38static u16 wm8903_reg_defaults[] = {
39 0x8903, /* R0 - SW Reset and ID */
40 0x0000, /* R1 - Revision Number */
41 0x0000, /* R2 */
42 0x0000, /* R3 */
43 0x0018, /* R4 - Bias Control 0 */
44 0x0000, /* R5 - VMID Control 0 */
45 0x0000, /* R6 - Mic Bias Control 0 */
46 0x0000, /* R7 */
47 0x0001, /* R8 - Analogue DAC 0 */
48 0x0000, /* R9 */
49 0x0001, /* R10 - Analogue ADC 0 */
50 0x0000, /* R11 */
51 0x0000, /* R12 - Power Management 0 */
52 0x0000, /* R13 - Power Management 1 */
53 0x0000, /* R14 - Power Management 2 */
54 0x0000, /* R15 - Power Management 3 */
55 0x0000, /* R16 - Power Management 4 */
56 0x0000, /* R17 - Power Management 5 */
57 0x0000, /* R18 - Power Management 6 */
58 0x0000, /* R19 */
59 0x0400, /* R20 - Clock Rates 0 */
60 0x0D07, /* R21 - Clock Rates 1 */
61 0x0000, /* R22 - Clock Rates 2 */
62 0x0000, /* R23 */
63 0x0050, /* R24 - Audio Interface 0 */
64 0x0242, /* R25 - Audio Interface 1 */
65 0x0008, /* R26 - Audio Interface 2 */
66 0x0022, /* R27 - Audio Interface 3 */
67 0x0000, /* R28 */
68 0x0000, /* R29 */
69 0x00C0, /* R30 - DAC Digital Volume Left */
70 0x00C0, /* R31 - DAC Digital Volume Right */
71 0x0000, /* R32 - DAC Digital 0 */
72 0x0000, /* R33 - DAC Digital 1 */
73 0x0000, /* R34 */
74 0x0000, /* R35 */
75 0x00C0, /* R36 - ADC Digital Volume Left */
76 0x00C0, /* R37 - ADC Digital Volume Right */
77 0x0000, /* R38 - ADC Digital 0 */
78 0x0073, /* R39 - Digital Microphone 0 */
79 0x09BF, /* R40 - DRC 0 */
80 0x3241, /* R41 - DRC 1 */
81 0x0020, /* R42 - DRC 2 */
82 0x0000, /* R43 - DRC 3 */
83 0x0085, /* R44 - Analogue Left Input 0 */
84 0x0085, /* R45 - Analogue Right Input 0 */
85 0x0044, /* R46 - Analogue Left Input 1 */
86 0x0044, /* R47 - Analogue Right Input 1 */
87 0x0000, /* R48 */
88 0x0000, /* R49 */
89 0x0008, /* R50 - Analogue Left Mix 0 */
90 0x0004, /* R51 - Analogue Right Mix 0 */
91 0x0000, /* R52 - Analogue Spk Mix Left 0 */
92 0x0000, /* R53 - Analogue Spk Mix Left 1 */
93 0x0000, /* R54 - Analogue Spk Mix Right 0 */
94 0x0000, /* R55 - Analogue Spk Mix Right 1 */
95 0x0000, /* R56 */
96 0x002D, /* R57 - Analogue OUT1 Left */
97 0x002D, /* R58 - Analogue OUT1 Right */
98 0x0039, /* R59 - Analogue OUT2 Left */
99 0x0039, /* R60 - Analogue OUT2 Right */
100 0x0100, /* R61 */
101 0x0139, /* R62 - Analogue OUT3 Left */
102 0x0139, /* R63 - Analogue OUT3 Right */
103 0x0000, /* R64 */
104 0x0000, /* R65 - Analogue SPK Output Control 0 */
105 0x0000, /* R66 */
106 0x0010, /* R67 - DC Servo 0 */
107 0x0100, /* R68 */
108 0x00A4, /* R69 - DC Servo 2 */
109 0x0807, /* R70 */
110 0x0000, /* R71 */
111 0x0000, /* R72 */
112 0x0000, /* R73 */
113 0x0000, /* R74 */
114 0x0000, /* R75 */
115 0x0000, /* R76 */
116 0x0000, /* R77 */
117 0x0000, /* R78 */
118 0x000E, /* R79 */
119 0x0000, /* R80 */
120 0x0000, /* R81 */
121 0x0000, /* R82 */
122 0x0000, /* R83 */
123 0x0000, /* R84 */
124 0x0000, /* R85 */
125 0x0000, /* R86 */
126 0x0006, /* R87 */
127 0x0000, /* R88 */
128 0x0000, /* R89 */
129 0x0000, /* R90 - Analogue HP 0 */
130 0x0060, /* R91 */
131 0x0000, /* R92 */
132 0x0000, /* R93 */
133 0x0000, /* R94 - Analogue Lineout 0 */
134 0x0060, /* R95 */
135 0x0000, /* R96 */
136 0x0000, /* R97 */
137 0x0000, /* R98 - Charge Pump 0 */
138 0x1F25, /* R99 */
139 0x2B19, /* R100 */
140 0x01C0, /* R101 */
141 0x01EF, /* R102 */
142 0x2B00, /* R103 */
143 0x0000, /* R104 - Class W 0 */
144 0x01C0, /* R105 */
145 0x1C10, /* R106 */
146 0x0000, /* R107 */
147 0x0000, /* R108 - Write Sequencer 0 */
148 0x0000, /* R109 - Write Sequencer 1 */
149 0x0000, /* R110 - Write Sequencer 2 */
150 0x0000, /* R111 - Write Sequencer 3 */
151 0x0000, /* R112 - Write Sequencer 4 */
152 0x0000, /* R113 */
153 0x0000, /* R114 - Control Interface */
154 0x0000, /* R115 */
155 0x00A8, /* R116 - GPIO Control 1 */
156 0x00A8, /* R117 - GPIO Control 2 */
157 0x00A8, /* R118 - GPIO Control 3 */
158 0x0220, /* R119 - GPIO Control 4 */
159 0x01A0, /* R120 - GPIO Control 5 */
160 0x0000, /* R121 - Interrupt Status 1 */
161 0xFFFF, /* R122 - Interrupt Status 1 Mask */
162 0x0000, /* R123 - Interrupt Polarity 1 */
163 0x0000, /* R124 */
164 0x0003, /* R125 */
165 0x0000, /* R126 - Interrupt Control */
166 0x0000, /* R127 */
167 0x0005, /* R128 */
168 0x0000, /* R129 - Control Interface Test 1 */
169 0x0000, /* R130 */
170 0x0000, /* R131 */
171 0x0000, /* R132 */
172 0x0000, /* R133 */
173 0x0000, /* R134 */
174 0x03FF, /* R135 */
175 0x0007, /* R136 */
176 0x0040, /* R137 */
177 0x0000, /* R138 */
178 0x0000, /* R139 */
179 0x0000, /* R140 */
180 0x0000, /* R141 */
181 0x0000, /* R142 */
182 0x0000, /* R143 */
183 0x0000, /* R144 */
184 0x0000, /* R145 */
185 0x0000, /* R146 */
186 0x0000, /* R147 */
187 0x4000, /* R148 */
188 0x6810, /* R149 - Charge Pump Test 1 */
189 0x0004, /* R150 */
190 0x0000, /* R151 */
191 0x0000, /* R152 */
192 0x0000, /* R153 */
193 0x0000, /* R154 */
194 0x0000, /* R155 */
195 0x0000, /* R156 */
196 0x0000, /* R157 */
197 0x0000, /* R158 */
198 0x0000, /* R159 */
199 0x0000, /* R160 */
200 0x0000, /* R161 */
201 0x0000, /* R162 */
202 0x0000, /* R163 */
203 0x0028, /* R164 - Clock Rate Test 4 */
204 0x0004, /* R165 */
205 0x0000, /* R166 */
206 0x0060, /* R167 */
207 0x0000, /* R168 */
208 0x0000, /* R169 */
209 0x0000, /* R170 */
210 0x0000, /* R171 */
211 0x0000, /* R172 - Analogue Output Bias 0 */
212};
213
d58d5d55
MB		 214struct wm8903_priv {
215 struct snd_soc_codec codec;
216 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
217
218 int sysclk;
219
220 /* Reference counts */
d58d5d55
MB		 221 int class_w_users;
222 int playback_active;
223 int capture_active;
224
225 struct snd_pcm_substream *master_substream;
226 struct snd_pcm_substream *slave_substream;
227};
228
8d50e447 229static int wm8903_volatile_register(unsigned int reg)
f1c0a02f
MB		 230{
231 switch (reg) {
232 case WM8903_SW_RESET_AND_ID:
233 case WM8903_REVISION_NUMBER:
234 case WM8903_INTERRUPT_STATUS_1:
235 case WM8903_WRITE_SEQUENCER_4:
8d50e447 236 return 1;
f1c0a02f
MB		 237
238 default:
f1c0a02f 239 return 0;
8d50e447 240 }
f1c0a02f
MB		 241}
242
243static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
244{
245 u16 reg[5];
246 struct i2c_client *i2c = codec->control_data;
247
248 BUG_ON(start > 48);
249
250 /* Enable the sequencer */
8d50e447 251 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
f1c0a02f 252 reg[0] |= WM8903_WSEQ_ENA;
8d50e447 253 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 254
255 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
256
8d50e447 257 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 258 start | WM8903_WSEQ_START);
259
260 /* Wait for it to complete. If we have the interrupt wired up then
261 * we could block waiting for an interrupt, though polling may still
262 * be desirable for diagnostic purposes.
263 */
264 do {
265 msleep(10);
266
8d50e447 267 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 268 } while (reg[4] & WM8903_WSEQ_BUSY);
269
270 dev_dbg(&i2c->dev, "Sequence complete\n");
271
272 /* Disable the sequencer again */
8d50e447 273 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
f1c0a02f
MB		 274 reg[0] & ~WM8903_WSEQ_ENA);
275
276 return 0;
277}
278
279static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
280{
281 int i;
282
283 /* There really ought to be something better we can do here :/ */
284 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 285 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 286}
287
288static void wm8903_reset(struct snd_soc_codec *codec)
289{
8d50e447 290 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 291 memcpy(codec->reg_cache, wm8903_reg_defaults,
292 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 293}
294
295#define WM8903_OUTPUT_SHORT 0x8
296#define WM8903_OUTPUT_OUT 0x4
297#define WM8903_OUTPUT_INT 0x2
298#define WM8903_OUTPUT_IN 0x1
299
42768a12
MB		 300static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
301 struct snd_kcontrol *kcontrol, int event)
302{
303 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
304 mdelay(4);
305
306 return 0;
307}
308
f1c0a02f
MB		 309/*
310 * Event for headphone and line out amplifier power changes. Special
311 * power up/down sequences are required in order to maximise pop/click
312 * performance.
313 */
314static int wm8903_output_event(struct snd_soc_dapm_widget *w,
315 struct snd_kcontrol *kcontrol, int event)
316{
317 struct snd_soc_codec *codec = w->codec;
f1c0a02f 318 u16 val;
0bc286e2 319 u16 reg;
d7d5c547
MB		 320 u16 dcs_reg;
321 u16 dcs_bit;
0bc286e2 322 int shift;
f1c0a02f
MB		 323
324 switch (w->reg) {
325 case WM8903_POWER_MANAGEMENT_2:
326 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 327 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 328 break;
329 case WM8903_POWER_MANAGEMENT_3:
330 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 331 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 332 break;
333 default:
334 BUG();
1e297a19 335 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 336 }
337
338 switch (w->shift) {
339 case 0:
340 shift = 0;
341 break;
342 case 1:
343 shift = 4;
344 break;
345 default:
346 BUG();
1e297a19 347 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 348 }
349
350 if (event & SND_SOC_DAPM_PRE_PMU) {
8d50e447 351 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 352
353 /* Short the output */
354 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 355 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 356 }
357
358 if (event & SND_SOC_DAPM_POST_PMU) {
8d50e447 359 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 360
361 val |= (WM8903_OUTPUT_IN << shift);
8d50e447 362 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 363
364 val |= (WM8903_OUTPUT_INT << shift);
8d50e447 365 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 366
367 /* Turn on the output ENA_OUTP */
368 val |= (WM8903_OUTPUT_OUT << shift);
8d50e447 369 snd_soc_write(codec, reg, val);
f1c0a02f 370
d7d5c547 371 /* Enable the DC servo */
8d50e447 372 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 373 dcs_reg |= dcs_bit;
8d50e447 374 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 375
f1c0a02f
MB		 376 /* Remove the short */
377 val |= (WM8903_OUTPUT_SHORT << shift);
8d50e447 378 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 379 }
380
381 if (event & SND_SOC_DAPM_PRE_PMD) {
8d50e447 382 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 383
384 /* Short the output */
385 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 386 snd_soc_write(codec, reg, val);
f1c0a02f 387
d7d5c547 388 /* Disable the DC servo */
8d50e447 389 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 390 dcs_reg &= ~dcs_bit;
8d50e447 391 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 392
f1c0a02f
MB		 393 /* Then disable the intermediate and output stages */
394 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
395 WM8903_OUTPUT_IN) << shift);
8d50e447 396 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 397 }
398
f1c0a02f
MB		 399 return 0;
400}
401
402/*
403 * When used with DAC outputs only the WM8903 charge pump supports
404 * operation in class W mode, providing very low power consumption
405 * when used with digital sources. Enable and disable this mode
406 * automatically depending on the mixer configuration.
407 *
408 * All the relevant controls are simple switches.
409 */
410static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
411 struct snd_ctl_elem_value *ucontrol)
412{
413 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
414 struct snd_soc_codec *codec = widget->codec;
415 struct wm8903_priv *wm8903 = codec->private_data;
416 struct i2c_client *i2c = codec->control_data;
417 u16 reg;
418 int ret;
419
8d50e447 420 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 421
422 /* Turn it off if we're about to enable bypass */
423 if (ucontrol->value.integer.value[0]) {
424 if (wm8903->class_w_users == 0) {
425 dev_dbg(&i2c->dev, "Disabling Class W\n");
8d50e447 426 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 427 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
428 }
429 wm8903->class_w_users++;
430 }
431
432 /* Implement the change */
433 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
434
435 /* If we've just disabled the last bypass path turn Class W on */
436 if (!ucontrol->value.integer.value[0]) {
437 if (wm8903->class_w_users == 1) {
438 dev_dbg(&i2c->dev, "Enabling Class W\n");
8d50e447 439 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 440 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
441 }
442 wm8903->class_w_users--;
443 }
444
445 dev_dbg(&i2c->dev, "Bypass use count now %d\n",
446 wm8903->class_w_users);
447
448 return ret;
449}
450
451#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
452{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
453 .info = snd_soc_info_volsw, \
454 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
455 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
456
457
458/* ALSA can only do steps of .01dB */
459static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
460
291ce18c 461static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 462static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
463
464static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
465static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
466static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
467static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
468static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
469
470static const char *drc_slope_text[] = {
471 "1", "1/2", "1/4", "1/8", "1/16", "0"
472};
473
474static const struct soc_enum drc_slope_r0 =
475 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
476
477static const struct soc_enum drc_slope_r1 =
478 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
479
480static const char *drc_attack_text[] = {
481 "instantaneous",
482 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
483 "46.4ms", "92.8ms", "185.6ms"
484};
485
486static const struct soc_enum drc_attack =
487 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
488
489static const char *drc_decay_text[] = {
490 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
491 "23.87s", "47.56s"
492};
493
494static const struct soc_enum drc_decay =
495 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
496
497static const char *drc_ff_delay_text[] = {
498 "5 samples", "9 samples"
499};
500
501static const struct soc_enum drc_ff_delay =
502 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
503
504static const char *drc_qr_decay_text[] = {
505 "0.725ms", "1.45ms", "5.8ms"
506};
507
508static const struct soc_enum drc_qr_decay =
509 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
510
511static const char *drc_smoothing_text[] = {
512 "Low", "Medium", "High"
513};
514
515static const struct soc_enum drc_smoothing =
516 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
517
518static const char *soft_mute_text[] = {
519 "Fast (fs/2)", "Slow (fs/32)"
520};
521
522static const struct soc_enum soft_mute =
523 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
524
525static const char *mute_mode_text[] = {
526 "Hard", "Soft"
527};
528
529static const struct soc_enum mute_mode =
530 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
531
532static const char *dac_deemphasis_text[] = {
533 "Disabled", "32kHz", "44.1kHz", "48kHz"
534};
535
536static const struct soc_enum dac_deemphasis =
537 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
538
539static const char *companding_text[] = {
540 "ulaw", "alaw"
541};
542
543static const struct soc_enum dac_companding =
544 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
545
546static const struct soc_enum adc_companding =
547 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
548
549static const char *input_mode_text[] = {
550 "Single-Ended", "Differential Line", "Differential Mic"
551};
552
553static const struct soc_enum linput_mode_enum =
554 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
555
556static const struct soc_enum rinput_mode_enum =
557 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
558
559static const char *linput_mux_text[] = {
560 "IN1L", "IN2L", "IN3L"
561};
562
563static const struct soc_enum linput_enum =
564 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
565
566static const struct soc_enum linput_inv_enum =
567 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
568
569static const char *rinput_mux_text[] = {
570 "IN1R", "IN2R", "IN3R"
571};
572
573static const struct soc_enum rinput_enum =
574 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
575
576static const struct soc_enum rinput_inv_enum =
577 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
578
579
291ce18c
MB		 580static const char *sidetone_text[] = {
581 "None", "Left", "Right"
582};
583
584static const struct soc_enum lsidetone_enum =
585 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
586
587static const struct soc_enum rsidetone_enum =
588 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
589
f1c0a02f
MB		 590static const struct snd_kcontrol_new wm8903_snd_controls[] = {
591
592/* Input PGAs - No TLV since the scale depends on PGA mode */
593SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 594 7, 1, 1),
f1c0a02f
MB		 595SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
596 0, 31, 0),
597SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
598 6, 1, 0),
599
600SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 601 7, 1, 1),
f1c0a02f
MB		 602SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
603 0, 31, 0),
604SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
605 6, 1, 0),
606
607/* ADCs */
608SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
609SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
610SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 611SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 612 drc_tlv_thresh),
613SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
614SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
615SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
616SOC_ENUM("DRC Attack Rate", drc_attack),
617SOC_ENUM("DRC Decay Rate", drc_decay),
618SOC_ENUM("DRC FF Delay", drc_ff_delay),
619SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
620SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 621SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 622SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
623SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
624SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 625SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 626SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
627
628SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
629 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
630SOC_ENUM("ADC Companding Mode", adc_companding),
631SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
632
291ce18c
MB		 633SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
634 12, 0, digital_sidetone_tlv),
635
f1c0a02f
MB		 636/* DAC */
637SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
638 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
639SOC_ENUM("DAC Soft Mute Rate", soft_mute),
640SOC_ENUM("DAC Mute Mode", mute_mode),
641SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
642SOC_ENUM("DAC De-emphasis", dac_deemphasis),
f1c0a02f
MB		 643SOC_ENUM("DAC Companding Mode", dac_companding),
644SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
645
646/* Headphones */
647SOC_DOUBLE_R("Headphone Switch",
648 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
649 8, 1, 1),
650SOC_DOUBLE_R("Headphone ZC Switch",
651 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
652 6, 1, 0),
653SOC_DOUBLE_R_TLV("Headphone Volume",
654 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
655 0, 63, 0, out_tlv),
656
657/* Line out */
658SOC_DOUBLE_R("Line Out Switch",
659 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
660 8, 1, 1),
661SOC_DOUBLE_R("Line Out ZC Switch",
662 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
663 6, 1, 0),
664SOC_DOUBLE_R_TLV("Line Out Volume",
665 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
666 0, 63, 0, out_tlv),
667
668/* Speaker */
669SOC_DOUBLE_R("Speaker Switch",
670 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
671SOC_DOUBLE_R("Speaker ZC Switch",
672 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
673SOC_DOUBLE_R_TLV("Speaker Volume",
674 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
675 0, 63, 0, out_tlv),
676};
677
f1c0a02f
MB		 678static const struct snd_kcontrol_new linput_mode_mux =
679 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
680
681static const struct snd_kcontrol_new rinput_mode_mux =
682 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
683
684static const struct snd_kcontrol_new linput_mux =
685 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
686
687static const struct snd_kcontrol_new linput_inv_mux =
688 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
689
690static const struct snd_kcontrol_new rinput_mux =
691 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
692
693static const struct snd_kcontrol_new rinput_inv_mux =
694 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
695
291ce18c
MB		 696static const struct snd_kcontrol_new lsidetone_mux =
697 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
698
699static const struct snd_kcontrol_new rsidetone_mux =
700 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
701
f1c0a02f
MB		 702static const struct snd_kcontrol_new left_output_mixer[] = {
703SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
704SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
705SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 706SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 707};
708
709static const struct snd_kcontrol_new right_output_mixer[] = {
710SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
711SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
712SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 713SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 714};
715
716static const struct snd_kcontrol_new left_speaker_mixer[] = {
717SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
718SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
719SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
720SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 721 0, 1, 0),
f1c0a02f
MB		 722};
723
724static const struct snd_kcontrol_new right_speaker_mixer[] = {
725SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
726SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
727SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
728 1, 1, 0),
729SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 730 0, 1, 0),
f1c0a02f
MB		 731};
732
733static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
734SND_SOC_DAPM_INPUT("IN1L"),
735SND_SOC_DAPM_INPUT("IN1R"),
736SND_SOC_DAPM_INPUT("IN2L"),
737SND_SOC_DAPM_INPUT("IN2R"),
738SND_SOC_DAPM_INPUT("IN3L"),
739SND_SOC_DAPM_INPUT("IN3R"),
740
741SND_SOC_DAPM_OUTPUT("HPOUTL"),
742SND_SOC_DAPM_OUTPUT("HPOUTR"),
743SND_SOC_DAPM_OUTPUT("LINEOUTL"),
744SND_SOC_DAPM_OUTPUT("LINEOUTR"),
745SND_SOC_DAPM_OUTPUT("LOP"),
746SND_SOC_DAPM_OUTPUT("LON"),
747SND_SOC_DAPM_OUTPUT("ROP"),
748SND_SOC_DAPM_OUTPUT("RON"),
749
750SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
751
752SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
753SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
754 &linput_inv_mux),
755SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
756
757SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
758SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
759 &rinput_inv_mux),
760SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
761
762SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
763SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
764
765SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
766SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
767
291ce18c
MB		 768SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
769SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
770
f1c0a02f
MB		 771SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
772SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
773
774SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
775 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
776SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
777 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
778
779SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
780 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
781SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
782 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
783
784SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
785 1, 0, NULL, 0, wm8903_output_event,
786 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 787 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 788SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
789 0, 0, NULL, 0, wm8903_output_event,
790 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 791 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 792
793SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
794 NULL, 0, wm8903_output_event,
795 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 796 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 797SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
798 NULL, 0, wm8903_output_event,
799 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 800 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 801
802SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
803 NULL, 0),
804SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
805 NULL, 0),
806
42768a12
MB		 807SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
808 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 809SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 810};
811
812static const struct snd_soc_dapm_route intercon[] = {
813
814 { "Left Input Mux", "IN1L", "IN1L" },
815 { "Left Input Mux", "IN2L", "IN2L" },
816 { "Left Input Mux", "IN3L", "IN3L" },
817
818 { "Left Input Inverting Mux", "IN1L", "IN1L" },
819 { "Left Input Inverting Mux", "IN2L", "IN2L" },
820 { "Left Input Inverting Mux", "IN3L", "IN3L" },
821
822 { "Right Input Mux", "IN1R", "IN1R" },
823 { "Right Input Mux", "IN2R", "IN2R" },
824 { "Right Input Mux", "IN3R", "IN3R" },
825
826 { "Right Input Inverting Mux", "IN1R", "IN1R" },
827 { "Right Input Inverting Mux", "IN2R", "IN2R" },
828 { "Right Input Inverting Mux", "IN3R", "IN3R" },
829
830 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
831 { "Left Input Mode Mux", "Differential Line",
832 "Left Input Mux" },
833 { "Left Input Mode Mux", "Differential Line",
834 "Left Input Inverting Mux" },
835 { "Left Input Mode Mux", "Differential Mic",
836 "Left Input Mux" },
837 { "Left Input Mode Mux", "Differential Mic",
838 "Left Input Inverting Mux" },
839
840 { "Right Input Mode Mux", "Single-Ended",
841 "Right Input Inverting Mux" },
842 { "Right Input Mode Mux", "Differential Line",
843 "Right Input Mux" },
844 { "Right Input Mode Mux", "Differential Line",
845 "Right Input Inverting Mux" },
846 { "Right Input Mode Mux", "Differential Mic",
847 "Right Input Mux" },
848 { "Right Input Mode Mux", "Differential Mic",
849 "Right Input Inverting Mux" },
850
851 { "Left Input PGA", NULL, "Left Input Mode Mux" },
852 { "Right Input PGA", NULL, "Right Input Mode Mux" },
853
854 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 855 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 856 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 857 { "ADCR", NULL, "CLK_DSP" },
858
291ce18c
MB		 859 { "DACL Sidetone", "Left", "ADCL" },
860 { "DACL Sidetone", "Right", "ADCR" },
861 { "DACR Sidetone", "Left", "ADCL" },
862 { "DACR Sidetone", "Right", "ADCR" },
863
864 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 865 { "DACL", NULL, "CLK_DSP" },
291ce18c 866 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 867 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 868
869 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
870 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
871 { "Left Output Mixer", "DACL Switch", "DACL" },
872 { "Left Output Mixer", "DACR Switch", "DACR" },
873
874 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
875 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
876 { "Right Output Mixer", "DACL Switch", "DACL" },
877 { "Right Output Mixer", "DACR Switch", "DACR" },
878
879 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
880 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
881 { "Left Speaker Mixer", "DACL Switch", "DACL" },
882 { "Left Speaker Mixer", "DACR Switch", "DACR" },
883
884 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
885 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
886 { "Right Speaker Mixer", "DACL Switch", "DACL" },
887 { "Right Speaker Mixer", "DACR Switch", "DACR" },
888
889 { "Left Line Output PGA", NULL, "Left Output Mixer" },
890 { "Right Line Output PGA", NULL, "Right Output Mixer" },
891
892 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
893 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
894
895 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
896 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
897
898 { "HPOUTL", NULL, "Left Headphone Output PGA" },
899 { "HPOUTR", NULL, "Right Headphone Output PGA" },
900
901 { "LINEOUTL", NULL, "Left Line Output PGA" },
902 { "LINEOUTR", NULL, "Right Line Output PGA" },
903
904 { "LOP", NULL, "Left Speaker PGA" },
905 { "LON", NULL, "Left Speaker PGA" },
906
907 { "ROP", NULL, "Right Speaker PGA" },
908 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 909
910 { "Left Headphone Output PGA", NULL, "Charge Pump" },
911 { "Right Headphone Output PGA", NULL, "Charge Pump" },
912 { "Left Line Output PGA", NULL, "Charge Pump" },
913 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 914};
915
916static int wm8903_add_widgets(struct snd_soc_codec *codec)
917{
918 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
919 ARRAY_SIZE(wm8903_dapm_widgets));
920
921 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
922
f1c0a02f
MB		 923 return 0;
924}
925
926static int wm8903_set_bias_level(struct snd_soc_codec *codec,
927 enum snd_soc_bias_level level)
928{
929 struct i2c_client *i2c = codec->control_data;
930 u16 reg, reg2;
931
932 switch (level) {
933 case SND_SOC_BIAS_ON:
934 case SND_SOC_BIAS_PREPARE:
8d50e447 935 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 936 reg &= ~(WM8903_VMID_RES_MASK);
937 reg |= WM8903_VMID_RES_50K;
8d50e447 938 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 939 break;
940
941 case SND_SOC_BIAS_STANDBY:
942 if (codec->bias_level == SND_SOC_BIAS_OFF) {
8d50e447 943 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 944 WM8903_CLK_SYS_ENA);
945
4dbfe809 946 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 947 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
948 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
949 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 950
f1c0a02f
MB		 951 wm8903_run_sequence(codec, 0);
952 wm8903_sync_reg_cache(codec, codec->reg_cache);
953
954 /* Enable low impedence charge pump output */
8d50e447 955 reg = snd_soc_read(codec,
f1c0a02f 956 WM8903_CONTROL_INTERFACE_TEST_1);
8d50e447 957 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f 958 reg | WM8903_TEST_KEY);
8d50e447
MB		 959 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
960 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
f1c0a02f 961 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
8d50e447 962 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f
MB		 963 reg);
964
965 /* By default no bypass paths are enabled so
966 * enable Class W support.
967 */
968 dev_dbg(&i2c->dev, "Enabling Class W\n");
8d50e447 969 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 970 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
971 }
972
8d50e447 973 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 974 reg &= ~(WM8903_VMID_RES_MASK);
975 reg |= WM8903_VMID_RES_250K;
8d50e447 976 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 977 break;
978
979 case SND_SOC_BIAS_OFF:
980 wm8903_run_sequence(codec, 32);
8d50e447 981 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
3b1228ab 982 reg &= ~WM8903_CLK_SYS_ENA;
8d50e447 983 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 984 break;
985 }
986
987 codec->bias_level = level;
988
989 return 0;
990}
991
992static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
993 int clk_id, unsigned int freq, int dir)
994{
995 struct snd_soc_codec *codec = codec_dai->codec;
996 struct wm8903_priv *wm8903 = codec->private_data;
997
998 wm8903->sysclk = freq;
999
1000 return 0;
1001}
1002
1003static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1004 unsigned int fmt)
1005{
1006 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1007 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1008
1009 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1010 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1011
1012 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1013 case SND_SOC_DAIFMT_CBS_CFS:
1014 break;
1015 case SND_SOC_DAIFMT_CBS_CFM:
1016 aif1 |= WM8903_LRCLK_DIR;
1017 break;
1018 case SND_SOC_DAIFMT_CBM_CFM:
1019 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1020 break;
1021 case SND_SOC_DAIFMT_CBM_CFS:
1022 aif1 |= WM8903_BCLK_DIR;
1023 break;
1024 default:
1025 return -EINVAL;
1026 }
1027
1028 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1029 case SND_SOC_DAIFMT_DSP_A:
1030 aif1 |= 0x3;
1031 break;
1032 case SND_SOC_DAIFMT_DSP_B:
1033 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1034 break;
1035 case SND_SOC_DAIFMT_I2S:
1036 aif1 |= 0x2;
1037 break;
1038 case SND_SOC_DAIFMT_RIGHT_J:
1039 aif1 |= 0x1;
1040 break;
1041 case SND_SOC_DAIFMT_LEFT_J:
1042 break;
1043 default:
1044 return -EINVAL;
1045 }
1046
1047 /* Clock inversion */
1048 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1049 case SND_SOC_DAIFMT_DSP_A:
1050 case SND_SOC_DAIFMT_DSP_B:
1051 /* frame inversion not valid for DSP modes */
1052 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1053 case SND_SOC_DAIFMT_NB_NF:
1054 break;
1055 case SND_SOC_DAIFMT_IB_NF:
1056 aif1 |= WM8903_AIF_BCLK_INV;
1057 break;
1058 default:
1059 return -EINVAL;
1060 }
1061 break;
1062 case SND_SOC_DAIFMT_I2S:
1063 case SND_SOC_DAIFMT_RIGHT_J:
1064 case SND_SOC_DAIFMT_LEFT_J:
1065 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1066 case SND_SOC_DAIFMT_NB_NF:
1067 break;
1068 case SND_SOC_DAIFMT_IB_IF:
1069 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1070 break;
1071 case SND_SOC_DAIFMT_IB_NF:
1072 aif1 |= WM8903_AIF_BCLK_INV;
1073 break;
1074 case SND_SOC_DAIFMT_NB_IF:
1075 aif1 |= WM8903_AIF_LRCLK_INV;
1076 break;
1077 default:
1078 return -EINVAL;
1079 }
1080 break;
1081 default:
1082 return -EINVAL;
1083 }
1084
8d50e447 1085 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1086
1087 return 0;
1088}
1089
1090static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1091{
1092 struct snd_soc_codec *codec = codec_dai->codec;
1093 u16 reg;
1094
8d50e447 1095 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1096
1097 if (mute)
1098 reg |= WM8903_DAC_MUTE;
1099 else
1100 reg &= ~WM8903_DAC_MUTE;
1101
8d50e447 1102 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1103
1104 return 0;
1105}
1106
1107/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1108 * for optimal performance so we list the lower rates first and match
1109 * on the last match we find. */
1110static struct {
1111 int div;
1112 int rate;
1113 int mode;
1114 int mclk_div;
1115} clk_sys_ratios[] = {
1116 { 64, 0x0, 0x0, 1 },
1117 { 68, 0x0, 0x1, 1 },
1118 { 125, 0x0, 0x2, 1 },
1119 { 128, 0x1, 0x0, 1 },
1120 { 136, 0x1, 0x1, 1 },
1121 { 192, 0x2, 0x0, 1 },
1122 { 204, 0x2, 0x1, 1 },
1123
1124 { 64, 0x0, 0x0, 2 },
1125 { 68, 0x0, 0x1, 2 },
1126 { 125, 0x0, 0x2, 2 },
1127 { 128, 0x1, 0x0, 2 },
1128 { 136, 0x1, 0x1, 2 },
1129 { 192, 0x2, 0x0, 2 },
1130 { 204, 0x2, 0x1, 2 },
1131
1132 { 250, 0x2, 0x2, 1 },
1133 { 256, 0x3, 0x0, 1 },
1134 { 272, 0x3, 0x1, 1 },
1135 { 384, 0x4, 0x0, 1 },
1136 { 408, 0x4, 0x1, 1 },
1137 { 375, 0x4, 0x2, 1 },
1138 { 512, 0x5, 0x0, 1 },
1139 { 544, 0x5, 0x1, 1 },
1140 { 500, 0x5, 0x2, 1 },
1141 { 768, 0x6, 0x0, 1 },
1142 { 816, 0x6, 0x1, 1 },
1143 { 750, 0x6, 0x2, 1 },
1144 { 1024, 0x7, 0x0, 1 },
1145 { 1088, 0x7, 0x1, 1 },
1146 { 1000, 0x7, 0x2, 1 },
1147 { 1408, 0x8, 0x0, 1 },
1148 { 1496, 0x8, 0x1, 1 },
1149 { 1536, 0x9, 0x0, 1 },
1150 { 1632, 0x9, 0x1, 1 },
1151 { 1500, 0x9, 0x2, 1 },
1152
1153 { 250, 0x2, 0x2, 2 },
1154 { 256, 0x3, 0x0, 2 },
1155 { 272, 0x3, 0x1, 2 },
1156 { 384, 0x4, 0x0, 2 },
1157 { 408, 0x4, 0x1, 2 },
1158 { 375, 0x4, 0x2, 2 },
1159 { 512, 0x5, 0x0, 2 },
1160 { 544, 0x5, 0x1, 2 },
1161 { 500, 0x5, 0x2, 2 },
1162 { 768, 0x6, 0x0, 2 },
1163 { 816, 0x6, 0x1, 2 },
1164 { 750, 0x6, 0x2, 2 },
1165 { 1024, 0x7, 0x0, 2 },
1166 { 1088, 0x7, 0x1, 2 },
1167 { 1000, 0x7, 0x2, 2 },
1168 { 1408, 0x8, 0x0, 2 },
1169 { 1496, 0x8, 0x1, 2 },
1170 { 1536, 0x9, 0x0, 2 },
1171 { 1632, 0x9, 0x1, 2 },
1172 { 1500, 0x9, 0x2, 2 },
1173};
1174
1175/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1176static struct {
1177 int ratio;
1178 int div;
1179} bclk_divs[] = {
1180 { 10, 0 },
f1c0a02f
MB		 1181 { 20, 2 },
1182 { 30, 3 },
1183 { 40, 4 },
1184 { 50, 5 },
f1c0a02f
MB		 1185 { 60, 7 },
1186 { 80, 8 },
1187 { 100, 9 },
f1c0a02f
MB		 1188 { 120, 11 },
1189 { 160, 12 },
1190 { 200, 13 },
1191 { 220, 14 },
1192 { 240, 15 },
f1c0a02f
MB		 1193 { 300, 17 },
1194 { 320, 18 },
1195 { 440, 19 },
1196 { 480, 20 },
1197};
1198
1199/* Sample rates for DSP */
1200static struct {
1201 int rate;
1202 int value;
1203} sample_rates[] = {
1204 { 8000, 0 },
1205 { 11025, 1 },
1206 { 12000, 2 },
1207 { 16000, 3 },
1208 { 22050, 4 },
1209 { 24000, 5 },
1210 { 32000, 6 },
1211 { 44100, 7 },
1212 { 48000, 8 },
1213 { 88200, 9 },
1214 { 96000, 10 },
1215 { 0, 0 },
1216};
1217
dee89c4d
MB		 1218static int wm8903_startup(struct snd_pcm_substream *substream,
1219 struct snd_soc_dai *dai)
f1c0a02f
MB		 1220{
1221 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1222 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1223 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1224 struct wm8903_priv *wm8903 = codec->private_data;
1225 struct i2c_client *i2c = codec->control_data;
1226 struct snd_pcm_runtime *master_runtime;
1227
1228 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1229 wm8903->playback_active++;
1230 else
1231 wm8903->capture_active++;
1232
1233 /* The DAI has shared clocks so if we already have a playback or
1234 * capture going then constrain this substream to match it.
1235 */
1236 if (wm8903->master_substream) {
1237 master_runtime = wm8903->master_substream->runtime;
1238
727fb909
MB		 1239 dev_dbg(&i2c->dev, "Constraining to %d bits\n",
1240 master_runtime->sample_bits);
f1c0a02f
MB		 1241
1242 snd_pcm_hw_constraint_minmax(substream->runtime,
1243 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1244 master_runtime->sample_bits,
1245 master_runtime->sample_bits);
1246
1247 wm8903->slave_substream = substream;
1248 } else
1249 wm8903->master_substream = substream;
1250
1251 return 0;
1252}
1253
dee89c4d
MB		 1254static void wm8903_shutdown(struct snd_pcm_substream *substream,
1255 struct snd_soc_dai *dai)
f1c0a02f
MB		 1256{
1257 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1258 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1259 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1260 struct wm8903_priv *wm8903 = codec->private_data;
1261
1262 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1263 wm8903->playback_active--;
1264 else
1265 wm8903->capture_active--;
1266
1267 if (wm8903->master_substream == substream)
1268 wm8903->master_substream = wm8903->slave_substream;
1269
1270 wm8903->slave_substream = NULL;
1271}
1272
1273static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1274 struct snd_pcm_hw_params *params,
1275 struct snd_soc_dai *dai)
f1c0a02f
MB		 1276{
1277 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1278 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1279 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1280 struct wm8903_priv *wm8903 = codec->private_data;
1281 struct i2c_client *i2c = codec->control_data;
1282 int fs = params_rate(params);
1283 int bclk;
1284 int bclk_div;
1285 int i;
1286 int dsp_config;
1287 int clk_config;
1288 int best_val;
1289 int cur_val;
1290 int clk_sys;
1291
8d50e447
MB		 1292 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1293 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1294 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1295 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1296 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1297 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1298
1299 if (substream == wm8903->slave_substream) {
1300 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
1301 return 0;
1302 }
1303
9e79261f
MB		 1304 /* Enable sloping stopband filter for low sample rates */
1305 if (fs <= 24000)
1306 dac_digital1 |= WM8903_DAC_SB_FILT;
1307 else
1308 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1309
f1c0a02f
MB		 1310 /* Configure sample rate logic for DSP - choose nearest rate */
1311 dsp_config = 0;
1312 best_val = abs(sample_rates[dsp_config].rate - fs);
1313 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1314 cur_val = abs(sample_rates[i].rate - fs);
1315 if (cur_val <= best_val) {
1316 dsp_config = i;
1317 best_val = cur_val;
1318 }
1319 }
1320
1321 /* Constraints should stop us hitting this but let's make sure */
1322 if (wm8903->capture_active)
1323 switch (sample_rates[dsp_config].rate) {
1324 case 88200:
1325 case 96000:
1326 dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
1327 fs);
1328 return -EINVAL;
1329
1330 default:
1331 break;
1332 }
1333
1334 dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1335 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1336 clock1 |= sample_rates[dsp_config].value;
1337
1338 aif1 &= ~WM8903_AIF_WL_MASK;
1339 bclk = 2 * fs;
1340 switch (params_format(params)) {
1341 case SNDRV_PCM_FORMAT_S16_LE:
1342 bclk *= 16;
1343 break;
1344 case SNDRV_PCM_FORMAT_S20_3LE:
1345 bclk *= 20;
1346 aif1 |= 0x4;
1347 break;
1348 case SNDRV_PCM_FORMAT_S24_LE:
1349 bclk *= 24;
1350 aif1 |= 0x8;
1351 break;
1352 case SNDRV_PCM_FORMAT_S32_LE:
1353 bclk *= 32;
1354 aif1 |= 0xc;
1355 break;
1356 default:
1357 return -EINVAL;
1358 }
1359
1360 dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1361 wm8903->sysclk, fs);
1362
1363 /* We may not have an MCLK which allows us to generate exactly
1364 * the clock we want, particularly with USB derived inputs, so
1365 * approximate.
1366 */
1367 clk_config = 0;
1368 best_val = abs((wm8903->sysclk /
1369 (clk_sys_ratios[0].mclk_div *
1370 clk_sys_ratios[0].div)) - fs);
1371 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1372 cur_val = abs((wm8903->sysclk /
1373 (clk_sys_ratios[i].mclk_div *
1374 clk_sys_ratios[i].div)) - fs);
1375
1376 if (cur_val <= best_val) {
1377 clk_config = i;
1378 best_val = cur_val;
1379 }
1380 }
1381
1382 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1383 clock0 |= WM8903_MCLKDIV2;
1384 clk_sys = wm8903->sysclk / 2;
1385 } else {
1386 clock0 &= ~WM8903_MCLKDIV2;
1387 clk_sys = wm8903->sysclk;
1388 }
1389
1390 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1391 WM8903_CLK_SYS_MODE_MASK);
1392 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1393 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1394
1395 dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1396 clk_sys_ratios[clk_config].rate,
1397 clk_sys_ratios[clk_config].mode,
1398 clk_sys_ratios[clk_config].div);
1399
1400 dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1401
1402 /* We may not get quite the right frequency if using
1403 * approximate clocks so look for the closest match that is
1404 * higher than the target (we need to ensure that there enough
1405 * BCLKs to clock out the samples).
1406 */
1407 bclk_div = 0;
1408 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1409 i = 1;
1410 while (i < ARRAY_SIZE(bclk_divs)) {
1411 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1412 if (cur_val < 0) /* BCLK table is sorted */
1413 break;
1414 bclk_div = i;
1415 best_val = cur_val;
1416 i++;
1417 }
1418
1419 aif2 &= ~WM8903_BCLK_DIV_MASK;
1420 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1421
1422 dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1423 bclk_divs[bclk_div].ratio / 10, bclk,
1424 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1425
1426 aif2 |= bclk_divs[bclk_div].div;
1427 aif3 |= bclk / fs;
1428
8d50e447
MB		 1429 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1430 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1431 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1432 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1433 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1434 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1435
1436 return 0;
1437}
1438
1439#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1440 SNDRV_PCM_RATE_11025 | \
1441 SNDRV_PCM_RATE_16000 | \
1442 SNDRV_PCM_RATE_22050 | \
1443 SNDRV_PCM_RATE_32000 | \
1444 SNDRV_PCM_RATE_44100 | \
1445 SNDRV_PCM_RATE_48000 | \
1446 SNDRV_PCM_RATE_88200 | \
1447 SNDRV_PCM_RATE_96000)
1448
1449#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1450 SNDRV_PCM_RATE_11025 | \
1451 SNDRV_PCM_RATE_16000 | \
1452 SNDRV_PCM_RATE_22050 | \
1453 SNDRV_PCM_RATE_32000 | \
1454 SNDRV_PCM_RATE_44100 | \
1455 SNDRV_PCM_RATE_48000)
1456
1457#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1458 SNDRV_PCM_FMTBIT_S20_3LE |\
1459 SNDRV_PCM_FMTBIT_S24_LE)
1460
6335d055
EM		 1461static struct snd_soc_dai_ops wm8903_dai_ops = {
1462 .startup = wm8903_startup,
1463 .shutdown = wm8903_shutdown,
1464 .hw_params = wm8903_hw_params,
1465 .digital_mute = wm8903_digital_mute,
1466 .set_fmt = wm8903_set_dai_fmt,
1467 .set_sysclk = wm8903_set_dai_sysclk,
1468};
1469
f1c0a02f
MB		 1470struct snd_soc_dai wm8903_dai = {
1471 .name = "WM8903",
1472 .playback = {
1473 .stream_name = "Playback",
1474 .channels_min = 2,
1475 .channels_max = 2,
1476 .rates = WM8903_PLAYBACK_RATES,
1477 .formats = WM8903_FORMATS,
1478 },
1479 .capture = {
1480 .stream_name = "Capture",
1481 .channels_min = 2,
1482 .channels_max = 2,
1483 .rates = WM8903_CAPTURE_RATES,
1484 .formats = WM8903_FORMATS,
1485 },
6335d055 1486 .ops = &wm8903_dai_ops,
0d960e88 1487 .symmetric_rates = 1,
f1c0a02f
MB		 1488};
1489EXPORT_SYMBOL_GPL(wm8903_dai);
1490
1491static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
1492{
1493 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1494 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1495
1496 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1497
1498 return 0;
1499}
1500
1501static int wm8903_resume(struct platform_device *pdev)
1502{
1503 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1504 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1505 struct i2c_client *i2c = codec->control_data;
1506 int i;
1507 u16 *reg_cache = codec->reg_cache;
40aa7030 1508 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1509 GFP_KERNEL);
1510
1511 /* Bring the codec back up to standby first to minimise pop/clicks */
1512 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1513 wm8903_set_bias_level(codec, codec->suspend_bias_level);
1514
1515 /* Sync back everything else */
1516 if (tmp_cache) {
1517 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1518 if (tmp_cache[i] != reg_cache[i])
8d50e447 1519 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1520 kfree(tmp_cache);
f1c0a02f
MB		 1521 } else {
1522 dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1523 }
1524
1525 return 0;
1526}
1527
d58d5d55
MB		 1528static struct snd_soc_codec *wm8903_codec;
1529
c6f29811
MB		 1530static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1531 const struct i2c_device_id *id)
f1c0a02f 1532{
d58d5d55
MB		 1533 struct wm8903_priv *wm8903;
1534 struct snd_soc_codec *codec;
1535 int ret;
f1c0a02f
MB		 1536 u16 val;
1537
d58d5d55
MB		 1538 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1539 if (wm8903 == NULL)
1540 return -ENOMEM;
f1c0a02f 1541
d58d5d55
MB		 1542 codec = &wm8903->codec;
1543
1544 mutex_init(&codec->mutex);
1545 INIT_LIST_HEAD(&codec->dapm_widgets);
1546 INIT_LIST_HEAD(&codec->dapm_paths);
1547
1548 codec->dev = &i2c->dev;
f1c0a02f
MB		 1549 codec->name = "WM8903";
1550 codec->owner = THIS_MODULE;
f1c0a02f
MB		 1551 codec->bias_level = SND_SOC_BIAS_OFF;
1552 codec->set_bias_level = wm8903_set_bias_level;
1553 codec->dai = &wm8903_dai;
1554 codec->num_dai = 1;
d58d5d55
MB		 1555 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
1556 codec->reg_cache = &wm8903->reg_cache[0];
1557 codec->private_data = wm8903;
8d50e447 1558 codec->volatile_register = wm8903_volatile_register;
d58d5d55
MB		 1559
1560 i2c_set_clientdata(i2c, codec);
1561 codec->control_data = i2c;
1562
8d50e447
MB		 1563 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1564 if (ret != 0) {
1565 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
1566 goto err;
1567 }
1568
1569 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55
MB		 1570 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1571 dev_err(&i2c->dev,
1572 "Device with ID register %x is not a WM8903\n", val);
1573 return -ENODEV;
f1c0a02f
MB		 1574 }
1575
8d50e447 1576 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
f1c0a02f
MB		 1577 dev_info(&i2c->dev, "WM8903 revision %d\n",
1578 val & WM8903_CHIP_REV_MASK);
1579
1580 wm8903_reset(codec);
1581
f1c0a02f
MB		 1582 /* power on device */
1583 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1584
1585 /* Latch volume update bits */
8d50e447 1586 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1587 val |= WM8903_ADCVU;
8d50e447
MB		 1588 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1589 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1590
8d50e447 1591 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1592 val |= WM8903_DACVU;
8d50e447
MB		 1593 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1594 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1595
8d50e447 1596 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1597 val |= WM8903_HPOUTVU;
8d50e447
MB		 1598 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1599 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1600
8d50e447 1601 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1602 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1603 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1604 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1605
8d50e447 1606 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1607 val |= WM8903_SPKVU;
8d50e447
MB		 1608 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1609 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1610
1611 /* Enable DAC soft mute by default */
8d50e447 1612 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1613 val |= WM8903_DAC_MUTEMODE;
8d50e447 1614 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
f1c0a02f 1615
d58d5d55
MB		 1616 wm8903_dai.dev = &i2c->dev;
1617 wm8903_codec = codec;
1618
1619 ret = snd_soc_register_codec(codec);
1620 if (ret != 0) {
1621 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1622 goto err;
1623 }
1624
1625 ret = snd_soc_register_dai(&wm8903_dai);
1626 if (ret != 0) {
1627 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1628 goto err_codec;
f1c0a02f
MB		 1629 }
1630
1631 return ret;
1632
d58d5d55
MB		 1633err_codec:
1634 snd_soc_unregister_codec(codec);
1635err:
1636 wm8903_codec = NULL;
1637 kfree(wm8903);
f1c0a02f
MB		 1638 return ret;
1639}
1640
c6f29811 1641static __devexit int wm8903_i2c_remove(struct i2c_client *client)
f1c0a02f 1642{
d58d5d55 1643 struct snd_soc_codec *codec = i2c_get_clientdata(client);
f1c0a02f 1644
d58d5d55
MB		 1645 snd_soc_unregister_dai(&wm8903_dai);
1646 snd_soc_unregister_codec(codec);
f1c0a02f 1647
d58d5d55 1648 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f1c0a02f 1649
d58d5d55
MB		 1650 kfree(codec->private_data);
1651
1652 wm8903_codec = NULL;
1653 wm8903_dai.dev = NULL;
f1c0a02f 1654
f1c0a02f
MB		 1655 return 0;
1656}
1657
1658/* i2c codec control layer */
1659static const struct i2c_device_id wm8903_i2c_id[] = {
1660 { "wm8903", 0 },
1661 { }
1662};
1663MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1664
1665static struct i2c_driver wm8903_i2c_driver = {
1666 .driver = {
1667 .name = "WM8903",
1668 .owner = THIS_MODULE,
1669 },
1670 .probe = wm8903_i2c_probe,
c6f29811 1671 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1672 .id_table = wm8903_i2c_id,
1673};
1674
f1c0a02f
MB		 1675static int wm8903_probe(struct platform_device *pdev)
1676{
1677 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
f1c0a02f
MB		 1678 int ret = 0;
1679
d58d5d55
MB		 1680 if (!wm8903_codec) {
1681 dev_err(&pdev->dev, "I2C device not yet probed\n");
1682 goto err;
f1c0a02f
MB		 1683 }
1684
6627a653 1685 socdev->card->codec = wm8903_codec;
f1c0a02f 1686
d58d5d55
MB		 1687 /* register pcms */
1688 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1689 if (ret < 0) {
1690 dev_err(&pdev->dev, "failed to create pcms\n");
1691 goto err;
f1c0a02f
MB		 1692 }
1693
6627a653 1694 snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls,
3e8e1952 1695 ARRAY_SIZE(wm8903_snd_controls));
6627a653 1696 wm8903_add_widgets(socdev->card->codec);
f1c0a02f 1697
f1c0a02f
MB		 1698 return ret;
1699
d58d5d55 1700err:
f1c0a02f
MB		 1701 return ret;
1702}
1703
1704/* power down chip */
1705static int wm8903_remove(struct platform_device *pdev)
1706{
1707 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1708 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1709
1710 if (codec->control_data)
1711 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1712
1713 snd_soc_free_pcms(socdev);
1714 snd_soc_dapm_free(socdev);
f1c0a02f
MB		 1715
1716 return 0;
1717}
1718
1719struct snd_soc_codec_device soc_codec_dev_wm8903 = {
1720 .probe = wm8903_probe,
1721 .remove = wm8903_remove,
1722 .suspend = wm8903_suspend,
1723 .resume = wm8903_resume,
1724};
1725EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
1726
c9b3a40f 1727static int __init wm8903_modinit(void)
64089b84 1728{
d58d5d55 1729 return i2c_add_driver(&wm8903_i2c_driver);
64089b84
MB		 1730}
1731module_init(wm8903_modinit);
1732
1733static void __exit wm8903_exit(void)
1734{
d58d5d55 1735 i2c_del_driver(&wm8903_i2c_driver);
64089b84
MB		 1736}
1737module_exit(wm8903_exit);
1738
f1c0a02f
MB		 1739MODULE_DESCRIPTION("ASoC WM8903 driver");
1740MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1741MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)