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Merge tag 'sched_ext-for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/tj...
[linux-2.6-block.git] / sound / soc / codecs / wm5100.c
CommitLineData
d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
6d4baf08
MB		 2/*
3 * wm5100.c -- WM5100 ALSA SoC Audio driver
4 *
656baaeb 5 * Copyright 2011-2 Wolfson Microelectronics plc
6d4baf08
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6d4baf08
MB		 8 */
9
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/init.h>
13#include <linux/delay.h>
0cf0f174 14#include <linux/export.h>
6d4baf08
MB		 15#include <linux/pm.h>
16#include <linux/gcd.h>
db1d1270 17#include <linux/gpio/driver.h>
8563cfe3 18#include <linux/gpio/consumer.h>
6d4baf08 19#include <linux/i2c.h>
62c1c401 20#include <linux/pm_runtime.h>
6d4baf08
MB		 21#include <linux/regulator/consumer.h>
22#include <linux/regulator/fixed.h>
23#include <linux/slab.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
ba896ede 28#include <sound/jack.h>
6d4baf08
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
31#include <sound/wm5100.h>
32
33#include "wm5100.h"
34
35#define WM5100_NUM_CORE_SUPPLIES 2
36static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
37 "DBVDD1",
38 "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
39};
40
41#define WM5100_AIFS 3
42#define WM5100_SYNC_SRS 3
43
44struct wm5100_fll {
45 int fref;
46 int fout;
47 int src;
48 struct completion lock;
49};
50
51/* codec private data */
52struct wm5100_priv {
46c1a877 53 struct device *dev;
bd132ec5 54 struct regmap *regmap;
61195838 55 struct snd_soc_component *component;
6d4baf08
MB		 56
57 struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
8563cfe3
LW		 58 struct gpio_desc *reset;
59 struct gpio_desc *ldo_ena;
60 struct gpio_desc *hp_pol;
6d4baf08
MB		 61
62 int rev;
63
64 int sysclk;
65 int asyncclk;
66
67 bool aif_async[WM5100_AIFS];
68 bool aif_symmetric[WM5100_AIFS];
69 int sr_ref[WM5100_SYNC_SRS];
70
71 bool out_ena[2];
72
ba896ede
MB		 73 struct snd_soc_jack *jack;
74 bool jack_detecting;
75 bool jack_mic;
76 int jack_mode;
2633f736 77 int jack_flips;
ba896ede 78
6d4baf08
MB		 79 struct wm5100_fll fll[2];
80
81 struct wm5100_pdata pdata;
82
83#ifdef CONFIG_GPIOLIB
84 struct gpio_chip gpio_chip;
85#endif
86};
87
88static int wm5100_sr_code[] = {
89 0,
90 12000,
91 24000,
92 48000,
93 96000,
94 192000,
95 384000,
96 768000,
97 0,
98 11025,
99 22050,
100 44100,
101 88200,
102 176400,
103 352800,
104 705600,
105 4000,
106 8000,
107 16000,
108 32000,
109 64000,
110 128000,
111 256000,
112 512000,
113};
114
115static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
116 WM5100_CLOCKING_4,
117 WM5100_CLOCKING_5,
118 WM5100_CLOCKING_6,
119};
120
61195838 121static int wm5100_alloc_sr(struct snd_soc_component *component, int rate)
6d4baf08 122{
61195838 123 struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
6d4baf08
MB		 124 int sr_code, sr_free, i;
125
126 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
127 if (wm5100_sr_code[i] == rate)
128 break;
129 if (i == ARRAY_SIZE(wm5100_sr_code)) {
61195838 130 dev_err(component->dev, "Unsupported sample rate: %dHz\n", rate);
6d4baf08
MB		 131 return -EINVAL;
132 }
133 sr_code = i;
134
135 if ((wm5100->sysclk % rate) == 0) {
136 /* Is this rate already in use? */
137 sr_free = -1;
138 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
139 if (!wm5100->sr_ref[i] && sr_free == -1) {
140 sr_free = i;
141 continue;
142 }
6d75dfc3 143 if ((snd_soc_component_read(component, wm5100_sr_regs[i]) &
6d4baf08
MB		 144 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
145 break;
146 }
147
148 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
149 wm5100->sr_ref[i]++;
61195838 150 dev_dbg(component->dev, "SR %dHz, slot %d, ref %d\n",
6d4baf08
MB		 151 rate, i, wm5100->sr_ref[i]);
152 return i;
153 }
154
155 if (sr_free == -1) {
61195838 156 dev_err(component->dev, "All SR slots already in use\n");
6d4baf08
MB		 157 return -EBUSY;
158 }
159
61195838 160 dev_dbg(component->dev, "Allocating SR slot %d for %dHz\n",
6d4baf08
MB		 161 sr_free, rate);
162 wm5100->sr_ref[sr_free]++;
61195838 163 snd_soc_component_update_bits(component, wm5100_sr_regs[sr_free],
6d4baf08
MB		 164 WM5100_SAMPLE_RATE_1_MASK,
165 sr_code);
166
167 return sr_free;
168
169 } else {
61195838 170 dev_err(component->dev,
6d4baf08
MB		 171 "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
172 rate, wm5100->sysclk, wm5100->asyncclk);
173 return -EINVAL;
174 }
175}
176
61195838 177static void wm5100_free_sr(struct snd_soc_component *component, int rate)
6d4baf08 178{
61195838 179 struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
6d4baf08
MB		 180 int i, sr_code;
181
182 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
183 if (wm5100_sr_code[i] == rate)
184 break;
185 if (i == ARRAY_SIZE(wm5100_sr_code)) {
61195838 186 dev_err(component->dev, "Unsupported sample rate: %dHz\n", rate);
6d4baf08
MB		 187 return;
188 }
189 sr_code = wm5100_sr_code[i];
190
191 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
192 if (!wm5100->sr_ref[i])
193 continue;
194
6d75dfc3 195 if ((snd_soc_component_read(component, wm5100_sr_regs[i]) &
6d4baf08
MB		 196 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
197 break;
198 }
199 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
200 wm5100->sr_ref[i]--;
61195838 201 dev_dbg(component->dev, "Dereference SR %dHz, count now %d\n",
6d4baf08
MB		 202 rate, wm5100->sr_ref[i]);
203 } else {
61195838 204 dev_warn(component->dev, "Freeing unreferenced sample rate %dHz\n",
6d4baf08
MB		 205 rate);
206 }
207}
208
588ac5e0 209static int wm5100_reset(struct wm5100_priv *wm5100)
6d4baf08 210{
8563cfe3
LW		 211 if (wm5100->reset) {
212 gpiod_set_value_cansleep(wm5100->reset, 1);
213 gpiod_set_value_cansleep(wm5100->reset, 0);
6d4baf08
MB		 214
215 return 0;
216 } else {
588ac5e0 217 return regmap_write(wm5100->regmap, WM5100_SOFTWARE_RESET, 0);
6d4baf08
MB		 218 }
219}
220
221static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
222static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
223static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
224static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
225static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
226
227static const char *wm5100_mixer_texts[] = {
228 "None",
229 "Tone Generator 1",
230 "Tone Generator 2",
231 "AEC loopback",
232 "IN1L",
233 "IN1R",
234 "IN2L",
235 "IN2R",
236 "IN3L",
237 "IN3R",
238 "IN4L",
239 "IN4R",
240 "AIF1RX1",
241 "AIF1RX2",
242 "AIF1RX3",
243 "AIF1RX4",
244 "AIF1RX5",
245 "AIF1RX6",
246 "AIF1RX7",
247 "AIF1RX8",
248 "AIF2RX1",
249 "AIF2RX2",
250 "AIF3RX1",
251 "AIF3RX2",
252 "EQ1",
253 "EQ2",
254 "EQ3",
255 "EQ4",
256 "DRC1L",
257 "DRC1R",
258 "LHPF1",
259 "LHPF2",
260 "LHPF3",
261 "LHPF4",
262 "DSP1.1",
263 "DSP1.2",
264 "DSP1.3",
265 "DSP1.4",
266 "DSP1.5",
267 "DSP1.6",
268 "DSP2.1",
269 "DSP2.2",
270 "DSP2.3",
271 "DSP2.4",
272 "DSP2.5",
273 "DSP2.6",
274 "DSP3.1",
275 "DSP3.2",
276 "DSP3.3",
277 "DSP3.4",
278 "DSP3.5",
279 "DSP3.6",
280 "ASRC1L",
281 "ASRC1R",
282 "ASRC2L",
283 "ASRC2R",
284 "ISRC1INT1",
285 "ISRC1INT2",
286 "ISRC1INT3",
287 "ISRC1INT4",
288 "ISRC2INT1",
289 "ISRC2INT2",
290 "ISRC2INT3",
291 "ISRC2INT4",
292 "ISRC1DEC1",
293 "ISRC1DEC2",
294 "ISRC1DEC3",
295 "ISRC1DEC4",
296 "ISRC2DEC1",
297 "ISRC2DEC2",
298 "ISRC2DEC3",
299 "ISRC2DEC4",
300};
301
302static int wm5100_mixer_values[] = {
303 0x00,
304 0x04, /* Tone */
305 0x05,
306 0x08, /* AEC */
307 0x10, /* Input */
308 0x11,
309 0x12,
310 0x13,
311 0x14,
312 0x15,
313 0x16,
314 0x17,
315 0x20, /* AIF */
316 0x21,
317 0x22,
318 0x23,
319 0x24,
320 0x25,
321 0x26,
322 0x27,
323 0x28,
324 0x29,
325 0x30, /* AIF3 - check */
326 0x31,
327 0x50, /* EQ */
328 0x51,
329 0x52,
330 0x53,
331 0x54,
332 0x58, /* DRC */
333 0x59,
334 0x60, /* LHPF1 */
335 0x61, /* LHPF2 */
336 0x62, /* LHPF3 */
337 0x63, /* LHPF4 */
338 0x68, /* DSP1 */
339 0x69,
340 0x6a,
341 0x6b,
342 0x6c,
343 0x6d,
344 0x70, /* DSP2 */
345 0x71,
346 0x72,
347 0x73,
348 0x74,
349 0x75,
350 0x78, /* DSP3 */
351 0x79,
352 0x7a,
353 0x7b,
354 0x7c,
355 0x7d,
356 0x90, /* ASRC1 */
357 0x91,
358 0x92, /* ASRC2 */
359 0x93,
360 0xa0, /* ISRC1DEC1 */
361 0xa1,
362 0xa2,
363 0xa3,
364 0xa4, /* ISRC1INT1 */
365 0xa5,
366 0xa6,
367 0xa7,
368 0xa8, /* ISRC2DEC1 */
369 0xa9,
370 0xaa,
371 0xab,
372 0xac, /* ISRC2INT1 */
373 0xad,
374 0xae,
375 0xaf,
376};
377
378#define WM5100_MIXER_CONTROLS(name, base) \
379 SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
380 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
381 SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
382 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
383 SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
384 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
385 SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
386 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
387
388#define WM5100_MUX_ENUM_DECL(name, reg) \
389 SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
390 wm5100_mixer_texts, wm5100_mixer_values)
391
392#define WM5100_MUX_CTL_DECL(name) \
393 const struct snd_kcontrol_new name##_mux = \
cda88669 394 SOC_DAPM_ENUM("Route", name##_enum)
6d4baf08
MB		 395
396#define WM5100_MIXER_ENUMS(name, base_reg) \
397 static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
398 static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
399 static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
400 static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
401 static WM5100_MUX_CTL_DECL(name##_in1); \
402 static WM5100_MUX_CTL_DECL(name##_in2); \
403 static WM5100_MUX_CTL_DECL(name##_in3); \
404 static WM5100_MUX_CTL_DECL(name##_in4)
405
406WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
407WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
408WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
409WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
410WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
411WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
412
413WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
414WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
415WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
416WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
417WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
418WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
419
420WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
421WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
422
423WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
424WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
425WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
426WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
427WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
428WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
429WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
430WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
431
432WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
433WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
434
435WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
436WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
437
438WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
439WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
440WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
441WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
442
443WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
444WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
445
446WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
447WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
448WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
449WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
450
451#define WM5100_MUX(name, ctrl) \
cda88669 452 SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
6d4baf08
MB		 453
454#define WM5100_MIXER_WIDGETS(name, name_str) \
455 WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
456 WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
457 WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
458 WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
459 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
460
461#define WM5100_MIXER_INPUT_ROUTES(name) \
462 { name, "Tone Generator 1", "Tone Generator 1" }, \
463 { name, "Tone Generator 2", "Tone Generator 2" }, \
464 { name, "IN1L", "IN1L PGA" }, \
465 { name, "IN1R", "IN1R PGA" }, \
466 { name, "IN2L", "IN2L PGA" }, \
467 { name, "IN2R", "IN2R PGA" }, \
468 { name, "IN3L", "IN3L PGA" }, \
469 { name, "IN3R", "IN3R PGA" }, \
470 { name, "IN4L", "IN4L PGA" }, \
471 { name, "IN4R", "IN4R PGA" }, \
472 { name, "AIF1RX1", "AIF1RX1" }, \
473 { name, "AIF1RX2", "AIF1RX2" }, \
474 { name, "AIF1RX3", "AIF1RX3" }, \
475 { name, "AIF1RX4", "AIF1RX4" }, \
476 { name, "AIF1RX5", "AIF1RX5" }, \
477 { name, "AIF1RX6", "AIF1RX6" }, \
478 { name, "AIF1RX7", "AIF1RX7" }, \
479 { name, "AIF1RX8", "AIF1RX8" }, \
480 { name, "AIF2RX1", "AIF2RX1" }, \
481 { name, "AIF2RX2", "AIF2RX2" }, \
482 { name, "AIF3RX1", "AIF3RX1" }, \
483 { name, "AIF3RX2", "AIF3RX2" }, \
484 { name, "EQ1", "EQ1" }, \
485 { name, "EQ2", "EQ2" }, \
486 { name, "EQ3", "EQ3" }, \
487 { name, "EQ4", "EQ4" }, \
488 { name, "DRC1L", "DRC1L" }, \
489 { name, "DRC1R", "DRC1R" }, \
490 { name, "LHPF1", "LHPF1" }, \
491 { name, "LHPF2", "LHPF2" }, \
492 { name, "LHPF3", "LHPF3" }, \
493 { name, "LHPF4", "LHPF4" }
494
495#define WM5100_MIXER_ROUTES(widget, name) \
496 { widget, NULL, name " Mixer" }, \
497 { name " Mixer", NULL, name " Input 1" }, \
498 { name " Mixer", NULL, name " Input 2" }, \
499 { name " Mixer", NULL, name " Input 3" }, \
500 { name " Mixer", NULL, name " Input 4" }, \
501 WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
502 WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
503 WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
504 WM5100_MIXER_INPUT_ROUTES(name " Input 4")
505
506static const char *wm5100_lhpf_mode_text[] = {
507 "Low-pass", "High-pass"
508};
509
0224ba6a
TI		 510static SOC_ENUM_SINGLE_DECL(wm5100_lhpf1_mode,
511 WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT,
512 wm5100_lhpf_mode_text);
6d4baf08 513
0224ba6a
TI		 514static SOC_ENUM_SINGLE_DECL(wm5100_lhpf2_mode,
515 WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT,
516 wm5100_lhpf_mode_text);
6d4baf08 517
0224ba6a
TI		 518static SOC_ENUM_SINGLE_DECL(wm5100_lhpf3_mode,
519 WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT,
520 wm5100_lhpf_mode_text);
6d4baf08 521
0224ba6a
TI		 522static SOC_ENUM_SINGLE_DECL(wm5100_lhpf4_mode,
523 WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT,
524 wm5100_lhpf_mode_text);
6d4baf08
MB		 525
526static const struct snd_kcontrol_new wm5100_snd_controls[] = {
527SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
528 WM5100_IN1_OSR_SHIFT, 1, 0),
529SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
530 WM5100_IN2_OSR_SHIFT, 1, 0),
531SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
532 WM5100_IN3_OSR_SHIFT, 1, 0),
533SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
534 WM5100_IN4_OSR_SHIFT, 1, 0),
535
536/* Only applicable for analogue inputs */
537SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
538 WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
539SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
540 WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
541SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
542 WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
543SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
544 WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
545
546SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
547 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
548 0, digital_tlv),
549SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
550 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
551 0, digital_tlv),
552SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
553 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
554 0, digital_tlv),
555SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
556 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
557 0, digital_tlv),
558
559SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
560 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
561SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
562 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
563SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
564 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
565SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
566 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
567
20fc4863
MB		 568SND_SOC_BYTES_MASK("EQ1 Coefficients", WM5100_EQ1_1, 20, WM5100_EQ1_ENA),
569SND_SOC_BYTES_MASK("EQ2 Coefficients", WM5100_EQ2_1, 20, WM5100_EQ2_ENA),
570SND_SOC_BYTES_MASK("EQ3 Coefficients", WM5100_EQ3_1, 20, WM5100_EQ3_ENA),
571SND_SOC_BYTES_MASK("EQ4 Coefficients", WM5100_EQ4_1, 20, WM5100_EQ4_ENA),
572
573SND_SOC_BYTES_MASK("DRC Coefficients", WM5100_DRC1_CTRL1, 5,
574 WM5100_DRCL_ENA | WM5100_DRCR_ENA),
575
57b70db2
CIK		 576SND_SOC_BYTES("LHPF1 Coefficients", WM5100_HPLPF1_2, 1),
577SND_SOC_BYTES("LHPF2 Coefficients", WM5100_HPLPF2_2, 1),
578SND_SOC_BYTES("LHPF3 Coefficients", WM5100_HPLPF3_2, 1),
579SND_SOC_BYTES("LHPF4 Coefficients", WM5100_HPLPF4_2, 1),
20fc4863 580
6d4baf08
MB		 581SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
582 WM5100_OUT1_OSR_SHIFT, 1, 0),
583SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
584 WM5100_OUT2_OSR_SHIFT, 1, 0),
585SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
586 WM5100_OUT3_OSR_SHIFT, 1, 0),
587SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
588 WM5100_OUT4_OSR_SHIFT, 1, 0),
589SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
590 WM5100_OUT5_OSR_SHIFT, 1, 0),
591SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
592 WM5100_OUT6_OSR_SHIFT, 1, 0),
593
594SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
595 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
596 digital_tlv),
597SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
598 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
599 digital_tlv),
600SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
601 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
602 digital_tlv),
603SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
604 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
605 digital_tlv),
606SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
607 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
608 digital_tlv),
609SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
610 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
611 digital_tlv),
612
613SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
614 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
615SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
616 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
617SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
618 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
619SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
620 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
621SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
622 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
623SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
624 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
625
626/* FIXME: Only valid from -12dB to 0dB (52-64) */
627SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
628 WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
629SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
630 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
631SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
632 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
633
634SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
635 WM5100_SPK1R_MUTE_SHIFT, 1, 1),
636SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
637 WM5100_SPK2R_MUTE_SHIFT, 1, 1),
638
639SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
640 24, 0, eq_tlv),
641SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
642 24, 0, eq_tlv),
643SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
644 24, 0, eq_tlv),
645SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
646 24, 0, eq_tlv),
647SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
648 24, 0, eq_tlv),
649
650SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
651 24, 0, eq_tlv),
652SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
653 24, 0, eq_tlv),
654SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
655 24, 0, eq_tlv),
656SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
657 24, 0, eq_tlv),
658SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
659 24, 0, eq_tlv),
660
661SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
662 24, 0, eq_tlv),
663SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
664 24, 0, eq_tlv),
665SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
666 24, 0, eq_tlv),
667SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
668 24, 0, eq_tlv),
669SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
670 24, 0, eq_tlv),
671
672SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
673 24, 0, eq_tlv),
674SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
675 24, 0, eq_tlv),
676SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
677 24, 0, eq_tlv),
678SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
679 24, 0, eq_tlv),
680SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
681 24, 0, eq_tlv),
682
683SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
684SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
685SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
686SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
687
688WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
689WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
690WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
691WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
692WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
693WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
694
695WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
696WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
697WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
698WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
699WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
700WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
701
702WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
703WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
704
705WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
706WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
707WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
708WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
709WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
710WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
711WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
712WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
713
714WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
715WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
716
717WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
718WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
719
720WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
721WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
722WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
723WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
724
725WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
726WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
cdaaf301
MB		 727SND_SOC_BYTES_MASK("DRC", WM5100_DRC1_CTRL1, 5,
728 WM5100_DRCL_ENA | WM5100_DRCR_ENA),
6d4baf08
MB		 729
730WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
731WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
732WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
733WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
734};
735
61195838 736static void wm5100_seq_notifier(struct snd_soc_component *component,
6d4baf08
MB		 737 enum snd_soc_dapm_type event, int subseq)
738{
61195838 739 struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
6d4baf08
MB		 740 u16 val, expect, i;
741
742 /* Wait for the outputs to flag themselves as enabled */
743 if (wm5100->out_ena[0]) {
6d75dfc3 744 expect = snd_soc_component_read(component, WM5100_CHANNEL_ENABLES_1);
6d4baf08 745 for (i = 0; i < 200; i++) {
6d75dfc3 746 val = snd_soc_component_read(component, WM5100_OUTPUT_STATUS_1);
6d4baf08
MB		 747 if (val == expect) {
748 wm5100->out_ena[0] = false;
749 break;
750 }
751 }
752 if (i == 200) {
61195838 753 dev_err(component->dev, "Timeout waiting for OUTPUT1 %x\n",
6d4baf08
MB		 754 expect);
755 }
756 }
757
758 if (wm5100->out_ena[1]) {
6d75dfc3 759 expect = snd_soc_component_read(component, WM5100_OUTPUT_ENABLES_2);
6d4baf08 760 for (i = 0; i < 200; i++) {
6d75dfc3 761 val = snd_soc_component_read(component, WM5100_OUTPUT_STATUS_2);
6d4baf08
MB		 762 if (val == expect) {
763 wm5100->out_ena[1] = false;
764 break;
765 }
766 }
767 if (i == 200) {
61195838 768 dev_err(component->dev, "Timeout waiting for OUTPUT2 %x\n",
6d4baf08
MB		 769 expect);
770 }
771 }
772}
773
774static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
775 struct snd_kcontrol *kcontrol,
776 int event)
777{
61195838
KM		 778 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
779 struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
6d4baf08
MB		 780
781 switch (w->reg) {
782 case WM5100_CHANNEL_ENABLES_1:
783 wm5100->out_ena[0] = true;
784 break;
785 case WM5100_OUTPUT_ENABLES_2:
786 wm5100->out_ena[0] = true;
787 break;
788 default:
789 break;
790 }
791
792 return 0;
793}
794
46c1a877 795static void wm5100_log_status3(struct wm5100_priv *wm5100, int val)
6d4baf08
MB		 796{
797 if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
46c1a877 798 dev_crit(wm5100->dev, "Speaker shutdown warning\n");
6d4baf08 799 if (val & WM5100_SPK_SHUTDOWN_EINT)
46c1a877 800 dev_crit(wm5100->dev, "Speaker shutdown\n");
6d4baf08 801 if (val & WM5100_CLKGEN_ERR_EINT)
46c1a877 802 dev_crit(wm5100->dev, "SYSCLK underclocked\n");
6d4baf08 803 if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
46c1a877 804 dev_crit(wm5100->dev, "ASYNCCLK underclocked\n");
6d4baf08
MB		 805}
806
46c1a877 807static void wm5100_log_status4(struct wm5100_priv *wm5100, int val)
6d4baf08
MB		 808{
809 if (val & WM5100_AIF3_ERR_EINT)
46c1a877 810 dev_err(wm5100->dev, "AIF3 configuration error\n");
6d4baf08 811 if (val & WM5100_AIF2_ERR_EINT)
46c1a877 812 dev_err(wm5100->dev, "AIF2 configuration error\n");
6d4baf08 813 if (val & WM5100_AIF1_ERR_EINT)
46c1a877 814 dev_err(wm5100->dev, "AIF1 configuration error\n");
6d4baf08 815 if (val & WM5100_CTRLIF_ERR_EINT)
46c1a877 816 dev_err(wm5100->dev, "Control interface error\n");
6d4baf08 817 if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
46c1a877 818 dev_err(wm5100->dev, "ISRC2 underclocked\n");
6d4baf08 819 if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
46c1a877 820 dev_err(wm5100->dev, "ISRC1 underclocked\n");
6d4baf08 821 if (val & WM5100_FX_UNDERCLOCKED_EINT)
46c1a877 822 dev_err(wm5100->dev, "FX underclocked\n");
6d4baf08 823 if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
46c1a877 824 dev_err(wm5100->dev, "AIF3 underclocked\n");
6d4baf08 825 if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
46c1a877 826 dev_err(wm5100->dev, "AIF2 underclocked\n");
6d4baf08 827 if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
46c1a877 828 dev_err(wm5100->dev, "AIF1 underclocked\n");
6d4baf08 829 if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
46c1a877 830 dev_err(wm5100->dev, "ASRC underclocked\n");
6d4baf08 831 if (val & WM5100_DAC_UNDERCLOCKED_EINT)
46c1a877 832 dev_err(wm5100->dev, "DAC underclocked\n");
6d4baf08 833 if (val & WM5100_ADC_UNDERCLOCKED_EINT)
46c1a877 834 dev_err(wm5100->dev, "ADC underclocked\n");
6d4baf08 835 if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
46c1a877 836 dev_err(wm5100->dev, "Mixer underclocked\n");
6d4baf08
MB		 837}
838
839static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
840 struct snd_kcontrol *kcontrol,
841 int event)
842{
61195838
KM		 843 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
844 struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
6d4baf08
MB		 845 int ret;
846
6d75dfc3 847 ret = snd_soc_component_read(component, WM5100_INTERRUPT_RAW_STATUS_3);
6d4baf08
MB		 848 ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
849 WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
850 WM5100_CLKGEN_ERR_ASYNC_STS;
46c1a877 851 wm5100_log_status3(wm5100, ret);
6d4baf08 852
6d75dfc3 853 ret = snd_soc_component_read(component, WM5100_INTERRUPT_RAW_STATUS_4);
46c1a877 854 wm5100_log_status4(wm5100, ret);
6d4baf08
MB		 855
856 return 0;
857}
858
859static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
860SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
861 NULL, 0),
862SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
863 0, NULL, 0),
864
822b4b8d
MB		 865SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
866SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
867SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
1cf73356 868
6d4baf08 869SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
1cf73356 870 NULL, 0),
6d4baf08
MB		 871SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
872 NULL, 0),
873SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
1cf73356 874 WM5100_CP2_BYPASS_SHIFT, 1, NULL, 0),
6d4baf08
MB		 875
876SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
877 0, NULL, 0),
878SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
879 0, NULL, 0),
880SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
881 0, NULL, 0),
882
883SND_SOC_DAPM_INPUT("IN1L"),
884SND_SOC_DAPM_INPUT("IN1R"),
885SND_SOC_DAPM_INPUT("IN2L"),
886SND_SOC_DAPM_INPUT("IN2R"),
887SND_SOC_DAPM_INPUT("IN3L"),
888SND_SOC_DAPM_INPUT("IN3R"),
889SND_SOC_DAPM_INPUT("IN4L"),
890SND_SOC_DAPM_INPUT("IN4R"),
dea8e237 891SND_SOC_DAPM_SIGGEN("TONE"),
6d4baf08
MB		 892
893SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
894 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
895SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
896 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
897SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
898 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
899SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
900 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
901SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
902 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
903SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
904 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
905SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
906 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
907SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
908 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
909
910SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
911 WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
912SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
913 WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
914
915SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
916 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
917SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
918 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
919SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
920 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
921SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
922 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
923SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
924 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
925SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
926 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
927SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
928 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
929SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
930 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
931
932SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
933 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
934SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
935 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
936
937SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
938 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
939SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
940 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
941
942SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
943 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
944SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
945 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
946SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
947 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
948SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
949 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
950SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
951 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
952SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
953 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
954SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
955 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
956SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
957 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
958
959SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
960 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
961SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
962 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
963
964SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
965 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
966SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
967 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
968
969SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
970 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
971SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
972 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
973SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
974 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
975SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
976 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
977SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
978 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
979SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
980 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
981SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
982 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
983SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
984 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
985SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
986 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
987SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
988 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
989SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
990 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
991SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
992 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
993SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
994 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
995SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
996 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
997
998SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
999SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
1000SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
1001SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
1002
1003SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
1004 NULL, 0),
1005SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
1006 NULL, 0),
1007
1008SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
1009 NULL, 0),
1010SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
1011 NULL, 0),
1012SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
1013 NULL, 0),
1014SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1015 NULL, 0),
1016
1017WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1018WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1019WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1020WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1021
1022WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1023WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1024
1025WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1026WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1027WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1028WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1029
1030WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1031WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1032WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1033WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1034WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1035WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1036WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1037WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1038
1039WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1040WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1041
1042WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1043WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1044
1045WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1046WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1047WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1048WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1049WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1050WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1051
1052WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1053WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1054WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1055WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1056WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1057WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1058
1059WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1060WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1061
1062SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1063SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1064SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1065SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1066SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1067SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1068SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1069SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1070SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1071SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1072SND_SOC_DAPM_OUTPUT("PWM1"),
1073SND_SOC_DAPM_OUTPUT("PWM2"),
1074};
1075
1076/* We register a _POST event if we don't have IRQ support so we can
1077 * look at the error status from the CODEC - if we've got the IRQ
1078 * hooked up then we will get prompted to look by an interrupt.
1079 */
1080static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1081SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1082};
1083
1084static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1cf73356
MB		 1085 { "CP1", NULL, "CPVDD" },
1086 { "CP2 Active", NULL, "CPVDD" },
1087
6d4baf08
MB		 1088 { "IN1L", NULL, "SYSCLK" },
1089 { "IN1R", NULL, "SYSCLK" },
1090 { "IN2L", NULL, "SYSCLK" },
1091 { "IN2R", NULL, "SYSCLK" },
1092 { "IN3L", NULL, "SYSCLK" },
1093 { "IN3R", NULL, "SYSCLK" },
1094 { "IN4L", NULL, "SYSCLK" },
1095 { "IN4R", NULL, "SYSCLK" },
1096
1097 { "OUT1L", NULL, "SYSCLK" },
1098 { "OUT1R", NULL, "SYSCLK" },
1099 { "OUT2L", NULL, "SYSCLK" },
1100 { "OUT2R", NULL, "SYSCLK" },
1101 { "OUT3L", NULL, "SYSCLK" },
1102 { "OUT3R", NULL, "SYSCLK" },
1103 { "OUT4L", NULL, "SYSCLK" },
1104 { "OUT4R", NULL, "SYSCLK" },
1105 { "OUT5L", NULL, "SYSCLK" },
1106 { "OUT5R", NULL, "SYSCLK" },
1107 { "OUT6L", NULL, "SYSCLK" },
1108 { "OUT6R", NULL, "SYSCLK" },
1109
1110 { "AIF1RX1", NULL, "SYSCLK" },
1111 { "AIF1RX2", NULL, "SYSCLK" },
1112 { "AIF1RX3", NULL, "SYSCLK" },
1113 { "AIF1RX4", NULL, "SYSCLK" },
1114 { "AIF1RX5", NULL, "SYSCLK" },
1115 { "AIF1RX6", NULL, "SYSCLK" },
1116 { "AIF1RX7", NULL, "SYSCLK" },
1117 { "AIF1RX8", NULL, "SYSCLK" },
1118
1119 { "AIF2RX1", NULL, "SYSCLK" },
7aefb086 1120 { "AIF2RX1", NULL, "DBVDD2" },
6d4baf08 1121 { "AIF2RX2", NULL, "SYSCLK" },
7aefb086 1122 { "AIF2RX2", NULL, "DBVDD2" },
6d4baf08
MB		 1123
1124 { "AIF3RX1", NULL, "SYSCLK" },
7aefb086 1125 { "AIF3RX1", NULL, "DBVDD3" },
6d4baf08 1126 { "AIF3RX2", NULL, "SYSCLK" },
7aefb086 1127 { "AIF3RX2", NULL, "DBVDD3" },
6d4baf08
MB		 1128
1129 { "AIF1TX1", NULL, "SYSCLK" },
1130 { "AIF1TX2", NULL, "SYSCLK" },
1131 { "AIF1TX3", NULL, "SYSCLK" },
1132 { "AIF1TX4", NULL, "SYSCLK" },
1133 { "AIF1TX5", NULL, "SYSCLK" },
1134 { "AIF1TX6", NULL, "SYSCLK" },
1135 { "AIF1TX7", NULL, "SYSCLK" },
1136 { "AIF1TX8", NULL, "SYSCLK" },
1137
1138 { "AIF2TX1", NULL, "SYSCLK" },
7aefb086 1139 { "AIF2TX1", NULL, "DBVDD2" },
6d4baf08 1140 { "AIF2TX2", NULL, "SYSCLK" },
7aefb086 1141 { "AIF2TX2", NULL, "DBVDD2" },
6d4baf08
MB		 1142
1143 { "AIF3TX1", NULL, "SYSCLK" },
7aefb086 1144 { "AIF3TX1", NULL, "DBVDD3" },
6d4baf08 1145 { "AIF3TX2", NULL, "SYSCLK" },
7aefb086 1146 { "AIF3TX2", NULL, "DBVDD3" },
6d4baf08
MB		 1147
1148 { "MICBIAS1", NULL, "CP2" },
1149 { "MICBIAS2", NULL, "CP2" },
1150 { "MICBIAS3", NULL, "CP2" },
1151
1152 { "IN1L PGA", NULL, "CP2" },
1153 { "IN1R PGA", NULL, "CP2" },
1154 { "IN2L PGA", NULL, "CP2" },
1155 { "IN2R PGA", NULL, "CP2" },
1156 { "IN3L PGA", NULL, "CP2" },
1157 { "IN3R PGA", NULL, "CP2" },
1158 { "IN4L PGA", NULL, "CP2" },
1159 { "IN4R PGA", NULL, "CP2" },
1160
1161 { "IN1L PGA", NULL, "CP2 Active" },
1162 { "IN1R PGA", NULL, "CP2 Active" },
1163 { "IN2L PGA", NULL, "CP2 Active" },
1164 { "IN2R PGA", NULL, "CP2 Active" },
1165 { "IN3L PGA", NULL, "CP2 Active" },
1166 { "IN3R PGA", NULL, "CP2 Active" },
1167 { "IN4L PGA", NULL, "CP2 Active" },
1168 { "IN4R PGA", NULL, "CP2 Active" },
1169
1170 { "OUT1L", NULL, "CP1" },
1171 { "OUT1R", NULL, "CP1" },
1172 { "OUT2L", NULL, "CP1" },
1173 { "OUT2R", NULL, "CP1" },
1174 { "OUT3L", NULL, "CP1" },
1175 { "OUT3R", NULL, "CP1" },
1176
1177 { "Tone Generator 1", NULL, "TONE" },
1178 { "Tone Generator 2", NULL, "TONE" },
1179
1180 { "IN1L PGA", NULL, "IN1L" },
1181 { "IN1R PGA", NULL, "IN1R" },
1182 { "IN2L PGA", NULL, "IN2L" },
1183 { "IN2R PGA", NULL, "IN2R" },
1184 { "IN3L PGA", NULL, "IN3L" },
1185 { "IN3R PGA", NULL, "IN3R" },
1186 { "IN4L PGA", NULL, "IN4L" },
1187 { "IN4R PGA", NULL, "IN4R" },
1188
1189 WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1190 WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1191 WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1192 WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1193 WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1194 WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1195
1196 WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1197 WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1198 WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1199 WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1200 WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1201 WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1202
1203 WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1204 WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1205
1206 WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1207 WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1208 WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1209 WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1210 WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1211 WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1212 WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1213 WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1214
1215 WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1216 WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1217
1218 WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1219 WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1220
1221 WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1222 WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1223 WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1224 WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1225
1226 WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1227 WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1228
1229 WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1230 WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1231 WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1232 WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1233
1234 { "HPOUT1L", NULL, "OUT1L" },
1235 { "HPOUT1R", NULL, "OUT1R" },
1236 { "HPOUT2L", NULL, "OUT2L" },
1237 { "HPOUT2R", NULL, "OUT2R" },
1238 { "HPOUT3L", NULL, "OUT3L" },
1239 { "HPOUT3R", NULL, "OUT3R" },
1240 { "SPKOUTL", NULL, "OUT4L" },
1241 { "SPKOUTR", NULL, "OUT4R" },
1242 { "SPKDAT1", NULL, "OUT5L" },
1243 { "SPKDAT1", NULL, "OUT5R" },
1244 { "SPKDAT2", NULL, "OUT6L" },
1245 { "SPKDAT2", NULL, "OUT6R" },
1246 { "PWM1", NULL, "PWM1 Driver" },
1247 { "PWM2", NULL, "PWM2 Driver" },
1248};
1249
8019ff6c 1250static const struct reg_sequence wm5100_reva_patches[] = {
6d4baf08
MB		 1251 { WM5100_AUDIO_IF_1_10, 0 },
1252 { WM5100_AUDIO_IF_1_11, 1 },
1253 { WM5100_AUDIO_IF_1_12, 2 },
1254 { WM5100_AUDIO_IF_1_13, 3 },
1255 { WM5100_AUDIO_IF_1_14, 4 },
1256 { WM5100_AUDIO_IF_1_15, 5 },
1257 { WM5100_AUDIO_IF_1_16, 6 },
1258 { WM5100_AUDIO_IF_1_17, 7 },
1259
1260 { WM5100_AUDIO_IF_1_18, 0 },
1261 { WM5100_AUDIO_IF_1_19, 1 },
1262 { WM5100_AUDIO_IF_1_20, 2 },
1263 { WM5100_AUDIO_IF_1_21, 3 },
1264 { WM5100_AUDIO_IF_1_22, 4 },
1265 { WM5100_AUDIO_IF_1_23, 5 },
1266 { WM5100_AUDIO_IF_1_24, 6 },
1267 { WM5100_AUDIO_IF_1_25, 7 },
1268
1269 { WM5100_AUDIO_IF_2_10, 0 },
1270 { WM5100_AUDIO_IF_2_11, 1 },
1271
1272 { WM5100_AUDIO_IF_2_18, 0 },
1273 { WM5100_AUDIO_IF_2_19, 1 },
1274
1275 { WM5100_AUDIO_IF_3_10, 0 },
1276 { WM5100_AUDIO_IF_3_11, 1 },
1277
1278 { WM5100_AUDIO_IF_3_18, 0 },
1279 { WM5100_AUDIO_IF_3_19, 1 },
1280};
1281
6d4baf08
MB		 1282static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1283{
61195838 1284 struct snd_soc_component *component = dai->component;
6d4baf08
MB		 1285 int lrclk, bclk, mask, base;
1286
9b523124 1287 base = dai->driver->base;
6d4baf08
MB		 1288
1289 lrclk = 0;
1290 bclk = 0;
1291
1292 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1293 case SND_SOC_DAIFMT_DSP_A:
1294 mask = 0;
1295 break;
6d4baf08
MB		 1296 case SND_SOC_DAIFMT_I2S:
1297 mask = 2;
1298 break;
6d4baf08 1299 default:
61195838 1300 dev_err(component->dev, "Unsupported DAI format %d\n",
6d4baf08
MB		 1301 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1302 return -EINVAL;
1303 }
1304
1305 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1306 case SND_SOC_DAIFMT_CBS_CFS:
1307 break;
1308 case SND_SOC_DAIFMT_CBS_CFM:
1309 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1310 break;
1311 case SND_SOC_DAIFMT_CBM_CFS:
1312 bclk |= WM5100_AIF1_BCLK_MSTR;
1313 break;
1314 case SND_SOC_DAIFMT_CBM_CFM:
1315 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1316 bclk |= WM5100_AIF1_BCLK_MSTR;
1317 break;
1318 default:
61195838 1319 dev_err(component->dev, "Unsupported master mode %d\n",
6d4baf08
MB		 1320 fmt & SND_SOC_DAIFMT_MASTER_MASK);
1321 return -EINVAL;
1322 }
1323
1324 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1325 case SND_SOC_DAIFMT_NB_NF:
1326 break;
1327 case SND_SOC_DAIFMT_IB_IF:
1328 bclk |= WM5100_AIF1_BCLK_INV;
1329 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1330 break;
1331 case SND_SOC_DAIFMT_IB_NF:
1332 bclk |= WM5100_AIF1_BCLK_INV;
1333 break;
1334 case SND_SOC_DAIFMT_NB_IF:
1335 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1336 break;
1337 default:
1338 return -EINVAL;
1339 }
1340
61195838 1341 snd_soc_component_update_bits(component, base + 1, WM5100_AIF1_BCLK_MSTR |
6d4baf08 1342 WM5100_AIF1_BCLK_INV, bclk);
61195838 1343 snd_soc_component_update_bits(component, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
6d4baf08 1344 WM5100_AIF1TX_LRCLK_INV, lrclk);
61195838 1345 snd_soc_component_update_bits(component, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
6d4baf08 1346 WM5100_AIF1TX_LRCLK_INV, lrclk);
61195838 1347 snd_soc_component_update_bits(component, base + 5, WM5100_AIF1_FMT_MASK, mask);
6d4baf08
MB		 1348
1349 return 0;
1350}
1351
1352#define WM5100_NUM_BCLK_RATES 19
1353
1354static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1355 32000,
1356 48000,
1357 64000,
1358 96000,
1359 128000,
1360 192000,
d73ec75c 1361 256000,
6d4baf08
MB		 1362 384000,
1363 512000,
1364 768000,
1365 1024000,
1366 1536000,
1367 2048000,
1368 3072000,
1369 4096000,
1370 6144000,
1371 8192000,
1372 12288000,
1373 24576000,
1374};
1375
1376static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1377 29400,
1378 44100,
1379 58800,
1380 88200,
1381 117600,
1382 176400,
1383 235200,
1384 352800,
1385 470400,
1386 705600,
1387 940800,
1388 1411200,
1389 1881600,
1390 2882400,
1391 3763200,
1392 5644800,
1393 7526400,
1394 11289600,
1395 22579600,
1396};
1397
1398static int wm5100_hw_params(struct snd_pcm_substream *substream,
1399 struct snd_pcm_hw_params *params,
1400 struct snd_soc_dai *dai)
1401{
61195838
KM		 1402 struct snd_soc_component *component = dai->component;
1403 struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
6d4baf08
MB		 1404 bool async = wm5100->aif_async[dai->id];
1405 int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1406 int *bclk_rates;
1407
9b523124 1408 base = dai->driver->base;
6d4baf08
MB		 1409
1410 /* Data sizes if not using TDM */
0a3dcb50 1411 wl = params_width(params);
6d4baf08
MB		 1412 if (wl < 0)
1413 return wl;
1414 fl = snd_soc_params_to_frame_size(params);
1415 if (fl < 0)
1416 return fl;
1417
61195838 1418 dev_dbg(component->dev, "Word length %d bits, frame length %d bits\n",
6d4baf08
MB		 1419 wl, fl);
1420
1421 /* Target BCLK rate */
1422 bclk = snd_soc_params_to_bclk(params);
1423 if (bclk < 0)
1424 return bclk;
1425
1426 /* Root for BCLK depends on SYS/ASYNCCLK */
1427 if (!async) {
1428 aif_rate = wm5100->sysclk;
61195838 1429 sr = wm5100_alloc_sr(component, params_rate(params));
6d4baf08
MB		 1430 if (sr < 0)
1431 return sr;
1432 } else {
1433 /* If we're in ASYNCCLK set the ASYNC sample rate */
1434 aif_rate = wm5100->asyncclk;
1435 sr = 3;
1436
1437 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1438 if (params_rate(params) == wm5100_sr_code[i])
1439 break;
1440 if (i == ARRAY_SIZE(wm5100_sr_code)) {
61195838 1441 dev_err(component->dev, "Invalid rate %dHzn",
6d4baf08
MB		 1442 params_rate(params));
1443 return -EINVAL;
1444 }
1445
1446 /* TODO: We should really check for symmetry */
61195838 1447 snd_soc_component_update_bits(component, WM5100_CLOCKING_8,
6d4baf08
MB		 1448 WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1449 }
1450
1451 if (!aif_rate) {
61195838 1452 dev_err(component->dev, "%s has no rate set\n",
6d4baf08
MB		 1453 async ? "ASYNCCLK" : "SYSCLK");
1454 return -EINVAL;
1455 }
1456
61195838 1457 dev_dbg(component->dev, "Target BCLK is %dHz, using %dHz %s\n",
6d4baf08
MB		 1458 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1459
1460 if (aif_rate % 4000)
1461 bclk_rates = wm5100_bclk_rates_cd;
1462 else
1463 bclk_rates = wm5100_bclk_rates_dat;
1464
1465 for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1466 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1467 break;
1468 if (i == WM5100_NUM_BCLK_RATES) {
61195838 1469 dev_err(component->dev,
6d4baf08
MB		 1470 "No valid BCLK for %dHz found from %dHz %s\n",
1471 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1472 return -EINVAL;
1473 }
1474
1475 bclk = i;
61195838
KM		 1476 dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1477 snd_soc_component_update_bits(component, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
6d4baf08
MB		 1478
1479 lrclk = bclk_rates[bclk] / params_rate(params);
61195838 1480 dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
6d4baf08
MB		 1481 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1482 wm5100->aif_symmetric[dai->id])
61195838 1483 snd_soc_component_update_bits(component, base + 7,
6d4baf08
MB		 1484 WM5100_AIF1RX_BCPF_MASK, lrclk);
1485 else
61195838 1486 snd_soc_component_update_bits(component, base + 6,
6d4baf08
MB		 1487 WM5100_AIF1TX_BCPF_MASK, lrclk);
1488
1489 i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1490 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
61195838 1491 snd_soc_component_update_bits(component, base + 9,
6d4baf08
MB		 1492 WM5100_AIF1RX_WL_MASK |
1493 WM5100_AIF1RX_SLOT_LEN_MASK, i);
1494 else
61195838 1495 snd_soc_component_update_bits(component, base + 8,
6d4baf08
MB		 1496 WM5100_AIF1TX_WL_MASK |
1497 WM5100_AIF1TX_SLOT_LEN_MASK, i);
1498
61195838 1499 snd_soc_component_update_bits(component, base + 4, WM5100_AIF1_RATE_MASK, sr);
6d4baf08
MB		 1500
1501 return 0;
1502}
1503
85e7652d 1504static const struct snd_soc_dai_ops wm5100_dai_ops = {
6d4baf08
MB		 1505 .set_fmt = wm5100_set_fmt,
1506 .hw_params = wm5100_hw_params,
1507};
1508
61195838 1509static int wm5100_set_sysclk(struct snd_soc_component *component, int clk_id,
6d4baf08
MB		 1510 int source, unsigned int freq, int dir)
1511{
61195838 1512 struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
6d4baf08
MB		 1513 int *rate_store;
1514 int fval, audio_rate, ret, reg;
1515
1516 switch (clk_id) {
1517 case WM5100_CLK_SYSCLK:
1518 reg = WM5100_CLOCKING_3;
1519 rate_store = &wm5100->sysclk;
1520 break;
1521 case WM5100_CLK_ASYNCCLK:
1522 reg = WM5100_CLOCKING_7;
1523 rate_store = &wm5100->asyncclk;
1524 break;
1525 case WM5100_CLK_32KHZ:
1526 /* The 32kHz clock is slightly different to the others */
1527 switch (source) {
1528 case WM5100_CLKSRC_MCLK1:
1529 case WM5100_CLKSRC_MCLK2:
1530 case WM5100_CLKSRC_SYSCLK:
61195838 1531 snd_soc_component_update_bits(component, WM5100_CLOCKING_1,
6d4baf08
MB		 1532 WM5100_CLK_32K_SRC_MASK,
1533 source);
1534 break;
1535 default:
1536 return -EINVAL;
1537 }
1538 return 0;
1539
1540 case WM5100_CLK_AIF1:
1541 case WM5100_CLK_AIF2:
1542 case WM5100_CLK_AIF3:
1543 /* Not real clocks, record which clock domain they're in */
1544 switch (source) {
1545 case WM5100_CLKSRC_SYSCLK:
1546 wm5100->aif_async[clk_id - 1] = false;
1547 break;
1548 case WM5100_CLKSRC_ASYNCCLK:
1549 wm5100->aif_async[clk_id - 1] = true;
1550 break;
1551 default:
61195838 1552 dev_err(component->dev, "Invalid source %d\n", source);
6d4baf08
MB		 1553 return -EINVAL;
1554 }
1555 return 0;
1556
1557 case WM5100_CLK_OPCLK:
1558 switch (freq) {
1559 case 5644800:
1560 case 6144000:
61195838 1561 snd_soc_component_update_bits(component, WM5100_MISC_GPIO_1,
6d4baf08
MB		 1562 WM5100_OPCLK_SEL_MASK, 0);
1563 break;
1564 case 11289600:
1565 case 12288000:
61195838 1566 snd_soc_component_update_bits(component, WM5100_MISC_GPIO_1,
6d4baf08
MB		 1567 WM5100_OPCLK_SEL_MASK, 0);
1568 break;
1569 case 22579200:
1570 case 24576000:
61195838 1571 snd_soc_component_update_bits(component, WM5100_MISC_GPIO_1,
6d4baf08
MB		 1572 WM5100_OPCLK_SEL_MASK, 0);
1573 break;
1574 default:
61195838 1575 dev_err(component->dev, "Unsupported OPCLK %dHz\n",
6d4baf08
MB		 1576 freq);
1577 return -EINVAL;
1578 }
1579 return 0;
1580
1581 default:
61195838 1582 dev_err(component->dev, "Unknown clock %d\n", clk_id);
6d4baf08
MB		 1583 return -EINVAL;
1584 }
1585
1586 switch (source) {
1587 case WM5100_CLKSRC_SYSCLK:
1588 case WM5100_CLKSRC_ASYNCCLK:
61195838 1589 dev_err(component->dev, "Invalid source %d\n", source);
6d4baf08
MB		 1590 return -EINVAL;
1591 }
1592
1593 switch (freq) {
1594 case 5644800:
1595 case 6144000:
1596 fval = 0;
1597 break;
1598 case 11289600:
1599 case 12288000:
1600 fval = 1;
1601 break;
1602 case 22579200:
11c2b5f2 1603 case 24576000:
6d4baf08
MB		 1604 fval = 2;
1605 break;
1606 default:
61195838 1607 dev_err(component->dev, "Invalid clock rate: %d\n", freq);
6d4baf08
MB		 1608 return -EINVAL;
1609 }
1610
1611 switch (freq) {
1612 case 5644800:
1613 case 11289600:
1614 case 22579200:
1615 audio_rate = 44100;
1616 break;
1617
1618 case 6144000:
1619 case 12288000:
11c2b5f2 1620 case 24576000:
6d4baf08
MB		 1621 audio_rate = 48000;
1622 break;
1623
1624 default:
1625 BUG();
1626 audio_rate = 0;
1627 break;
1628 }
1629
1630 /* TODO: Check if MCLKs are in use and enable/disable pulls to
1631 * match.
1632 */
1633
61195838 1634 snd_soc_component_update_bits(component, reg, WM5100_SYSCLK_FREQ_MASK |
6d4baf08
MB		 1635 WM5100_SYSCLK_SRC_MASK,
1636 fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1637
1638 /* If this is SYSCLK then configure the clock rate for the
1639 * internal audio functions to the natural sample rate for
1640 * this clock rate.
1641 */
1642 if (clk_id == WM5100_CLK_SYSCLK) {
61195838 1643 dev_dbg(component->dev, "Setting primary audio rate to %dHz",
6d4baf08
MB		 1644 audio_rate);
1645 if (0 && *rate_store)
61195838
KM		 1646 wm5100_free_sr(component, audio_rate);
1647 ret = wm5100_alloc_sr(component, audio_rate);
6d4baf08 1648 if (ret != 0)
61195838 1649 dev_warn(component->dev, "Primary audio slot is %d\n",
6d4baf08
MB		 1650 ret);
1651 }
1652
1653 *rate_store = freq;
1654
1655 return 0;
1656}
1657
1658struct _fll_div {
1659 u16 fll_fratio;
1660 u16 fll_outdiv;
1661 u16 fll_refclk_div;
1662 u16 n;
1663 u16 theta;
1664 u16 lambda;
1665};
1666
1667static struct {
1668 unsigned int min;
1669 unsigned int max;
1670 u16 fll_fratio;
1671 int ratio;
1672} fll_fratios[] = {
1673 { 0, 64000, 4, 16 },
1674 { 64000, 128000, 3, 8 },
1675 { 128000, 256000, 2, 4 },
1676 { 256000, 1000000, 1, 2 },
1677 { 1000000, 13500000, 0, 1 },
1678};
1679
1680static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1681 unsigned int Fout)
1682{
1683 unsigned int target;
1684 unsigned int div;
1685 unsigned int fratio, gcd_fll;
1686 int i;
1687
1688 /* Fref must be <=13.5MHz */
1689 div = 1;
1690 fll_div->fll_refclk_div = 0;
1691 while ((Fref / div) > 13500000) {
1692 div *= 2;
1693 fll_div->fll_refclk_div++;
1694
1695 if (div > 8) {
1696 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1697 Fref);
1698 return -EINVAL;
1699 }
1700 }
1701
1702 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1703
1704 /* Apply the division for our remaining calculations */
1705 Fref /= div;
1706
1707 /* Fvco should be 90-100MHz; don't check the upper bound */
1708 div = 2;
1709 while (Fout * div < 90000000) {
1710 div++;
1711 if (div > 64) {
1712 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1713 Fout);
1714 return -EINVAL;
1715 }
1716 }
1717 target = Fout * div;
1718 fll_div->fll_outdiv = div - 1;
1719
1720 pr_debug("FLL Fvco=%dHz\n", target);
1721
1722 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1723 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1724 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1725 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1726 fratio = fll_fratios[i].ratio;
1727 break;
1728 }
1729 }
1730 if (i == ARRAY_SIZE(fll_fratios)) {
1731 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1732 return -EINVAL;
1733 }
1734
1735 fll_div->n = target / (fratio * Fref);
1736
1737 if (target % Fref == 0) {
1738 fll_div->theta = 0;
1739 fll_div->lambda = 0;
1740 } else {
1741 gcd_fll = gcd(target, fratio * Fref);
1742
1743 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1744 / gcd_fll;
1745 fll_div->lambda = (fratio * Fref) / gcd_fll;
1746 }
1747
1748 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1749 fll_div->n, fll_div->theta, fll_div->lambda);
1750 pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1751 fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1752 fll_div->fll_refclk_div);
1753
1754 return 0;
1755}
1756
61195838 1757static int wm5100_set_fll(struct snd_soc_component *component, int fll_id, int source,
6d4baf08
MB		 1758 unsigned int Fref, unsigned int Fout)
1759{
61195838
KM		 1760 struct i2c_client *i2c = to_i2c_client(component->dev);
1761 struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
6d4baf08
MB		 1762 struct _fll_div factors;
1763 struct wm5100_fll *fll;
1764 int ret, base, lock, i, timeout;
905a8086 1765 unsigned long time_left;
6d4baf08
MB		 1766
1767 switch (fll_id) {
1768 case WM5100_FLL1:
1769 fll = &wm5100->fll[0];
1770 base = WM5100_FLL1_CONTROL_1 - 1;
1771 lock = WM5100_FLL1_LOCK_STS;
1772 break;
1773 case WM5100_FLL2:
1774 fll = &wm5100->fll[1];
1775 base = WM5100_FLL2_CONTROL_2 - 1;
1776 lock = WM5100_FLL2_LOCK_STS;
1777 break;
1778 default:
61195838 1779 dev_err(component->dev, "Unknown FLL %d\n",fll_id);
6d4baf08
MB		 1780 return -EINVAL;
1781 }
1782
1783 if (!Fout) {
61195838 1784 dev_dbg(component->dev, "FLL%d disabled", fll_id);
62c1c401 1785 if (fll->fout)
61195838 1786 pm_runtime_put(component->dev);
6d4baf08 1787 fll->fout = 0;
61195838 1788 snd_soc_component_update_bits(component, base + 1, WM5100_FLL1_ENA, 0);
6d4baf08
MB		 1789 return 0;
1790 }
1791
1792 switch (source) {
1793 case WM5100_FLL_SRC_MCLK1:
1794 case WM5100_FLL_SRC_MCLK2:
1795 case WM5100_FLL_SRC_FLL1:
1796 case WM5100_FLL_SRC_FLL2:
1797 case WM5100_FLL_SRC_AIF1BCLK:
1798 case WM5100_FLL_SRC_AIF2BCLK:
1799 case WM5100_FLL_SRC_AIF3BCLK:
1800 break;
1801 default:
61195838 1802 dev_err(component->dev, "Invalid FLL source %d\n", source);
6d4baf08
MB		 1803 return -EINVAL;
1804 }
1805
1806 ret = fll_factors(&factors, Fref, Fout);
1807 if (ret < 0)
1808 return ret;
1809
1810 /* Disable the FLL while we reconfigure */
61195838 1811 snd_soc_component_update_bits(component, base + 1, WM5100_FLL1_ENA, 0);
6d4baf08 1812
61195838 1813 snd_soc_component_update_bits(component, base + 2,
6d4baf08
MB		 1814 WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1815 (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1816 factors.fll_fratio);
61195838 1817 snd_soc_component_update_bits(component, base + 3, WM5100_FLL1_THETA_MASK,
6d4baf08 1818 factors.theta);
61195838
KM		 1819 snd_soc_component_update_bits(component, base + 5, WM5100_FLL1_N_MASK, factors.n);
1820 snd_soc_component_update_bits(component, base + 6,
6d4baf08
MB		 1821 WM5100_FLL1_REFCLK_DIV_MASK |
1822 WM5100_FLL1_REFCLK_SRC_MASK,
1823 (factors.fll_refclk_div
1824 << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
61195838 1825 snd_soc_component_update_bits(component, base + 7, WM5100_FLL1_LAMBDA_MASK,
6d4baf08
MB		 1826 factors.lambda);
1827
1828 /* Clear any pending completions */
1829 try_wait_for_completion(&fll->lock);
1830
61195838 1831 pm_runtime_get_sync(component->dev);
62c1c401 1832
61195838 1833 snd_soc_component_update_bits(component, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
6d4baf08
MB		 1834
1835 if (i2c->irq)
1836 timeout = 2;
1837 else
1838 timeout = 50;
1839
61195838 1840 snd_soc_component_update_bits(component, WM5100_CLOCKING_3, WM5100_SYSCLK_ENA,
bd132ec5
MB		 1841 WM5100_SYSCLK_ENA);
1842
6d4baf08
MB		 1843 /* Poll for the lock; will use interrupt when we can test */
1844 for (i = 0; i < timeout; i++) {
1845 if (i2c->irq) {
905a8086
NMG		 1846 time_left = wait_for_completion_timeout(&fll->lock,
1847 msecs_to_jiffies(25));
1848 if (time_left > 0)
6d4baf08
MB		 1849 break;
1850 } else {
1851 msleep(1);
1852 }
1853
6d75dfc3 1854 ret = snd_soc_component_read(component,
6d4baf08
MB		 1855 WM5100_INTERRUPT_RAW_STATUS_3);
1856 if (ret < 0) {
61195838 1857 dev_err(component->dev,
6d4baf08
MB		 1858 "Failed to read FLL status: %d\n",
1859 ret);
1860 continue;
1861 }
1862 if (ret & lock)
1863 break;
1864 }
1865 if (i == timeout) {
61195838
KM		 1866 dev_err(component->dev, "FLL%d lock timed out\n", fll_id);
1867 pm_runtime_put(component->dev);
6d4baf08
MB		 1868 return -ETIMEDOUT;
1869 }
1870
1871 fll->src = source;
1872 fll->fref = Fref;
1873 fll->fout = Fout;
1874
61195838 1875 dev_dbg(component->dev, "FLL%d running %dHz->%dHz\n", fll_id,
6d4baf08
MB		 1876 Fref, Fout);
1877
1878 return 0;
1879}
1880
1881/* Actually go much higher */
1882#define WM5100_RATES SNDRV_PCM_RATE_8000_192000
1883
1884#define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1885 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1886
1887static struct snd_soc_dai_driver wm5100_dai[] = {
1888 {
1889 .name = "wm5100-aif1",
9b523124 1890 .base = WM5100_AUDIO_IF_1_1 - 1,
6d4baf08
MB		 1891 .playback = {
1892 .stream_name = "AIF1 Playback",
1893 .channels_min = 2,
1894 .channels_max = 2,
1895 .rates = WM5100_RATES,
1896 .formats = WM5100_FORMATS,
1897 },
1898 .capture = {
1899 .stream_name = "AIF1 Capture",
1900 .channels_min = 2,
1901 .channels_max = 2,
1902 .rates = WM5100_RATES,
1903 .formats = WM5100_FORMATS,
1904 },
1905 .ops = &wm5100_dai_ops,
1906 },
1907 {
1908 .name = "wm5100-aif2",
1909 .id = 1,
9b523124 1910 .base = WM5100_AUDIO_IF_2_1 - 1,
6d4baf08
MB		 1911 .playback = {
1912 .stream_name = "AIF2 Playback",
1913 .channels_min = 2,
1914 .channels_max = 2,
1915 .rates = WM5100_RATES,
1916 .formats = WM5100_FORMATS,
1917 },
1918 .capture = {
1919 .stream_name = "AIF2 Capture",
1920 .channels_min = 2,
1921 .channels_max = 2,
1922 .rates = WM5100_RATES,
1923 .formats = WM5100_FORMATS,
1924 },
1925 .ops = &wm5100_dai_ops,
1926 },
1927 {
1928 .name = "wm5100-aif3",
1929 .id = 2,
9b523124 1930 .base = WM5100_AUDIO_IF_3_1 - 1,
6d4baf08
MB		 1931 .playback = {
1932 .stream_name = "AIF3 Playback",
1933 .channels_min = 2,
1934 .channels_max = 2,
1935 .rates = WM5100_RATES,
1936 .formats = WM5100_FORMATS,
1937 },
1938 .capture = {
1939 .stream_name = "AIF3 Capture",
1940 .channels_min = 2,
1941 .channels_max = 2,
1942 .rates = WM5100_RATES,
1943 .formats = WM5100_FORMATS,
1944 },
1945 .ops = &wm5100_dai_ops,
1946 },
1947};
1948
1949static int wm5100_dig_vu[] = {
1950 WM5100_ADC_DIGITAL_VOLUME_1L,
1951 WM5100_ADC_DIGITAL_VOLUME_1R,
1952 WM5100_ADC_DIGITAL_VOLUME_2L,
1953 WM5100_ADC_DIGITAL_VOLUME_2R,
1954 WM5100_ADC_DIGITAL_VOLUME_3L,
1955 WM5100_ADC_DIGITAL_VOLUME_3R,
1956 WM5100_ADC_DIGITAL_VOLUME_4L,
1957 WM5100_ADC_DIGITAL_VOLUME_4R,
1958
1959 WM5100_DAC_DIGITAL_VOLUME_1L,
1960 WM5100_DAC_DIGITAL_VOLUME_1R,
1961 WM5100_DAC_DIGITAL_VOLUME_2L,
1962 WM5100_DAC_DIGITAL_VOLUME_2R,
1963 WM5100_DAC_DIGITAL_VOLUME_3L,
1964 WM5100_DAC_DIGITAL_VOLUME_3R,
1965 WM5100_DAC_DIGITAL_VOLUME_4L,
1966 WM5100_DAC_DIGITAL_VOLUME_4R,
1967 WM5100_DAC_DIGITAL_VOLUME_5L,
1968 WM5100_DAC_DIGITAL_VOLUME_5R,
1969 WM5100_DAC_DIGITAL_VOLUME_6L,
1970 WM5100_DAC_DIGITAL_VOLUME_6R,
1971};
1972
46c1a877 1973static void wm5100_set_detect_mode(struct wm5100_priv *wm5100, int the_mode)
ba896ede 1974{
ba896ede
MB		 1975 struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
1976
95ff71e9
TI		 1977 if (WARN_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes)))
1978 return;
ba896ede 1979
8563cfe3 1980 gpiod_set_value_cansleep(wm5100->hp_pol, mode->hp_pol);
46c1a877
MB		 1981 regmap_update_bits(wm5100->regmap, WM5100_ACCESSORY_DETECT_MODE_1,
1982 WM5100_ACCDET_BIAS_SRC_MASK |
1983 WM5100_ACCDET_SRC,
1984 (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
1985 mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
1986 regmap_update_bits(wm5100->regmap, WM5100_MISC_CONTROL,
1987 WM5100_HPCOM_SRC,
1988 mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
ba896ede
MB		 1989
1990 wm5100->jack_mode = the_mode;
1991
46c1a877 1992 dev_dbg(wm5100->dev, "Set microphone polarity to %d\n",
ba896ede
MB		 1993 wm5100->jack_mode);
1994}
1995
2633f736
MB		 1996static void wm5100_report_headphone(struct wm5100_priv *wm5100)
1997{
1998 dev_dbg(wm5100->dev, "Headphone detected\n");
1999 wm5100->jack_detecting = false;
2000 snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
2001 SND_JACK_HEADPHONE);
2002
2003 /* Increase the detection rate a bit for responsiveness. */
2004 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2005 WM5100_ACCDET_RATE_MASK,
2006 7 << WM5100_ACCDET_RATE_SHIFT);
2007}
2008
46c1a877 2009static void wm5100_micd_irq(struct wm5100_priv *wm5100)
ba896ede 2010{
46c1a877
MB		 2011 unsigned int val;
2012 int ret;
ba896ede 2013
46c1a877
MB		 2014 ret = regmap_read(wm5100->regmap, WM5100_MIC_DETECT_3, &val);
2015 if (ret != 0) {
fd9f069d 2016 dev_err(wm5100->dev, "Failed to read microphone status: %d\n",
46c1a877
MB		 2017 ret);
2018 return;
2019 }
ba896ede 2020
46c1a877 2021 dev_dbg(wm5100->dev, "Microphone event: %x\n", val);
ba896ede
MB		 2022
2023 if (!(val & WM5100_ACCDET_VALID)) {
46c1a877 2024 dev_warn(wm5100->dev, "Microphone detection state invalid\n");
ba896ede
MB		 2025 return;
2026 }
2027
2028 /* No accessory, reset everything and report removal */
2029 if (!(val & WM5100_ACCDET_STS)) {
46c1a877 2030 dev_dbg(wm5100->dev, "Jack removal detected\n");
ba896ede
MB		 2031 wm5100->jack_mic = false;
2032 wm5100->jack_detecting = true;
2633f736 2033 wm5100->jack_flips = 0;
ba896ede
MB		 2034 snd_soc_jack_report(wm5100->jack, 0,
2035 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2036 SND_JACK_BTN_0);
2037
46c1a877
MB		 2038 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2039 WM5100_ACCDET_RATE_MASK,
2040 WM5100_ACCDET_RATE_MASK);
ba896ede
MB		 2041 return;
2042 }
2043
2044 /* If the measurement is very high we've got a microphone,
2045 * either we just detected one or if we already reported then
2046 * we've got a button release event.
2047 */
2048 if (val & 0x400) {
2049 if (wm5100->jack_detecting) {
46c1a877 2050 dev_dbg(wm5100->dev, "Microphone detected\n");
ba896ede 2051 wm5100->jack_mic = true;
9fb83526 2052 wm5100->jack_detecting = false;
ba896ede
MB		 2053 snd_soc_jack_report(wm5100->jack,
2054 SND_JACK_HEADSET,
2055 SND_JACK_HEADSET | SND_JACK_BTN_0);
2056
2057 /* Increase poll rate to give better responsiveness
2058 * for buttons */
46c1a877
MB		 2059 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2060 WM5100_ACCDET_RATE_MASK,
2061 5 << WM5100_ACCDET_RATE_SHIFT);
ba896ede 2062 } else {
46c1a877 2063 dev_dbg(wm5100->dev, "Mic button up\n");
ba896ede
MB		 2064 snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
2065 }
2066
2067 return;
2068 }
2069
2070 /* If we detected a lower impedence during initial startup
2071 * then we probably have the wrong polarity, flip it. Don't
2072 * do this for the lowest impedences to speed up detection of
2633f736
MB		 2073 * plain headphones and give up if neither polarity looks
2074 * sensible.
ba896ede
MB		 2075 */
2076 if (wm5100->jack_detecting && (val & 0x3f8)) {
2633f736
MB		 2077 wm5100->jack_flips++;
2078
2079 if (wm5100->jack_flips > 1)
2080 wm5100_report_headphone(wm5100);
2081 else
2082 wm5100_set_detect_mode(wm5100, !wm5100->jack_mode);
ba896ede
MB		 2083
2084 return;
2085 }
2086
2087 /* Don't distinguish between buttons, just report any low
2088 * impedence as BTN_0.
2089 */
2090 if (val & 0x3fc) {
2091 if (wm5100->jack_mic) {
46c1a877 2092 dev_dbg(wm5100->dev, "Mic button detected\n");
ba896ede
MB		 2093 snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
2094 SND_JACK_BTN_0);
2095 } else if (wm5100->jack_detecting) {
2633f736 2096 wm5100_report_headphone(wm5100);
ba896ede
MB		 2097 }
2098 }
2099}
2100
61195838 2101int wm5100_detect(struct snd_soc_component *component, struct snd_soc_jack *jack)
ba896ede 2102{
61195838
KM		 2103 struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
2104 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
ba896ede
MB		 2105
2106 if (jack) {
2107 wm5100->jack = jack;
2108 wm5100->jack_detecting = true;
2633f736 2109 wm5100->jack_flips = 0;
ba896ede 2110
46c1a877 2111 wm5100_set_detect_mode(wm5100, 0);
ba896ede
MB		 2112
2113 /* Slowest detection rate, gives debounce for initial
2114 * detection */
61195838 2115 snd_soc_component_update_bits(component, WM5100_MIC_DETECT_1,
ba896ede
MB		 2116 WM5100_ACCDET_BIAS_STARTTIME_MASK |
2117 WM5100_ACCDET_RATE_MASK,
2118 (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
2119 WM5100_ACCDET_RATE_MASK);
2120
2121 /* We need the charge pump to power MICBIAS */
e951f267
CK		 2122 snd_soc_dapm_mutex_lock(dapm);
2123
2124 snd_soc_dapm_force_enable_pin_unlocked(dapm, "CP2");
2125 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
2126
2127 snd_soc_dapm_sync_unlocked(dapm);
2128
2129 snd_soc_dapm_mutex_unlock(dapm);
ba896ede
MB		 2130
2131 /* We start off just enabling microphone detection - even a
2132 * plain headphone will trigger detection.
2133 */
61195838 2134 snd_soc_component_update_bits(component, WM5100_MIC_DETECT_1,
ba896ede
MB		 2135 WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
2136
61195838 2137 snd_soc_component_update_bits(component, WM5100_INTERRUPT_STATUS_3_MASK,
ba896ede
MB		 2138 WM5100_IM_ACCDET_EINT, 0);
2139 } else {
61195838 2140 snd_soc_component_update_bits(component, WM5100_INTERRUPT_STATUS_3_MASK,
ba896ede
MB		 2141 WM5100_IM_HPDET_EINT |
2142 WM5100_IM_ACCDET_EINT,
2143 WM5100_IM_HPDET_EINT |
2144 WM5100_IM_ACCDET_EINT);
61195838 2145 snd_soc_component_update_bits(component, WM5100_MIC_DETECT_1,
ba896ede
MB		 2146 WM5100_ACCDET_ENA, 0);
2147 wm5100->jack = NULL;
2148 }
2149
2150 return 0;
2151}
0cf0f174 2152EXPORT_SYMBOL_GPL(wm5100_detect);
ba896ede 2153
6d4baf08
MB		 2154static irqreturn_t wm5100_irq(int irq, void *data)
2155{
46c1a877 2156 struct wm5100_priv *wm5100 = data;
6d4baf08 2157 irqreturn_t status = IRQ_NONE;
46c1a877
MB		 2158 unsigned int irq_val, mask_val;
2159 int ret;
6d4baf08 2160
46c1a877
MB		 2161 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, &irq_val);
2162 if (ret < 0) {
2163 dev_err(wm5100->dev, "Failed to read IRQ status 3: %d\n",
2164 ret);
6d4baf08
MB		 2165 irq_val = 0;
2166 }
6d4baf08 2167
46c1a877
MB		 2168 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3_MASK,
2169 &mask_val);
2170 if (ret < 0) {
2171 dev_err(wm5100->dev, "Failed to read IRQ mask 3: %d\n",
2172 ret);
2173 mask_val = 0xffff;
2174 }
2175
2176 irq_val &= ~mask_val;
2177
2178 regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, irq_val);
6d4baf08
MB		 2179
2180 if (irq_val)
2181 status = IRQ_HANDLED;
2182
46c1a877 2183 wm5100_log_status3(wm5100, irq_val);
6d4baf08
MB		 2184
2185 if (irq_val & WM5100_FLL1_LOCK_EINT) {
46c1a877 2186 dev_dbg(wm5100->dev, "FLL1 locked\n");
6d4baf08
MB		 2187 complete(&wm5100->fll[0].lock);
2188 }
2189 if (irq_val & WM5100_FLL2_LOCK_EINT) {
46c1a877 2190 dev_dbg(wm5100->dev, "FLL2 locked\n");
6d4baf08
MB		 2191 complete(&wm5100->fll[1].lock);
2192 }
2193
ba896ede 2194 if (irq_val & WM5100_ACCDET_EINT)
46c1a877 2195 wm5100_micd_irq(wm5100);
ba896ede 2196
46c1a877
MB		 2197 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, &irq_val);
2198 if (ret < 0) {
2199 dev_err(wm5100->dev, "Failed to read IRQ status 4: %d\n",
2200 ret);
6d4baf08
MB		 2201 irq_val = 0;
2202 }
46c1a877
MB		 2203
2204 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4_MASK,
2205 &mask_val);
2206 if (ret < 0) {
2207 dev_err(wm5100->dev, "Failed to read IRQ mask 4: %d\n",
2208 ret);
2209 mask_val = 0xffff;
2210 }
2211
2212 irq_val &= ~mask_val;
6d4baf08
MB		 2213
2214 if (irq_val)
2215 status = IRQ_HANDLED;
2216
46c1a877 2217 regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, irq_val);
6d4baf08 2218
46c1a877 2219 wm5100_log_status4(wm5100, irq_val);
6d4baf08
MB		 2220
2221 return status;
2222}
2223
2224static irqreturn_t wm5100_edge_irq(int irq, void *data)
2225{
2226 irqreturn_t ret = IRQ_NONE;
2227 irqreturn_t val;
2228
2229 do {
2230 val = wm5100_irq(irq, data);
2231 if (val != IRQ_NONE)
2232 ret = val;
2233 } while (val != IRQ_NONE);
2234
2235 return ret;
2236}
2237
2238#ifdef CONFIG_GPIOLIB
6d4baf08
MB		 2239static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2240{
db1d1270 2241 struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
6d4baf08 2242
9db16e4c
MB		 2243 regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2244 WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
6d4baf08
MB		 2245}
2246
2247static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2248 unsigned offset, int value)
2249{
db1d1270 2250 struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
64964e82 2251 int val, ret;
6d4baf08
MB		 2252
2253 val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2254
9db16e4c
MB		 2255 ret = regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2256 WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2257 WM5100_GP1_LVL, val);
64964e82
MB		 2258 if (ret < 0)
2259 return ret;
2260 else
2261 return 0;
6d4baf08
MB		 2262}
2263
2264static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2265{
db1d1270 2266 struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
9db16e4c 2267 unsigned int reg;
6d4baf08
MB		 2268 int ret;
2269
9db16e4c 2270 ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, &reg);
6d4baf08
MB		 2271 if (ret < 0)
2272 return ret;
2273
9db16e4c 2274 return (reg & WM5100_GP1_LVL) != 0;
6d4baf08
MB		 2275}
2276
2277static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2278{
db1d1270 2279 struct wm5100_priv *wm5100 = gpiochip_get_data(chip);
6d4baf08 2280
9db16e4c
MB		 2281 return regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2282 WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2283 (1 << WM5100_GP1_FN_SHIFT) |
2284 (1 << WM5100_GP1_DIR_SHIFT));
6d4baf08
MB		 2285}
2286
c59b24f8 2287static const struct gpio_chip wm5100_template_chip = {
6d4baf08
MB		 2288 .label = "wm5100",
2289 .owner = THIS_MODULE,
2290 .direction_output = wm5100_gpio_direction_out,
2291 .set = wm5100_gpio_set,
2292 .direction_input = wm5100_gpio_direction_in,
2293 .get = wm5100_gpio_get,
2294 .can_sleep = 1,
2295};
2296
9db16e4c 2297static void wm5100_init_gpio(struct i2c_client *i2c)
6d4baf08 2298{
9db16e4c 2299 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
6d4baf08
MB		 2300 int ret;
2301
2302 wm5100->gpio_chip = wm5100_template_chip;
2303 wm5100->gpio_chip.ngpio = 6;
58383c78 2304 wm5100->gpio_chip.parent = &i2c->dev;
8563cfe3 2305 wm5100->gpio_chip.base = -1;
6d4baf08 2306
db1d1270 2307 ret = gpiochip_add_data(&wm5100->gpio_chip, wm5100);
6d4baf08 2308 if (ret != 0)
9db16e4c 2309 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
6d4baf08
MB		 2310}
2311
9db16e4c 2312static void wm5100_free_gpio(struct i2c_client *i2c)
6d4baf08 2313{
9db16e4c 2314 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
6d4baf08 2315
88d5e520 2316 gpiochip_remove(&wm5100->gpio_chip);
6d4baf08
MB		 2317}
2318#else
9db16e4c 2319static void wm5100_init_gpio(struct i2c_client *i2c)
6d4baf08
MB		 2320{
2321}
2322
9db16e4c 2323static void wm5100_free_gpio(struct i2c_client *i2c)
6d4baf08
MB		 2324{
2325}
2326#endif
2327
61195838 2328static int wm5100_probe(struct snd_soc_component *component)
6d4baf08 2329{
61195838
KM		 2330 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2331 struct i2c_client *i2c = to_i2c_client(component->dev);
2332 struct wm5100_priv *wm5100 = snd_soc_component_get_drvdata(component);
09452f23 2333 int ret, i;
6d4baf08 2334
61195838 2335 wm5100->component = component;
6d4baf08 2336
6d4baf08 2337 for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
61195838 2338 snd_soc_component_update_bits(component, wm5100_dig_vu[i], WM5100_OUT_VU,
6d4baf08
MB		 2339 WM5100_OUT_VU);
2340
6d4baf08 2341 /* Don't debounce interrupts to support use of SYSCLK only */
61195838
KM		 2342 snd_soc_component_write(component, WM5100_IRQ_DEBOUNCE_1, 0);
2343 snd_soc_component_write(component, WM5100_IRQ_DEBOUNCE_2, 0);
6d4baf08
MB		 2344
2345 /* TODO: check if we're symmetric */
2346
09452f23 2347 if (i2c->irq)
002d1c4e 2348 snd_soc_dapm_new_controls(dapm, wm5100_dapm_widgets_noirq,
6d4baf08 2349 ARRAY_SIZE(wm5100_dapm_widgets_noirq));
6d4baf08 2350
8563cfe3
LW		 2351 wm5100->hp_pol = devm_gpiod_get_optional(&i2c->dev, "hp-pol",
2352 GPIOD_OUT_HIGH);
2353 if (IS_ERR(wm5100->hp_pol)) {
2354 ret = PTR_ERR(wm5100->hp_pol);
2355 dev_err(&i2c->dev, "Failed to request HP_POL GPIO: %d\n",
2356 ret);
2357 return ret;
6d4baf08
MB		 2358 }
2359
6d4baf08 2360 return 0;
6d4baf08
MB		 2361}
2362
61195838
KM		 2363static const struct snd_soc_component_driver soc_component_dev_wm5100 = {
2364 .probe = wm5100_probe,
61195838
KM		 2365 .set_sysclk = wm5100_set_sysclk,
2366 .set_pll = wm5100_set_fll,
2367 .seq_notifier = wm5100_seq_notifier,
2368 .controls = wm5100_snd_controls,
2369 .num_controls = ARRAY_SIZE(wm5100_snd_controls),
2370 .dapm_widgets = wm5100_dapm_widgets,
2371 .num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
2372 .dapm_routes = wm5100_dapm_routes,
2373 .num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
2374 .use_pmdown_time = 1,
2375 .endianness = 1,
bd132ec5 2376};
6d4baf08 2377
bd132ec5
MB		 2378static const struct regmap_config wm5100_regmap = {
2379 .reg_bits = 16,
2380 .val_bits = 16,
6d4baf08 2381
bd132ec5
MB		 2382 .max_register = WM5100_MAX_REGISTER,
2383 .reg_defaults = wm5100_reg_defaults,
2384 .num_reg_defaults = ARRAY_SIZE(wm5100_reg_defaults),
2385 .volatile_reg = wm5100_volatile_register,
2386 .readable_reg = wm5100_readable_register,
4f2e3688 2387 .cache_type = REGCACHE_MAPLE,
6d4baf08
MB		 2388};
2389
a188fcba
MB		 2390static const unsigned int wm5100_mic_ctrl_reg[] = {
2391 WM5100_IN1L_CONTROL,
2392 WM5100_IN2L_CONTROL,
2393 WM5100_IN3L_CONTROL,
2394 WM5100_IN4L_CONTROL,
2395};
2396
97b0b6e3 2397static int wm5100_i2c_probe(struct i2c_client *i2c)
6d4baf08
MB		 2398{
2399 struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2400 struct wm5100_priv *wm5100;
588ac5e0 2401 unsigned int reg;
09452f23 2402 int ret, i, irq_flags;
6d4baf08 2403
a81b82c0
MB		 2404 wm5100 = devm_kzalloc(&i2c->dev, sizeof(struct wm5100_priv),
2405 GFP_KERNEL);
6d4baf08
MB		 2406 if (wm5100 == NULL)
2407 return -ENOMEM;
2408
46c1a877
MB		 2409 wm5100->dev = &i2c->dev;
2410
77caabaa 2411 wm5100->regmap = devm_regmap_init_i2c(i2c, &wm5100_regmap);
bd132ec5
MB		 2412 if (IS_ERR(wm5100->regmap)) {
2413 ret = PTR_ERR(wm5100->regmap);
2414 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2415 ret);
a81b82c0 2416 goto err;
bd132ec5
MB		 2417 }
2418
6d4baf08
MB		 2419 for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2420 init_completion(&wm5100->fll[i].lock);
2421
2422 if (pdata)
2423 wm5100->pdata = *pdata;
2424
2425 i2c_set_clientdata(i2c, wm5100);
2426
588ac5e0
MB		 2427 for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2428 wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2429
17e3e57b
MB		 2430 ret = devm_regulator_bulk_get(&i2c->dev,
2431 ARRAY_SIZE(wm5100->core_supplies),
2432 wm5100->core_supplies);
588ac5e0
MB		 2433 if (ret != 0) {
2434 dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2435 ret);
77caabaa 2436 goto err;
588ac5e0
MB		 2437 }
2438
588ac5e0
MB		 2439 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2440 wm5100->core_supplies);
2441 if (ret != 0) {
2442 dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2443 ret);
77caabaa 2444 goto err;
588ac5e0
MB		 2445 }
2446
8563cfe3
LW		 2447 wm5100->ldo_ena = devm_gpiod_get_optional(&i2c->dev, "wlf,ldo1ena",
2448 GPIOD_OUT_HIGH);
2449 if (IS_ERR(wm5100->ldo_ena)) {
2450 ret = PTR_ERR(wm5100->ldo_ena);
2451 dev_err(&i2c->dev, "Failed to request LDOENA GPIO: %d\n", ret);
2452 goto err_enable;
2453 }
2454 if (wm5100->ldo_ena) {
2455 gpiod_set_consumer_name(wm5100->ldo_ena, "WM5100 LDOENA");
588ac5e0
MB		 2456 msleep(2);
2457 }
2458
8563cfe3
LW		 2459 wm5100->reset = devm_gpiod_get_optional(&i2c->dev, "reset",
2460 GPIOD_OUT_LOW);
2461 if (IS_ERR(wm5100->reset)) {
2462 ret = PTR_ERR(wm5100->reset);
2463 dev_err(&i2c->dev, "Failed to request /RESET GPIO: %d\n", ret);
2464 goto err_ldo;
588ac5e0 2465 }
8563cfe3 2466 gpiod_set_consumer_name(wm5100->reset, "WM5100 /RESET");
588ac5e0
MB		 2467
2468 ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, &reg);
2469 if (ret < 0) {
0132615d 2470 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
588ac5e0
MB		 2471 goto err_reset;
2472 }
2473 switch (reg) {
2474 case 0x8997:
2475 case 0x5100:
2476 break;
2477
2478 default:
2479 dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg);
2480 ret = -EINVAL;
2481 goto err_reset;
2482 }
2483
2484 ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, &reg);
2485 if (ret < 0) {
2486 dev_err(&i2c->dev, "Failed to read revision register\n");
2487 goto err_reset;
2488 }
2489 wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK;
2490
2491 dev_info(&i2c->dev, "revision %c\n", wm5100->rev + 'A');
2492
2493 ret = wm5100_reset(wm5100);
2494 if (ret < 0) {
2495 dev_err(&i2c->dev, "Failed to issue reset\n");
2496 goto err_reset;
2497 }
2498
15b52f10
MB		 2499 switch (wm5100->rev) {
2500 case 0:
2501 ret = regmap_register_patch(wm5100->regmap,
2502 wm5100_reva_patches,
2503 ARRAY_SIZE(wm5100_reva_patches));
2504 if (ret != 0) {
2505 dev_err(&i2c->dev, "Failed to register patches: %d\n",
2506 ret);
2507 goto err_reset;
2508 }
2509 break;
2510 default:
2511 break;
2512 }
2513
2514
9db16e4c
MB		 2515 wm5100_init_gpio(i2c);
2516
d9b5e9c6
MB		 2517 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2518 if (!wm5100->pdata.gpio_defaults[i])
2519 continue;
2520
2521 regmap_write(wm5100->regmap, WM5100_GPIO_CTRL_1 + i,
2522 wm5100->pdata.gpio_defaults[i]);
2523 }
2524
2525 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
a188fcba 2526 regmap_update_bits(wm5100->regmap, wm5100_mic_ctrl_reg[i],
d9b5e9c6
MB		 2527 WM5100_IN1_MODE_MASK |
2528 WM5100_IN1_DMIC_SUP_MASK,
2529 (wm5100->pdata.in_mode[i] <<
2530 WM5100_IN1_MODE_SHIFT) |
2531 (wm5100->pdata.dmic_sup[i] <<
2532 WM5100_IN1_DMIC_SUP_SHIFT));
2533 }
2534
09452f23
MB		 2535 if (i2c->irq) {
2536 if (wm5100->pdata.irq_flags)
2537 irq_flags = wm5100->pdata.irq_flags;
2538 else
2539 irq_flags = IRQF_TRIGGER_LOW;
2540
2541 irq_flags |= IRQF_ONESHOT;
2542
2543 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2544 ret = request_threaded_irq(i2c->irq, NULL,
efc04ca2 2545 wm5100_edge_irq, irq_flags,
09452f23
MB		 2546 "wm5100", wm5100);
2547 else
2548 ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
efc04ca2 2549 irq_flags, "wm5100",
09452f23
MB		 2550 wm5100);
2551
2552 if (ret != 0) {
2553 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
2554 i2c->irq, ret);
2555 } else {
2556 /* Enable default interrupts */
2557 regmap_update_bits(wm5100->regmap,
2558 WM5100_INTERRUPT_STATUS_3_MASK,
2559 WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2560 WM5100_IM_SPK_SHUTDOWN_EINT |
2561 WM5100_IM_ASRC2_LOCK_EINT |
2562 WM5100_IM_ASRC1_LOCK_EINT |
2563 WM5100_IM_FLL2_LOCK_EINT |
2564 WM5100_IM_FLL1_LOCK_EINT |
2565 WM5100_CLKGEN_ERR_EINT |
2566 WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2567
2568 regmap_update_bits(wm5100->regmap,
2569 WM5100_INTERRUPT_STATUS_4_MASK,
2570 WM5100_AIF3_ERR_EINT |
2571 WM5100_AIF2_ERR_EINT |
2572 WM5100_AIF1_ERR_EINT |
2573 WM5100_CTRLIF_ERR_EINT |
2574 WM5100_ISRC2_UNDERCLOCKED_EINT |
2575 WM5100_ISRC1_UNDERCLOCKED_EINT |
2576 WM5100_FX_UNDERCLOCKED_EINT |
2577 WM5100_AIF3_UNDERCLOCKED_EINT |
2578 WM5100_AIF2_UNDERCLOCKED_EINT |
2579 WM5100_AIF1_UNDERCLOCKED_EINT |
2580 WM5100_ASRC_UNDERCLOCKED_EINT |
2581 WM5100_DAC_UNDERCLOCKED_EINT |
2582 WM5100_ADC_UNDERCLOCKED_EINT |
2583 WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2584 }
2585 }
2586
62c1c401
MB		 2587 pm_runtime_set_active(&i2c->dev);
2588 pm_runtime_enable(&i2c->dev);
2589 pm_request_idle(&i2c->dev);
2590
61195838
KM		 2591 ret = devm_snd_soc_register_component(&i2c->dev,
2592 &soc_component_dev_wm5100, wm5100_dai,
6d4baf08
MB		 2593 ARRAY_SIZE(wm5100_dai));
2594 if (ret < 0) {
2595 dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
588ac5e0 2596 goto err_reset;
6d4baf08
MB		 2597 }
2598
2599 return ret;
bd132ec5 2600
588ac5e0 2601err_reset:
b1176bbb 2602 pm_runtime_disable(&i2c->dev);
09452f23
MB		 2603 if (i2c->irq)
2604 free_irq(i2c->irq, wm5100);
9db16e4c 2605 wm5100_free_gpio(i2c);
8563cfe3 2606 gpiod_set_value_cansleep(wm5100->reset, 1);
588ac5e0 2607err_ldo:
8563cfe3 2608 gpiod_set_value_cansleep(wm5100->ldo_ena, 0);
588ac5e0
MB		 2609err_enable:
2610 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2611 wm5100->core_supplies);
a81b82c0 2612err:
bd132ec5 2613 return ret;
6d4baf08
MB		 2614}
2615
ed5c2f5f 2616static void wm5100_i2c_remove(struct i2c_client *i2c)
6d4baf08 2617{
09452f23 2618 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
bd132ec5 2619
b1176bbb 2620 pm_runtime_disable(&i2c->dev);
09452f23
MB		 2621 if (i2c->irq)
2622 free_irq(i2c->irq, wm5100);
2623 wm5100_free_gpio(i2c);
8563cfe3
LW		 2624 gpiod_set_value_cansleep(wm5100->reset, 1);
2625 gpiod_set_value_cansleep(wm5100->ldo_ena, 0);
6d4baf08
MB		 2626}
2627
641d334b 2628#ifdef CONFIG_PM
62c1c401
MB		 2629static int wm5100_runtime_suspend(struct device *dev)
2630{
2631 struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2632
2633 regcache_cache_only(wm5100->regmap, true);
2634 regcache_mark_dirty(wm5100->regmap);
8563cfe3 2635 gpiod_set_value_cansleep(wm5100->ldo_ena, 0);
62c1c401
MB		 2636 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2637 wm5100->core_supplies);
2638
2639 return 0;
2640}
2641
2642static int wm5100_runtime_resume(struct device *dev)
2643{
2644 struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2645 int ret;
2646
2647 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2648 wm5100->core_supplies);
2649 if (ret != 0) {
2650 dev_err(dev, "Failed to enable supplies: %d\n",
2651 ret);
2652 return ret;
2653 }
2654
8563cfe3
LW		 2655 if (wm5100->ldo_ena) {
2656 gpiod_set_value_cansleep(wm5100->ldo_ena, 1);
62c1c401
MB		 2657 msleep(2);
2658 }
2659
2660 regcache_cache_only(wm5100->regmap, false);
2661 regcache_sync(wm5100->regmap);
2662
2663 return 0;
2664}
2665#endif
2666
42d1b8ce 2667static const struct dev_pm_ops wm5100_pm = {
62c1c401
MB		 2668 SET_RUNTIME_PM_OPS(wm5100_runtime_suspend, wm5100_runtime_resume,
2669 NULL)
2670};
2671
6d4baf08 2672static const struct i2c_device_id wm5100_i2c_id[] = {
ba2a2c37 2673 { "wm5100" },
6d4baf08
MB		 2674 { }
2675};
2676MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2677
2678static struct i2c_driver wm5100_i2c_driver = {
2679 .driver = {
2680 .name = "wm5100",
62c1c401 2681 .pm = &wm5100_pm,
6d4baf08 2682 },
9abcd240 2683 .probe = wm5100_i2c_probe,
7a79e94e 2684 .remove = wm5100_i2c_remove,
6d4baf08
MB		 2685 .id_table = wm5100_i2c_id,
2686};
2687
d5644076 2688module_i2c_driver(wm5100_i2c_driver);
6d4baf08
MB		 2689
2690MODULE_DESCRIPTION("ASoC WM5100 driver");
2691MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2692MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)