projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: SSM2602: assign last substream to the master when shutting down
[linux-block.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 118 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 119};
120
7393958f
PU		 121/* codec private data */
122struct twl4030_priv {
123 unsigned int bypass_state;
124 unsigned int codec_powered;
125 unsigned int codec_muted;
7220b9f4
PU		 126
127 struct snd_pcm_substream *master_substream;
128 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 129
130 unsigned int configured;
131 unsigned int rate;
132 unsigned int sample_bits;
133 unsigned int channels;
6943c92e
PU		 134
135 unsigned int sysclk;
136
137 /* Headset output state handling */
138 unsigned int hsl_enabled;
139 unsigned int hsr_enabled;
7393958f
PU		 140};
141
cc17557e
SS		 142/*
143 * read twl4030 register cache
144 */
145static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
146 unsigned int reg)
147{
cc17557e 148
91432e97
IM		 149 if (reg >= TWL4030_CACHEREGNUM)
150 return -EIO;
151
cc17557e
SS		 152 return cache[reg];
153}
154
155/*
156 * write twl4030 register cache
157 */
158static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
159 u8 reg, u8 value)
160{
161 u8 *cache = codec->reg_cache;
162
163 if (reg >= TWL4030_CACHEREGNUM)
164 return;
165 cache[reg] = value;
166}
167
168/*
169 * write to the twl4030 register space
170 */
171static int twl4030_write(struct snd_soc_codec *codec,
172 unsigned int reg, unsigned int value)
173{
174 twl4030_write_reg_cache(codec, reg, value);
f3b5d300
PU		 175 if (likely(reg < TWL4030_REG_SW_SHADOW))
176 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
177 reg);
178 else
179 return 0;
cc17557e
SS		 180}
181
db04e2c5 182static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 183{
7393958f 184 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 185 u8 mode;
186
7393958f
PU		 187 if (enable == twl4030->codec_powered)
188 return;
189
cc17557e 190 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 191 if (enable)
192 mode |= TWL4030_CODECPDZ;
193 else
194 mode &= ~TWL4030_CODECPDZ;
cc17557e 195
db04e2c5 196 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
7393958f 197 twl4030->codec_powered = enable;
cc17557e
SS		 198
199 /* REVISIT: this delay is present in TI sample drivers */
200 /* but there seems to be no TRM requirement for it */
201 udelay(10);
202}
203
204static void twl4030_init_chip(struct snd_soc_codec *codec)
205{
16a30fbb 206 u8 *cache = codec->reg_cache;
cc17557e
SS		 207 int i;
208
209 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 210 twl4030_codec_enable(codec, 0);
cc17557e
SS		 211
212 /* set all audio section registers to reasonable defaults */
213 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
16a30fbb 214 twl4030_write(codec, i, cache[i]);
cc17557e
SS		 215
216}
217
7393958f
PU		 218static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
219{
220 struct twl4030_priv *twl4030 = codec->private_data;
221 u8 reg_val;
222
223 if (mute == twl4030->codec_muted)
224 return;
225
226 if (mute) {
227 /* Bypass the reg_cache and mute the volumes
228 * Headset mute is done in it's own event handler
229 * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
230 */
231 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
232 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
233 reg_val & (~TWL4030_EAR_GAIN),
234 TWL4030_REG_EAR_CTL);
235
236 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
237 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
238 reg_val & (~TWL4030_PREDL_GAIN),
239 TWL4030_REG_PREDL_CTL);
240 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
241 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
242 reg_val & (~TWL4030_PREDR_GAIN),
243 TWL4030_REG_PREDL_CTL);
244
245 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
246 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
247 reg_val & (~TWL4030_PRECKL_GAIN),
248 TWL4030_REG_PRECKL_CTL);
249 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
250 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
c198d811 251 reg_val & (~TWL4030_PRECKR_GAIN),
7393958f
PU		 252 TWL4030_REG_PRECKR_CTL);
253
254 /* Disable PLL */
255 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
256 reg_val &= ~TWL4030_APLL_EN;
257 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
258 } else {
259 /* Restore the volumes
260 * Headset mute is done in it's own event handler
261 * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
262 */
263 twl4030_write(codec, TWL4030_REG_EAR_CTL,
264 twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
265
266 twl4030_write(codec, TWL4030_REG_PREDL_CTL,
267 twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
268 twl4030_write(codec, TWL4030_REG_PREDR_CTL,
269 twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
270
271 twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
272 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
273 twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
274 twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
275
276 /* Enable PLL */
277 reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
278 reg_val |= TWL4030_APLL_EN;
279 twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
280 }
281
282 twl4030->codec_muted = mute;
283}
284
006f367e
PU		 285static void twl4030_power_up(struct snd_soc_codec *codec)
286{
7393958f 287 struct twl4030_priv *twl4030 = codec->private_data;
006f367e
PU		 288 u8 anamicl, regmisc1, byte;
289 int i = 0;
290
7393958f
PU		 291 if (twl4030->codec_powered)
292 return;
293
006f367e
PU		 294 /* set CODECPDZ to turn on codec */
295 twl4030_codec_enable(codec, 1);
296
297 /* initiate offset cancellation */
298 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
299 twl4030_write(codec, TWL4030_REG_ANAMICL,
300 anamicl | TWL4030_CNCL_OFFSET_START);
301
302 /* wait for offset cancellation to complete */
303 do {
304 /* this takes a little while, so don't slam i2c */
305 udelay(2000);
306 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
307 TWL4030_REG_ANAMICL);
308 } while ((i++ < 100) &&
309 ((byte & TWL4030_CNCL_OFFSET_START) ==
310 TWL4030_CNCL_OFFSET_START));
311
312 /* Make sure that the reg_cache has the same value as the HW */
313 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
314
315 /* anti-pop when changing analog gain */
316 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
317 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
318 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
319
320 /* toggle CODECPDZ as per TRM */
321 twl4030_codec_enable(codec, 0);
322 twl4030_codec_enable(codec, 1);
323}
324
7393958f
PU		 325/*
326 * Unconditional power down
327 */
006f367e
PU		 328static void twl4030_power_down(struct snd_soc_codec *codec)
329{
330 /* power down */
331 twl4030_codec_enable(codec, 0);
332}
333
5e98a464 334/* Earpiece */
1a787e7a
JS		 335static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
336 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
337 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
338 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
339 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
340};
5e98a464 341
2a6f5c58 342/* PreDrive Left */
1a787e7a
JS		 343static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
344 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
345 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
346 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
347 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
348};
2a6f5c58
PU		 349
350/* PreDrive Right */
1a787e7a
JS		 351static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
352 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
353 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
354 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
355 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
356};
2a6f5c58 357
dfad21a2 358/* Headset Left */
1a787e7a
JS		 359static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
360 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
361 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
362 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
363};
dfad21a2
PU		 364
365/* Headset Right */
1a787e7a
JS		 366static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
367 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
368 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
369 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
370};
dfad21a2 371
5152d8c2 372/* Carkit Left */
1a787e7a
JS		 373static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
374 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
375 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
376 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
377};
5152d8c2
PU		 378
379/* Carkit Right */
1a787e7a
JS		 380static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
381 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
382 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
383 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
384};
5152d8c2 385
df339804
PU		 386/* Handsfree Left */
387static const char *twl4030_handsfreel_texts[] =
1a787e7a 388 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 389
390static const struct soc_enum twl4030_handsfreel_enum =
391 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
392 ARRAY_SIZE(twl4030_handsfreel_texts),
393 twl4030_handsfreel_texts);
394
395static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
396SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
397
0f89bdca
PU		 398/* Handsfree Left virtual mute */
399static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
400 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
401
df339804
PU		 402/* Handsfree Right */
403static const char *twl4030_handsfreer_texts[] =
1a787e7a 404 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 405
406static const struct soc_enum twl4030_handsfreer_enum =
407 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
408 ARRAY_SIZE(twl4030_handsfreer_texts),
409 twl4030_handsfreer_texts);
410
411static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
412SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
413
0f89bdca
PU		 414/* Handsfree Right virtual mute */
415static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
416 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
417
376f7839
PU		 418/* Vibra */
419/* Vibra audio path selection */
420static const char *twl4030_vibra_texts[] =
421 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
422
423static const struct soc_enum twl4030_vibra_enum =
424 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
425 ARRAY_SIZE(twl4030_vibra_texts),
426 twl4030_vibra_texts);
427
428static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
429SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
430
431/* Vibra path selection: local vibrator (PWM) or audio driven */
432static const char *twl4030_vibrapath_texts[] =
433 {"Local vibrator", "Audio"};
434
435static const struct soc_enum twl4030_vibrapath_enum =
436 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
437 ARRAY_SIZE(twl4030_vibrapath_texts),
438 twl4030_vibrapath_texts);
439
440static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
441SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
442
276c6222 443/* Left analog microphone selection */
97b8096d
JS		 444static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
445 SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
446 SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
447 SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
448 SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
449};
276c6222
PU		 450
451/* Right analog microphone selection */
97b8096d
JS		 452static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
453 SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
181da78c 454 SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 455};
276c6222
PU		 456
457/* TX1 L/R Analog/Digital microphone selection */
458static const char *twl4030_micpathtx1_texts[] =
459 {"Analog", "Digimic0"};
460
461static const struct soc_enum twl4030_micpathtx1_enum =
462 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
463 ARRAY_SIZE(twl4030_micpathtx1_texts),
464 twl4030_micpathtx1_texts);
465
466static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
467SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
468
469/* TX2 L/R Analog/Digital microphone selection */
470static const char *twl4030_micpathtx2_texts[] =
471 {"Analog", "Digimic1"};
472
473static const struct soc_enum twl4030_micpathtx2_enum =
474 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
475 ARRAY_SIZE(twl4030_micpathtx2_texts),
476 twl4030_micpathtx2_texts);
477
478static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
479SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
480
7393958f
PU		 481/* Analog bypass for AudioR1 */
482static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
483 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
484
485/* Analog bypass for AudioL1 */
486static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
487 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
488
489/* Analog bypass for AudioR2 */
490static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
491 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
492
493/* Analog bypass for AudioL2 */
494static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
495 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
496
fcd274a3
LCM		 497/* Analog bypass for Voice */
498static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
499 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
500
6bab83fd
PU		 501/* Digital bypass gain, 0 mutes the bypass */
502static const unsigned int twl4030_dapm_dbypass_tlv[] = {
503 TLV_DB_RANGE_HEAD(2),
504 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
505 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
506};
507
508/* Digital bypass left (TX1L -> RX2L) */
509static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
510 SOC_DAPM_SINGLE_TLV("Volume",
511 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
512 twl4030_dapm_dbypass_tlv);
513
514/* Digital bypass right (TX1R -> RX2R) */
515static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
516 SOC_DAPM_SINGLE_TLV("Volume",
517 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
518 twl4030_dapm_dbypass_tlv);
519
ee8f6894
LCM		 520/*
521 * Voice Sidetone GAIN volume control:
522 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
523 */
524static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
525
526/* Digital bypass voice: sidetone (VUL -> VDL)*/
527static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
528 SOC_DAPM_SINGLE_TLV("Volume",
529 TWL4030_REG_VSTPGA, 0, 0x29, 0,
530 twl4030_dapm_dbypassv_tlv);
531
276c6222
PU		 532static int micpath_event(struct snd_soc_dapm_widget *w,
533 struct snd_kcontrol *kcontrol, int event)
534{
535 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
536 unsigned char adcmicsel, micbias_ctl;
537
538 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
539 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
540 /* Prepare the bits for the given TX path:
541 * shift_l == 0: TX1 microphone path
542 * shift_l == 2: TX2 microphone path */
543 if (e->shift_l) {
544 /* TX2 microphone path */
545 if (adcmicsel & TWL4030_TX2IN_SEL)
546 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
547 else
548 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
549 } else {
550 /* TX1 microphone path */
551 if (adcmicsel & TWL4030_TX1IN_SEL)
552 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
553 else
554 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
555 }
556
557 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
558
559 return 0;
560}
561
5a2e9a48 562static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 563{
49d92c7d
SM		 564 unsigned char hs_ctl;
565
5a2e9a48 566 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 567
5a2e9a48
PU		 568 if (ramp) {
569 /* HF ramp-up */
570 hs_ctl |= TWL4030_HF_CTL_REF_EN;
571 twl4030_write(codec, reg, hs_ctl);
572 udelay(10);
49d92c7d 573 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 574 twl4030_write(codec, reg, hs_ctl);
575 udelay(40);
49d92c7d 576 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 577 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 578 twl4030_write(codec, reg, hs_ctl);
49d92c7d 579 } else {
5a2e9a48
PU		 580 /* HF ramp-down */
581 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
582 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
583 twl4030_write(codec, reg, hs_ctl);
584 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
585 twl4030_write(codec, reg, hs_ctl);
586 udelay(40);
587 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
588 twl4030_write(codec, reg, hs_ctl);
49d92c7d 589 }
5a2e9a48 590}
49d92c7d 591
5a2e9a48
PU		 592static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
593 struct snd_kcontrol *kcontrol, int event)
594{
595 switch (event) {
596 case SND_SOC_DAPM_POST_PMU:
597 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
598 break;
599 case SND_SOC_DAPM_POST_PMD:
600 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
601 break;
602 }
603 return 0;
604}
605
606static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
607 struct snd_kcontrol *kcontrol, int event)
608{
609 switch (event) {
610 case SND_SOC_DAPM_POST_PMU:
611 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
612 break;
613 case SND_SOC_DAPM_POST_PMD:
614 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
615 break;
616 }
49d92c7d
SM		 617 return 0;
618}
619
6943c92e 620static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5
PU		 621{
622 unsigned char hs_gain, hs_pop;
6943c92e
PU		 623 struct twl4030_priv *twl4030 = codec->private_data;
624 /* Base values for ramp delay calculation: 2^19 - 2^26 */
625 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
626 8388608, 16777216, 33554432, 67108864};
aad749e5 627
6943c92e
PU		 628 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
629 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 630
6943c92e
PU		 631 if (ramp) {
632 /* Headset ramp-up according to the TRM */
aad749e5 633 hs_pop |= TWL4030_VMID_EN;
6943c92e
PU		 634 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
635 twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
aad749e5 636 hs_pop |= TWL4030_RAMP_EN;
6943c92e
PU		 637 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
638 } else {
639 /* Headset ramp-down _not_ according to
640 * the TRM, but in a way that it is working */
aad749e5 641 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 642 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
643 /* Wait ramp delay time + 1, so the VMID can settle */
644 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
645 twl4030->sysclk) + 1);
aad749e5
PU		 646 /* Bypass the reg_cache to mute the headset */
647 twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
648 hs_gain & (~0x0f),
649 TWL4030_REG_HS_GAIN_SET);
6943c92e 650
aad749e5 651 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 652 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
653 }
654}
655
656static int headsetlpga_event(struct snd_soc_dapm_widget *w,
657 struct snd_kcontrol *kcontrol, int event)
658{
659 struct twl4030_priv *twl4030 = w->codec->private_data;
660
661 switch (event) {
662 case SND_SOC_DAPM_POST_PMU:
663 /* Do the ramp-up only once */
664 if (!twl4030->hsr_enabled)
665 headset_ramp(w->codec, 1);
666
667 twl4030->hsl_enabled = 1;
668 break;
669 case SND_SOC_DAPM_POST_PMD:
670 /* Do the ramp-down only if both headsetL/R is disabled */
671 if (!twl4030->hsr_enabled)
672 headset_ramp(w->codec, 0);
673
674 twl4030->hsl_enabled = 0;
675 break;
676 }
677 return 0;
678}
679
680static int headsetrpga_event(struct snd_soc_dapm_widget *w,
681 struct snd_kcontrol *kcontrol, int event)
682{
683 struct twl4030_priv *twl4030 = w->codec->private_data;
684
685 switch (event) {
686 case SND_SOC_DAPM_POST_PMU:
687 /* Do the ramp-up only once */
688 if (!twl4030->hsl_enabled)
689 headset_ramp(w->codec, 1);
690
691 twl4030->hsr_enabled = 1;
692 break;
693 case SND_SOC_DAPM_POST_PMD:
694 /* Do the ramp-down only if both headsetL/R is disabled */
695 if (!twl4030->hsl_enabled)
696 headset_ramp(w->codec, 0);
697
698 twl4030->hsr_enabled = 0;
aad749e5
PU		 699 break;
700 }
701 return 0;
702}
703
7393958f
PU		 704static int bypass_event(struct snd_soc_dapm_widget *w,
705 struct snd_kcontrol *kcontrol, int event)
706{
707 struct soc_mixer_control *m =
708 (struct soc_mixer_control *)w->kcontrols->private_value;
709 struct twl4030_priv *twl4030 = w->codec->private_data;
fcd274a3 710 unsigned char reg, misc;
7393958f
PU		 711
712 reg = twl4030_read_reg_cache(w->codec, m->reg);
6bab83fd
PU		 713
714 if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
715 /* Analog bypass */
716 if (reg & (1 << m->shift))
717 twl4030->bypass_state |=
718 (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
719 else
720 twl4030->bypass_state &=
721 ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
fcd274a3
LCM		 722 } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
723 /* Analog voice bypass */
724 if (reg & (1 << m->shift))
725 twl4030->bypass_state |= (1 << 4);
726 else
727 twl4030->bypass_state &= ~(1 << 4);
ee8f6894
LCM		 728 } else if (m->reg == TWL4030_REG_VSTPGA) {
729 /* Voice digital bypass */
730 if (reg)
731 twl4030->bypass_state |= (1 << 5);
732 else
733 twl4030->bypass_state &= ~(1 << 5);
6bab83fd
PU		 734 } else {
735 /* Digital bypass */
736 if (reg & (0x7 << m->shift))
ee8f6894 737 twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
6bab83fd 738 else
ee8f6894 739 twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
6bab83fd 740 }
7393958f 741
fcd274a3
LCM		 742 /* Enable master analog loopback mode if any analog switch is enabled*/
743 misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
744 if (twl4030->bypass_state & 0x1F)
745 misc |= TWL4030_FMLOOP_EN;
746 else
747 misc &= ~TWL4030_FMLOOP_EN;
748 twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
749
7393958f
PU		 750 if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
751 if (twl4030->bypass_state)
752 twl4030_codec_mute(w->codec, 0);
753 else
754 twl4030_codec_mute(w->codec, 1);
755 }
756 return 0;
757}
758
b0bd53a7
PU		 759/*
760 * Some of the gain controls in TWL (mostly those which are associated with
761 * the outputs) are implemented in an interesting way:
762 * 0x0 : Power down (mute)
763 * 0x1 : 6dB
764 * 0x2 : 0 dB
765 * 0x3 : -6 dB
766 * Inverting not going to help with these.
767 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
768 */
769#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
770 xinvert, tlv_array) \
771{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
772 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
773 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
774 .tlv.p = (tlv_array), \
775 .info = snd_soc_info_volsw, \
776 .get = snd_soc_get_volsw_twl4030, \
777 .put = snd_soc_put_volsw_twl4030, \
778 .private_value = (unsigned long)&(struct soc_mixer_control) \
779 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
780 .max = xmax, .invert = xinvert} }
781#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
782 xinvert, tlv_array) \
783{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
784 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
785 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
786 .tlv.p = (tlv_array), \
787 .info = snd_soc_info_volsw_2r, \
788 .get = snd_soc_get_volsw_r2_twl4030,\
789 .put = snd_soc_put_volsw_r2_twl4030, \
790 .private_value = (unsigned long)&(struct soc_mixer_control) \
791 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 792 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 793#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
794 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
795 xinvert, tlv_array)
796
797static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
798 struct snd_ctl_elem_value *ucontrol)
799{
800 struct soc_mixer_control *mc =
801 (struct soc_mixer_control *)kcontrol->private_value;
802 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
803 unsigned int reg = mc->reg;
804 unsigned int shift = mc->shift;
805 unsigned int rshift = mc->rshift;
806 int max = mc->max;
807 int mask = (1 << fls(max)) - 1;
808
809 ucontrol->value.integer.value[0] =
810 (snd_soc_read(codec, reg) >> shift) & mask;
811 if (ucontrol->value.integer.value[0])
812 ucontrol->value.integer.value[0] =
813 max + 1 - ucontrol->value.integer.value[0];
814
815 if (shift != rshift) {
816 ucontrol->value.integer.value[1] =
817 (snd_soc_read(codec, reg) >> rshift) & mask;
818 if (ucontrol->value.integer.value[1])
819 ucontrol->value.integer.value[1] =
820 max + 1 - ucontrol->value.integer.value[1];
821 }
822
823 return 0;
824}
825
826static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
827 struct snd_ctl_elem_value *ucontrol)
828{
829 struct soc_mixer_control *mc =
830 (struct soc_mixer_control *)kcontrol->private_value;
831 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
832 unsigned int reg = mc->reg;
833 unsigned int shift = mc->shift;
834 unsigned int rshift = mc->rshift;
835 int max = mc->max;
836 int mask = (1 << fls(max)) - 1;
837 unsigned short val, val2, val_mask;
838
839 val = (ucontrol->value.integer.value[0] & mask);
840
841 val_mask = mask << shift;
842 if (val)
843 val = max + 1 - val;
844 val = val << shift;
845 if (shift != rshift) {
846 val2 = (ucontrol->value.integer.value[1] & mask);
847 val_mask |= mask << rshift;
848 if (val2)
849 val2 = max + 1 - val2;
850 val |= val2 << rshift;
851 }
852 return snd_soc_update_bits(codec, reg, val_mask, val);
853}
854
855static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
856 struct snd_ctl_elem_value *ucontrol)
857{
858 struct soc_mixer_control *mc =
859 (struct soc_mixer_control *)kcontrol->private_value;
860 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
861 unsigned int reg = mc->reg;
862 unsigned int reg2 = mc->rreg;
863 unsigned int shift = mc->shift;
864 int max = mc->max;
865 int mask = (1<<fls(max))-1;
866
867 ucontrol->value.integer.value[0] =
868 (snd_soc_read(codec, reg) >> shift) & mask;
869 ucontrol->value.integer.value[1] =
870 (snd_soc_read(codec, reg2) >> shift) & mask;
871
872 if (ucontrol->value.integer.value[0])
873 ucontrol->value.integer.value[0] =
874 max + 1 - ucontrol->value.integer.value[0];
875 if (ucontrol->value.integer.value[1])
876 ucontrol->value.integer.value[1] =
877 max + 1 - ucontrol->value.integer.value[1];
878
879 return 0;
880}
881
882static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
883 struct snd_ctl_elem_value *ucontrol)
884{
885 struct soc_mixer_control *mc =
886 (struct soc_mixer_control *)kcontrol->private_value;
887 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
888 unsigned int reg = mc->reg;
889 unsigned int reg2 = mc->rreg;
890 unsigned int shift = mc->shift;
891 int max = mc->max;
892 int mask = (1 << fls(max)) - 1;
893 int err;
894 unsigned short val, val2, val_mask;
895
896 val_mask = mask << shift;
897 val = (ucontrol->value.integer.value[0] & mask);
898 val2 = (ucontrol->value.integer.value[1] & mask);
899
900 if (val)
901 val = max + 1 - val;
902 if (val2)
903 val2 = max + 1 - val2;
904
905 val = val << shift;
906 val2 = val2 << shift;
907
908 err = snd_soc_update_bits(codec, reg, val_mask, val);
909 if (err < 0)
910 return err;
911
912 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
913 return err;
914}
915
b74bd40f
LCM		 916/* Codec operation modes */
917static const char *twl4030_op_modes_texts[] = {
918 "Option 2 (voice/audio)", "Option 1 (audio)"
919};
920
921static const struct soc_enum twl4030_op_modes_enum =
922 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
923 ARRAY_SIZE(twl4030_op_modes_texts),
924 twl4030_op_modes_texts);
925
926int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
927 struct snd_ctl_elem_value *ucontrol)
928{
929 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
930 struct twl4030_priv *twl4030 = codec->private_data;
931 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
932 unsigned short val;
933 unsigned short mask, bitmask;
934
935 if (twl4030->configured) {
936 printk(KERN_ERR "twl4030 operation mode cannot be "
937 "changed on-the-fly\n");
938 return -EBUSY;
939 }
940
941 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
942 ;
943 if (ucontrol->value.enumerated.item[0] > e->max - 1)
944 return -EINVAL;
945
946 val = ucontrol->value.enumerated.item[0] << e->shift_l;
947 mask = (bitmask - 1) << e->shift_l;
948 if (e->shift_l != e->shift_r) {
949 if (ucontrol->value.enumerated.item[1] > e->max - 1)
950 return -EINVAL;
951 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
952 mask |= (bitmask - 1) << e->shift_r;
953 }
954
955 return snd_soc_update_bits(codec, e->reg, mask, val);
956}
957
c10b82cf
PU		 958/*
959 * FGAIN volume control:
960 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
961 */
d889a72c 962static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 963
0d33ea0b
PU		 964/*
965 * CGAIN volume control:
966 * 0 dB to 12 dB in 6 dB steps
967 * value 2 and 3 means 12 dB
968 */
d889a72c
PU		 969static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
970
1a787e7a
JS		 971/*
972 * Voice Downlink GAIN volume control:
973 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
974 */
975static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
976
d889a72c
PU		 977/*
978 * Analog playback gain
979 * -24 dB to 12 dB in 2 dB steps
980 */
981static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 982
4290239c
PU		 983/*
984 * Gain controls tied to outputs
985 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
986 */
987static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
988
18cc8d8d
JS		 989/*
990 * Gain control for earpiece amplifier
991 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
992 */
993static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
994
381a22b5
PU		 995/*
996 * Capture gain after the ADCs
997 * from 0 dB to 31 dB in 1 dB steps
998 */
999static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1000
5920b453
GI		 1001/*
1002 * Gain control for input amplifiers
1003 * 0 dB to 30 dB in 6 dB steps
1004 */
1005static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1006
89492be8
PU		 1007static const char *twl4030_rampdelay_texts[] = {
1008 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1009 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1010 "3495/2581/1748 ms"
1011};
1012
1013static const struct soc_enum twl4030_rampdelay_enum =
1014 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1015 ARRAY_SIZE(twl4030_rampdelay_texts),
1016 twl4030_rampdelay_texts);
1017
376f7839
PU		 1018/* Vibra H-bridge direction mode */
1019static const char *twl4030_vibradirmode_texts[] = {
1020 "Vibra H-bridge direction", "Audio data MSB",
1021};
1022
1023static const struct soc_enum twl4030_vibradirmode_enum =
1024 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1025 ARRAY_SIZE(twl4030_vibradirmode_texts),
1026 twl4030_vibradirmode_texts);
1027
1028/* Vibra H-bridge direction */
1029static const char *twl4030_vibradir_texts[] = {
1030 "Positive polarity", "Negative polarity",
1031};
1032
1033static const struct soc_enum twl4030_vibradir_enum =
1034 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1035 ARRAY_SIZE(twl4030_vibradir_texts),
1036 twl4030_vibradir_texts);
1037
cc17557e 1038static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1039 /* Codec operation mode control */
1040 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1041 snd_soc_get_enum_double,
1042 snd_soc_put_twl4030_opmode_enum_double),
1043
d889a72c
PU		 1044 /* Common playback gain controls */
1045 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1046 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1047 0, 0x3f, 0, digital_fine_tlv),
1048 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1049 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1050 0, 0x3f, 0, digital_fine_tlv),
1051
1052 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1053 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1054 6, 0x2, 0, digital_coarse_tlv),
1055 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1056 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1057 6, 0x2, 0, digital_coarse_tlv),
1058
1059 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1060 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1061 3, 0x12, 1, analog_tlv),
1062 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1063 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1064 3, 0x12, 1, analog_tlv),
44c55870
PU		 1065 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1066 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1067 1, 1, 0),
1068 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1069 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1070 1, 1, 0),
381a22b5 1071
1a787e7a
JS		 1072 /* Common voice downlink gain controls */
1073 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1074 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1075
1076 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1077 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1078
1079 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1080 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1081
4290239c
PU		 1082 /* Separate output gain controls */
1083 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1084 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1085 4, 3, 0, output_tvl),
1086
1087 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1088 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1089
1090 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1091 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1092 4, 3, 0, output_tvl),
1093
1094 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1095 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1096
381a22b5 1097 /* Common capture gain controls */
276c6222 1098 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1099 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1100 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1101 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1102 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1103 0, 0x1f, 0, digital_capture_tlv),
5920b453 1104
276c6222 1105 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1106 0, 3, 5, 0, input_gain_tlv),
89492be8
PU		 1107
1108 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1109
1110 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1111 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
cc17557e
SS		 1112};
1113
cc17557e 1114static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1115 /* Left channel inputs */
1116 SND_SOC_DAPM_INPUT("MAINMIC"),
1117 SND_SOC_DAPM_INPUT("HSMIC"),
1118 SND_SOC_DAPM_INPUT("AUXL"),
1119 SND_SOC_DAPM_INPUT("CARKITMIC"),
1120 /* Right channel inputs */
1121 SND_SOC_DAPM_INPUT("SUBMIC"),
1122 SND_SOC_DAPM_INPUT("AUXR"),
1123 /* Digital microphones (Stereo) */
1124 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1125 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1126
1127 /* Outputs */
cc17557e
SS		 1128 SND_SOC_DAPM_OUTPUT("OUTL"),
1129 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 1130 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1131 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1132 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1133 SND_SOC_DAPM_OUTPUT("HSOL"),
1134 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1135 SND_SOC_DAPM_OUTPUT("CARKITL"),
1136 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1137 SND_SOC_DAPM_OUTPUT("HFL"),
1138 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1139 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1140
53b5047d 1141 /* DACs */
b4852b79 1142 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1143 SND_SOC_NOPM, 0, 0),
b4852b79 1144 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1145 SND_SOC_NOPM, 0, 0),
b4852b79 1146 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1147 SND_SOC_NOPM, 0, 0),
b4852b79 1148 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1149 SND_SOC_NOPM, 0, 0),
1a787e7a 1150 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1151 SND_SOC_NOPM, 0, 0),
cc17557e 1152
7393958f
PU		 1153 /* Analog bypasses */
1154 SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1155 &twl4030_dapm_abypassr1_control, bypass_event,
1156 SND_SOC_DAPM_POST_REG),
1157 SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1158 &twl4030_dapm_abypassl1_control,
1159 bypass_event, SND_SOC_DAPM_POST_REG),
1160 SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1161 &twl4030_dapm_abypassr2_control,
1162 bypass_event, SND_SOC_DAPM_POST_REG),
1163 SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1164 &twl4030_dapm_abypassl2_control,
1165 bypass_event, SND_SOC_DAPM_POST_REG),
fcd274a3
LCM		 1166 SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1167 &twl4030_dapm_abypassv_control,
1168 bypass_event, SND_SOC_DAPM_POST_REG),
7393958f 1169
6bab83fd
PU		 1170 /* Digital bypasses */
1171 SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1172 &twl4030_dapm_dbypassl_control, bypass_event,
1173 SND_SOC_DAPM_POST_REG),
1174 SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1175 &twl4030_dapm_dbypassr_control, bypass_event,
1176 SND_SOC_DAPM_POST_REG),
ee8f6894
LCM		 1177 SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1178 &twl4030_dapm_dbypassv_control, bypass_event,
1179 SND_SOC_DAPM_POST_REG),
6bab83fd 1180
4005d39a
PU		 1181 /* Digital mixers, power control for the physical DACs */
1182 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1183 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1184 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1185 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1186 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1187 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1188 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1189 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1190 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1191 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1192
1193 /* Analog mixers, power control for the physical PGAs */
1194 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1195 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1196 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1197 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1198 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1199 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1200 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1201 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1202 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1203 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1204
1a787e7a 1205 /* Output MIXER controls */
5e98a464 1206 /* Earpiece */
1a787e7a
JS		 1207 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1208 &twl4030_dapm_earpiece_controls[0],
1209 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
2a6f5c58 1210 /* PreDrivL/R */
1a787e7a
JS		 1211 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1212 &twl4030_dapm_predrivel_controls[0],
1213 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1214 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1215 &twl4030_dapm_predriver_controls[0],
1216 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
dfad21a2 1217 /* HeadsetL/R */
6943c92e 1218 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1219 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1220 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1221 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1222 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1223 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1224 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1225 &twl4030_dapm_hsor_controls[0],
1226 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1227 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1228 0, 0, NULL, 0, headsetrpga_event,
1229 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1230 /* CarkitL/R */
1a787e7a
JS		 1231 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1232 &twl4030_dapm_carkitl_controls[0],
1233 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1234 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1235 &twl4030_dapm_carkitr_controls[0],
1236 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1237
1238 /* Output MUX controls */
df339804 1239 /* HandsfreeL/R */
5a2e9a48
PU		 1240 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1241 &twl4030_dapm_handsfreel_control),
0f89bdca
PU		 1242 SND_SOC_DAPM_SWITCH("HandsfreeL Switch", SND_SOC_NOPM, 0, 0,
1243 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1244 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1245 0, 0, NULL, 0, handsfreelpga_event,
1246 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1247 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1248 &twl4030_dapm_handsfreer_control),
0f89bdca
PU		 1249 SND_SOC_DAPM_SWITCH("HandsfreeR Switch", SND_SOC_NOPM, 0, 0,
1250 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1251 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1252 0, 0, NULL, 0, handsfreerpga_event,
1253 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839
PU		 1254 /* Vibra */
1255 SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1256 &twl4030_dapm_vibra_control),
1257 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1258 &twl4030_dapm_vibrapath_control),
5e98a464 1259
276c6222
PU		 1260 /* Introducing four virtual ADC, since TWL4030 have four channel for
1261 capture */
1262 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1263 SND_SOC_NOPM, 0, 0),
1264 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1265 SND_SOC_NOPM, 0, 0),
1266 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1267 SND_SOC_NOPM, 0, 0),
1268 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1269 SND_SOC_NOPM, 0, 0),
1270
1271 /* Analog/Digital mic path selection.
1272 TX1 Left/Right: either analog Left/Right or Digimic0
1273 TX2 Left/Right: either analog Left/Right or Digimic1 */
1274 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1275 &twl4030_dapm_micpathtx1_control, micpath_event,
1276 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1277 SND_SOC_DAPM_POST_REG),
1278 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1279 &twl4030_dapm_micpathtx2_control, micpath_event,
1280 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
1281 SND_SOC_DAPM_POST_REG),
1282
97b8096d
JS		 1283 /* Analog input mixers for the capture amplifiers */
1284 SND_SOC_DAPM_MIXER("Analog Left Capture Route",
1285 TWL4030_REG_ANAMICL, 4, 0,
1286 &twl4030_dapm_analoglmic_controls[0],
1287 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1288 SND_SOC_DAPM_MIXER("Analog Right Capture Route",
1289 TWL4030_REG_ANAMICR, 4, 0,
1290 &twl4030_dapm_analogrmic_controls[0],
1291 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1292
fb2a2f84
PU		 1293 SND_SOC_DAPM_PGA("ADC Physical Left",
1294 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1295 SND_SOC_DAPM_PGA("ADC Physical Right",
1296 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222
PU		 1297
1298 SND_SOC_DAPM_PGA("Digimic0 Enable",
1299 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
1300 SND_SOC_DAPM_PGA("Digimic1 Enable",
1301 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
1302
1303 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1304 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1305 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1306
cc17557e
SS		 1307};
1308
1309static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1310 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1311 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1312 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1313 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1314 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1315
1316 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1317 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1318 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1319 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1320 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1321
5e98a464
PU		 1322 /* Internal playback routings */
1323 /* Earpiece */
4005d39a
PU		 1324 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1325 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1326 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1327 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
2a6f5c58 1328 /* PreDrivL */
4005d39a
PU		 1329 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1330 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1331 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1332 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
2a6f5c58 1333 /* PreDrivR */
4005d39a
PU		 1334 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1335 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1336 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1337 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
dfad21a2 1338 /* HeadsetL */
4005d39a
PU		 1339 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1340 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1341 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1342 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1343 /* HeadsetR */
4005d39a
PU		 1344 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1345 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1346 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1347 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1348 /* CarkitL */
4005d39a
PU		 1349 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1350 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1351 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
5152d8c2 1352 /* CarkitR */
4005d39a
PU		 1353 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1354 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1355 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
df339804 1356 /* HandsfreeL */
4005d39a
PU		 1357 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1358 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1359 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1360 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
0f89bdca
PU		 1361 {"HandsfreeL Switch", "Switch", "HandsfreeL Mux"},
1362 {"HandsfreeL PGA", NULL, "HandsfreeL Switch"},
df339804 1363 /* HandsfreeR */
4005d39a
PU		 1364 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1365 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1366 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1367 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
0f89bdca
PU		 1368 {"HandsfreeR Switch", "Switch", "HandsfreeR Mux"},
1369 {"HandsfreeR PGA", NULL, "HandsfreeR Switch"},
376f7839
PU		 1370 /* Vibra */
1371 {"Vibra Mux", "AudioL1", "DAC Left1"},
1372 {"Vibra Mux", "AudioR1", "DAC Right1"},
1373 {"Vibra Mux", "AudioL2", "DAC Left2"},
1374 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1375
cc17557e 1376 /* outputs */
4005d39a
PU		 1377 {"OUTL", NULL, "Analog L2 Playback Mixer"},
1378 {"OUTR", NULL, "Analog R2 Playback Mixer"},
1a787e7a
JS		 1379 {"EARPIECE", NULL, "Earpiece Mixer"},
1380 {"PREDRIVEL", NULL, "PredriveL Mixer"},
1381 {"PREDRIVER", NULL, "PredriveR Mixer"},
6943c92e
PU		 1382 {"HSOL", NULL, "HeadsetL PGA"},
1383 {"HSOR", NULL, "HeadsetR PGA"},
1a787e7a
JS		 1384 {"CARKITL", NULL, "CarkitL Mixer"},
1385 {"CARKITR", NULL, "CarkitR Mixer"},
5a2e9a48
PU		 1386 {"HFL", NULL, "HandsfreeL PGA"},
1387 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1388 {"Vibra Route", "Audio", "Vibra Mux"},
1389 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1390
276c6222
PU		 1391 /* Capture path */
1392 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
1393 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
1394 {"Analog Left Capture Route", "AUXL", "AUXL"},
1395 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
1396
1397 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
1398 {"Analog Right Capture Route", "AUXR", "AUXR"},
1399
fb2a2f84
PU		 1400 {"ADC Physical Left", NULL, "Analog Left Capture Route"},
1401 {"ADC Physical Right", NULL, "Analog Right Capture Route"},
276c6222
PU		 1402
1403 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1404 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1405
1406 /* TX1 Left capture path */
fb2a2f84 1407 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1408 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1409 /* TX1 Right capture path */
fb2a2f84 1410 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1411 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1412 /* TX2 Left capture path */
fb2a2f84 1413 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1414 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1415 /* TX2 Right capture path */
fb2a2f84 1416 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1417 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1418
1419 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1420 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1421 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1422 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1423
7393958f
PU		 1424 /* Analog bypass routes */
1425 {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
1426 {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
1427 {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
1428 {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
fcd274a3 1429 {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
7393958f
PU		 1430
1431 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1432 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1433 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1434 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1435 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1436
6bab83fd
PU		 1437 /* Digital bypass routes */
1438 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1439 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1440 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1441
4005d39a
PU		 1442 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1443 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1444 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1445
cc17557e
SS		 1446};
1447
1448static int twl4030_add_widgets(struct snd_soc_codec *codec)
1449{
1450 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1451 ARRAY_SIZE(twl4030_dapm_widgets));
1452
1453 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1454
1455 snd_soc_dapm_new_widgets(codec);
1456 return 0;
1457}
1458
cc17557e
SS		 1459static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1460 enum snd_soc_bias_level level)
1461{
7393958f
PU		 1462 struct twl4030_priv *twl4030 = codec->private_data;
1463
cc17557e
SS		 1464 switch (level) {
1465 case SND_SOC_BIAS_ON:
7393958f 1466 twl4030_codec_mute(codec, 0);
cc17557e
SS		 1467 break;
1468 case SND_SOC_BIAS_PREPARE:
7393958f
PU		 1469 twl4030_power_up(codec);
1470 if (twl4030->bypass_state)
1471 twl4030_codec_mute(codec, 0);
1472 else
1473 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1474 break;
1475 case SND_SOC_BIAS_STANDBY:
7393958f
PU		 1476 twl4030_power_up(codec);
1477 if (twl4030->bypass_state)
1478 twl4030_codec_mute(codec, 0);
1479 else
1480 twl4030_codec_mute(codec, 1);
cc17557e
SS		 1481 break;
1482 case SND_SOC_BIAS_OFF:
1483 twl4030_power_down(codec);
1484 break;
1485 }
1486 codec->bias_level = level;
1487
1488 return 0;
1489}
1490
6b87a91f
PU		 1491static void twl4030_constraints(struct twl4030_priv *twl4030,
1492 struct snd_pcm_substream *mst_substream)
1493{
1494 struct snd_pcm_substream *slv_substream;
1495
1496 /* Pick the stream, which need to be constrained */
1497 if (mst_substream == twl4030->master_substream)
1498 slv_substream = twl4030->slave_substream;
1499 else if (mst_substream == twl4030->slave_substream)
1500 slv_substream = twl4030->master_substream;
1501 else /* This should not happen.. */
1502 return;
1503
1504 /* Set the constraints according to the already configured stream */
1505 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1506 SNDRV_PCM_HW_PARAM_RATE,
1507 twl4030->rate,
1508 twl4030->rate);
1509
1510 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1511 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1512 twl4030->sample_bits,
1513 twl4030->sample_bits);
1514
1515 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1516 SNDRV_PCM_HW_PARAM_CHANNELS,
1517 twl4030->channels,
1518 twl4030->channels);
1519}
1520
8a1f936a
PU		 1521/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1522 * capture has to be enabled/disabled. */
1523static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1524 int enable)
1525{
1526 u8 reg, mask;
1527
1528 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1529
1530 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1531 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1532 else
1533 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1534
1535 if (enable)
1536 reg |= mask;
1537 else
1538 reg &= ~mask;
1539
1540 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1541}
1542
d6648da1
PU		 1543static int twl4030_startup(struct snd_pcm_substream *substream,
1544 struct snd_soc_dai *dai)
7220b9f4
PU		 1545{
1546 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1547 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1548 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1549 struct twl4030_priv *twl4030 = codec->private_data;
1550
7220b9f4 1551 if (twl4030->master_substream) {
7220b9f4 1552 twl4030->slave_substream = substream;
6b87a91f
PU		 1553 /* The DAI has one configuration for playback and capture, so
1554 * if the DAI has been already configured then constrain this
1555 * substream to match it. */
1556 if (twl4030->configured)
1557 twl4030_constraints(twl4030, twl4030->master_substream);
1558 } else {
8a1f936a
PU		 1559 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1560 TWL4030_OPTION_1)) {
1561 /* In option2 4 channel is not supported, set the
1562 * constraint for the first stream for channels, the
1563 * second stream will 'inherit' this cosntraint */
1564 snd_pcm_hw_constraint_minmax(substream->runtime,
1565 SNDRV_PCM_HW_PARAM_CHANNELS,
1566 2, 2);
1567 }
7220b9f4 1568 twl4030->master_substream = substream;
6b87a91f 1569 }
7220b9f4
PU		 1570
1571 return 0;
1572}
1573
d6648da1
PU		 1574static void twl4030_shutdown(struct snd_pcm_substream *substream,
1575 struct snd_soc_dai *dai)
7220b9f4
PU		 1576{
1577 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1578 struct snd_soc_device *socdev = rtd->socdev;
d6648da1 1579 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4
PU		 1580 struct twl4030_priv *twl4030 = codec->private_data;
1581
1582 if (twl4030->master_substream == substream)
1583 twl4030->master_substream = twl4030->slave_substream;
1584
1585 twl4030->slave_substream = NULL;
6b87a91f
PU		 1586
1587 /* If all streams are closed, or the remaining stream has not yet
1588 * been configured than set the DAI as not configured. */
1589 if (!twl4030->master_substream)
1590 twl4030->configured = 0;
1591 else if (!twl4030->master_substream->runtime->channels)
1592 twl4030->configured = 0;
8a1f936a
PU		 1593
1594 /* If the closing substream had 4 channel, do the necessary cleanup */
1595 if (substream->runtime->channels == 4)
1596 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1597}
1598
cc17557e 1599static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1600 struct snd_pcm_hw_params *params,
1601 struct snd_soc_dai *dai)
cc17557e
SS		 1602{
1603 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1604 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1605 struct snd_soc_codec *codec = socdev->card->codec;
7220b9f4 1606 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1607 u8 mode, old_mode, format, old_format;
1608
8a1f936a
PU		 1609 /* If the substream has 4 channel, do the necessary setup */
1610 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1611 u8 format, mode;
1612
1613 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1614 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1615
1616 /* Safety check: are we in the correct operating mode and
1617 * the interface is in TDM mode? */
1618 if ((mode & TWL4030_OPTION_1) &&
1619 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1620 twl4030_tdm_enable(codec, substream->stream, 1);
1621 else
1622 return -EINVAL;
1623 }
1624
6b87a91f
PU		 1625 if (twl4030->configured)
1626 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1627 return 0;
1628
cc17557e
SS		 1629 /* bit rate */
1630 old_mode = twl4030_read_reg_cache(codec,
1631 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1632 mode = old_mode & ~TWL4030_APLL_RATE;
1633
1634 switch (params_rate(params)) {
1635 case 8000:
1636 mode |= TWL4030_APLL_RATE_8000;
1637 break;
1638 case 11025:
1639 mode |= TWL4030_APLL_RATE_11025;
1640 break;
1641 case 12000:
1642 mode |= TWL4030_APLL_RATE_12000;
1643 break;
1644 case 16000:
1645 mode |= TWL4030_APLL_RATE_16000;
1646 break;
1647 case 22050:
1648 mode |= TWL4030_APLL_RATE_22050;
1649 break;
1650 case 24000:
1651 mode |= TWL4030_APLL_RATE_24000;
1652 break;
1653 case 32000:
1654 mode |= TWL4030_APLL_RATE_32000;
1655 break;
1656 case 44100:
1657 mode |= TWL4030_APLL_RATE_44100;
1658 break;
1659 case 48000:
1660 mode |= TWL4030_APLL_RATE_48000;
1661 break;
103f211d
PU		 1662 case 96000:
1663 mode |= TWL4030_APLL_RATE_96000;
1664 break;
cc17557e
SS		 1665 default:
1666 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1667 params_rate(params));
1668 return -EINVAL;
1669 }
1670
1671 if (mode != old_mode) {
1672 /* change rate and set CODECPDZ */
7393958f 1673 twl4030_codec_enable(codec, 0);
cc17557e 1674 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1675 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1676 }
1677
1678 /* sample size */
1679 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1680 format = old_format;
1681 format &= ~TWL4030_DATA_WIDTH;
1682 switch (params_format(params)) {
1683 case SNDRV_PCM_FORMAT_S16_LE:
1684 format |= TWL4030_DATA_WIDTH_16S_16W;
1685 break;
1686 case SNDRV_PCM_FORMAT_S24_LE:
1687 format |= TWL4030_DATA_WIDTH_32S_24W;
1688 break;
1689 default:
1690 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1691 params_format(params));
1692 return -EINVAL;
1693 }
1694
1695 if (format != old_format) {
1696
1697 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1698 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1699
1700 /* change format */
1701 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1702
1703 /* set CODECPDZ afterwards */
db04e2c5 1704 twl4030_codec_enable(codec, 1);
cc17557e 1705 }
6b87a91f
PU		 1706
1707 /* Store the important parameters for the DAI configuration and set
1708 * the DAI as configured */
1709 twl4030->configured = 1;
1710 twl4030->rate = params_rate(params);
1711 twl4030->sample_bits = hw_param_interval(params,
1712 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1713 twl4030->channels = params_channels(params);
1714
1715 /* If both playback and capture streams are open, and one of them
1716 * is setting the hw parameters right now (since we are here), set
1717 * constraints to the other stream to match the current one. */
1718 if (twl4030->slave_substream)
1719 twl4030_constraints(twl4030, substream);
1720
cc17557e
SS		 1721 return 0;
1722}
1723
1724static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1725 int clk_id, unsigned int freq, int dir)
1726{
1727 struct snd_soc_codec *codec = codec_dai->codec;
6943c92e 1728 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 1729 u8 infreq;
1730
1731 switch (freq) {
1732 case 19200000:
1733 infreq = TWL4030_APLL_INFREQ_19200KHZ;
6943c92e 1734 twl4030->sysclk = 19200;
cc17557e
SS		 1735 break;
1736 case 26000000:
1737 infreq = TWL4030_APLL_INFREQ_26000KHZ;
6943c92e 1738 twl4030->sysclk = 26000;
cc17557e
SS		 1739 break;
1740 case 38400000:
1741 infreq = TWL4030_APLL_INFREQ_38400KHZ;
6943c92e 1742 twl4030->sysclk = 38400;
cc17557e
SS		 1743 break;
1744 default:
1745 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1746 freq);
1747 return -EINVAL;
1748 }
1749
1750 infreq |= TWL4030_APLL_EN;
1751 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1752
1753 return 0;
1754}
1755
1756static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1757 unsigned int fmt)
1758{
1759 struct snd_soc_codec *codec = codec_dai->codec;
1760 u8 old_format, format;
1761
1762 /* get format */
1763 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1764 format = old_format;
1765
1766 /* set master/slave audio interface */
1767 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1768 case SND_SOC_DAIFMT_CBM_CFM:
1769 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1770 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1771 break;
1772 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1773 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1774 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1775 break;
1776 default:
1777 return -EINVAL;
1778 }
1779
1780 /* interface format */
1781 format &= ~TWL4030_AIF_FORMAT;
1782 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1783 case SND_SOC_DAIFMT_I2S:
1784 format |= TWL4030_AIF_FORMAT_CODEC;
1785 break;
8a1f936a
PU		 1786 case SND_SOC_DAIFMT_DSP_A:
1787 format |= TWL4030_AIF_FORMAT_TDM;
1788 break;
cc17557e
SS		 1789 default:
1790 return -EINVAL;
1791 }
1792
1793 if (format != old_format) {
1794
1795 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1796 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1797
1798 /* change format */
1799 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1800
1801 /* set CODECPDZ afterwards */
db04e2c5 1802 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1803 }
1804
1805 return 0;
1806}
1807
b7a755a8
MLC		 1808/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1809 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1810static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1811 int enable)
1812{
1813 u8 reg, mask;
1814
1815 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1816
1817 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1818 mask = TWL4030_ARXL1_VRX_EN;
1819 else
1820 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1821
1822 if (enable)
1823 reg |= mask;
1824 else
1825 reg &= ~mask;
1826
1827 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1828}
1829
7154b3e8
JS		 1830static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1831 struct snd_soc_dai *dai)
1832{
1833 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1834 struct snd_soc_device *socdev = rtd->socdev;
1835 struct snd_soc_codec *codec = socdev->card->codec;
1836 u8 infreq;
1837 u8 mode;
1838
1839 /* If the system master clock is not 26MHz, the voice PCM interface is
1840 * not avilable.
1841 */
1842 infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
1843 & TWL4030_APLL_INFREQ;
1844
1845 if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
1846 printk(KERN_ERR "TWL4030 voice startup: "
1847 "MCLK is not 26MHz, call set_sysclk() on init\n");
1848 return -EINVAL;
1849 }
1850
1851 /* If the codec mode is not option2, the voice PCM interface is not
1852 * avilable.
1853 */
1854 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1855 & TWL4030_OPT_MODE;
1856
1857 if (mode != TWL4030_OPTION_2) {
1858 printk(KERN_ERR "TWL4030 voice startup: "
1859 "the codec mode is not option2\n");
1860 return -EINVAL;
1861 }
1862
1863 return 0;
1864}
1865
b7a755a8
MLC		 1866static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
1867 struct snd_soc_dai *dai)
1868{
1869 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1870 struct snd_soc_device *socdev = rtd->socdev;
1871 struct snd_soc_codec *codec = socdev->card->codec;
1872
1873 /* Enable voice digital filters */
1874 twl4030_voice_enable(codec, substream->stream, 0);
1875}
1876
7154b3e8
JS		 1877static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
1878 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1879{
1880 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1881 struct snd_soc_device *socdev = rtd->socdev;
1882 struct snd_soc_codec *codec = socdev->card->codec;
1883 u8 old_mode, mode;
1884
b7a755a8
MLC		 1885 /* Enable voice digital filters */
1886 twl4030_voice_enable(codec, substream->stream, 1);
1887
7154b3e8
JS		 1888 /* bit rate */
1889 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
1890 & ~(TWL4030_CODECPDZ);
1891 mode = old_mode;
1892
1893 switch (params_rate(params)) {
1894 case 8000:
1895 mode &= ~(TWL4030_SEL_16K);
1896 break;
1897 case 16000:
1898 mode |= TWL4030_SEL_16K;
1899 break;
1900 default:
1901 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
1902 params_rate(params));
1903 return -EINVAL;
1904 }
1905
1906 if (mode != old_mode) {
1907 /* change rate and set CODECPDZ */
1908 twl4030_codec_enable(codec, 0);
1909 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1910 twl4030_codec_enable(codec, 1);
1911 }
1912
1913 return 0;
1914}
1915
1916static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1917 int clk_id, unsigned int freq, int dir)
1918{
1919 struct snd_soc_codec *codec = codec_dai->codec;
1920 u8 infreq;
1921
1922 switch (freq) {
1923 case 26000000:
1924 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1925 break;
1926 default:
1927 printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
1928 freq);
1929 return -EINVAL;
1930 }
1931
1932 infreq |= TWL4030_APLL_EN;
1933 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1934
1935 return 0;
1936}
1937
1938static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1939 unsigned int fmt)
1940{
1941 struct snd_soc_codec *codec = codec_dai->codec;
1942 u8 old_format, format;
1943
1944 /* get format */
1945 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
1946 format = old_format;
1947
1948 /* set master/slave audio interface */
1949 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1950 case SND_SOC_DAIFMT_CBS_CFM:
1951 format &= ~(TWL4030_VIF_SLAVE_EN);
1952 break;
1953 case SND_SOC_DAIFMT_CBS_CFS:
1954 format |= TWL4030_VIF_SLAVE_EN;
1955 break;
1956 default:
1957 return -EINVAL;
1958 }
1959
1960 /* clock inversion */
1961 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1962 case SND_SOC_DAIFMT_IB_NF:
1963 format &= ~(TWL4030_VIF_FORMAT);
1964 break;
1965 case SND_SOC_DAIFMT_NB_IF:
1966 format |= TWL4030_VIF_FORMAT;
1967 break;
1968 default:
1969 return -EINVAL;
1970 }
1971
1972 if (format != old_format) {
1973 /* change format and set CODECPDZ */
1974 twl4030_codec_enable(codec, 0);
1975 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
1976 twl4030_codec_enable(codec, 1);
1977 }
1978
1979 return 0;
1980}
1981
bbba9444 1982#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1983#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1984
10d9e3d9 1985static struct snd_soc_dai_ops twl4030_dai_ops = {
7220b9f4
PU		 1986 .startup = twl4030_startup,
1987 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 1988 .hw_params = twl4030_hw_params,
1989 .set_sysclk = twl4030_set_dai_sysclk,
1990 .set_fmt = twl4030_set_dai_fmt,
1991};
1992
7154b3e8
JS		 1993static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
1994 .startup = twl4030_voice_startup,
b7a755a8 1995 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 1996 .hw_params = twl4030_voice_hw_params,
1997 .set_sysclk = twl4030_voice_set_dai_sysclk,
1998 .set_fmt = twl4030_voice_set_dai_fmt,
1999};
2000
2001struct snd_soc_dai twl4030_dai[] = {
2002{
cc17557e
SS		 2003 .name = "twl4030",
2004 .playback = {
b4852b79 2005 .stream_name = "HiFi Playback",
cc17557e 2006 .channels_min = 2,
8a1f936a 2007 .channels_max = 4,
31ad0f31 2008 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2009 .formats = TWL4030_FORMATS,},
2010 .capture = {
2011 .stream_name = "Capture",
2012 .channels_min = 2,
8a1f936a 2013 .channels_max = 4,
cc17557e
SS		 2014 .rates = TWL4030_RATES,
2015 .formats = TWL4030_FORMATS,},
10d9e3d9 2016 .ops = &twl4030_dai_ops,
7154b3e8
JS		 2017},
2018{
2019 .name = "twl4030 Voice",
2020 .playback = {
b4852b79 2021 .stream_name = "Voice Playback",
7154b3e8
JS		 2022 .channels_min = 1,
2023 .channels_max = 1,
2024 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2025 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2026 .capture = {
2027 .stream_name = "Capture",
2028 .channels_min = 1,
2029 .channels_max = 2,
2030 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2031 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2032 .ops = &twl4030_dai_voice_ops,
2033},
cc17557e
SS		 2034};
2035EXPORT_SYMBOL_GPL(twl4030_dai);
2036
2037static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
2038{
2039 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2040 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2041
2042 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2043
2044 return 0;
2045}
2046
2047static int twl4030_resume(struct platform_device *pdev)
2048{
2049 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2050 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2051
2052 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2053 twl4030_set_bias_level(codec, codec->suspend_bias_level);
2054 return 0;
2055}
2056
2057/*
2058 * initialize the driver
2059 * register the mixer and dsp interfaces with the kernel
2060 */
2061
2062static int twl4030_init(struct snd_soc_device *socdev)
2063{
6627a653 2064 struct snd_soc_codec *codec = socdev->card->codec;
9da28c7b
PU		 2065 struct twl4030_setup_data *setup = socdev->codec_data;
2066 struct twl4030_priv *twl4030 = codec->private_data;
cc17557e
SS		 2067 int ret = 0;
2068
2069 printk(KERN_INFO "TWL4030 Audio Codec init \n");
2070
2071 codec->name = "twl4030";
2072 codec->owner = THIS_MODULE;
2073 codec->read = twl4030_read_reg_cache;
2074 codec->write = twl4030_write;
2075 codec->set_bias_level = twl4030_set_bias_level;
7154b3e8
JS		 2076 codec->dai = twl4030_dai;
2077 codec->num_dai = ARRAY_SIZE(twl4030_dai),
cc17557e
SS		 2078 codec->reg_cache_size = sizeof(twl4030_reg);
2079 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
2080 GFP_KERNEL);
2081 if (codec->reg_cache == NULL)
2082 return -ENOMEM;
2083
9da28c7b
PU		 2084 /* Configuration for headset ramp delay from setup data */
2085 if (setup) {
2086 unsigned char hs_pop;
2087
2088 if (setup->sysclk)
2089 twl4030->sysclk = setup->sysclk;
2090 else
2091 twl4030->sysclk = 26000;
2092
2093 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
2094 hs_pop &= ~TWL4030_RAMP_DELAY;
2095 hs_pop |= (setup->ramp_delay_value << 2);
2096 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
2097 } else {
2098 twl4030->sysclk = 26000;
2099 }
2100
cc17557e
SS		 2101 /* register pcms */
2102 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
2103 if (ret < 0) {
2104 printk(KERN_ERR "twl4030: failed to create pcms\n");
2105 goto pcm_err;
2106 }
2107
2108 twl4030_init_chip(codec);
2109
2110 /* power on device */
2111 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2112
3e8e1952
IM		 2113 snd_soc_add_controls(codec, twl4030_snd_controls,
2114 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 2115 twl4030_add_widgets(codec);
2116
968a6025 2117 ret = snd_soc_init_card(socdev);
cc17557e
SS		 2118 if (ret < 0) {
2119 printk(KERN_ERR "twl4030: failed to register card\n");
2120 goto card_err;
2121 }
2122
2123 return ret;
2124
2125card_err:
2126 snd_soc_free_pcms(socdev);
2127 snd_soc_dapm_free(socdev);
2128pcm_err:
2129 kfree(codec->reg_cache);
2130 return ret;
2131}
2132
2133static struct snd_soc_device *twl4030_socdev;
2134
2135static int twl4030_probe(struct platform_device *pdev)
2136{
2137 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
2138 struct snd_soc_codec *codec;
7393958f 2139 struct twl4030_priv *twl4030;
cc17557e
SS		 2140
2141 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
2142 if (codec == NULL)
2143 return -ENOMEM;
2144
7393958f
PU		 2145 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2146 if (twl4030 == NULL) {
2147 kfree(codec);
2148 return -ENOMEM;
2149 }
2150
2151 codec->private_data = twl4030;
6627a653 2152 socdev->card->codec = codec;
cc17557e
SS		 2153 mutex_init(&codec->mutex);
2154 INIT_LIST_HEAD(&codec->dapm_widgets);
2155 INIT_LIST_HEAD(&codec->dapm_paths);
2156
2157 twl4030_socdev = socdev;
2158 twl4030_init(socdev);
2159
2160 return 0;
2161}
2162
2163static int twl4030_remove(struct platform_device *pdev)
2164{
2165 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 2166 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 2167
2168 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
7393958f 2169 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
c6d1662b
PU		 2170 snd_soc_free_pcms(socdev);
2171 snd_soc_dapm_free(socdev);
7393958f 2172 kfree(codec->private_data);
cc17557e
SS		 2173 kfree(codec);
2174
2175 return 0;
2176}
2177
2178struct snd_soc_codec_device soc_codec_dev_twl4030 = {
2179 .probe = twl4030_probe,
2180 .remove = twl4030_remove,
2181 .suspend = twl4030_suspend,
2182 .resume = twl4030_resume,
2183};
2184EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
2185
24e07db8 2186static int __init twl4030_modinit(void)
64089b84 2187{
7154b3e8 2188 return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84 2189}
24e07db8 2190module_init(twl4030_modinit);
64089b84
MB		 2191
2192static void __exit twl4030_exit(void)
2193{
7154b3e8 2194 snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
64089b84
MB		 2195}
2196module_exit(twl4030_exit);
2197
cc17557e
SS		 2198MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2199MODULE_AUTHOR("Steve Sakoman");
2200MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)