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ASoC: TWL4030: Code clean up for codec power up and down
[linux-2.6-block.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
29#include <linux/i2c/twl4030.h>
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/initval.h>
c10b82cf 36#include <sound/tlv.h>
cc17557e
SS		 37
38#include "twl4030.h"
39
40/*
41 * twl4030 register cache & default register settings
42 */
43static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
44 0x00, /* this register not used */
db04e2c5 45 0x91, /* REG_CODEC_MODE (0x1) */
cc17557e
SS		 46 0xc3, /* REG_OPTION (0x2) */
47 0x00, /* REG_UNKNOWN (0x3) */
48 0x00, /* REG_MICBIAS_CTL (0x4) */
5920b453
GI		 49 0x20, /* REG_ANAMICL (0x5) */
50 0x00, /* REG_ANAMICR (0x6) */
51 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 52 0x00, /* REG_ADCMICSEL (0x8) */
53 0x00, /* REG_DIGMIXING (0x9) */
54 0x0c, /* REG_ATXL1PGA (0xA) */
55 0x0c, /* REG_ATXR1PGA (0xB) */
56 0x00, /* REG_AVTXL2PGA (0xC) */
57 0x00, /* REG_AVTXR2PGA (0xD) */
58 0x01, /* REG_AUDIO_IF (0xE) */
59 0x00, /* REG_VOICE_IF (0xF) */
60 0x00, /* REG_ARXR1PGA (0x10) */
61 0x00, /* REG_ARXL1PGA (0x11) */
62 0x6c, /* REG_ARXR2PGA (0x12) */
63 0x6c, /* REG_ARXL2PGA (0x13) */
64 0x00, /* REG_VRXPGA (0x14) */
65 0x00, /* REG_VSTPGA (0x15) */
66 0x00, /* REG_VRX2ARXPGA (0x16) */
67 0x0c, /* REG_AVDAC_CTL (0x17) */
68 0x00, /* REG_ARX2VTXPGA (0x18) */
69 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
70 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
71 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
72 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
73 0x00, /* REG_ATX2ARXPGA (0x1D) */
74 0x00, /* REG_BT_IF (0x1E) */
75 0x00, /* REG_BTPGA (0x1F) */
76 0x00, /* REG_BTSTPGA (0x20) */
77 0x00, /* REG_EAR_CTL (0x21) */
78 0x24, /* REG_HS_SEL (0x22) */
79 0x0a, /* REG_HS_GAIN_SET (0x23) */
80 0x00, /* REG_HS_POPN_SET (0x24) */
81 0x00, /* REG_PREDL_CTL (0x25) */
82 0x00, /* REG_PREDR_CTL (0x26) */
83 0x00, /* REG_PRECKL_CTL (0x27) */
84 0x00, /* REG_PRECKR_CTL (0x28) */
85 0x00, /* REG_HFL_CTL (0x29) */
86 0x00, /* REG_HFR_CTL (0x2A) */
87 0x00, /* REG_ALC_CTL (0x2B) */
88 0x00, /* REG_ALC_SET1 (0x2C) */
89 0x00, /* REG_ALC_SET2 (0x2D) */
90 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 91 0x00, /* REG_SOFTVOL_CTL (0x2F) */
cc17557e
SS		 92 0x00, /* REG_DTMF_FREQSEL (0x30) */
93 0x00, /* REG_DTMF_TONEXT1H (0x31) */
94 0x00, /* REG_DTMF_TONEXT1L (0x32) */
95 0x00, /* REG_DTMF_TONEXT2H (0x33) */
96 0x00, /* REG_DTMF_TONEXT2L (0x34) */
97 0x00, /* REG_DTMF_TONOFF (0x35) */
98 0x00, /* REG_DTMF_WANONOFF (0x36) */
99 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
100 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
101 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
102 0x16, /* REG_APLL_CTL (0x3A) */
103 0x00, /* REG_DTMF_CTL (0x3B) */
104 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
105 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
106 0x00, /* REG_MISC_SET_1 (0x3E) */
107 0x00, /* REG_PCMBTMUX (0x3F) */
108 0x00, /* not used (0x40) */
109 0x00, /* not used (0x41) */
110 0x00, /* not used (0x42) */
111 0x00, /* REG_RX_PATH_SEL (0x43) */
112 0x00, /* REG_VDL_APGA_CTL (0x44) */
113 0x00, /* REG_VIBRA_CTL (0x45) */
114 0x00, /* REG_VIBRA_SET (0x46) */
115 0x00, /* REG_VIBRA_PWM_SET (0x47) */
116 0x00, /* REG_ANAMIC_GAIN (0x48) */
117 0x00, /* REG_MISC_SET_2 (0x49) */
118};
119
120/*
121 * read twl4030 register cache
122 */
123static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
124 unsigned int reg)
125{
126 u8 *cache = codec->reg_cache;
127
91432e97
IM		 128 if (reg >= TWL4030_CACHEREGNUM)
129 return -EIO;
130
cc17557e
SS		 131 return cache[reg];
132}
133
134/*
135 * write twl4030 register cache
136 */
137static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
138 u8 reg, u8 value)
139{
140 u8 *cache = codec->reg_cache;
141
142 if (reg >= TWL4030_CACHEREGNUM)
143 return;
144 cache[reg] = value;
145}
146
147/*
148 * write to the twl4030 register space
149 */
150static int twl4030_write(struct snd_soc_codec *codec,
151 unsigned int reg, unsigned int value)
152{
153 twl4030_write_reg_cache(codec, reg, value);
154 return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
155}
156
db04e2c5 157static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e
SS		 158{
159 u8 mode;
160
161 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
db04e2c5
PU		 162 if (enable)
163 mode |= TWL4030_CODECPDZ;
164 else
165 mode &= ~TWL4030_CODECPDZ;
cc17557e 166
db04e2c5 167 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
cc17557e
SS		 168
169 /* REVISIT: this delay is present in TI sample drivers */
170 /* but there seems to be no TRM requirement for it */
171 udelay(10);
172}
173
174static void twl4030_init_chip(struct snd_soc_codec *codec)
175{
176 int i;
177
178 /* clear CODECPDZ prior to setting register defaults */
db04e2c5 179 twl4030_codec_enable(codec, 0);
cc17557e
SS		 180
181 /* set all audio section registers to reasonable defaults */
182 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
183 twl4030_write(codec, i, twl4030_reg[i]);
184
185}
186
5e98a464
PU		 187/* Earpiece */
188static const char *twl4030_earpiece_texts[] =
2f423577 189 {"Off", "DACL1", "DACL2", "DACR1"};
5e98a464 190
2f423577
PU		 191static const unsigned int twl4030_earpiece_values[] =
192 {0x0, 0x1, 0x2, 0x4};
193
cb1ace04 194static const struct soc_enum twl4030_earpiece_enum =
2f423577 195 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
5e98a464 196 ARRAY_SIZE(twl4030_earpiece_texts),
2f423577
PU		 197 twl4030_earpiece_texts,
198 twl4030_earpiece_values);
5e98a464
PU		 199
200static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
2f423577 201SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
5e98a464 202
2a6f5c58
PU		 203/* PreDrive Left */
204static const char *twl4030_predrivel_texts[] =
2f423577
PU		 205 {"Off", "DACL1", "DACL2", "DACR2"};
206
207static const unsigned int twl4030_predrivel_values[] =
208 {0x0, 0x1, 0x2, 0x4};
2a6f5c58 209
cb1ace04 210static const struct soc_enum twl4030_predrivel_enum =
2f423577 211 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
2a6f5c58 212 ARRAY_SIZE(twl4030_predrivel_texts),
2f423577
PU		 213 twl4030_predrivel_texts,
214 twl4030_predrivel_values);
2a6f5c58
PU		 215
216static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
2f423577 217SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
2a6f5c58
PU		 218
219/* PreDrive Right */
220static const char *twl4030_predriver_texts[] =
2f423577 221 {"Off", "DACR1", "DACR2", "DACL2"};
2a6f5c58 222
2f423577
PU		 223static const unsigned int twl4030_predriver_values[] =
224 {0x0, 0x1, 0x2, 0x4};
225
cb1ace04 226static const struct soc_enum twl4030_predriver_enum =
2f423577 227 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
2a6f5c58 228 ARRAY_SIZE(twl4030_predriver_texts),
2f423577
PU		 229 twl4030_predriver_texts,
230 twl4030_predriver_values);
2a6f5c58
PU		 231
232static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
2f423577 233SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
2a6f5c58 234
dfad21a2
PU		 235/* Headset Left */
236static const char *twl4030_hsol_texts[] =
237 {"Off", "DACL1", "DACL2"};
238
239static const struct soc_enum twl4030_hsol_enum =
240 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
241 ARRAY_SIZE(twl4030_hsol_texts),
242 twl4030_hsol_texts);
243
244static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
245SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
246
247/* Headset Right */
248static const char *twl4030_hsor_texts[] =
249 {"Off", "DACR1", "DACR2"};
250
251static const struct soc_enum twl4030_hsor_enum =
252 SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
253 ARRAY_SIZE(twl4030_hsor_texts),
254 twl4030_hsor_texts);
255
256static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
257SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
258
5152d8c2
PU		 259/* Carkit Left */
260static const char *twl4030_carkitl_texts[] =
261 {"Off", "DACL1", "DACL2"};
262
263static const struct soc_enum twl4030_carkitl_enum =
264 SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
265 ARRAY_SIZE(twl4030_carkitl_texts),
266 twl4030_carkitl_texts);
267
268static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
269SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
270
271/* Carkit Right */
272static const char *twl4030_carkitr_texts[] =
273 {"Off", "DACR1", "DACR2"};
274
275static const struct soc_enum twl4030_carkitr_enum =
276 SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
277 ARRAY_SIZE(twl4030_carkitr_texts),
278 twl4030_carkitr_texts);
279
280static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
281SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
282
df339804
PU		 283/* Handsfree Left */
284static const char *twl4030_handsfreel_texts[] =
285 {"Voice", "DACL1", "DACL2", "DACR2"};
286
287static const struct soc_enum twl4030_handsfreel_enum =
288 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
289 ARRAY_SIZE(twl4030_handsfreel_texts),
290 twl4030_handsfreel_texts);
291
292static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
293SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
294
295/* Handsfree Right */
296static const char *twl4030_handsfreer_texts[] =
297 {"Voice", "DACR1", "DACR2", "DACL2"};
298
299static const struct soc_enum twl4030_handsfreer_enum =
300 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
301 ARRAY_SIZE(twl4030_handsfreer_texts),
302 twl4030_handsfreer_texts);
303
304static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
305SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
306
276c6222
PU		 307/* Left analog microphone selection */
308static const char *twl4030_analoglmic_texts[] =
2f423577
PU		 309 {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
310
311static const unsigned int twl4030_analoglmic_values[] =
312 {0x0, 0x1, 0x2, 0x4, 0x8};
276c6222 313
cb1ace04 314static const struct soc_enum twl4030_analoglmic_enum =
2f423577 315 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
276c6222 316 ARRAY_SIZE(twl4030_analoglmic_texts),
2f423577
PU		 317 twl4030_analoglmic_texts,
318 twl4030_analoglmic_values);
276c6222
PU		 319
320static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
2f423577 321SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
276c6222
PU		 322
323/* Right analog microphone selection */
324static const char *twl4030_analogrmic_texts[] =
2f423577 325 {"Off", "Sub mic", "AUXR"};
276c6222 326
2f423577
PU		 327static const unsigned int twl4030_analogrmic_values[] =
328 {0x0, 0x1, 0x4};
329
cb1ace04 330static const struct soc_enum twl4030_analogrmic_enum =
2f423577 331 SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
276c6222 332 ARRAY_SIZE(twl4030_analogrmic_texts),
2f423577
PU		 333 twl4030_analogrmic_texts,
334 twl4030_analogrmic_values);
276c6222
PU		 335
336static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
2f423577 337SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
276c6222
PU		 338
339/* TX1 L/R Analog/Digital microphone selection */
340static const char *twl4030_micpathtx1_texts[] =
341 {"Analog", "Digimic0"};
342
343static const struct soc_enum twl4030_micpathtx1_enum =
344 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
345 ARRAY_SIZE(twl4030_micpathtx1_texts),
346 twl4030_micpathtx1_texts);
347
348static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
349SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
350
351/* TX2 L/R Analog/Digital microphone selection */
352static const char *twl4030_micpathtx2_texts[] =
353 {"Analog", "Digimic1"};
354
355static const struct soc_enum twl4030_micpathtx2_enum =
356 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
357 ARRAY_SIZE(twl4030_micpathtx2_texts),
358 twl4030_micpathtx2_texts);
359
360static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
361SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
362
276c6222
PU		 363static int micpath_event(struct snd_soc_dapm_widget *w,
364 struct snd_kcontrol *kcontrol, int event)
365{
366 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
367 unsigned char adcmicsel, micbias_ctl;
368
369 adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
370 micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
371 /* Prepare the bits for the given TX path:
372 * shift_l == 0: TX1 microphone path
373 * shift_l == 2: TX2 microphone path */
374 if (e->shift_l) {
375 /* TX2 microphone path */
376 if (adcmicsel & TWL4030_TX2IN_SEL)
377 micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
378 else
379 micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
380 } else {
381 /* TX1 microphone path */
382 if (adcmicsel & TWL4030_TX1IN_SEL)
383 micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
384 else
385 micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
386 }
387
388 twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
389
390 return 0;
391}
392
49d92c7d
SM		 393static int handsfree_event(struct snd_soc_dapm_widget *w,
394 struct snd_kcontrol *kcontrol, int event)
395{
396 struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
397 unsigned char hs_ctl;
398
399 hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
400
401 if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
402 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
403 twl4030_write(w->codec, e->reg, hs_ctl);
404 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
405 twl4030_write(w->codec, e->reg, hs_ctl);
406 hs_ctl |= TWL4030_HF_CTL_HB_EN;
407 twl4030_write(w->codec, e->reg, hs_ctl);
408 } else {
409 hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
410 | TWL4030_HF_CTL_HB_EN);
411 twl4030_write(w->codec, e->reg, hs_ctl);
412 }
413
414 return 0;
415}
416
b0bd53a7
PU		 417/*
418 * Some of the gain controls in TWL (mostly those which are associated with
419 * the outputs) are implemented in an interesting way:
420 * 0x0 : Power down (mute)
421 * 0x1 : 6dB
422 * 0x2 : 0 dB
423 * 0x3 : -6 dB
424 * Inverting not going to help with these.
425 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
426 */
427#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
428 xinvert, tlv_array) \
429{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
430 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
431 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
432 .tlv.p = (tlv_array), \
433 .info = snd_soc_info_volsw, \
434 .get = snd_soc_get_volsw_twl4030, \
435 .put = snd_soc_put_volsw_twl4030, \
436 .private_value = (unsigned long)&(struct soc_mixer_control) \
437 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
438 .max = xmax, .invert = xinvert} }
439#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
440 xinvert, tlv_array) \
441{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
442 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
443 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
444 .tlv.p = (tlv_array), \
445 .info = snd_soc_info_volsw_2r, \
446 .get = snd_soc_get_volsw_r2_twl4030,\
447 .put = snd_soc_put_volsw_r2_twl4030, \
448 .private_value = (unsigned long)&(struct soc_mixer_control) \
449 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 450 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 451#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
452 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
453 xinvert, tlv_array)
454
455static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
456 struct snd_ctl_elem_value *ucontrol)
457{
458 struct soc_mixer_control *mc =
459 (struct soc_mixer_control *)kcontrol->private_value;
460 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
461 unsigned int reg = mc->reg;
462 unsigned int shift = mc->shift;
463 unsigned int rshift = mc->rshift;
464 int max = mc->max;
465 int mask = (1 << fls(max)) - 1;
466
467 ucontrol->value.integer.value[0] =
468 (snd_soc_read(codec, reg) >> shift) & mask;
469 if (ucontrol->value.integer.value[0])
470 ucontrol->value.integer.value[0] =
471 max + 1 - ucontrol->value.integer.value[0];
472
473 if (shift != rshift) {
474 ucontrol->value.integer.value[1] =
475 (snd_soc_read(codec, reg) >> rshift) & mask;
476 if (ucontrol->value.integer.value[1])
477 ucontrol->value.integer.value[1] =
478 max + 1 - ucontrol->value.integer.value[1];
479 }
480
481 return 0;
482}
483
484static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
485 struct snd_ctl_elem_value *ucontrol)
486{
487 struct soc_mixer_control *mc =
488 (struct soc_mixer_control *)kcontrol->private_value;
489 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
490 unsigned int reg = mc->reg;
491 unsigned int shift = mc->shift;
492 unsigned int rshift = mc->rshift;
493 int max = mc->max;
494 int mask = (1 << fls(max)) - 1;
495 unsigned short val, val2, val_mask;
496
497 val = (ucontrol->value.integer.value[0] & mask);
498
499 val_mask = mask << shift;
500 if (val)
501 val = max + 1 - val;
502 val = val << shift;
503 if (shift != rshift) {
504 val2 = (ucontrol->value.integer.value[1] & mask);
505 val_mask |= mask << rshift;
506 if (val2)
507 val2 = max + 1 - val2;
508 val |= val2 << rshift;
509 }
510 return snd_soc_update_bits(codec, reg, val_mask, val);
511}
512
513static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
514 struct snd_ctl_elem_value *ucontrol)
515{
516 struct soc_mixer_control *mc =
517 (struct soc_mixer_control *)kcontrol->private_value;
518 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
519 unsigned int reg = mc->reg;
520 unsigned int reg2 = mc->rreg;
521 unsigned int shift = mc->shift;
522 int max = mc->max;
523 int mask = (1<<fls(max))-1;
524
525 ucontrol->value.integer.value[0] =
526 (snd_soc_read(codec, reg) >> shift) & mask;
527 ucontrol->value.integer.value[1] =
528 (snd_soc_read(codec, reg2) >> shift) & mask;
529
530 if (ucontrol->value.integer.value[0])
531 ucontrol->value.integer.value[0] =
532 max + 1 - ucontrol->value.integer.value[0];
533 if (ucontrol->value.integer.value[1])
534 ucontrol->value.integer.value[1] =
535 max + 1 - ucontrol->value.integer.value[1];
536
537 return 0;
538}
539
540static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
541 struct snd_ctl_elem_value *ucontrol)
542{
543 struct soc_mixer_control *mc =
544 (struct soc_mixer_control *)kcontrol->private_value;
545 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
546 unsigned int reg = mc->reg;
547 unsigned int reg2 = mc->rreg;
548 unsigned int shift = mc->shift;
549 int max = mc->max;
550 int mask = (1 << fls(max)) - 1;
551 int err;
552 unsigned short val, val2, val_mask;
553
554 val_mask = mask << shift;
555 val = (ucontrol->value.integer.value[0] & mask);
556 val2 = (ucontrol->value.integer.value[1] & mask);
557
558 if (val)
559 val = max + 1 - val;
560 if (val2)
561 val2 = max + 1 - val2;
562
563 val = val << shift;
564 val2 = val2 << shift;
565
566 err = snd_soc_update_bits(codec, reg, val_mask, val);
567 if (err < 0)
568 return err;
569
570 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
571 return err;
572}
573
c10b82cf
PU		 574/*
575 * FGAIN volume control:
576 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
577 */
d889a72c 578static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 579
0d33ea0b
PU		 580/*
581 * CGAIN volume control:
582 * 0 dB to 12 dB in 6 dB steps
583 * value 2 and 3 means 12 dB
584 */
d889a72c
PU		 585static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
586
587/*
588 * Analog playback gain
589 * -24 dB to 12 dB in 2 dB steps
590 */
591static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 592
4290239c
PU		 593/*
594 * Gain controls tied to outputs
595 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
596 */
597static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
598
381a22b5
PU		 599/*
600 * Capture gain after the ADCs
601 * from 0 dB to 31 dB in 1 dB steps
602 */
603static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
604
5920b453
GI		 605/*
606 * Gain control for input amplifiers
607 * 0 dB to 30 dB in 6 dB steps
608 */
609static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
610
cc17557e 611static const struct snd_kcontrol_new twl4030_snd_controls[] = {
d889a72c
PU		 612 /* Common playback gain controls */
613 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
614 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
615 0, 0x3f, 0, digital_fine_tlv),
616 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
617 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
618 0, 0x3f, 0, digital_fine_tlv),
619
620 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
621 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
622 6, 0x2, 0, digital_coarse_tlv),
623 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
624 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
625 6, 0x2, 0, digital_coarse_tlv),
626
627 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
628 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
629 3, 0x12, 1, analog_tlv),
630 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
631 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
632 3, 0x12, 1, analog_tlv),
44c55870
PU		 633 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
634 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
635 1, 1, 0),
636 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
637 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
638 1, 1, 0),
381a22b5 639
4290239c
PU		 640 /* Separate output gain controls */
641 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
642 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
643 4, 3, 0, output_tvl),
644
645 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
646 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
647
648 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
649 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
650 4, 3, 0, output_tvl),
651
652 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
653 TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
654
381a22b5 655 /* Common capture gain controls */
276c6222 656 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 657 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
658 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 659 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
660 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
661 0, 0x1f, 0, digital_capture_tlv),
5920b453 662
276c6222 663 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 664 0, 3, 5, 0, input_gain_tlv),
cc17557e
SS		 665};
666
cc17557e 667static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 668 /* Left channel inputs */
669 SND_SOC_DAPM_INPUT("MAINMIC"),
670 SND_SOC_DAPM_INPUT("HSMIC"),
671 SND_SOC_DAPM_INPUT("AUXL"),
672 SND_SOC_DAPM_INPUT("CARKITMIC"),
673 /* Right channel inputs */
674 SND_SOC_DAPM_INPUT("SUBMIC"),
675 SND_SOC_DAPM_INPUT("AUXR"),
676 /* Digital microphones (Stereo) */
677 SND_SOC_DAPM_INPUT("DIGIMIC0"),
678 SND_SOC_DAPM_INPUT("DIGIMIC1"),
679
680 /* Outputs */
cc17557e
SS		 681 SND_SOC_DAPM_OUTPUT("OUTL"),
682 SND_SOC_DAPM_OUTPUT("OUTR"),
5e98a464 683 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 684 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
685 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 686 SND_SOC_DAPM_OUTPUT("HSOL"),
687 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 688 SND_SOC_DAPM_OUTPUT("CARKITL"),
689 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 690 SND_SOC_DAPM_OUTPUT("HFL"),
691 SND_SOC_DAPM_OUTPUT("HFR"),
cc17557e 692
53b5047d 693 /* DACs */
1e5fa31f 694 SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
53b5047d 695 TWL4030_REG_AVDAC_CTL, 0, 0),
1e5fa31f 696 SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
53b5047d 697 TWL4030_REG_AVDAC_CTL, 1, 0),
1e5fa31f 698 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
53b5047d 699 TWL4030_REG_AVDAC_CTL, 2, 0),
1e5fa31f 700 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
53b5047d 701 TWL4030_REG_AVDAC_CTL, 3, 0),
cc17557e 702
44c55870
PU		 703 /* Analog PGAs */
704 SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
705 0, 0, NULL, 0),
706 SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
707 0, 0, NULL, 0),
708 SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
709 0, 0, NULL, 0),
710 SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
711 0, 0, NULL, 0),
712
5e98a464
PU		 713 /* Output MUX controls */
714 /* Earpiece */
2f423577
PU		 715 SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
716 &twl4030_dapm_earpiece_control),
2a6f5c58 717 /* PreDrivL/R */
2f423577
PU		 718 SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
719 &twl4030_dapm_predrivel_control),
720 SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
721 &twl4030_dapm_predriver_control),
dfad21a2
PU		 722 /* HeadsetL/R */
723 SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
724 &twl4030_dapm_hsol_control),
725 SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
726 &twl4030_dapm_hsor_control),
5152d8c2
PU		 727 /* CarkitL/R */
728 SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
729 &twl4030_dapm_carkitl_control),
730 SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
731 &twl4030_dapm_carkitr_control),
df339804 732 /* HandsfreeL/R */
49d92c7d
SM		 733 SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
734 &twl4030_dapm_handsfreel_control, handsfree_event,
735 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
736 SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
737 &twl4030_dapm_handsfreer_control, handsfree_event,
738 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5e98a464 739
276c6222
PU		 740 /* Introducing four virtual ADC, since TWL4030 have four channel for
741 capture */
742 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
743 SND_SOC_NOPM, 0, 0),
744 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
745 SND_SOC_NOPM, 0, 0),
746 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
747 SND_SOC_NOPM, 0, 0),
748 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
749 SND_SOC_NOPM, 0, 0),
750
751 /* Analog/Digital mic path selection.
752 TX1 Left/Right: either analog Left/Right or Digimic0
753 TX2 Left/Right: either analog Left/Right or Digimic1 */
754 SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
755 &twl4030_dapm_micpathtx1_control, micpath_event,
756 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
757 SND_SOC_DAPM_POST_REG),
758 SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
759 &twl4030_dapm_micpathtx2_control, micpath_event,
760 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
761 SND_SOC_DAPM_POST_REG),
762
763 /* Analog input muxes with power switch for the physical ADCL/R */
2f423577
PU		 764 SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
765 TWL4030_REG_AVADC_CTL, 3, 0, &twl4030_dapm_analoglmic_control),
766 SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
767 TWL4030_REG_AVADC_CTL, 1, 0, &twl4030_dapm_analogrmic_control),
276c6222
PU		 768
769 SND_SOC_DAPM_PGA("Analog Left Amplifier",
770 TWL4030_REG_ANAMICL, 4, 0, NULL, 0),
771 SND_SOC_DAPM_PGA("Analog Right Amplifier",
772 TWL4030_REG_ANAMICR, 4, 0, NULL, 0),
773
774 SND_SOC_DAPM_PGA("Digimic0 Enable",
775 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
776 SND_SOC_DAPM_PGA("Digimic1 Enable",
777 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
778
779 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
780 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
781 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
cc17557e
SS		 782};
783
784static const struct snd_soc_dapm_route intercon[] = {
1e5fa31f
PU		 785 {"ARXL1_APGA", NULL, "DAC Left1"},
786 {"ARXR1_APGA", NULL, "DAC Right1"},
787 {"ARXL2_APGA", NULL, "DAC Left2"},
788 {"ARXR2_APGA", NULL, "DAC Right2"},
44c55870 789
5e98a464
PU		 790 /* Internal playback routings */
791 /* Earpiece */
792 {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
793 {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
794 {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
2a6f5c58
PU		 795 /* PreDrivL */
796 {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
797 {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
798 {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
799 /* PreDrivR */
800 {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
801 {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
802 {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
dfad21a2
PU		 803 /* HeadsetL */
804 {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
805 {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
806 /* HeadsetR */
807 {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
808 {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
5152d8c2
PU		 809 /* CarkitL */
810 {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
811 {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
812 /* CarkitR */
813 {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
814 {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
df339804
PU		 815 /* HandsfreeL */
816 {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
817 {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
818 {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
819 /* HandsfreeR */
820 {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
821 {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
822 {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
5e98a464 823
cc17557e 824 /* outputs */
44c55870
PU		 825 {"OUTL", NULL, "ARXL2_APGA"},
826 {"OUTR", NULL, "ARXR2_APGA"},
5e98a464 827 {"EARPIECE", NULL, "Earpiece Mux"},
2a6f5c58
PU		 828 {"PREDRIVEL", NULL, "PredriveL Mux"},
829 {"PREDRIVER", NULL, "PredriveR Mux"},
dfad21a2
PU		 830 {"HSOL", NULL, "HeadsetL Mux"},
831 {"HSOR", NULL, "HeadsetR Mux"},
5152d8c2
PU		 832 {"CARKITL", NULL, "CarkitL Mux"},
833 {"CARKITR", NULL, "CarkitR Mux"},
df339804
PU		 834 {"HFL", NULL, "HandsfreeL Mux"},
835 {"HFR", NULL, "HandsfreeR Mux"},
cc17557e 836
276c6222
PU		 837 /* Capture path */
838 {"Analog Left Capture Route", "Main mic", "MAINMIC"},
839 {"Analog Left Capture Route", "Headset mic", "HSMIC"},
840 {"Analog Left Capture Route", "AUXL", "AUXL"},
841 {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
842
843 {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
844 {"Analog Right Capture Route", "AUXR", "AUXR"},
845
846 {"Analog Left Amplifier", NULL, "Analog Left Capture Route"},
847 {"Analog Right Amplifier", NULL, "Analog Right Capture Route"},
848
849 {"Digimic0 Enable", NULL, "DIGIMIC0"},
850 {"Digimic1 Enable", NULL, "DIGIMIC1"},
851
852 /* TX1 Left capture path */
853 {"TX1 Capture Route", "Analog", "Analog Left Amplifier"},
854 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
855 /* TX1 Right capture path */
856 {"TX1 Capture Route", "Analog", "Analog Right Amplifier"},
857 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
858 /* TX2 Left capture path */
859 {"TX2 Capture Route", "Analog", "Analog Left Amplifier"},
860 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
861 /* TX2 Right capture path */
862 {"TX2 Capture Route", "Analog", "Analog Right Amplifier"},
863 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
864
865 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
866 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
867 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
868 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
869
cc17557e
SS		 870};
871
872static int twl4030_add_widgets(struct snd_soc_codec *codec)
873{
874 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
875 ARRAY_SIZE(twl4030_dapm_widgets));
876
877 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
878
879 snd_soc_dapm_new_widgets(codec);
880 return 0;
881}
882
883static void twl4030_power_up(struct snd_soc_codec *codec)
884{
ca4513fe 885 u8 anamicl, regmisc1, byte, popn;
cc17557e
SS		 886 int i = 0;
887
888 /* set CODECPDZ to turn on codec */
db04e2c5 889 twl4030_codec_enable(codec, 1);
cc17557e
SS		 890
891 /* initiate offset cancellation */
892 anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
893 twl4030_write(codec, TWL4030_REG_ANAMICL,
894 anamicl | TWL4030_CNCL_OFFSET_START);
895
276c6222 896
cc17557e
SS		 897 /* wait for offset cancellation to complete */
898 do {
899 /* this takes a little while, so don't slam i2c */
900 udelay(2000);
901 twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
902 TWL4030_REG_ANAMICL);
903 } while ((i++ < 100) &&
904 ((byte & TWL4030_CNCL_OFFSET_START) ==
905 TWL4030_CNCL_OFFSET_START));
906
3fc93030
PU		 907 /* Make sure that the reg_cache has the same value as the HW */
908 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
909
cc17557e
SS		 910 /* anti-pop when changing analog gain */
911 regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
912 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
913 regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
914
915 /* toggle CODECPDZ as per TRM */
db04e2c5
PU		 916 twl4030_codec_enable(codec, 0);
917 twl4030_codec_enable(codec, 1);
cc17557e
SS		 918
919 /* program anti-pop with bias ramp delay */
920 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
921 popn &= TWL4030_RAMP_DELAY;
922 popn |= TWL4030_RAMP_DELAY_645MS;
923 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
924 popn |= TWL4030_VMID_EN;
925 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
926
cc17557e
SS		 927 /* enable anti-pop ramp */
928 popn |= TWL4030_RAMP_EN;
929 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
930}
931
932static void twl4030_power_down(struct snd_soc_codec *codec)
933{
ca4513fe 934 u8 popn;
cc17557e
SS		 935
936 /* disable anti-pop ramp */
937 popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
938 popn &= ~TWL4030_RAMP_EN;
939 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
940
cc17557e
SS		 941 /* disable bias out */
942 popn &= ~TWL4030_VMID_EN;
943 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
944
945 /* power down */
db04e2c5 946 twl4030_codec_enable(codec, 0);
cc17557e
SS		 947}
948
949static int twl4030_set_bias_level(struct snd_soc_codec *codec,
950 enum snd_soc_bias_level level)
951{
952 switch (level) {
953 case SND_SOC_BIAS_ON:
954 twl4030_power_up(codec);
955 break;
956 case SND_SOC_BIAS_PREPARE:
957 /* TODO: develop a twl4030_prepare function */
958 break;
959 case SND_SOC_BIAS_STANDBY:
960 /* TODO: develop a twl4030_standby function */
961 twl4030_power_down(codec);
962 break;
963 case SND_SOC_BIAS_OFF:
964 twl4030_power_down(codec);
965 break;
966 }
967 codec->bias_level = level;
968
969 return 0;
970}
971
972static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 973 struct snd_pcm_hw_params *params,
974 struct snd_soc_dai *dai)
cc17557e
SS		 975{
976 struct snd_soc_pcm_runtime *rtd = substream->private_data;
977 struct snd_soc_device *socdev = rtd->socdev;
6627a653 978 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 979 u8 mode, old_mode, format, old_format;
980
981
982 /* bit rate */
983 old_mode = twl4030_read_reg_cache(codec,
984 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
985 mode = old_mode & ~TWL4030_APLL_RATE;
986
987 switch (params_rate(params)) {
988 case 8000:
989 mode |= TWL4030_APLL_RATE_8000;
990 break;
991 case 11025:
992 mode |= TWL4030_APLL_RATE_11025;
993 break;
994 case 12000:
995 mode |= TWL4030_APLL_RATE_12000;
996 break;
997 case 16000:
998 mode |= TWL4030_APLL_RATE_16000;
999 break;
1000 case 22050:
1001 mode |= TWL4030_APLL_RATE_22050;
1002 break;
1003 case 24000:
1004 mode |= TWL4030_APLL_RATE_24000;
1005 break;
1006 case 32000:
1007 mode |= TWL4030_APLL_RATE_32000;
1008 break;
1009 case 44100:
1010 mode |= TWL4030_APLL_RATE_44100;
1011 break;
1012 case 48000:
1013 mode |= TWL4030_APLL_RATE_48000;
1014 break;
1015 default:
1016 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1017 params_rate(params));
1018 return -EINVAL;
1019 }
1020
1021 if (mode != old_mode) {
1022 /* change rate and set CODECPDZ */
1023 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
db04e2c5 1024 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1025 }
1026
1027 /* sample size */
1028 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1029 format = old_format;
1030 format &= ~TWL4030_DATA_WIDTH;
1031 switch (params_format(params)) {
1032 case SNDRV_PCM_FORMAT_S16_LE:
1033 format |= TWL4030_DATA_WIDTH_16S_16W;
1034 break;
1035 case SNDRV_PCM_FORMAT_S24_LE:
1036 format |= TWL4030_DATA_WIDTH_32S_24W;
1037 break;
1038 default:
1039 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1040 params_format(params));
1041 return -EINVAL;
1042 }
1043
1044 if (format != old_format) {
1045
1046 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1047 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1048
1049 /* change format */
1050 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1051
1052 /* set CODECPDZ afterwards */
db04e2c5 1053 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1054 }
1055 return 0;
1056}
1057
1058static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1059 int clk_id, unsigned int freq, int dir)
1060{
1061 struct snd_soc_codec *codec = codec_dai->codec;
1062 u8 infreq;
1063
1064 switch (freq) {
1065 case 19200000:
1066 infreq = TWL4030_APLL_INFREQ_19200KHZ;
1067 break;
1068 case 26000000:
1069 infreq = TWL4030_APLL_INFREQ_26000KHZ;
1070 break;
1071 case 38400000:
1072 infreq = TWL4030_APLL_INFREQ_38400KHZ;
1073 break;
1074 default:
1075 printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
1076 freq);
1077 return -EINVAL;
1078 }
1079
1080 infreq |= TWL4030_APLL_EN;
1081 twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
1082
1083 return 0;
1084}
1085
1086static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1087 unsigned int fmt)
1088{
1089 struct snd_soc_codec *codec = codec_dai->codec;
1090 u8 old_format, format;
1091
1092 /* get format */
1093 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1094 format = old_format;
1095
1096 /* set master/slave audio interface */
1097 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1098 case SND_SOC_DAIFMT_CBM_CFM:
1099 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1100 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1101 break;
1102 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1103 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1104 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1105 break;
1106 default:
1107 return -EINVAL;
1108 }
1109
1110 /* interface format */
1111 format &= ~TWL4030_AIF_FORMAT;
1112 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1113 case SND_SOC_DAIFMT_I2S:
1114 format |= TWL4030_AIF_FORMAT_CODEC;
1115 break;
1116 default:
1117 return -EINVAL;
1118 }
1119
1120 if (format != old_format) {
1121
1122 /* clear CODECPDZ before changing format (codec requirement) */
db04e2c5 1123 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1124
1125 /* change format */
1126 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1127
1128 /* set CODECPDZ afterwards */
db04e2c5 1129 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1130 }
1131
1132 return 0;
1133}
1134
bbba9444 1135#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 1136#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
1137
1138struct snd_soc_dai twl4030_dai = {
1139 .name = "twl4030",
1140 .playback = {
1141 .stream_name = "Playback",
1142 .channels_min = 2,
1143 .channels_max = 2,
1144 .rates = TWL4030_RATES,
1145 .formats = TWL4030_FORMATS,},
1146 .capture = {
1147 .stream_name = "Capture",
1148 .channels_min = 2,
1149 .channels_max = 2,
1150 .rates = TWL4030_RATES,
1151 .formats = TWL4030_FORMATS,},
1152 .ops = {
1153 .hw_params = twl4030_hw_params,
cc17557e
SS		 1154 .set_sysclk = twl4030_set_dai_sysclk,
1155 .set_fmt = twl4030_set_dai_fmt,
1156 }
1157};
1158EXPORT_SYMBOL_GPL(twl4030_dai);
1159
1160static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
1161{
1162 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1163 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1164
1165 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
1166
1167 return 0;
1168}
1169
1170static int twl4030_resume(struct platform_device *pdev)
1171{
1172 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1173 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1174
1175 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1176 twl4030_set_bias_level(codec, codec->suspend_bias_level);
1177 return 0;
1178}
1179
1180/*
1181 * initialize the driver
1182 * register the mixer and dsp interfaces with the kernel
1183 */
1184
1185static int twl4030_init(struct snd_soc_device *socdev)
1186{
6627a653 1187 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1188 int ret = 0;
1189
1190 printk(KERN_INFO "TWL4030 Audio Codec init \n");
1191
1192 codec->name = "twl4030";
1193 codec->owner = THIS_MODULE;
1194 codec->read = twl4030_read_reg_cache;
1195 codec->write = twl4030_write;
1196 codec->set_bias_level = twl4030_set_bias_level;
1197 codec->dai = &twl4030_dai;
1198 codec->num_dai = 1;
1199 codec->reg_cache_size = sizeof(twl4030_reg);
1200 codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
1201 GFP_KERNEL);
1202 if (codec->reg_cache == NULL)
1203 return -ENOMEM;
1204
1205 /* register pcms */
1206 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1207 if (ret < 0) {
1208 printk(KERN_ERR "twl4030: failed to create pcms\n");
1209 goto pcm_err;
1210 }
1211
1212 twl4030_init_chip(codec);
1213
1214 /* power on device */
1215 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1216
3e8e1952
IM		 1217 snd_soc_add_controls(codec, twl4030_snd_controls,
1218 ARRAY_SIZE(twl4030_snd_controls));
cc17557e
SS		 1219 twl4030_add_widgets(codec);
1220
968a6025 1221 ret = snd_soc_init_card(socdev);
cc17557e
SS		 1222 if (ret < 0) {
1223 printk(KERN_ERR "twl4030: failed to register card\n");
1224 goto card_err;
1225 }
1226
1227 return ret;
1228
1229card_err:
1230 snd_soc_free_pcms(socdev);
1231 snd_soc_dapm_free(socdev);
1232pcm_err:
1233 kfree(codec->reg_cache);
1234 return ret;
1235}
1236
1237static struct snd_soc_device *twl4030_socdev;
1238
1239static int twl4030_probe(struct platform_device *pdev)
1240{
1241 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1242 struct snd_soc_codec *codec;
1243
1244 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1245 if (codec == NULL)
1246 return -ENOMEM;
1247
6627a653 1248 socdev->card->codec = codec;
cc17557e
SS		 1249 mutex_init(&codec->mutex);
1250 INIT_LIST_HEAD(&codec->dapm_widgets);
1251 INIT_LIST_HEAD(&codec->dapm_paths);
1252
1253 twl4030_socdev = socdev;
1254 twl4030_init(socdev);
1255
1256 return 0;
1257}
1258
1259static int twl4030_remove(struct platform_device *pdev)
1260{
1261 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1262 struct snd_soc_codec *codec = socdev->card->codec;
cc17557e
SS		 1263
1264 printk(KERN_INFO "TWL4030 Audio Codec remove\n");
c6d1662b
PU		 1265 snd_soc_free_pcms(socdev);
1266 snd_soc_dapm_free(socdev);
cc17557e
SS		 1267 kfree(codec);
1268
1269 return 0;
1270}
1271
1272struct snd_soc_codec_device soc_codec_dev_twl4030 = {
1273 .probe = twl4030_probe,
1274 .remove = twl4030_remove,
1275 .suspend = twl4030_suspend,
1276 .resume = twl4030_resume,
1277};
1278EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
1279
24e07db8 1280static int __init twl4030_modinit(void)
64089b84
MB		 1281{
1282 return snd_soc_register_dai(&twl4030_dai);
1283}
24e07db8 1284module_init(twl4030_modinit);
64089b84
MB		 1285
1286static void __exit twl4030_exit(void)
1287{
1288 snd_soc_unregister_dai(&twl4030_dai);
1289}
1290module_exit(twl4030_exit);
1291
cc17557e
SS		 1292MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
1293MODULE_AUTHOR("Steve Sakoman");
1294MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)