Commit | Line | Data |
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cc17557e SS |
1 | /* |
2 | * ALSA SoC TWL4030 codec driver | |
3 | * | |
4 | * Author: Steve Sakoman, <steve@sakoman.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/pm.h> | |
27 | #include <linux/i2c.h> | |
28 | #include <linux/platform_device.h> | |
b07682b6 | 29 | #include <linux/i2c/twl.h> |
cc17557e SS |
30 | #include <sound/core.h> |
31 | #include <sound/pcm.h> | |
32 | #include <sound/pcm_params.h> | |
33 | #include <sound/soc.h> | |
34 | #include <sound/soc-dapm.h> | |
35 | #include <sound/initval.h> | |
c10b82cf | 36 | #include <sound/tlv.h> |
cc17557e SS |
37 | |
38 | #include "twl4030.h" | |
39 | ||
40 | /* | |
41 | * twl4030 register cache & default register settings | |
42 | */ | |
43 | static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = { | |
44 | 0x00, /* this register not used */ | |
db04e2c5 | 45 | 0x91, /* REG_CODEC_MODE (0x1) */ |
cc17557e SS |
46 | 0xc3, /* REG_OPTION (0x2) */ |
47 | 0x00, /* REG_UNKNOWN (0x3) */ | |
48 | 0x00, /* REG_MICBIAS_CTL (0x4) */ | |
5920b453 GI |
49 | 0x20, /* REG_ANAMICL (0x5) */ |
50 | 0x00, /* REG_ANAMICR (0x6) */ | |
51 | 0x00, /* REG_AVADC_CTL (0x7) */ | |
cc17557e SS |
52 | 0x00, /* REG_ADCMICSEL (0x8) */ |
53 | 0x00, /* REG_DIGMIXING (0x9) */ | |
54 | 0x0c, /* REG_ATXL1PGA (0xA) */ | |
55 | 0x0c, /* REG_ATXR1PGA (0xB) */ | |
56 | 0x00, /* REG_AVTXL2PGA (0xC) */ | |
57 | 0x00, /* REG_AVTXR2PGA (0xD) */ | |
c42a59ea | 58 | 0x00, /* REG_AUDIO_IF (0xE) */ |
cc17557e SS |
59 | 0x00, /* REG_VOICE_IF (0xF) */ |
60 | 0x00, /* REG_ARXR1PGA (0x10) */ | |
61 | 0x00, /* REG_ARXL1PGA (0x11) */ | |
62 | 0x6c, /* REG_ARXR2PGA (0x12) */ | |
63 | 0x6c, /* REG_ARXL2PGA (0x13) */ | |
64 | 0x00, /* REG_VRXPGA (0x14) */ | |
65 | 0x00, /* REG_VSTPGA (0x15) */ | |
66 | 0x00, /* REG_VRX2ARXPGA (0x16) */ | |
c8124593 | 67 | 0x00, /* REG_AVDAC_CTL (0x17) */ |
cc17557e SS |
68 | 0x00, /* REG_ARX2VTXPGA (0x18) */ |
69 | 0x00, /* REG_ARXL1_APGA_CTL (0x19) */ | |
70 | 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */ | |
c8124593 PU |
71 | 0x4a, /* REG_ARXL2_APGA_CTL (0x1B) */ |
72 | 0x4a, /* REG_ARXR2_APGA_CTL (0x1C) */ | |
cc17557e SS |
73 | 0x00, /* REG_ATX2ARXPGA (0x1D) */ |
74 | 0x00, /* REG_BT_IF (0x1E) */ | |
75 | 0x00, /* REG_BTPGA (0x1F) */ | |
76 | 0x00, /* REG_BTSTPGA (0x20) */ | |
77 | 0x00, /* REG_EAR_CTL (0x21) */ | |
e47c796d PU |
78 | 0x00, /* REG_HS_SEL (0x22) */ |
79 | 0x00, /* REG_HS_GAIN_SET (0x23) */ | |
cc17557e SS |
80 | 0x00, /* REG_HS_POPN_SET (0x24) */ |
81 | 0x00, /* REG_PREDL_CTL (0x25) */ | |
82 | 0x00, /* REG_PREDR_CTL (0x26) */ | |
83 | 0x00, /* REG_PRECKL_CTL (0x27) */ | |
84 | 0x00, /* REG_PRECKR_CTL (0x28) */ | |
85 | 0x00, /* REG_HFL_CTL (0x29) */ | |
86 | 0x00, /* REG_HFR_CTL (0x2A) */ | |
87 | 0x00, /* REG_ALC_CTL (0x2B) */ | |
88 | 0x00, /* REG_ALC_SET1 (0x2C) */ | |
89 | 0x00, /* REG_ALC_SET2 (0x2D) */ | |
90 | 0x00, /* REG_BOOST_CTL (0x2E) */ | |
f8d05bdb | 91 | 0x00, /* REG_SOFTVOL_CTL (0x2F) */ |
cc17557e SS |
92 | 0x00, /* REG_DTMF_FREQSEL (0x30) */ |
93 | 0x00, /* REG_DTMF_TONEXT1H (0x31) */ | |
94 | 0x00, /* REG_DTMF_TONEXT1L (0x32) */ | |
95 | 0x00, /* REG_DTMF_TONEXT2H (0x33) */ | |
96 | 0x00, /* REG_DTMF_TONEXT2L (0x34) */ | |
97 | 0x00, /* REG_DTMF_TONOFF (0x35) */ | |
98 | 0x00, /* REG_DTMF_WANONOFF (0x36) */ | |
99 | 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */ | |
100 | 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */ | |
101 | 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */ | |
c8124593 | 102 | 0x06, /* REG_APLL_CTL (0x3A) */ |
cc17557e SS |
103 | 0x00, /* REG_DTMF_CTL (0x3B) */ |
104 | 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */ | |
105 | 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */ | |
106 | 0x00, /* REG_MISC_SET_1 (0x3E) */ | |
107 | 0x00, /* REG_PCMBTMUX (0x3F) */ | |
108 | 0x00, /* not used (0x40) */ | |
109 | 0x00, /* not used (0x41) */ | |
110 | 0x00, /* not used (0x42) */ | |
111 | 0x00, /* REG_RX_PATH_SEL (0x43) */ | |
112 | 0x00, /* REG_VDL_APGA_CTL (0x44) */ | |
113 | 0x00, /* REG_VIBRA_CTL (0x45) */ | |
114 | 0x00, /* REG_VIBRA_SET (0x46) */ | |
115 | 0x00, /* REG_VIBRA_PWM_SET (0x47) */ | |
116 | 0x00, /* REG_ANAMIC_GAIN (0x48) */ | |
117 | 0x00, /* REG_MISC_SET_2 (0x49) */ | |
f3b5d300 | 118 | 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */ |
cc17557e SS |
119 | }; |
120 | ||
7393958f PU |
121 | /* codec private data */ |
122 | struct twl4030_priv { | |
7a1fecf5 PU |
123 | struct snd_soc_codec codec; |
124 | ||
7393958f | 125 | unsigned int codec_powered; |
2845fa13 | 126 | unsigned int apll_enabled; |
7220b9f4 PU |
127 | |
128 | struct snd_pcm_substream *master_substream; | |
129 | struct snd_pcm_substream *slave_substream; | |
6b87a91f PU |
130 | |
131 | unsigned int configured; | |
132 | unsigned int rate; | |
133 | unsigned int sample_bits; | |
134 | unsigned int channels; | |
6943c92e PU |
135 | |
136 | unsigned int sysclk; | |
137 | ||
c96907f2 PU |
138 | /* Output (with associated amp) states */ |
139 | u8 hsl_enabled, hsr_enabled; | |
140 | u8 earpiece_enabled; | |
141 | u8 predrivel_enabled, predriver_enabled; | |
142 | u8 carkitl_enabled, carkitr_enabled; | |
7393958f PU |
143 | }; |
144 | ||
cc17557e SS |
145 | /* |
146 | * read twl4030 register cache | |
147 | */ | |
148 | static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec, | |
149 | unsigned int reg) | |
150 | { | |
d08664fd | 151 | u8 *cache = codec->reg_cache; |
cc17557e | 152 | |
91432e97 IM |
153 | if (reg >= TWL4030_CACHEREGNUM) |
154 | return -EIO; | |
155 | ||
cc17557e SS |
156 | return cache[reg]; |
157 | } | |
158 | ||
159 | /* | |
160 | * write twl4030 register cache | |
161 | */ | |
162 | static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec, | |
163 | u8 reg, u8 value) | |
164 | { | |
165 | u8 *cache = codec->reg_cache; | |
166 | ||
167 | if (reg >= TWL4030_CACHEREGNUM) | |
168 | return; | |
169 | cache[reg] = value; | |
170 | } | |
171 | ||
172 | /* | |
173 | * write to the twl4030 register space | |
174 | */ | |
175 | static int twl4030_write(struct snd_soc_codec *codec, | |
176 | unsigned int reg, unsigned int value) | |
177 | { | |
b2c812e2 | 178 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
c96907f2 PU |
179 | int write_to_reg = 0; |
180 | ||
cc17557e | 181 | twl4030_write_reg_cache(codec, reg, value); |
c96907f2 PU |
182 | if (likely(reg < TWL4030_REG_SW_SHADOW)) { |
183 | /* Decide if the given register can be written */ | |
184 | switch (reg) { | |
185 | case TWL4030_REG_EAR_CTL: | |
186 | if (twl4030->earpiece_enabled) | |
187 | write_to_reg = 1; | |
188 | break; | |
189 | case TWL4030_REG_PREDL_CTL: | |
190 | if (twl4030->predrivel_enabled) | |
191 | write_to_reg = 1; | |
192 | break; | |
193 | case TWL4030_REG_PREDR_CTL: | |
194 | if (twl4030->predriver_enabled) | |
195 | write_to_reg = 1; | |
196 | break; | |
197 | case TWL4030_REG_PRECKL_CTL: | |
198 | if (twl4030->carkitl_enabled) | |
199 | write_to_reg = 1; | |
200 | break; | |
201 | case TWL4030_REG_PRECKR_CTL: | |
202 | if (twl4030->carkitr_enabled) | |
203 | write_to_reg = 1; | |
204 | break; | |
205 | case TWL4030_REG_HS_GAIN_SET: | |
206 | if (twl4030->hsl_enabled || twl4030->hsr_enabled) | |
207 | write_to_reg = 1; | |
208 | break; | |
209 | default: | |
210 | /* All other register can be written */ | |
211 | write_to_reg = 1; | |
212 | break; | |
213 | } | |
214 | if (write_to_reg) | |
215 | return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, | |
216 | value, reg); | |
217 | } | |
218 | return 0; | |
cc17557e SS |
219 | } |
220 | ||
db04e2c5 | 221 | static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) |
cc17557e | 222 | { |
b2c812e2 | 223 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7a1fecf5 | 224 | int mode; |
cc17557e | 225 | |
7393958f PU |
226 | if (enable == twl4030->codec_powered) |
227 | return; | |
228 | ||
db04e2c5 | 229 | if (enable) |
7a1fecf5 | 230 | mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER); |
db04e2c5 | 231 | else |
7a1fecf5 | 232 | mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER); |
cc17557e | 233 | |
7a1fecf5 PU |
234 | if (mode >= 0) { |
235 | twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode); | |
236 | twl4030->codec_powered = enable; | |
237 | } | |
cc17557e SS |
238 | |
239 | /* REVISIT: this delay is present in TI sample drivers */ | |
240 | /* but there seems to be no TRM requirement for it */ | |
241 | udelay(10); | |
242 | } | |
243 | ||
244 | static void twl4030_init_chip(struct snd_soc_codec *codec) | |
245 | { | |
16a30fbb | 246 | u8 *cache = codec->reg_cache; |
cc17557e SS |
247 | int i; |
248 | ||
249 | /* clear CODECPDZ prior to setting register defaults */ | |
db04e2c5 | 250 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
251 | |
252 | /* set all audio section registers to reasonable defaults */ | |
253 | for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++) | |
68d01955 PU |
254 | if (i != TWL4030_REG_APLL_CTL) |
255 | twl4030_write(codec, i, cache[i]); | |
cc17557e SS |
256 | |
257 | } | |
258 | ||
2845fa13 | 259 | static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable) |
7393958f | 260 | { |
b2c812e2 | 261 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7a1fecf5 | 262 | int status; |
7393958f | 263 | |
2845fa13 | 264 | if (enable == twl4030->apll_enabled) |
7393958f PU |
265 | return; |
266 | ||
2845fa13 | 267 | if (enable) |
7393958f | 268 | /* Enable PLL */ |
7a1fecf5 | 269 | status = twl4030_codec_enable_resource(TWL4030_CODEC_RES_APLL); |
2845fa13 PU |
270 | else |
271 | /* Disable PLL */ | |
272 | status = twl4030_codec_disable_resource(TWL4030_CODEC_RES_APLL); | |
7a1fecf5 PU |
273 | |
274 | if (status >= 0) | |
275 | twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status); | |
7393958f | 276 | |
2845fa13 | 277 | twl4030->apll_enabled = enable; |
7393958f PU |
278 | } |
279 | ||
006f367e PU |
280 | static void twl4030_power_up(struct snd_soc_codec *codec) |
281 | { | |
b2c812e2 | 282 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
006f367e PU |
283 | u8 anamicl, regmisc1, byte; |
284 | int i = 0; | |
285 | ||
7393958f PU |
286 | if (twl4030->codec_powered) |
287 | return; | |
288 | ||
006f367e PU |
289 | /* set CODECPDZ to turn on codec */ |
290 | twl4030_codec_enable(codec, 1); | |
291 | ||
292 | /* initiate offset cancellation */ | |
293 | anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL); | |
294 | twl4030_write(codec, TWL4030_REG_ANAMICL, | |
295 | anamicl | TWL4030_CNCL_OFFSET_START); | |
296 | ||
297 | /* wait for offset cancellation to complete */ | |
298 | do { | |
299 | /* this takes a little while, so don't slam i2c */ | |
300 | udelay(2000); | |
fc7b92fc | 301 | twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, |
006f367e PU |
302 | TWL4030_REG_ANAMICL); |
303 | } while ((i++ < 100) && | |
304 | ((byte & TWL4030_CNCL_OFFSET_START) == | |
305 | TWL4030_CNCL_OFFSET_START)); | |
306 | ||
307 | /* Make sure that the reg_cache has the same value as the HW */ | |
308 | twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte); | |
309 | ||
310 | /* anti-pop when changing analog gain */ | |
311 | regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1); | |
312 | twl4030_write(codec, TWL4030_REG_MISC_SET_1, | |
313 | regmisc1 | TWL4030_SMOOTH_ANAVOL_EN); | |
314 | ||
315 | /* toggle CODECPDZ as per TRM */ | |
316 | twl4030_codec_enable(codec, 0); | |
317 | twl4030_codec_enable(codec, 1); | |
318 | } | |
319 | ||
7393958f PU |
320 | /* |
321 | * Unconditional power down | |
322 | */ | |
006f367e PU |
323 | static void twl4030_power_down(struct snd_soc_codec *codec) |
324 | { | |
325 | /* power down */ | |
326 | twl4030_codec_enable(codec, 0); | |
327 | } | |
328 | ||
5e98a464 | 329 | /* Earpiece */ |
1a787e7a JS |
330 | static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = { |
331 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0), | |
332 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0), | |
333 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0), | |
334 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0), | |
335 | }; | |
5e98a464 | 336 | |
2a6f5c58 | 337 | /* PreDrive Left */ |
1a787e7a JS |
338 | static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = { |
339 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0), | |
340 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0), | |
341 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0), | |
342 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0), | |
343 | }; | |
2a6f5c58 PU |
344 | |
345 | /* PreDrive Right */ | |
1a787e7a JS |
346 | static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = { |
347 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0), | |
348 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0), | |
349 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0), | |
350 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0), | |
351 | }; | |
2a6f5c58 | 352 | |
dfad21a2 | 353 | /* Headset Left */ |
1a787e7a JS |
354 | static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = { |
355 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0), | |
356 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0), | |
357 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0), | |
358 | }; | |
dfad21a2 PU |
359 | |
360 | /* Headset Right */ | |
1a787e7a JS |
361 | static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = { |
362 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0), | |
363 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0), | |
364 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0), | |
365 | }; | |
dfad21a2 | 366 | |
5152d8c2 | 367 | /* Carkit Left */ |
1a787e7a JS |
368 | static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = { |
369 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0), | |
370 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0), | |
371 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0), | |
372 | }; | |
5152d8c2 PU |
373 | |
374 | /* Carkit Right */ | |
1a787e7a JS |
375 | static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = { |
376 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0), | |
377 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0), | |
378 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0), | |
379 | }; | |
5152d8c2 | 380 | |
df339804 PU |
381 | /* Handsfree Left */ |
382 | static const char *twl4030_handsfreel_texts[] = | |
1a787e7a | 383 | {"Voice", "AudioL1", "AudioL2", "AudioR2"}; |
df339804 PU |
384 | |
385 | static const struct soc_enum twl4030_handsfreel_enum = | |
386 | SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0, | |
387 | ARRAY_SIZE(twl4030_handsfreel_texts), | |
388 | twl4030_handsfreel_texts); | |
389 | ||
390 | static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control = | |
391 | SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum); | |
392 | ||
0f89bdca PU |
393 | /* Handsfree Left virtual mute */ |
394 | static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control = | |
395 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0); | |
396 | ||
df339804 PU |
397 | /* Handsfree Right */ |
398 | static const char *twl4030_handsfreer_texts[] = | |
1a787e7a | 399 | {"Voice", "AudioR1", "AudioR2", "AudioL2"}; |
df339804 PU |
400 | |
401 | static const struct soc_enum twl4030_handsfreer_enum = | |
402 | SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0, | |
403 | ARRAY_SIZE(twl4030_handsfreer_texts), | |
404 | twl4030_handsfreer_texts); | |
405 | ||
406 | static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control = | |
407 | SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum); | |
408 | ||
0f89bdca PU |
409 | /* Handsfree Right virtual mute */ |
410 | static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control = | |
411 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0); | |
412 | ||
376f7839 PU |
413 | /* Vibra */ |
414 | /* Vibra audio path selection */ | |
415 | static const char *twl4030_vibra_texts[] = | |
416 | {"AudioL1", "AudioR1", "AudioL2", "AudioR2"}; | |
417 | ||
418 | static const struct soc_enum twl4030_vibra_enum = | |
419 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2, | |
420 | ARRAY_SIZE(twl4030_vibra_texts), | |
421 | twl4030_vibra_texts); | |
422 | ||
423 | static const struct snd_kcontrol_new twl4030_dapm_vibra_control = | |
424 | SOC_DAPM_ENUM("Route", twl4030_vibra_enum); | |
425 | ||
426 | /* Vibra path selection: local vibrator (PWM) or audio driven */ | |
427 | static const char *twl4030_vibrapath_texts[] = | |
428 | {"Local vibrator", "Audio"}; | |
429 | ||
430 | static const struct soc_enum twl4030_vibrapath_enum = | |
431 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4, | |
432 | ARRAY_SIZE(twl4030_vibrapath_texts), | |
433 | twl4030_vibrapath_texts); | |
434 | ||
435 | static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control = | |
436 | SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum); | |
437 | ||
276c6222 | 438 | /* Left analog microphone selection */ |
97b8096d | 439 | static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = { |
9028935d PU |
440 | SOC_DAPM_SINGLE("Main Mic Capture Switch", |
441 | TWL4030_REG_ANAMICL, 0, 1, 0), | |
442 | SOC_DAPM_SINGLE("Headset Mic Capture Switch", | |
443 | TWL4030_REG_ANAMICL, 1, 1, 0), | |
444 | SOC_DAPM_SINGLE("AUXL Capture Switch", | |
445 | TWL4030_REG_ANAMICL, 2, 1, 0), | |
446 | SOC_DAPM_SINGLE("Carkit Mic Capture Switch", | |
447 | TWL4030_REG_ANAMICL, 3, 1, 0), | |
97b8096d | 448 | }; |
276c6222 PU |
449 | |
450 | /* Right analog microphone selection */ | |
97b8096d | 451 | static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = { |
9028935d PU |
452 | SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0), |
453 | SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0), | |
97b8096d | 454 | }; |
276c6222 PU |
455 | |
456 | /* TX1 L/R Analog/Digital microphone selection */ | |
457 | static const char *twl4030_micpathtx1_texts[] = | |
458 | {"Analog", "Digimic0"}; | |
459 | ||
460 | static const struct soc_enum twl4030_micpathtx1_enum = | |
461 | SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0, | |
462 | ARRAY_SIZE(twl4030_micpathtx1_texts), | |
463 | twl4030_micpathtx1_texts); | |
464 | ||
465 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control = | |
466 | SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum); | |
467 | ||
468 | /* TX2 L/R Analog/Digital microphone selection */ | |
469 | static const char *twl4030_micpathtx2_texts[] = | |
470 | {"Analog", "Digimic1"}; | |
471 | ||
472 | static const struct soc_enum twl4030_micpathtx2_enum = | |
473 | SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2, | |
474 | ARRAY_SIZE(twl4030_micpathtx2_texts), | |
475 | twl4030_micpathtx2_texts); | |
476 | ||
477 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control = | |
478 | SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum); | |
479 | ||
7393958f PU |
480 | /* Analog bypass for AudioR1 */ |
481 | static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control = | |
482 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0); | |
483 | ||
484 | /* Analog bypass for AudioL1 */ | |
485 | static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control = | |
486 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0); | |
487 | ||
488 | /* Analog bypass for AudioR2 */ | |
489 | static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control = | |
490 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0); | |
491 | ||
492 | /* Analog bypass for AudioL2 */ | |
493 | static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control = | |
494 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0); | |
495 | ||
fcd274a3 LCM |
496 | /* Analog bypass for Voice */ |
497 | static const struct snd_kcontrol_new twl4030_dapm_abypassv_control = | |
498 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0); | |
499 | ||
6bab83fd PU |
500 | /* Digital bypass gain, 0 mutes the bypass */ |
501 | static const unsigned int twl4030_dapm_dbypass_tlv[] = { | |
502 | TLV_DB_RANGE_HEAD(2), | |
503 | 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1), | |
504 | 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0), | |
505 | }; | |
506 | ||
507 | /* Digital bypass left (TX1L -> RX2L) */ | |
508 | static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control = | |
509 | SOC_DAPM_SINGLE_TLV("Volume", | |
510 | TWL4030_REG_ATX2ARXPGA, 3, 7, 0, | |
511 | twl4030_dapm_dbypass_tlv); | |
512 | ||
513 | /* Digital bypass right (TX1R -> RX2R) */ | |
514 | static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control = | |
515 | SOC_DAPM_SINGLE_TLV("Volume", | |
516 | TWL4030_REG_ATX2ARXPGA, 0, 7, 0, | |
517 | twl4030_dapm_dbypass_tlv); | |
518 | ||
ee8f6894 LCM |
519 | /* |
520 | * Voice Sidetone GAIN volume control: | |
521 | * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB) | |
522 | */ | |
523 | static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1); | |
524 | ||
525 | /* Digital bypass voice: sidetone (VUL -> VDL)*/ | |
526 | static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control = | |
527 | SOC_DAPM_SINGLE_TLV("Volume", | |
528 | TWL4030_REG_VSTPGA, 0, 0x29, 0, | |
529 | twl4030_dapm_dbypassv_tlv); | |
530 | ||
276c6222 PU |
531 | static int micpath_event(struct snd_soc_dapm_widget *w, |
532 | struct snd_kcontrol *kcontrol, int event) | |
533 | { | |
534 | struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value; | |
535 | unsigned char adcmicsel, micbias_ctl; | |
536 | ||
537 | adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL); | |
538 | micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL); | |
539 | /* Prepare the bits for the given TX path: | |
540 | * shift_l == 0: TX1 microphone path | |
541 | * shift_l == 2: TX2 microphone path */ | |
542 | if (e->shift_l) { | |
543 | /* TX2 microphone path */ | |
544 | if (adcmicsel & TWL4030_TX2IN_SEL) | |
545 | micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */ | |
546 | else | |
547 | micbias_ctl &= ~TWL4030_MICBIAS2_CTL; | |
548 | } else { | |
549 | /* TX1 microphone path */ | |
550 | if (adcmicsel & TWL4030_TX1IN_SEL) | |
551 | micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */ | |
552 | else | |
553 | micbias_ctl &= ~TWL4030_MICBIAS1_CTL; | |
554 | } | |
555 | ||
556 | twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl); | |
557 | ||
558 | return 0; | |
559 | } | |
560 | ||
9008adf9 PU |
561 | /* |
562 | * Output PGA builder: | |
563 | * Handle the muting and unmuting of the given output (turning off the | |
564 | * amplifier associated with the output pin) | |
c96907f2 PU |
565 | * On mute bypass the reg_cache and write 0 to the register |
566 | * On unmute: restore the register content from the reg_cache | |
9008adf9 PU |
567 | * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R |
568 | */ | |
569 | #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \ | |
570 | static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \ | |
571 | struct snd_kcontrol *kcontrol, int event) \ | |
572 | { \ | |
b2c812e2 | 573 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \ |
9008adf9 PU |
574 | \ |
575 | switch (event) { \ | |
576 | case SND_SOC_DAPM_POST_PMU: \ | |
c96907f2 | 577 | twl4030->pin_name##_enabled = 1; \ |
9008adf9 PU |
578 | twl4030_write(w->codec, reg, \ |
579 | twl4030_read_reg_cache(w->codec, reg)); \ | |
580 | break; \ | |
581 | case SND_SOC_DAPM_POST_PMD: \ | |
c96907f2 PU |
582 | twl4030->pin_name##_enabled = 0; \ |
583 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \ | |
584 | 0, reg); \ | |
9008adf9 PU |
585 | break; \ |
586 | } \ | |
587 | return 0; \ | |
588 | } | |
589 | ||
590 | TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN); | |
591 | TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN); | |
592 | TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN); | |
593 | TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN); | |
594 | TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN); | |
595 | ||
5a2e9a48 | 596 | static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp) |
49d92c7d | 597 | { |
49d92c7d SM |
598 | unsigned char hs_ctl; |
599 | ||
5a2e9a48 | 600 | hs_ctl = twl4030_read_reg_cache(codec, reg); |
49d92c7d | 601 | |
5a2e9a48 PU |
602 | if (ramp) { |
603 | /* HF ramp-up */ | |
604 | hs_ctl |= TWL4030_HF_CTL_REF_EN; | |
605 | twl4030_write(codec, reg, hs_ctl); | |
606 | udelay(10); | |
49d92c7d | 607 | hs_ctl |= TWL4030_HF_CTL_RAMP_EN; |
5a2e9a48 PU |
608 | twl4030_write(codec, reg, hs_ctl); |
609 | udelay(40); | |
49d92c7d | 610 | hs_ctl |= TWL4030_HF_CTL_LOOP_EN; |
49d92c7d | 611 | hs_ctl |= TWL4030_HF_CTL_HB_EN; |
5a2e9a48 | 612 | twl4030_write(codec, reg, hs_ctl); |
49d92c7d | 613 | } else { |
5a2e9a48 PU |
614 | /* HF ramp-down */ |
615 | hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN; | |
616 | hs_ctl &= ~TWL4030_HF_CTL_HB_EN; | |
617 | twl4030_write(codec, reg, hs_ctl); | |
618 | hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN; | |
619 | twl4030_write(codec, reg, hs_ctl); | |
620 | udelay(40); | |
621 | hs_ctl &= ~TWL4030_HF_CTL_REF_EN; | |
622 | twl4030_write(codec, reg, hs_ctl); | |
49d92c7d | 623 | } |
5a2e9a48 | 624 | } |
49d92c7d | 625 | |
5a2e9a48 PU |
626 | static int handsfreelpga_event(struct snd_soc_dapm_widget *w, |
627 | struct snd_kcontrol *kcontrol, int event) | |
628 | { | |
629 | switch (event) { | |
630 | case SND_SOC_DAPM_POST_PMU: | |
631 | handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1); | |
632 | break; | |
633 | case SND_SOC_DAPM_POST_PMD: | |
634 | handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0); | |
635 | break; | |
636 | } | |
637 | return 0; | |
638 | } | |
639 | ||
640 | static int handsfreerpga_event(struct snd_soc_dapm_widget *w, | |
641 | struct snd_kcontrol *kcontrol, int event) | |
642 | { | |
643 | switch (event) { | |
644 | case SND_SOC_DAPM_POST_PMU: | |
645 | handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1); | |
646 | break; | |
647 | case SND_SOC_DAPM_POST_PMD: | |
648 | handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0); | |
649 | break; | |
650 | } | |
49d92c7d SM |
651 | return 0; |
652 | } | |
653 | ||
86139a13 JV |
654 | static int vibramux_event(struct snd_soc_dapm_widget *w, |
655 | struct snd_kcontrol *kcontrol, int event) | |
656 | { | |
657 | twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff); | |
658 | return 0; | |
659 | } | |
660 | ||
7729cf74 PU |
661 | static int apll_event(struct snd_soc_dapm_widget *w, |
662 | struct snd_kcontrol *kcontrol, int event) | |
663 | { | |
664 | switch (event) { | |
665 | case SND_SOC_DAPM_PRE_PMU: | |
666 | twl4030_apll_enable(w->codec, 1); | |
667 | break; | |
668 | case SND_SOC_DAPM_POST_PMD: | |
669 | twl4030_apll_enable(w->codec, 0); | |
670 | break; | |
671 | } | |
672 | return 0; | |
673 | } | |
674 | ||
6943c92e | 675 | static void headset_ramp(struct snd_soc_codec *codec, int ramp) |
aad749e5 | 676 | { |
4e49ffd1 CVJ |
677 | struct snd_soc_device *socdev = codec->socdev; |
678 | struct twl4030_setup_data *setup = socdev->codec_data; | |
679 | ||
aad749e5 | 680 | unsigned char hs_gain, hs_pop; |
b2c812e2 | 681 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
6943c92e PU |
682 | /* Base values for ramp delay calculation: 2^19 - 2^26 */ |
683 | unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304, | |
684 | 8388608, 16777216, 33554432, 67108864}; | |
aad749e5 | 685 | |
6943c92e PU |
686 | hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET); |
687 | hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); | |
aad749e5 | 688 | |
4e49ffd1 CVJ |
689 | /* Enable external mute control, this dramatically reduces |
690 | * the pop-noise */ | |
691 | if (setup && setup->hs_extmute) { | |
692 | if (setup->set_hs_extmute) { | |
693 | setup->set_hs_extmute(1); | |
694 | } else { | |
695 | hs_pop |= TWL4030_EXTMUTE; | |
696 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
697 | } | |
698 | } | |
699 | ||
6943c92e PU |
700 | if (ramp) { |
701 | /* Headset ramp-up according to the TRM */ | |
aad749e5 | 702 | hs_pop |= TWL4030_VMID_EN; |
6943c92e | 703 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
c96907f2 PU |
704 | /* Actually write to the register */ |
705 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, | |
706 | hs_gain, | |
707 | TWL4030_REG_HS_GAIN_SET); | |
aad749e5 | 708 | hs_pop |= TWL4030_RAMP_EN; |
6943c92e | 709 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
4e49ffd1 CVJ |
710 | /* Wait ramp delay time + 1, so the VMID can settle */ |
711 | mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / | |
712 | twl4030->sysclk) + 1); | |
6943c92e PU |
713 | } else { |
714 | /* Headset ramp-down _not_ according to | |
715 | * the TRM, but in a way that it is working */ | |
aad749e5 | 716 | hs_pop &= ~TWL4030_RAMP_EN; |
6943c92e PU |
717 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
718 | /* Wait ramp delay time + 1, so the VMID can settle */ | |
719 | mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / | |
720 | twl4030->sysclk) + 1); | |
aad749e5 | 721 | /* Bypass the reg_cache to mute the headset */ |
fc7b92fc | 722 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, |
aad749e5 PU |
723 | hs_gain & (~0x0f), |
724 | TWL4030_REG_HS_GAIN_SET); | |
6943c92e | 725 | |
aad749e5 | 726 | hs_pop &= ~TWL4030_VMID_EN; |
6943c92e PU |
727 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
728 | } | |
4e49ffd1 CVJ |
729 | |
730 | /* Disable external mute */ | |
731 | if (setup && setup->hs_extmute) { | |
732 | if (setup->set_hs_extmute) { | |
733 | setup->set_hs_extmute(0); | |
734 | } else { | |
735 | hs_pop &= ~TWL4030_EXTMUTE; | |
736 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
737 | } | |
738 | } | |
6943c92e PU |
739 | } |
740 | ||
741 | static int headsetlpga_event(struct snd_soc_dapm_widget *w, | |
742 | struct snd_kcontrol *kcontrol, int event) | |
743 | { | |
b2c812e2 | 744 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); |
6943c92e PU |
745 | |
746 | switch (event) { | |
747 | case SND_SOC_DAPM_POST_PMU: | |
748 | /* Do the ramp-up only once */ | |
749 | if (!twl4030->hsr_enabled) | |
750 | headset_ramp(w->codec, 1); | |
751 | ||
752 | twl4030->hsl_enabled = 1; | |
753 | break; | |
754 | case SND_SOC_DAPM_POST_PMD: | |
755 | /* Do the ramp-down only if both headsetL/R is disabled */ | |
756 | if (!twl4030->hsr_enabled) | |
757 | headset_ramp(w->codec, 0); | |
758 | ||
759 | twl4030->hsl_enabled = 0; | |
760 | break; | |
761 | } | |
762 | return 0; | |
763 | } | |
764 | ||
765 | static int headsetrpga_event(struct snd_soc_dapm_widget *w, | |
766 | struct snd_kcontrol *kcontrol, int event) | |
767 | { | |
b2c812e2 | 768 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); |
6943c92e PU |
769 | |
770 | switch (event) { | |
771 | case SND_SOC_DAPM_POST_PMU: | |
772 | /* Do the ramp-up only once */ | |
773 | if (!twl4030->hsl_enabled) | |
774 | headset_ramp(w->codec, 1); | |
775 | ||
776 | twl4030->hsr_enabled = 1; | |
777 | break; | |
778 | case SND_SOC_DAPM_POST_PMD: | |
779 | /* Do the ramp-down only if both headsetL/R is disabled */ | |
780 | if (!twl4030->hsl_enabled) | |
781 | headset_ramp(w->codec, 0); | |
782 | ||
783 | twl4030->hsr_enabled = 0; | |
aad749e5 PU |
784 | break; |
785 | } | |
786 | return 0; | |
787 | } | |
788 | ||
b0bd53a7 PU |
789 | /* |
790 | * Some of the gain controls in TWL (mostly those which are associated with | |
791 | * the outputs) are implemented in an interesting way: | |
792 | * 0x0 : Power down (mute) | |
793 | * 0x1 : 6dB | |
794 | * 0x2 : 0 dB | |
795 | * 0x3 : -6 dB | |
796 | * Inverting not going to help with these. | |
797 | * Custom volsw and volsw_2r get/put functions to handle these gain bits. | |
798 | */ | |
799 | #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\ | |
800 | xinvert, tlv_array) \ | |
801 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ | |
802 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | |
803 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | |
804 | .tlv.p = (tlv_array), \ | |
805 | .info = snd_soc_info_volsw, \ | |
806 | .get = snd_soc_get_volsw_twl4030, \ | |
807 | .put = snd_soc_put_volsw_twl4030, \ | |
808 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
809 | {.reg = xreg, .shift = shift_left, .rshift = shift_right,\ | |
810 | .max = xmax, .invert = xinvert} } | |
811 | #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\ | |
812 | xinvert, tlv_array) \ | |
813 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ | |
814 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ | |
815 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ | |
816 | .tlv.p = (tlv_array), \ | |
817 | .info = snd_soc_info_volsw_2r, \ | |
818 | .get = snd_soc_get_volsw_r2_twl4030,\ | |
819 | .put = snd_soc_put_volsw_r2_twl4030, \ | |
820 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
821 | {.reg = reg_left, .rreg = reg_right, .shift = xshift, \ | |
64089b84 | 822 | .rshift = xshift, .max = xmax, .invert = xinvert} } |
b0bd53a7 PU |
823 | #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \ |
824 | SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \ | |
825 | xinvert, tlv_array) | |
826 | ||
827 | static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
828 | struct snd_ctl_elem_value *ucontrol) | |
829 | { | |
830 | struct soc_mixer_control *mc = | |
831 | (struct soc_mixer_control *)kcontrol->private_value; | |
832 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
833 | unsigned int reg = mc->reg; | |
834 | unsigned int shift = mc->shift; | |
835 | unsigned int rshift = mc->rshift; | |
836 | int max = mc->max; | |
837 | int mask = (1 << fls(max)) - 1; | |
838 | ||
839 | ucontrol->value.integer.value[0] = | |
840 | (snd_soc_read(codec, reg) >> shift) & mask; | |
841 | if (ucontrol->value.integer.value[0]) | |
842 | ucontrol->value.integer.value[0] = | |
843 | max + 1 - ucontrol->value.integer.value[0]; | |
844 | ||
845 | if (shift != rshift) { | |
846 | ucontrol->value.integer.value[1] = | |
847 | (snd_soc_read(codec, reg) >> rshift) & mask; | |
848 | if (ucontrol->value.integer.value[1]) | |
849 | ucontrol->value.integer.value[1] = | |
850 | max + 1 - ucontrol->value.integer.value[1]; | |
851 | } | |
852 | ||
853 | return 0; | |
854 | } | |
855 | ||
856 | static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
857 | struct snd_ctl_elem_value *ucontrol) | |
858 | { | |
859 | struct soc_mixer_control *mc = | |
860 | (struct soc_mixer_control *)kcontrol->private_value; | |
861 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
862 | unsigned int reg = mc->reg; | |
863 | unsigned int shift = mc->shift; | |
864 | unsigned int rshift = mc->rshift; | |
865 | int max = mc->max; | |
866 | int mask = (1 << fls(max)) - 1; | |
867 | unsigned short val, val2, val_mask; | |
868 | ||
869 | val = (ucontrol->value.integer.value[0] & mask); | |
870 | ||
871 | val_mask = mask << shift; | |
872 | if (val) | |
873 | val = max + 1 - val; | |
874 | val = val << shift; | |
875 | if (shift != rshift) { | |
876 | val2 = (ucontrol->value.integer.value[1] & mask); | |
877 | val_mask |= mask << rshift; | |
878 | if (val2) | |
879 | val2 = max + 1 - val2; | |
880 | val |= val2 << rshift; | |
881 | } | |
882 | return snd_soc_update_bits(codec, reg, val_mask, val); | |
883 | } | |
884 | ||
885 | static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
886 | struct snd_ctl_elem_value *ucontrol) | |
887 | { | |
888 | struct soc_mixer_control *mc = | |
889 | (struct soc_mixer_control *)kcontrol->private_value; | |
890 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
891 | unsigned int reg = mc->reg; | |
892 | unsigned int reg2 = mc->rreg; | |
893 | unsigned int shift = mc->shift; | |
894 | int max = mc->max; | |
895 | int mask = (1<<fls(max))-1; | |
896 | ||
897 | ucontrol->value.integer.value[0] = | |
898 | (snd_soc_read(codec, reg) >> shift) & mask; | |
899 | ucontrol->value.integer.value[1] = | |
900 | (snd_soc_read(codec, reg2) >> shift) & mask; | |
901 | ||
902 | if (ucontrol->value.integer.value[0]) | |
903 | ucontrol->value.integer.value[0] = | |
904 | max + 1 - ucontrol->value.integer.value[0]; | |
905 | if (ucontrol->value.integer.value[1]) | |
906 | ucontrol->value.integer.value[1] = | |
907 | max + 1 - ucontrol->value.integer.value[1]; | |
908 | ||
909 | return 0; | |
910 | } | |
911 | ||
912 | static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
913 | struct snd_ctl_elem_value *ucontrol) | |
914 | { | |
915 | struct soc_mixer_control *mc = | |
916 | (struct soc_mixer_control *)kcontrol->private_value; | |
917 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
918 | unsigned int reg = mc->reg; | |
919 | unsigned int reg2 = mc->rreg; | |
920 | unsigned int shift = mc->shift; | |
921 | int max = mc->max; | |
922 | int mask = (1 << fls(max)) - 1; | |
923 | int err; | |
924 | unsigned short val, val2, val_mask; | |
925 | ||
926 | val_mask = mask << shift; | |
927 | val = (ucontrol->value.integer.value[0] & mask); | |
928 | val2 = (ucontrol->value.integer.value[1] & mask); | |
929 | ||
930 | if (val) | |
931 | val = max + 1 - val; | |
932 | if (val2) | |
933 | val2 = max + 1 - val2; | |
934 | ||
935 | val = val << shift; | |
936 | val2 = val2 << shift; | |
937 | ||
938 | err = snd_soc_update_bits(codec, reg, val_mask, val); | |
939 | if (err < 0) | |
940 | return err; | |
941 | ||
942 | err = snd_soc_update_bits(codec, reg2, val_mask, val2); | |
943 | return err; | |
944 | } | |
945 | ||
b74bd40f LCM |
946 | /* Codec operation modes */ |
947 | static const char *twl4030_op_modes_texts[] = { | |
948 | "Option 2 (voice/audio)", "Option 1 (audio)" | |
949 | }; | |
950 | ||
951 | static const struct soc_enum twl4030_op_modes_enum = | |
952 | SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0, | |
953 | ARRAY_SIZE(twl4030_op_modes_texts), | |
954 | twl4030_op_modes_texts); | |
955 | ||
423c238d | 956 | static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol, |
b74bd40f LCM |
957 | struct snd_ctl_elem_value *ucontrol) |
958 | { | |
959 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 960 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
b74bd40f LCM |
961 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
962 | unsigned short val; | |
963 | unsigned short mask, bitmask; | |
964 | ||
965 | if (twl4030->configured) { | |
966 | printk(KERN_ERR "twl4030 operation mode cannot be " | |
967 | "changed on-the-fly\n"); | |
968 | return -EBUSY; | |
969 | } | |
970 | ||
971 | for (bitmask = 1; bitmask < e->max; bitmask <<= 1) | |
972 | ; | |
973 | if (ucontrol->value.enumerated.item[0] > e->max - 1) | |
974 | return -EINVAL; | |
975 | ||
976 | val = ucontrol->value.enumerated.item[0] << e->shift_l; | |
977 | mask = (bitmask - 1) << e->shift_l; | |
978 | if (e->shift_l != e->shift_r) { | |
979 | if (ucontrol->value.enumerated.item[1] > e->max - 1) | |
980 | return -EINVAL; | |
981 | val |= ucontrol->value.enumerated.item[1] << e->shift_r; | |
982 | mask |= (bitmask - 1) << e->shift_r; | |
983 | } | |
984 | ||
985 | return snd_soc_update_bits(codec, e->reg, mask, val); | |
986 | } | |
987 | ||
c10b82cf PU |
988 | /* |
989 | * FGAIN volume control: | |
990 | * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB) | |
991 | */ | |
d889a72c | 992 | static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1); |
c10b82cf | 993 | |
0d33ea0b PU |
994 | /* |
995 | * CGAIN volume control: | |
996 | * 0 dB to 12 dB in 6 dB steps | |
997 | * value 2 and 3 means 12 dB | |
998 | */ | |
d889a72c PU |
999 | static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0); |
1000 | ||
1a787e7a JS |
1001 | /* |
1002 | * Voice Downlink GAIN volume control: | |
1003 | * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB) | |
1004 | */ | |
1005 | static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1); | |
1006 | ||
d889a72c PU |
1007 | /* |
1008 | * Analog playback gain | |
1009 | * -24 dB to 12 dB in 2 dB steps | |
1010 | */ | |
1011 | static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0); | |
0d33ea0b | 1012 | |
4290239c PU |
1013 | /* |
1014 | * Gain controls tied to outputs | |
1015 | * -6 dB to 6 dB in 6 dB steps (mute instead of -12) | |
1016 | */ | |
1017 | static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1); | |
1018 | ||
18cc8d8d JS |
1019 | /* |
1020 | * Gain control for earpiece amplifier | |
1021 | * 0 dB to 12 dB in 6 dB steps (mute instead of -6) | |
1022 | */ | |
1023 | static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1); | |
1024 | ||
381a22b5 PU |
1025 | /* |
1026 | * Capture gain after the ADCs | |
1027 | * from 0 dB to 31 dB in 1 dB steps | |
1028 | */ | |
1029 | static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0); | |
1030 | ||
5920b453 GI |
1031 | /* |
1032 | * Gain control for input amplifiers | |
1033 | * 0 dB to 30 dB in 6 dB steps | |
1034 | */ | |
1035 | static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0); | |
1036 | ||
328d0a13 LCM |
1037 | /* AVADC clock priority */ |
1038 | static const char *twl4030_avadc_clk_priority_texts[] = { | |
1039 | "Voice high priority", "HiFi high priority" | |
1040 | }; | |
1041 | ||
1042 | static const struct soc_enum twl4030_avadc_clk_priority_enum = | |
1043 | SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2, | |
1044 | ARRAY_SIZE(twl4030_avadc_clk_priority_texts), | |
1045 | twl4030_avadc_clk_priority_texts); | |
1046 | ||
89492be8 PU |
1047 | static const char *twl4030_rampdelay_texts[] = { |
1048 | "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms", | |
1049 | "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms", | |
1050 | "3495/2581/1748 ms" | |
1051 | }; | |
1052 | ||
1053 | static const struct soc_enum twl4030_rampdelay_enum = | |
1054 | SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2, | |
1055 | ARRAY_SIZE(twl4030_rampdelay_texts), | |
1056 | twl4030_rampdelay_texts); | |
1057 | ||
376f7839 PU |
1058 | /* Vibra H-bridge direction mode */ |
1059 | static const char *twl4030_vibradirmode_texts[] = { | |
1060 | "Vibra H-bridge direction", "Audio data MSB", | |
1061 | }; | |
1062 | ||
1063 | static const struct soc_enum twl4030_vibradirmode_enum = | |
1064 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5, | |
1065 | ARRAY_SIZE(twl4030_vibradirmode_texts), | |
1066 | twl4030_vibradirmode_texts); | |
1067 | ||
1068 | /* Vibra H-bridge direction */ | |
1069 | static const char *twl4030_vibradir_texts[] = { | |
1070 | "Positive polarity", "Negative polarity", | |
1071 | }; | |
1072 | ||
1073 | static const struct soc_enum twl4030_vibradir_enum = | |
1074 | SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1, | |
1075 | ARRAY_SIZE(twl4030_vibradir_texts), | |
1076 | twl4030_vibradir_texts); | |
1077 | ||
cc17557e | 1078 | static const struct snd_kcontrol_new twl4030_snd_controls[] = { |
b74bd40f LCM |
1079 | /* Codec operation mode control */ |
1080 | SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum, | |
1081 | snd_soc_get_enum_double, | |
1082 | snd_soc_put_twl4030_opmode_enum_double), | |
1083 | ||
d889a72c PU |
1084 | /* Common playback gain controls */ |
1085 | SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume", | |
1086 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
1087 | 0, 0x3f, 0, digital_fine_tlv), | |
1088 | SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume", | |
1089 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
1090 | 0, 0x3f, 0, digital_fine_tlv), | |
1091 | ||
1092 | SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume", | |
1093 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
1094 | 6, 0x2, 0, digital_coarse_tlv), | |
1095 | SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume", | |
1096 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
1097 | 6, 0x2, 0, digital_coarse_tlv), | |
1098 | ||
1099 | SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume", | |
1100 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
1101 | 3, 0x12, 1, analog_tlv), | |
1102 | SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume", | |
1103 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
1104 | 3, 0x12, 1, analog_tlv), | |
44c55870 PU |
1105 | SOC_DOUBLE_R("DAC1 Analog Playback Switch", |
1106 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
1107 | 1, 1, 0), | |
1108 | SOC_DOUBLE_R("DAC2 Analog Playback Switch", | |
1109 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
1110 | 1, 1, 0), | |
381a22b5 | 1111 | |
1a787e7a JS |
1112 | /* Common voice downlink gain controls */ |
1113 | SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume", | |
1114 | TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv), | |
1115 | ||
1116 | SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume", | |
1117 | TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv), | |
1118 | ||
1119 | SOC_SINGLE("DAC Voice Analog Downlink Switch", | |
1120 | TWL4030_REG_VDL_APGA_CTL, 1, 1, 0), | |
1121 | ||
4290239c PU |
1122 | /* Separate output gain controls */ |
1123 | SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume", | |
1124 | TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL, | |
1125 | 4, 3, 0, output_tvl), | |
1126 | ||
1127 | SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume", | |
1128 | TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl), | |
1129 | ||
1130 | SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume", | |
1131 | TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL, | |
1132 | 4, 3, 0, output_tvl), | |
1133 | ||
1134 | SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume", | |
18cc8d8d | 1135 | TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl), |
4290239c | 1136 | |
381a22b5 | 1137 | /* Common capture gain controls */ |
276c6222 | 1138 | SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume", |
381a22b5 PU |
1139 | TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA, |
1140 | 0, 0x1f, 0, digital_capture_tlv), | |
276c6222 PU |
1141 | SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume", |
1142 | TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA, | |
1143 | 0, 0x1f, 0, digital_capture_tlv), | |
5920b453 | 1144 | |
276c6222 | 1145 | SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN, |
5920b453 | 1146 | 0, 3, 5, 0, input_gain_tlv), |
89492be8 | 1147 | |
328d0a13 LCM |
1148 | SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum), |
1149 | ||
89492be8 | 1150 | SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum), |
376f7839 PU |
1151 | |
1152 | SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum), | |
1153 | SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum), | |
cc17557e SS |
1154 | }; |
1155 | ||
cc17557e | 1156 | static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { |
276c6222 PU |
1157 | /* Left channel inputs */ |
1158 | SND_SOC_DAPM_INPUT("MAINMIC"), | |
1159 | SND_SOC_DAPM_INPUT("HSMIC"), | |
1160 | SND_SOC_DAPM_INPUT("AUXL"), | |
1161 | SND_SOC_DAPM_INPUT("CARKITMIC"), | |
1162 | /* Right channel inputs */ | |
1163 | SND_SOC_DAPM_INPUT("SUBMIC"), | |
1164 | SND_SOC_DAPM_INPUT("AUXR"), | |
1165 | /* Digital microphones (Stereo) */ | |
1166 | SND_SOC_DAPM_INPUT("DIGIMIC0"), | |
1167 | SND_SOC_DAPM_INPUT("DIGIMIC1"), | |
1168 | ||
1169 | /* Outputs */ | |
cc17557e SS |
1170 | SND_SOC_DAPM_OUTPUT("OUTL"), |
1171 | SND_SOC_DAPM_OUTPUT("OUTR"), | |
5e98a464 | 1172 | SND_SOC_DAPM_OUTPUT("EARPIECE"), |
2a6f5c58 PU |
1173 | SND_SOC_DAPM_OUTPUT("PREDRIVEL"), |
1174 | SND_SOC_DAPM_OUTPUT("PREDRIVER"), | |
dfad21a2 PU |
1175 | SND_SOC_DAPM_OUTPUT("HSOL"), |
1176 | SND_SOC_DAPM_OUTPUT("HSOR"), | |
6a1bee4a PU |
1177 | SND_SOC_DAPM_OUTPUT("CARKITL"), |
1178 | SND_SOC_DAPM_OUTPUT("CARKITR"), | |
df339804 PU |
1179 | SND_SOC_DAPM_OUTPUT("HFL"), |
1180 | SND_SOC_DAPM_OUTPUT("HFR"), | |
376f7839 | 1181 | SND_SOC_DAPM_OUTPUT("VIBRA"), |
cc17557e | 1182 | |
53b5047d | 1183 | /* DACs */ |
b4852b79 | 1184 | SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback", |
7393958f | 1185 | SND_SOC_NOPM, 0, 0), |
b4852b79 | 1186 | SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback", |
7393958f | 1187 | SND_SOC_NOPM, 0, 0), |
b4852b79 | 1188 | SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback", |
7393958f | 1189 | SND_SOC_NOPM, 0, 0), |
b4852b79 | 1190 | SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback", |
7393958f | 1191 | SND_SOC_NOPM, 0, 0), |
1a787e7a | 1192 | SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback", |
fcd274a3 | 1193 | SND_SOC_NOPM, 0, 0), |
cc17557e | 1194 | |
7393958f | 1195 | /* Analog bypasses */ |
78e08e2f PU |
1196 | SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0, |
1197 | &twl4030_dapm_abypassr1_control), | |
1198 | SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1199 | &twl4030_dapm_abypassl1_control), | |
1200 | SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1201 | &twl4030_dapm_abypassr2_control), | |
1202 | SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1203 | &twl4030_dapm_abypassl2_control), | |
1204 | SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1205 | &twl4030_dapm_abypassv_control), | |
1206 | ||
1207 | /* Master analog loopback switch */ | |
1208 | SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0, | |
1209 | NULL, 0), | |
7393958f | 1210 | |
6bab83fd | 1211 | /* Digital bypasses */ |
78e08e2f PU |
1212 | SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0, |
1213 | &twl4030_dapm_dbypassl_control), | |
1214 | SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0, | |
1215 | &twl4030_dapm_dbypassr_control), | |
1216 | SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0, | |
1217 | &twl4030_dapm_dbypassv_control), | |
6bab83fd | 1218 | |
4005d39a PU |
1219 | /* Digital mixers, power control for the physical DACs */ |
1220 | SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer", | |
1221 | TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0), | |
1222 | SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer", | |
1223 | TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0), | |
1224 | SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer", | |
1225 | TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0), | |
1226 | SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer", | |
1227 | TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0), | |
1228 | SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer", | |
1229 | TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0), | |
1230 | ||
1231 | /* Analog mixers, power control for the physical PGAs */ | |
1232 | SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", | |
1233 | TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0), | |
1234 | SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", | |
1235 | TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0), | |
1236 | SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", | |
1237 | TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0), | |
1238 | SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", | |
1239 | TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0), | |
1240 | SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer", | |
1241 | TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0), | |
7393958f | 1242 | |
7729cf74 PU |
1243 | SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event, |
1244 | SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD), | |
1245 | ||
c42a59ea PU |
1246 | SND_SOC_DAPM_SUPPLY("AIF Enable", TWL4030_REG_AUDIO_IF, 0, 0, NULL, 0), |
1247 | ||
1a787e7a | 1248 | /* Output MIXER controls */ |
5e98a464 | 1249 | /* Earpiece */ |
1a787e7a JS |
1250 | SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0, |
1251 | &twl4030_dapm_earpiece_controls[0], | |
1252 | ARRAY_SIZE(twl4030_dapm_earpiece_controls)), | |
9008adf9 PU |
1253 | SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM, |
1254 | 0, 0, NULL, 0, earpiecepga_event, | |
1255 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
2a6f5c58 | 1256 | /* PreDrivL/R */ |
1a787e7a JS |
1257 | SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0, |
1258 | &twl4030_dapm_predrivel_controls[0], | |
1259 | ARRAY_SIZE(twl4030_dapm_predrivel_controls)), | |
9008adf9 PU |
1260 | SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM, |
1261 | 0, 0, NULL, 0, predrivelpga_event, | |
1262 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1263 | SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0, |
1264 | &twl4030_dapm_predriver_controls[0], | |
1265 | ARRAY_SIZE(twl4030_dapm_predriver_controls)), | |
9008adf9 PU |
1266 | SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM, |
1267 | 0, 0, NULL, 0, predriverpga_event, | |
1268 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
dfad21a2 | 1269 | /* HeadsetL/R */ |
6943c92e | 1270 | SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0, |
1a787e7a | 1271 | &twl4030_dapm_hsol_controls[0], |
6943c92e PU |
1272 | ARRAY_SIZE(twl4030_dapm_hsol_controls)), |
1273 | SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM, | |
1274 | 0, 0, NULL, 0, headsetlpga_event, | |
1a787e7a JS |
1275 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), |
1276 | SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0, | |
1277 | &twl4030_dapm_hsor_controls[0], | |
1278 | ARRAY_SIZE(twl4030_dapm_hsor_controls)), | |
6943c92e PU |
1279 | SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM, |
1280 | 0, 0, NULL, 0, headsetrpga_event, | |
1281 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
5152d8c2 | 1282 | /* CarkitL/R */ |
1a787e7a JS |
1283 | SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0, |
1284 | &twl4030_dapm_carkitl_controls[0], | |
1285 | ARRAY_SIZE(twl4030_dapm_carkitl_controls)), | |
9008adf9 PU |
1286 | SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM, |
1287 | 0, 0, NULL, 0, carkitlpga_event, | |
1288 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1289 | SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0, |
1290 | &twl4030_dapm_carkitr_controls[0], | |
1291 | ARRAY_SIZE(twl4030_dapm_carkitr_controls)), | |
9008adf9 PU |
1292 | SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM, |
1293 | 0, 0, NULL, 0, carkitrpga_event, | |
1294 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1295 | |
1296 | /* Output MUX controls */ | |
df339804 | 1297 | /* HandsfreeL/R */ |
5a2e9a48 PU |
1298 | SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0, |
1299 | &twl4030_dapm_handsfreel_control), | |
e3c7dbb0 | 1300 | SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0, |
0f89bdca | 1301 | &twl4030_dapm_handsfreelmute_control), |
5a2e9a48 PU |
1302 | SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM, |
1303 | 0, 0, NULL, 0, handsfreelpga_event, | |
1304 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1305 | SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0, | |
1306 | &twl4030_dapm_handsfreer_control), | |
e3c7dbb0 | 1307 | SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0, |
0f89bdca | 1308 | &twl4030_dapm_handsfreermute_control), |
5a2e9a48 PU |
1309 | SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM, |
1310 | 0, 0, NULL, 0, handsfreerpga_event, | |
1311 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
376f7839 | 1312 | /* Vibra */ |
86139a13 JV |
1313 | SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0, |
1314 | &twl4030_dapm_vibra_control, vibramux_event, | |
1315 | SND_SOC_DAPM_PRE_PMU), | |
376f7839 PU |
1316 | SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0, |
1317 | &twl4030_dapm_vibrapath_control), | |
5e98a464 | 1318 | |
276c6222 PU |
1319 | /* Introducing four virtual ADC, since TWL4030 have four channel for |
1320 | capture */ | |
1321 | SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture", | |
1322 | SND_SOC_NOPM, 0, 0), | |
1323 | SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture", | |
1324 | SND_SOC_NOPM, 0, 0), | |
1325 | SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture", | |
1326 | SND_SOC_NOPM, 0, 0), | |
1327 | SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture", | |
1328 | SND_SOC_NOPM, 0, 0), | |
1329 | ||
1330 | /* Analog/Digital mic path selection. | |
1331 | TX1 Left/Right: either analog Left/Right or Digimic0 | |
1332 | TX2 Left/Right: either analog Left/Right or Digimic1 */ | |
1333 | SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0, | |
1334 | &twl4030_dapm_micpathtx1_control, micpath_event, | |
1335 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| | |
1336 | SND_SOC_DAPM_POST_REG), | |
1337 | SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0, | |
1338 | &twl4030_dapm_micpathtx2_control, micpath_event, | |
1339 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD| | |
1340 | SND_SOC_DAPM_POST_REG), | |
1341 | ||
97b8096d | 1342 | /* Analog input mixers for the capture amplifiers */ |
9028935d | 1343 | SND_SOC_DAPM_MIXER("Analog Left", |
97b8096d JS |
1344 | TWL4030_REG_ANAMICL, 4, 0, |
1345 | &twl4030_dapm_analoglmic_controls[0], | |
1346 | ARRAY_SIZE(twl4030_dapm_analoglmic_controls)), | |
9028935d | 1347 | SND_SOC_DAPM_MIXER("Analog Right", |
97b8096d JS |
1348 | TWL4030_REG_ANAMICR, 4, 0, |
1349 | &twl4030_dapm_analogrmic_controls[0], | |
1350 | ARRAY_SIZE(twl4030_dapm_analogrmic_controls)), | |
276c6222 | 1351 | |
fb2a2f84 PU |
1352 | SND_SOC_DAPM_PGA("ADC Physical Left", |
1353 | TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0), | |
1354 | SND_SOC_DAPM_PGA("ADC Physical Right", | |
1355 | TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0), | |
276c6222 PU |
1356 | |
1357 | SND_SOC_DAPM_PGA("Digimic0 Enable", | |
1358 | TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0), | |
1359 | SND_SOC_DAPM_PGA("Digimic1 Enable", | |
1360 | TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0), | |
1361 | ||
1362 | SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0), | |
1363 | SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0), | |
1364 | SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0), | |
7393958f | 1365 | |
cc17557e SS |
1366 | }; |
1367 | ||
1368 | static const struct snd_soc_dapm_route intercon[] = { | |
4005d39a PU |
1369 | {"Digital L1 Playback Mixer", NULL, "DAC Left1"}, |
1370 | {"Digital R1 Playback Mixer", NULL, "DAC Right1"}, | |
1371 | {"Digital L2 Playback Mixer", NULL, "DAC Left2"}, | |
1372 | {"Digital R2 Playback Mixer", NULL, "DAC Right2"}, | |
1373 | {"Digital Voice Playback Mixer", NULL, "DAC Voice"}, | |
1374 | ||
7729cf74 PU |
1375 | /* Supply for the digital part (APLL) */ |
1376 | {"Digital R1 Playback Mixer", NULL, "APLL Enable"}, | |
1377 | {"Digital L1 Playback Mixer", NULL, "APLL Enable"}, | |
1378 | {"Digital R2 Playback Mixer", NULL, "APLL Enable"}, | |
1379 | {"Digital L2 Playback Mixer", NULL, "APLL Enable"}, | |
1380 | {"Digital Voice Playback Mixer", NULL, "APLL Enable"}, | |
1381 | ||
c42a59ea PU |
1382 | {"Digital R1 Playback Mixer", NULL, "AIF Enable"}, |
1383 | {"Digital L1 Playback Mixer", NULL, "AIF Enable"}, | |
1384 | {"Digital R2 Playback Mixer", NULL, "AIF Enable"}, | |
1385 | {"Digital L2 Playback Mixer", NULL, "AIF Enable"}, | |
1386 | ||
4005d39a PU |
1387 | {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"}, |
1388 | {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"}, | |
1389 | {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"}, | |
1390 | {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"}, | |
1391 | {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"}, | |
1a787e7a | 1392 | |
5e98a464 PU |
1393 | /* Internal playback routings */ |
1394 | /* Earpiece */ | |
4005d39a PU |
1395 | {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1396 | {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1397 | {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
1398 | {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
9008adf9 | 1399 | {"Earpiece PGA", NULL, "Earpiece Mixer"}, |
2a6f5c58 | 1400 | /* PreDrivL */ |
4005d39a PU |
1401 | {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1402 | {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1403 | {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
1404 | {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
9008adf9 | 1405 | {"PredriveL PGA", NULL, "PredriveL Mixer"}, |
2a6f5c58 | 1406 | /* PreDrivR */ |
4005d39a PU |
1407 | {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1408 | {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1409 | {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
1410 | {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
9008adf9 | 1411 | {"PredriveR PGA", NULL, "PredriveR Mixer"}, |
dfad21a2 | 1412 | /* HeadsetL */ |
4005d39a PU |
1413 | {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1414 | {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1415 | {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
6943c92e | 1416 | {"HeadsetL PGA", NULL, "HeadsetL Mixer"}, |
dfad21a2 | 1417 | /* HeadsetR */ |
4005d39a PU |
1418 | {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1419 | {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1420 | {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
6943c92e | 1421 | {"HeadsetR PGA", NULL, "HeadsetR Mixer"}, |
5152d8c2 | 1422 | /* CarkitL */ |
4005d39a PU |
1423 | {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1424 | {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1425 | {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
9008adf9 | 1426 | {"CarkitL PGA", NULL, "CarkitL Mixer"}, |
5152d8c2 | 1427 | /* CarkitR */ |
4005d39a PU |
1428 | {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1429 | {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1430 | {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
9008adf9 | 1431 | {"CarkitR PGA", NULL, "CarkitR Mixer"}, |
df339804 | 1432 | /* HandsfreeL */ |
4005d39a PU |
1433 | {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"}, |
1434 | {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"}, | |
1435 | {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"}, | |
1436 | {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"}, | |
e3c7dbb0 LCM |
1437 | {"HandsfreeL", "Switch", "HandsfreeL Mux"}, |
1438 | {"HandsfreeL PGA", NULL, "HandsfreeL"}, | |
df339804 | 1439 | /* HandsfreeR */ |
4005d39a PU |
1440 | {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"}, |
1441 | {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"}, | |
1442 | {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"}, | |
1443 | {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"}, | |
e3c7dbb0 LCM |
1444 | {"HandsfreeR", "Switch", "HandsfreeR Mux"}, |
1445 | {"HandsfreeR PGA", NULL, "HandsfreeR"}, | |
376f7839 PU |
1446 | /* Vibra */ |
1447 | {"Vibra Mux", "AudioL1", "DAC Left1"}, | |
1448 | {"Vibra Mux", "AudioR1", "DAC Right1"}, | |
1449 | {"Vibra Mux", "AudioL2", "DAC Left2"}, | |
1450 | {"Vibra Mux", "AudioR2", "DAC Right2"}, | |
5e98a464 | 1451 | |
cc17557e | 1452 | /* outputs */ |
4005d39a PU |
1453 | {"OUTL", NULL, "Analog L2 Playback Mixer"}, |
1454 | {"OUTR", NULL, "Analog R2 Playback Mixer"}, | |
9008adf9 PU |
1455 | {"EARPIECE", NULL, "Earpiece PGA"}, |
1456 | {"PREDRIVEL", NULL, "PredriveL PGA"}, | |
1457 | {"PREDRIVER", NULL, "PredriveR PGA"}, | |
6943c92e PU |
1458 | {"HSOL", NULL, "HeadsetL PGA"}, |
1459 | {"HSOR", NULL, "HeadsetR PGA"}, | |
9008adf9 PU |
1460 | {"CARKITL", NULL, "CarkitL PGA"}, |
1461 | {"CARKITR", NULL, "CarkitR PGA"}, | |
5a2e9a48 PU |
1462 | {"HFL", NULL, "HandsfreeL PGA"}, |
1463 | {"HFR", NULL, "HandsfreeR PGA"}, | |
376f7839 PU |
1464 | {"Vibra Route", "Audio", "Vibra Mux"}, |
1465 | {"VIBRA", NULL, "Vibra Route"}, | |
cc17557e | 1466 | |
276c6222 | 1467 | /* Capture path */ |
9028935d PU |
1468 | {"Analog Left", "Main Mic Capture Switch", "MAINMIC"}, |
1469 | {"Analog Left", "Headset Mic Capture Switch", "HSMIC"}, | |
1470 | {"Analog Left", "AUXL Capture Switch", "AUXL"}, | |
1471 | {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"}, | |
276c6222 | 1472 | |
9028935d PU |
1473 | {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"}, |
1474 | {"Analog Right", "AUXR Capture Switch", "AUXR"}, | |
276c6222 | 1475 | |
9028935d PU |
1476 | {"ADC Physical Left", NULL, "Analog Left"}, |
1477 | {"ADC Physical Right", NULL, "Analog Right"}, | |
276c6222 PU |
1478 | |
1479 | {"Digimic0 Enable", NULL, "DIGIMIC0"}, | |
1480 | {"Digimic1 Enable", NULL, "DIGIMIC1"}, | |
1481 | ||
1482 | /* TX1 Left capture path */ | |
fb2a2f84 | 1483 | {"TX1 Capture Route", "Analog", "ADC Physical Left"}, |
276c6222 PU |
1484 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, |
1485 | /* TX1 Right capture path */ | |
fb2a2f84 | 1486 | {"TX1 Capture Route", "Analog", "ADC Physical Right"}, |
276c6222 PU |
1487 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, |
1488 | /* TX2 Left capture path */ | |
fb2a2f84 | 1489 | {"TX2 Capture Route", "Analog", "ADC Physical Left"}, |
276c6222 PU |
1490 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, |
1491 | /* TX2 Right capture path */ | |
fb2a2f84 | 1492 | {"TX2 Capture Route", "Analog", "ADC Physical Right"}, |
276c6222 PU |
1493 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, |
1494 | ||
1495 | {"ADC Virtual Left1", NULL, "TX1 Capture Route"}, | |
1496 | {"ADC Virtual Right1", NULL, "TX1 Capture Route"}, | |
1497 | {"ADC Virtual Left2", NULL, "TX2 Capture Route"}, | |
1498 | {"ADC Virtual Right2", NULL, "TX2 Capture Route"}, | |
1499 | ||
1c3d2002 PU |
1500 | {"ADC Virtual Left1", NULL, "APLL Enable"}, |
1501 | {"ADC Virtual Right1", NULL, "APLL Enable"}, | |
1502 | {"ADC Virtual Left2", NULL, "APLL Enable"}, | |
1503 | {"ADC Virtual Right2", NULL, "APLL Enable"}, | |
1504 | ||
c42a59ea PU |
1505 | {"ADC Virtual Left1", NULL, "AIF Enable"}, |
1506 | {"ADC Virtual Right1", NULL, "AIF Enable"}, | |
1507 | {"ADC Virtual Left2", NULL, "AIF Enable"}, | |
1508 | {"ADC Virtual Right2", NULL, "AIF Enable"}, | |
1509 | ||
7393958f | 1510 | /* Analog bypass routes */ |
9028935d PU |
1511 | {"Right1 Analog Loopback", "Switch", "Analog Right"}, |
1512 | {"Left1 Analog Loopback", "Switch", "Analog Left"}, | |
1513 | {"Right2 Analog Loopback", "Switch", "Analog Right"}, | |
1514 | {"Left2 Analog Loopback", "Switch", "Analog Left"}, | |
1515 | {"Voice Analog Loopback", "Switch", "Analog Left"}, | |
7393958f | 1516 | |
78e08e2f PU |
1517 | /* Supply for the Analog loopbacks */ |
1518 | {"Right1 Analog Loopback", NULL, "FM Loop Enable"}, | |
1519 | {"Left1 Analog Loopback", NULL, "FM Loop Enable"}, | |
1520 | {"Right2 Analog Loopback", NULL, "FM Loop Enable"}, | |
1521 | {"Left2 Analog Loopback", NULL, "FM Loop Enable"}, | |
1522 | {"Voice Analog Loopback", NULL, "FM Loop Enable"}, | |
1523 | ||
7393958f PU |
1524 | {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"}, |
1525 | {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"}, | |
1526 | {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"}, | |
1527 | {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"}, | |
fcd274a3 | 1528 | {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"}, |
7393958f | 1529 | |
6bab83fd PU |
1530 | /* Digital bypass routes */ |
1531 | {"Right Digital Loopback", "Volume", "TX1 Capture Route"}, | |
1532 | {"Left Digital Loopback", "Volume", "TX1 Capture Route"}, | |
ee8f6894 | 1533 | {"Voice Digital Loopback", "Volume", "TX2 Capture Route"}, |
6bab83fd | 1534 | |
4005d39a PU |
1535 | {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"}, |
1536 | {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"}, | |
1537 | {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"}, | |
6bab83fd | 1538 | |
cc17557e SS |
1539 | }; |
1540 | ||
1541 | static int twl4030_add_widgets(struct snd_soc_codec *codec) | |
1542 | { | |
1543 | snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets, | |
1544 | ARRAY_SIZE(twl4030_dapm_widgets)); | |
1545 | ||
1546 | snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon)); | |
1547 | ||
cc17557e SS |
1548 | return 0; |
1549 | } | |
1550 | ||
cc17557e SS |
1551 | static int twl4030_set_bias_level(struct snd_soc_codec *codec, |
1552 | enum snd_soc_bias_level level) | |
1553 | { | |
1554 | switch (level) { | |
1555 | case SND_SOC_BIAS_ON: | |
cc17557e SS |
1556 | break; |
1557 | case SND_SOC_BIAS_PREPARE: | |
cc17557e SS |
1558 | break; |
1559 | case SND_SOC_BIAS_STANDBY: | |
78e08e2f PU |
1560 | if (codec->bias_level == SND_SOC_BIAS_OFF) |
1561 | twl4030_power_up(codec); | |
cc17557e SS |
1562 | break; |
1563 | case SND_SOC_BIAS_OFF: | |
1564 | twl4030_power_down(codec); | |
1565 | break; | |
1566 | } | |
1567 | codec->bias_level = level; | |
1568 | ||
1569 | return 0; | |
1570 | } | |
1571 | ||
6b87a91f PU |
1572 | static void twl4030_constraints(struct twl4030_priv *twl4030, |
1573 | struct snd_pcm_substream *mst_substream) | |
1574 | { | |
1575 | struct snd_pcm_substream *slv_substream; | |
1576 | ||
1577 | /* Pick the stream, which need to be constrained */ | |
1578 | if (mst_substream == twl4030->master_substream) | |
1579 | slv_substream = twl4030->slave_substream; | |
1580 | else if (mst_substream == twl4030->slave_substream) | |
1581 | slv_substream = twl4030->master_substream; | |
1582 | else /* This should not happen.. */ | |
1583 | return; | |
1584 | ||
1585 | /* Set the constraints according to the already configured stream */ | |
1586 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1587 | SNDRV_PCM_HW_PARAM_RATE, | |
1588 | twl4030->rate, | |
1589 | twl4030->rate); | |
1590 | ||
1591 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1592 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
1593 | twl4030->sample_bits, | |
1594 | twl4030->sample_bits); | |
1595 | ||
1596 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1597 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1598 | twl4030->channels, | |
1599 | twl4030->channels); | |
1600 | } | |
1601 | ||
8a1f936a PU |
1602 | /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for |
1603 | * capture has to be enabled/disabled. */ | |
1604 | static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction, | |
1605 | int enable) | |
1606 | { | |
1607 | u8 reg, mask; | |
1608 | ||
1609 | reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION); | |
1610 | ||
1611 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1612 | mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN; | |
1613 | else | |
1614 | mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; | |
1615 | ||
1616 | if (enable) | |
1617 | reg |= mask; | |
1618 | else | |
1619 | reg &= ~mask; | |
1620 | ||
1621 | twl4030_write(codec, TWL4030_REG_OPTION, reg); | |
1622 | } | |
1623 | ||
d6648da1 PU |
1624 | static int twl4030_startup(struct snd_pcm_substream *substream, |
1625 | struct snd_soc_dai *dai) | |
7220b9f4 PU |
1626 | { |
1627 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1628 | struct snd_soc_device *socdev = rtd->socdev; | |
d6648da1 | 1629 | struct snd_soc_codec *codec = socdev->card->codec; |
b2c812e2 | 1630 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7220b9f4 | 1631 | |
7220b9f4 | 1632 | if (twl4030->master_substream) { |
7220b9f4 | 1633 | twl4030->slave_substream = substream; |
6b87a91f PU |
1634 | /* The DAI has one configuration for playback and capture, so |
1635 | * if the DAI has been already configured then constrain this | |
1636 | * substream to match it. */ | |
1637 | if (twl4030->configured) | |
1638 | twl4030_constraints(twl4030, twl4030->master_substream); | |
1639 | } else { | |
8a1f936a PU |
1640 | if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) & |
1641 | TWL4030_OPTION_1)) { | |
1642 | /* In option2 4 channel is not supported, set the | |
1643 | * constraint for the first stream for channels, the | |
1644 | * second stream will 'inherit' this cosntraint */ | |
1645 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
1646 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1647 | 2, 2); | |
1648 | } | |
7220b9f4 | 1649 | twl4030->master_substream = substream; |
6b87a91f | 1650 | } |
7220b9f4 PU |
1651 | |
1652 | return 0; | |
1653 | } | |
1654 | ||
d6648da1 PU |
1655 | static void twl4030_shutdown(struct snd_pcm_substream *substream, |
1656 | struct snd_soc_dai *dai) | |
7220b9f4 PU |
1657 | { |
1658 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1659 | struct snd_soc_device *socdev = rtd->socdev; | |
d6648da1 | 1660 | struct snd_soc_codec *codec = socdev->card->codec; |
b2c812e2 | 1661 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7220b9f4 PU |
1662 | |
1663 | if (twl4030->master_substream == substream) | |
1664 | twl4030->master_substream = twl4030->slave_substream; | |
1665 | ||
1666 | twl4030->slave_substream = NULL; | |
6b87a91f PU |
1667 | |
1668 | /* If all streams are closed, or the remaining stream has not yet | |
1669 | * been configured than set the DAI as not configured. */ | |
1670 | if (!twl4030->master_substream) | |
1671 | twl4030->configured = 0; | |
1672 | else if (!twl4030->master_substream->runtime->channels) | |
1673 | twl4030->configured = 0; | |
8a1f936a PU |
1674 | |
1675 | /* If the closing substream had 4 channel, do the necessary cleanup */ | |
1676 | if (substream->runtime->channels == 4) | |
1677 | twl4030_tdm_enable(codec, substream->stream, 0); | |
7220b9f4 PU |
1678 | } |
1679 | ||
cc17557e | 1680 | static int twl4030_hw_params(struct snd_pcm_substream *substream, |
dee89c4d MB |
1681 | struct snd_pcm_hw_params *params, |
1682 | struct snd_soc_dai *dai) | |
cc17557e SS |
1683 | { |
1684 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1685 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 1686 | struct snd_soc_codec *codec = socdev->card->codec; |
b2c812e2 | 1687 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
cc17557e SS |
1688 | u8 mode, old_mode, format, old_format; |
1689 | ||
8a1f936a PU |
1690 | /* If the substream has 4 channel, do the necessary setup */ |
1691 | if (params_channels(params) == 4) { | |
eaf1ac8b PU |
1692 | format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); |
1693 | mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE); | |
1694 | ||
1695 | /* Safety check: are we in the correct operating mode and | |
1696 | * the interface is in TDM mode? */ | |
1697 | if ((mode & TWL4030_OPTION_1) && | |
1698 | ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM)) | |
8a1f936a PU |
1699 | twl4030_tdm_enable(codec, substream->stream, 1); |
1700 | else | |
1701 | return -EINVAL; | |
1702 | } | |
1703 | ||
6b87a91f PU |
1704 | if (twl4030->configured) |
1705 | /* Ignoring hw_params for already configured DAI */ | |
7220b9f4 PU |
1706 | return 0; |
1707 | ||
cc17557e SS |
1708 | /* bit rate */ |
1709 | old_mode = twl4030_read_reg_cache(codec, | |
1710 | TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; | |
1711 | mode = old_mode & ~TWL4030_APLL_RATE; | |
1712 | ||
1713 | switch (params_rate(params)) { | |
1714 | case 8000: | |
1715 | mode |= TWL4030_APLL_RATE_8000; | |
1716 | break; | |
1717 | case 11025: | |
1718 | mode |= TWL4030_APLL_RATE_11025; | |
1719 | break; | |
1720 | case 12000: | |
1721 | mode |= TWL4030_APLL_RATE_12000; | |
1722 | break; | |
1723 | case 16000: | |
1724 | mode |= TWL4030_APLL_RATE_16000; | |
1725 | break; | |
1726 | case 22050: | |
1727 | mode |= TWL4030_APLL_RATE_22050; | |
1728 | break; | |
1729 | case 24000: | |
1730 | mode |= TWL4030_APLL_RATE_24000; | |
1731 | break; | |
1732 | case 32000: | |
1733 | mode |= TWL4030_APLL_RATE_32000; | |
1734 | break; | |
1735 | case 44100: | |
1736 | mode |= TWL4030_APLL_RATE_44100; | |
1737 | break; | |
1738 | case 48000: | |
1739 | mode |= TWL4030_APLL_RATE_48000; | |
1740 | break; | |
103f211d PU |
1741 | case 96000: |
1742 | mode |= TWL4030_APLL_RATE_96000; | |
1743 | break; | |
cc17557e SS |
1744 | default: |
1745 | printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n", | |
1746 | params_rate(params)); | |
1747 | return -EINVAL; | |
1748 | } | |
1749 | ||
1750 | if (mode != old_mode) { | |
1751 | /* change rate and set CODECPDZ */ | |
7393958f | 1752 | twl4030_codec_enable(codec, 0); |
cc17557e | 1753 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); |
db04e2c5 | 1754 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1755 | } |
1756 | ||
1757 | /* sample size */ | |
1758 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1759 | format = old_format; | |
1760 | format &= ~TWL4030_DATA_WIDTH; | |
1761 | switch (params_format(params)) { | |
1762 | case SNDRV_PCM_FORMAT_S16_LE: | |
1763 | format |= TWL4030_DATA_WIDTH_16S_16W; | |
1764 | break; | |
1765 | case SNDRV_PCM_FORMAT_S24_LE: | |
1766 | format |= TWL4030_DATA_WIDTH_32S_24W; | |
1767 | break; | |
1768 | default: | |
1769 | printk(KERN_ERR "TWL4030 hw params: unknown format %d\n", | |
1770 | params_format(params)); | |
1771 | return -EINVAL; | |
1772 | } | |
1773 | ||
1774 | if (format != old_format) { | |
1775 | ||
1776 | /* clear CODECPDZ before changing format (codec requirement) */ | |
db04e2c5 | 1777 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
1778 | |
1779 | /* change format */ | |
1780 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1781 | ||
1782 | /* set CODECPDZ afterwards */ | |
db04e2c5 | 1783 | twl4030_codec_enable(codec, 1); |
cc17557e | 1784 | } |
6b87a91f PU |
1785 | |
1786 | /* Store the important parameters for the DAI configuration and set | |
1787 | * the DAI as configured */ | |
1788 | twl4030->configured = 1; | |
1789 | twl4030->rate = params_rate(params); | |
1790 | twl4030->sample_bits = hw_param_interval(params, | |
1791 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; | |
1792 | twl4030->channels = params_channels(params); | |
1793 | ||
1794 | /* If both playback and capture streams are open, and one of them | |
1795 | * is setting the hw parameters right now (since we are here), set | |
1796 | * constraints to the other stream to match the current one. */ | |
1797 | if (twl4030->slave_substream) | |
1798 | twl4030_constraints(twl4030, substream); | |
1799 | ||
cc17557e SS |
1800 | return 0; |
1801 | } | |
1802 | ||
1803 | static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
1804 | int clk_id, unsigned int freq, int dir) | |
1805 | { | |
1806 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1807 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
cc17557e SS |
1808 | |
1809 | switch (freq) { | |
1810 | case 19200000: | |
cc17557e | 1811 | case 26000000: |
cc17557e | 1812 | case 38400000: |
cc17557e SS |
1813 | break; |
1814 | default: | |
68d01955 | 1815 | dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq); |
cc17557e SS |
1816 | return -EINVAL; |
1817 | } | |
1818 | ||
68d01955 PU |
1819 | if ((freq / 1000) != twl4030->sysclk) { |
1820 | dev_err(codec->dev, | |
1821 | "Mismatch in APLL mclk: %u (configured: %u)\n", | |
1822 | freq, twl4030->sysclk * 1000); | |
1823 | return -EINVAL; | |
1824 | } | |
cc17557e SS |
1825 | |
1826 | return 0; | |
1827 | } | |
1828 | ||
1829 | static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1830 | unsigned int fmt) | |
1831 | { | |
1832 | struct snd_soc_codec *codec = codec_dai->codec; | |
1833 | u8 old_format, format; | |
1834 | ||
1835 | /* get format */ | |
1836 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1837 | format = old_format; | |
1838 | ||
1839 | /* set master/slave audio interface */ | |
1840 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1841 | case SND_SOC_DAIFMT_CBM_CFM: | |
1842 | format &= ~(TWL4030_AIF_SLAVE_EN); | |
e18c94d2 | 1843 | format &= ~(TWL4030_CLK256FS_EN); |
cc17557e SS |
1844 | break; |
1845 | case SND_SOC_DAIFMT_CBS_CFS: | |
cc17557e | 1846 | format |= TWL4030_AIF_SLAVE_EN; |
e18c94d2 | 1847 | format |= TWL4030_CLK256FS_EN; |
cc17557e SS |
1848 | break; |
1849 | default: | |
1850 | return -EINVAL; | |
1851 | } | |
1852 | ||
1853 | /* interface format */ | |
1854 | format &= ~TWL4030_AIF_FORMAT; | |
1855 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1856 | case SND_SOC_DAIFMT_I2S: | |
1857 | format |= TWL4030_AIF_FORMAT_CODEC; | |
1858 | break; | |
8a1f936a PU |
1859 | case SND_SOC_DAIFMT_DSP_A: |
1860 | format |= TWL4030_AIF_FORMAT_TDM; | |
1861 | break; | |
cc17557e SS |
1862 | default: |
1863 | return -EINVAL; | |
1864 | } | |
1865 | ||
1866 | if (format != old_format) { | |
1867 | ||
1868 | /* clear CODECPDZ before changing format (codec requirement) */ | |
db04e2c5 | 1869 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
1870 | |
1871 | /* change format */ | |
1872 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1873 | ||
1874 | /* set CODECPDZ afterwards */ | |
db04e2c5 | 1875 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1876 | } |
1877 | ||
1878 | return 0; | |
1879 | } | |
1880 | ||
68140443 LCM |
1881 | static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate) |
1882 | { | |
1883 | struct snd_soc_codec *codec = dai->codec; | |
1884 | u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF); | |
1885 | ||
1886 | if (tristate) | |
1887 | reg |= TWL4030_AIF_TRI_EN; | |
1888 | else | |
1889 | reg &= ~TWL4030_AIF_TRI_EN; | |
1890 | ||
1891 | return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg); | |
1892 | } | |
1893 | ||
b7a755a8 MLC |
1894 | /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R |
1895 | * (VTXL, VTXR) for uplink has to be enabled/disabled. */ | |
1896 | static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction, | |
1897 | int enable) | |
1898 | { | |
1899 | u8 reg, mask; | |
1900 | ||
1901 | reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION); | |
1902 | ||
1903 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1904 | mask = TWL4030_ARXL1_VRX_EN; | |
1905 | else | |
1906 | mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; | |
1907 | ||
1908 | if (enable) | |
1909 | reg |= mask; | |
1910 | else | |
1911 | reg &= ~mask; | |
1912 | ||
1913 | twl4030_write(codec, TWL4030_REG_OPTION, reg); | |
1914 | } | |
1915 | ||
7154b3e8 JS |
1916 | static int twl4030_voice_startup(struct snd_pcm_substream *substream, |
1917 | struct snd_soc_dai *dai) | |
1918 | { | |
1919 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1920 | struct snd_soc_device *socdev = rtd->socdev; | |
1921 | struct snd_soc_codec *codec = socdev->card->codec; | |
b2c812e2 | 1922 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7154b3e8 JS |
1923 | u8 mode; |
1924 | ||
1925 | /* If the system master clock is not 26MHz, the voice PCM interface is | |
1926 | * not avilable. | |
1927 | */ | |
68d01955 PU |
1928 | if (twl4030->sysclk != 26000) { |
1929 | dev_err(codec->dev, "The board is configured for %u Hz, while" | |
1930 | "the Voice interface needs 26MHz APLL mclk\n", | |
1931 | twl4030->sysclk * 1000); | |
7154b3e8 JS |
1932 | return -EINVAL; |
1933 | } | |
1934 | ||
1935 | /* If the codec mode is not option2, the voice PCM interface is not | |
1936 | * avilable. | |
1937 | */ | |
1938 | mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) | |
1939 | & TWL4030_OPT_MODE; | |
1940 | ||
1941 | if (mode != TWL4030_OPTION_2) { | |
1942 | printk(KERN_ERR "TWL4030 voice startup: " | |
1943 | "the codec mode is not option2\n"); | |
1944 | return -EINVAL; | |
1945 | } | |
1946 | ||
1947 | return 0; | |
1948 | } | |
1949 | ||
b7a755a8 MLC |
1950 | static void twl4030_voice_shutdown(struct snd_pcm_substream *substream, |
1951 | struct snd_soc_dai *dai) | |
1952 | { | |
1953 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1954 | struct snd_soc_device *socdev = rtd->socdev; | |
1955 | struct snd_soc_codec *codec = socdev->card->codec; | |
1956 | ||
1957 | /* Enable voice digital filters */ | |
1958 | twl4030_voice_enable(codec, substream->stream, 0); | |
1959 | } | |
1960 | ||
7154b3e8 JS |
1961 | static int twl4030_voice_hw_params(struct snd_pcm_substream *substream, |
1962 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
1963 | { | |
1964 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
1965 | struct snd_soc_device *socdev = rtd->socdev; | |
1966 | struct snd_soc_codec *codec = socdev->card->codec; | |
1967 | u8 old_mode, mode; | |
1968 | ||
b7a755a8 MLC |
1969 | /* Enable voice digital filters */ |
1970 | twl4030_voice_enable(codec, substream->stream, 1); | |
1971 | ||
7154b3e8 JS |
1972 | /* bit rate */ |
1973 | old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) | |
1974 | & ~(TWL4030_CODECPDZ); | |
1975 | mode = old_mode; | |
1976 | ||
1977 | switch (params_rate(params)) { | |
1978 | case 8000: | |
1979 | mode &= ~(TWL4030_SEL_16K); | |
1980 | break; | |
1981 | case 16000: | |
1982 | mode |= TWL4030_SEL_16K; | |
1983 | break; | |
1984 | default: | |
1985 | printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n", | |
1986 | params_rate(params)); | |
1987 | return -EINVAL; | |
1988 | } | |
1989 | ||
1990 | if (mode != old_mode) { | |
1991 | /* change rate and set CODECPDZ */ | |
1992 | twl4030_codec_enable(codec, 0); | |
1993 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
1994 | twl4030_codec_enable(codec, 1); | |
1995 | } | |
1996 | ||
1997 | return 0; | |
1998 | } | |
1999 | ||
2000 | static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
2001 | int clk_id, unsigned int freq, int dir) | |
2002 | { | |
2003 | struct snd_soc_codec *codec = codec_dai->codec; | |
68d01955 | 2004 | struct twl4030_priv *twl4030 = codec->private_data; |
7154b3e8 | 2005 | |
68d01955 PU |
2006 | if (freq != 26000000) { |
2007 | dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice" | |
2008 | "interface needs 26MHz APLL mclk\n", freq); | |
2009 | return -EINVAL; | |
2010 | } | |
2011 | if ((freq / 1000) != twl4030->sysclk) { | |
2012 | dev_err(codec->dev, | |
2013 | "Mismatch in APLL mclk: %u (configured: %u)\n", | |
2014 | freq, twl4030->sysclk * 1000); | |
7154b3e8 JS |
2015 | return -EINVAL; |
2016 | } | |
7154b3e8 JS |
2017 | return 0; |
2018 | } | |
2019 | ||
2020 | static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
2021 | unsigned int fmt) | |
2022 | { | |
2023 | struct snd_soc_codec *codec = codec_dai->codec; | |
2024 | u8 old_format, format; | |
2025 | ||
2026 | /* get format */ | |
2027 | old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF); | |
2028 | format = old_format; | |
2029 | ||
2030 | /* set master/slave audio interface */ | |
2031 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
c264301c | 2032 | case SND_SOC_DAIFMT_CBM_CFM: |
7154b3e8 JS |
2033 | format &= ~(TWL4030_VIF_SLAVE_EN); |
2034 | break; | |
2035 | case SND_SOC_DAIFMT_CBS_CFS: | |
2036 | format |= TWL4030_VIF_SLAVE_EN; | |
2037 | break; | |
2038 | default: | |
2039 | return -EINVAL; | |
2040 | } | |
2041 | ||
2042 | /* clock inversion */ | |
2043 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2044 | case SND_SOC_DAIFMT_IB_NF: | |
2045 | format &= ~(TWL4030_VIF_FORMAT); | |
2046 | break; | |
2047 | case SND_SOC_DAIFMT_NB_IF: | |
2048 | format |= TWL4030_VIF_FORMAT; | |
2049 | break; | |
2050 | default: | |
2051 | return -EINVAL; | |
2052 | } | |
2053 | ||
2054 | if (format != old_format) { | |
2055 | /* change format and set CODECPDZ */ | |
2056 | twl4030_codec_enable(codec, 0); | |
2057 | twl4030_write(codec, TWL4030_REG_VOICE_IF, format); | |
2058 | twl4030_codec_enable(codec, 1); | |
2059 | } | |
2060 | ||
2061 | return 0; | |
2062 | } | |
2063 | ||
68140443 LCM |
2064 | static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate) |
2065 | { | |
2066 | struct snd_soc_codec *codec = dai->codec; | |
2067 | u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF); | |
2068 | ||
2069 | if (tristate) | |
2070 | reg |= TWL4030_VIF_TRI_EN; | |
2071 | else | |
2072 | reg &= ~TWL4030_VIF_TRI_EN; | |
2073 | ||
2074 | return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg); | |
2075 | } | |
2076 | ||
bbba9444 | 2077 | #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) |
cc17557e SS |
2078 | #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE) |
2079 | ||
10d9e3d9 | 2080 | static struct snd_soc_dai_ops twl4030_dai_ops = { |
7220b9f4 PU |
2081 | .startup = twl4030_startup, |
2082 | .shutdown = twl4030_shutdown, | |
10d9e3d9 JS |
2083 | .hw_params = twl4030_hw_params, |
2084 | .set_sysclk = twl4030_set_dai_sysclk, | |
2085 | .set_fmt = twl4030_set_dai_fmt, | |
68140443 | 2086 | .set_tristate = twl4030_set_tristate, |
10d9e3d9 JS |
2087 | }; |
2088 | ||
7154b3e8 JS |
2089 | static struct snd_soc_dai_ops twl4030_dai_voice_ops = { |
2090 | .startup = twl4030_voice_startup, | |
b7a755a8 | 2091 | .shutdown = twl4030_voice_shutdown, |
7154b3e8 JS |
2092 | .hw_params = twl4030_voice_hw_params, |
2093 | .set_sysclk = twl4030_voice_set_dai_sysclk, | |
2094 | .set_fmt = twl4030_voice_set_dai_fmt, | |
68140443 | 2095 | .set_tristate = twl4030_voice_set_tristate, |
7154b3e8 JS |
2096 | }; |
2097 | ||
2098 | struct snd_soc_dai twl4030_dai[] = { | |
2099 | { | |
cc17557e SS |
2100 | .name = "twl4030", |
2101 | .playback = { | |
b4852b79 | 2102 | .stream_name = "HiFi Playback", |
cc17557e | 2103 | .channels_min = 2, |
8a1f936a | 2104 | .channels_max = 4, |
31ad0f31 | 2105 | .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000, |
cc17557e SS |
2106 | .formats = TWL4030_FORMATS,}, |
2107 | .capture = { | |
2108 | .stream_name = "Capture", | |
2109 | .channels_min = 2, | |
8a1f936a | 2110 | .channels_max = 4, |
cc17557e SS |
2111 | .rates = TWL4030_RATES, |
2112 | .formats = TWL4030_FORMATS,}, | |
10d9e3d9 | 2113 | .ops = &twl4030_dai_ops, |
7154b3e8 JS |
2114 | }, |
2115 | { | |
2116 | .name = "twl4030 Voice", | |
2117 | .playback = { | |
b4852b79 | 2118 | .stream_name = "Voice Playback", |
7154b3e8 JS |
2119 | .channels_min = 1, |
2120 | .channels_max = 1, | |
2121 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, | |
2122 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
2123 | .capture = { | |
2124 | .stream_name = "Capture", | |
2125 | .channels_min = 1, | |
2126 | .channels_max = 2, | |
2127 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, | |
2128 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
2129 | .ops = &twl4030_dai_voice_ops, | |
2130 | }, | |
cc17557e SS |
2131 | }; |
2132 | EXPORT_SYMBOL_GPL(twl4030_dai); | |
2133 | ||
7a1fecf5 | 2134 | static int twl4030_soc_suspend(struct platform_device *pdev, pm_message_t state) |
cc17557e SS |
2135 | { |
2136 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 2137 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
2138 | |
2139 | twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2140 | ||
2141 | return 0; | |
2142 | } | |
2143 | ||
7a1fecf5 | 2144 | static int twl4030_soc_resume(struct platform_device *pdev) |
cc17557e SS |
2145 | { |
2146 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 2147 | struct snd_soc_codec *codec = socdev->card->codec; |
cc17557e SS |
2148 | |
2149 | twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2150 | twl4030_set_bias_level(codec, codec->suspend_bias_level); | |
2151 | return 0; | |
2152 | } | |
2153 | ||
7a1fecf5 | 2154 | static struct snd_soc_codec *twl4030_codec; |
cc17557e | 2155 | |
7a1fecf5 | 2156 | static int twl4030_soc_probe(struct platform_device *pdev) |
cc17557e | 2157 | { |
7a1fecf5 | 2158 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
9da28c7b | 2159 | struct twl4030_setup_data *setup = socdev->codec_data; |
7a1fecf5 PU |
2160 | struct snd_soc_codec *codec; |
2161 | struct twl4030_priv *twl4030; | |
2162 | int ret; | |
cc17557e | 2163 | |
7a1fecf5 | 2164 | BUG_ON(!twl4030_codec); |
cc17557e | 2165 | |
7a1fecf5 | 2166 | codec = twl4030_codec; |
b2c812e2 | 2167 | twl4030 = snd_soc_codec_get_drvdata(codec); |
7a1fecf5 | 2168 | socdev->card->codec = codec; |
cc17557e | 2169 | |
9da28c7b PU |
2170 | /* Configuration for headset ramp delay from setup data */ |
2171 | if (setup) { | |
2172 | unsigned char hs_pop; | |
2173 | ||
68d01955 PU |
2174 | if (setup->sysclk != twl4030->sysclk) |
2175 | dev_warn(&pdev->dev, | |
2176 | "Mismatch in APLL mclk: %u (configured: %u)\n", | |
2177 | setup->sysclk, twl4030->sysclk); | |
9da28c7b PU |
2178 | |
2179 | hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET); | |
2180 | hs_pop &= ~TWL4030_RAMP_DELAY; | |
2181 | hs_pop |= (setup->ramp_delay_value << 2); | |
2182 | twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
9da28c7b PU |
2183 | } |
2184 | ||
cc17557e SS |
2185 | /* register pcms */ |
2186 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
2187 | if (ret < 0) { | |
7a1fecf5 PU |
2188 | dev_err(&pdev->dev, "failed to create pcms\n"); |
2189 | return ret; | |
cc17557e SS |
2190 | } |
2191 | ||
3e8e1952 IM |
2192 | snd_soc_add_controls(codec, twl4030_snd_controls, |
2193 | ARRAY_SIZE(twl4030_snd_controls)); | |
cc17557e SS |
2194 | twl4030_add_widgets(codec); |
2195 | ||
7a1fecf5 | 2196 | return 0; |
cc17557e SS |
2197 | } |
2198 | ||
7a1fecf5 | 2199 | static int twl4030_soc_remove(struct platform_device *pdev) |
cc17557e SS |
2200 | { |
2201 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
7a1fecf5 PU |
2202 | struct snd_soc_codec *codec = socdev->card->codec; |
2203 | ||
2204 | twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2205 | snd_soc_free_pcms(socdev); | |
2206 | snd_soc_dapm_free(socdev); | |
7a1fecf5 PU |
2207 | |
2208 | return 0; | |
2209 | } | |
2210 | ||
2211 | static int __devinit twl4030_codec_probe(struct platform_device *pdev) | |
2212 | { | |
2213 | struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data; | |
cc17557e | 2214 | struct snd_soc_codec *codec; |
7393958f | 2215 | struct twl4030_priv *twl4030; |
7a1fecf5 | 2216 | int ret; |
cc17557e | 2217 | |
68d01955 PU |
2218 | if (!pdata) { |
2219 | dev_err(&pdev->dev, "platform_data is missing\n"); | |
7a1fecf5 PU |
2220 | return -EINVAL; |
2221 | } | |
cc17557e | 2222 | |
7393958f PU |
2223 | twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL); |
2224 | if (twl4030 == NULL) { | |
7a1fecf5 | 2225 | dev_err(&pdev->dev, "Can not allocate memroy\n"); |
7393958f PU |
2226 | return -ENOMEM; |
2227 | } | |
2228 | ||
7a1fecf5 | 2229 | codec = &twl4030->codec; |
b2c812e2 | 2230 | snd_soc_codec_set_drvdata(codec, twl4030); |
7a1fecf5 PU |
2231 | codec->dev = &pdev->dev; |
2232 | twl4030_dai[0].dev = &pdev->dev; | |
2233 | twl4030_dai[1].dev = &pdev->dev; | |
2234 | ||
cc17557e SS |
2235 | mutex_init(&codec->mutex); |
2236 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
2237 | INIT_LIST_HEAD(&codec->dapm_paths); | |
2238 | ||
7a1fecf5 PU |
2239 | codec->name = "twl4030"; |
2240 | codec->owner = THIS_MODULE; | |
2241 | codec->read = twl4030_read_reg_cache; | |
2242 | codec->write = twl4030_write; | |
2243 | codec->set_bias_level = twl4030_set_bias_level; | |
2244 | codec->dai = twl4030_dai; | |
fd63df22 | 2245 | codec->num_dai = ARRAY_SIZE(twl4030_dai); |
7a1fecf5 PU |
2246 | codec->reg_cache_size = sizeof(twl4030_reg); |
2247 | codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg), | |
2248 | GFP_KERNEL); | |
2249 | if (codec->reg_cache == NULL) { | |
2250 | ret = -ENOMEM; | |
2251 | goto error_cache; | |
2252 | } | |
2253 | ||
2254 | platform_set_drvdata(pdev, twl4030); | |
2255 | twl4030_codec = codec; | |
2256 | ||
2257 | /* Set the defaults, and power up the codec */ | |
68d01955 | 2258 | twl4030->sysclk = twl4030_codec_get_mclk() / 1000; |
7a1fecf5 | 2259 | twl4030_init_chip(codec); |
b3f5a272 | 2260 | codec->bias_level = SND_SOC_BIAS_OFF; |
7a1fecf5 PU |
2261 | twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
2262 | ||
2263 | ret = snd_soc_register_codec(codec); | |
2264 | if (ret != 0) { | |
2265 | dev_err(codec->dev, "Failed to register codec: %d\n", ret); | |
2266 | goto error_codec; | |
2267 | } | |
2268 | ||
2269 | ret = snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai)); | |
2270 | if (ret != 0) { | |
2271 | dev_err(codec->dev, "Failed to register DAIs: %d\n", ret); | |
2272 | snd_soc_unregister_codec(codec); | |
2273 | goto error_codec; | |
2274 | } | |
cc17557e SS |
2275 | |
2276 | return 0; | |
7a1fecf5 PU |
2277 | |
2278 | error_codec: | |
2279 | twl4030_power_down(codec); | |
2280 | kfree(codec->reg_cache); | |
2281 | error_cache: | |
2282 | kfree(twl4030); | |
2283 | return ret; | |
cc17557e SS |
2284 | } |
2285 | ||
7a1fecf5 | 2286 | static int __devexit twl4030_codec_remove(struct platform_device *pdev) |
cc17557e | 2287 | { |
7a1fecf5 | 2288 | struct twl4030_priv *twl4030 = platform_get_drvdata(pdev); |
cc17557e | 2289 | |
cb67286d PU |
2290 | snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai)); |
2291 | snd_soc_unregister_codec(&twl4030->codec); | |
2292 | kfree(twl4030->codec.reg_cache); | |
7a1fecf5 | 2293 | kfree(twl4030); |
cc17557e | 2294 | |
7a1fecf5 | 2295 | twl4030_codec = NULL; |
cc17557e SS |
2296 | return 0; |
2297 | } | |
2298 | ||
7a1fecf5 PU |
2299 | MODULE_ALIAS("platform:twl4030_codec_audio"); |
2300 | ||
2301 | static struct platform_driver twl4030_codec_driver = { | |
2302 | .probe = twl4030_codec_probe, | |
2303 | .remove = __devexit_p(twl4030_codec_remove), | |
2304 | .driver = { | |
2305 | .name = "twl4030_codec_audio", | |
2306 | .owner = THIS_MODULE, | |
2307 | }, | |
cc17557e | 2308 | }; |
cc17557e | 2309 | |
24e07db8 | 2310 | static int __init twl4030_modinit(void) |
64089b84 | 2311 | { |
7a1fecf5 | 2312 | return platform_driver_register(&twl4030_codec_driver); |
64089b84 | 2313 | } |
24e07db8 | 2314 | module_init(twl4030_modinit); |
64089b84 MB |
2315 | |
2316 | static void __exit twl4030_exit(void) | |
2317 | { | |
7a1fecf5 | 2318 | platform_driver_unregister(&twl4030_codec_driver); |
64089b84 MB |
2319 | } |
2320 | module_exit(twl4030_exit); | |
2321 | ||
7a1fecf5 PU |
2322 | struct snd_soc_codec_device soc_codec_dev_twl4030 = { |
2323 | .probe = twl4030_soc_probe, | |
2324 | .remove = twl4030_soc_remove, | |
2325 | .suspend = twl4030_soc_suspend, | |
2326 | .resume = twl4030_soc_resume, | |
2327 | }; | |
2328 | EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030); | |
2329 | ||
cc17557e SS |
2330 | MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); |
2331 | MODULE_AUTHOR("Steve Sakoman"); | |
2332 | MODULE_LICENSE("GPL"); |