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ASoC: Automatically determine control_data for soc-cache users
[linux-2.6-block.git] / sound / soc / codecs / twl4030.c
CommitLineData
cc17557e
SS		 1/*
2 * ALSA SoC TWL4030 codec driver
3 *
4 * Author: Steve Sakoman, <steve@sakoman.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
28#include <linux/platform_device.h>
b07682b6 29#include <linux/i2c/twl.h>
5a0e3ad6 30#include <linux/slab.h>
cc17557e
SS		 31#include <sound/core.h>
32#include <sound/pcm.h>
33#include <sound/pcm_params.h>
34#include <sound/soc.h>
35#include <sound/soc-dapm.h>
36#include <sound/initval.h>
c10b82cf 37#include <sound/tlv.h>
cc17557e 38
f0fba2ad
LG		 39/* Register descriptions are here */
40#include <linux/mfd/twl4030-codec.h>
41
42/* Shadow register used by the audio driver */
43#define TWL4030_REG_SW_SHADOW 0x4A
44#define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1)
45
46/* TWL4030_REG_SW_SHADOW (0x4A) Fields */
47#define TWL4030_HFL_EN 0x01
48#define TWL4030_HFR_EN 0x02
cc17557e
SS		 49
50/*
51 * twl4030 register cache & default register settings
52 */
53static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
54 0x00, /* this register not used */
33f92ed4 55 0x00, /* REG_CODEC_MODE (0x1) */
ee4ccac7 56 0x00, /* REG_OPTION (0x2) */
cc17557e
SS		 57 0x00, /* REG_UNKNOWN (0x3) */
58 0x00, /* REG_MICBIAS_CTL (0x4) */
979bb1f4 59 0x00, /* REG_ANAMICL (0x5) */
5920b453
GI		 60 0x00, /* REG_ANAMICR (0x6) */
61 0x00, /* REG_AVADC_CTL (0x7) */
cc17557e
SS		 62 0x00, /* REG_ADCMICSEL (0x8) */
63 0x00, /* REG_DIGMIXING (0x9) */
33f92ed4
PU		 64 0x0f, /* REG_ATXL1PGA (0xA) */
65 0x0f, /* REG_ATXR1PGA (0xB) */
66 0x0f, /* REG_AVTXL2PGA (0xC) */
67 0x0f, /* REG_AVTXR2PGA (0xD) */
c42a59ea 68 0x00, /* REG_AUDIO_IF (0xE) */
cc17557e 69 0x00, /* REG_VOICE_IF (0xF) */
33f92ed4
PU		 70 0x3f, /* REG_ARXR1PGA (0x10) */
71 0x3f, /* REG_ARXL1PGA (0x11) */
72 0x3f, /* REG_ARXR2PGA (0x12) */
73 0x3f, /* REG_ARXL2PGA (0x13) */
74 0x25, /* REG_VRXPGA (0x14) */
cc17557e
SS		 75 0x00, /* REG_VSTPGA (0x15) */
76 0x00, /* REG_VRX2ARXPGA (0x16) */
c8124593 77 0x00, /* REG_AVDAC_CTL (0x17) */
cc17557e 78 0x00, /* REG_ARX2VTXPGA (0x18) */
33f92ed4
PU		 79 0x32, /* REG_ARXL1_APGA_CTL (0x19) */
80 0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
81 0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
82 0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
cc17557e
SS		 83 0x00, /* REG_ATX2ARXPGA (0x1D) */
84 0x00, /* REG_BT_IF (0x1E) */
33f92ed4 85 0x55, /* REG_BTPGA (0x1F) */
cc17557e
SS		 86 0x00, /* REG_BTSTPGA (0x20) */
87 0x00, /* REG_EAR_CTL (0x21) */
e47c796d
PU		 88 0x00, /* REG_HS_SEL (0x22) */
89 0x00, /* REG_HS_GAIN_SET (0x23) */
cc17557e
SS		 90 0x00, /* REG_HS_POPN_SET (0x24) */
91 0x00, /* REG_PREDL_CTL (0x25) */
92 0x00, /* REG_PREDR_CTL (0x26) */
93 0x00, /* REG_PRECKL_CTL (0x27) */
94 0x00, /* REG_PRECKR_CTL (0x28) */
95 0x00, /* REG_HFL_CTL (0x29) */
96 0x00, /* REG_HFR_CTL (0x2A) */
33f92ed4 97 0x05, /* REG_ALC_CTL (0x2B) */
cc17557e
SS		 98 0x00, /* REG_ALC_SET1 (0x2C) */
99 0x00, /* REG_ALC_SET2 (0x2D) */
100 0x00, /* REG_BOOST_CTL (0x2E) */
f8d05bdb 101 0x00, /* REG_SOFTVOL_CTL (0x2F) */
33f92ed4 102 0x13, /* REG_DTMF_FREQSEL (0x30) */
cc17557e
SS		 103 0x00, /* REG_DTMF_TONEXT1H (0x31) */
104 0x00, /* REG_DTMF_TONEXT1L (0x32) */
105 0x00, /* REG_DTMF_TONEXT2H (0x33) */
106 0x00, /* REG_DTMF_TONEXT2L (0x34) */
33f92ed4
PU		 107 0x79, /* REG_DTMF_TONOFF (0x35) */
108 0x11, /* REG_DTMF_WANONOFF (0x36) */
cc17557e
SS		 109 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
110 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
111 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
c8124593 112 0x06, /* REG_APLL_CTL (0x3A) */
cc17557e 113 0x00, /* REG_DTMF_CTL (0x3B) */
33f92ed4
PU		 114 0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
115 0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
cc17557e
SS		 116 0x00, /* REG_MISC_SET_1 (0x3E) */
117 0x00, /* REG_PCMBTMUX (0x3F) */
118 0x00, /* not used (0x40) */
119 0x00, /* not used (0x41) */
120 0x00, /* not used (0x42) */
121 0x00, /* REG_RX_PATH_SEL (0x43) */
33f92ed4 122 0x32, /* REG_VDL_APGA_CTL (0x44) */
cc17557e
SS		 123 0x00, /* REG_VIBRA_CTL (0x45) */
124 0x00, /* REG_VIBRA_SET (0x46) */
125 0x00, /* REG_VIBRA_PWM_SET (0x47) */
126 0x00, /* REG_ANAMIC_GAIN (0x48) */
127 0x00, /* REG_MISC_SET_2 (0x49) */
f3b5d300 128 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
cc17557e
SS		 129};
130
7393958f
PU		 131/* codec private data */
132struct twl4030_priv {
7a1fecf5
PU		 133 struct snd_soc_codec codec;
134
7393958f 135 unsigned int codec_powered;
7b4c734e
PU		 136
137 /* reference counts of AIF/APLL users */
2845fa13 138 unsigned int apll_enabled;
7220b9f4
PU		 139
140 struct snd_pcm_substream *master_substream;
141 struct snd_pcm_substream *slave_substream;
6b87a91f
PU		 142
143 unsigned int configured;
144 unsigned int rate;
145 unsigned int sample_bits;
146 unsigned int channels;
6943c92e
PU		 147
148 unsigned int sysclk;
149
c96907f2
PU		 150 /* Output (with associated amp) states */
151 u8 hsl_enabled, hsr_enabled;
152 u8 earpiece_enabled;
153 u8 predrivel_enabled, predriver_enabled;
154 u8 carkitl_enabled, carkitr_enabled;
01ea6ba2
PU		 155
156 /* Delay needed after enabling the digimic interface */
157 unsigned int digimic_delay;
7393958f
PU		 158};
159
cc17557e
SS		 160/*
161 * read twl4030 register cache
162 */
163static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
164 unsigned int reg)
165{
d08664fd 166 u8 *cache = codec->reg_cache;
cc17557e 167
91432e97
IM		 168 if (reg >= TWL4030_CACHEREGNUM)
169 return -EIO;
170
cc17557e
SS		 171 return cache[reg];
172}
173
174/*
175 * write twl4030 register cache
176 */
177static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
178 u8 reg, u8 value)
179{
180 u8 *cache = codec->reg_cache;
181
182 if (reg >= TWL4030_CACHEREGNUM)
183 return;
184 cache[reg] = value;
185}
186
187/*
188 * write to the twl4030 register space
189 */
190static int twl4030_write(struct snd_soc_codec *codec,
191 unsigned int reg, unsigned int value)
192{
b2c812e2 193 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
c96907f2
PU		 194 int write_to_reg = 0;
195
cc17557e 196 twl4030_write_reg_cache(codec, reg, value);
c96907f2
PU		 197 if (likely(reg < TWL4030_REG_SW_SHADOW)) {
198 /* Decide if the given register can be written */
199 switch (reg) {
200 case TWL4030_REG_EAR_CTL:
201 if (twl4030->earpiece_enabled)
202 write_to_reg = 1;
203 break;
204 case TWL4030_REG_PREDL_CTL:
205 if (twl4030->predrivel_enabled)
206 write_to_reg = 1;
207 break;
208 case TWL4030_REG_PREDR_CTL:
209 if (twl4030->predriver_enabled)
210 write_to_reg = 1;
211 break;
212 case TWL4030_REG_PRECKL_CTL:
213 if (twl4030->carkitl_enabled)
214 write_to_reg = 1;
215 break;
216 case TWL4030_REG_PRECKR_CTL:
217 if (twl4030->carkitr_enabled)
218 write_to_reg = 1;
219 break;
220 case TWL4030_REG_HS_GAIN_SET:
221 if (twl4030->hsl_enabled || twl4030->hsr_enabled)
222 write_to_reg = 1;
223 break;
224 default:
225 /* All other register can be written */
226 write_to_reg = 1;
227 break;
228 }
229 if (write_to_reg)
230 return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
231 value, reg);
232 }
233 return 0;
cc17557e
SS		 234}
235
db04e2c5 236static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
cc17557e 237{
b2c812e2 238 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7a1fecf5 239 int mode;
cc17557e 240
7393958f
PU		 241 if (enable == twl4030->codec_powered)
242 return;
243
db04e2c5 244 if (enable)
7a1fecf5 245 mode = twl4030_codec_enable_resource(TWL4030_CODEC_RES_POWER);
db04e2c5 246 else
7a1fecf5 247 mode = twl4030_codec_disable_resource(TWL4030_CODEC_RES_POWER);
cc17557e 248
7a1fecf5
PU		 249 if (mode >= 0) {
250 twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
251 twl4030->codec_powered = enable;
252 }
cc17557e
SS		 253
254 /* REVISIT: this delay is present in TI sample drivers */
255 /* but there seems to be no TRM requirement for it */
256 udelay(10);
257}
258
9fdcc0f7 259static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
cc17557e 260{
9fdcc0f7
PU		 261 int i, difference = 0;
262 u8 val;
263
264 dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
265 for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
266 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
267 if (val != twl4030_reg[i]) {
268 difference++;
269 dev_dbg(codec->dev,
270 "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
271 i, val, twl4030_reg[i]);
272 }
273 }
274 dev_dbg(codec->dev, "Found %d non maching registers. %s\n",
275 difference, difference ? "Not OK" : "OK");
276}
cc17557e 277
a3a29b55
PU		 278static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
279{
280 int i;
cc17557e
SS		 281
282 /* set all audio section registers to reasonable defaults */
283 for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
68d01955 284 if (i != TWL4030_REG_APLL_CTL)
a3a29b55 285 twl4030_write(codec, i, twl4030_reg[i]);
cc17557e
SS		 286
287}
288
f0fba2ad 289static void twl4030_init_chip(struct snd_soc_codec *codec)
7393958f 290{
f0fba2ad 291 struct twl4030_codec_audio_data *pdata = dev_get_platdata(codec->dev);
b2c812e2 292 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
ee4ccac7
PU		 293 u8 reg, byte;
294 int i = 0;
7393958f 295
9fdcc0f7 296 /* Check defaults, if instructed before anything else */
f0fba2ad 297 if (pdata && pdata->check_defaults)
9fdcc0f7 298 twl4030_check_defaults(codec);
7a1fecf5 299
a3a29b55 300 /* Reset registers, if no setup data or if instructed to do so */
f0fba2ad 301 if (!pdata || (pdata && pdata->reset_registers))
a3a29b55 302 twl4030_reset_registers(codec);
7393958f 303
ee4ccac7 304 /* Refresh APLL_CTL register from HW */
9fdcc0f7 305 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
ee4ccac7
PU		 306 TWL4030_REG_APLL_CTL);
307 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
006f367e 308
ee4ccac7
PU		 309 /* anti-pop when changing analog gain */
310 reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
311 twl4030_write(codec, TWL4030_REG_MISC_SET_1,
312 reg | TWL4030_SMOOTH_ANAVOL_EN);
7393958f 313
ee4ccac7
PU		 314 twl4030_write(codec, TWL4030_REG_OPTION,
315 TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
316 TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
006f367e 317
3c36cc68
PU		 318 /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
319 twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
320
ee4ccac7 321 /* Machine dependent setup */
f0fba2ad 322 if (!pdata)
7393958f
PU		 323 return;
324
f0fba2ad 325 twl4030->digimic_delay = pdata->digimic_delay;
ee4ccac7
PU		 326
327 reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
328 reg &= ~TWL4030_RAMP_DELAY;
f0fba2ad 329 reg |= (pdata->ramp_delay_value << 2);
ee4ccac7 330 twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
006f367e
PU		 331
332 /* initiate offset cancellation */
ee4ccac7
PU		 333 twl4030_codec_enable(codec, 1);
334
335 reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
336 reg &= ~TWL4030_OFFSET_CNCL_SEL;
f0fba2ad 337 reg |= pdata->offset_cncl_path;
006f367e 338 twl4030_write(codec, TWL4030_REG_ANAMICL,
ee4ccac7 339 reg | TWL4030_CNCL_OFFSET_START);
006f367e
PU		 340
341 /* wait for offset cancellation to complete */
342 do {
343 /* this takes a little while, so don't slam i2c */
344 udelay(2000);
fc7b92fc 345 twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
006f367e
PU		 346 TWL4030_REG_ANAMICL);
347 } while ((i++ < 100) &&
348 ((byte & TWL4030_CNCL_OFFSET_START) ==
349 TWL4030_CNCL_OFFSET_START));
350
351 /* Make sure that the reg_cache has the same value as the HW */
352 twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
353
006f367e 354 twl4030_codec_enable(codec, 0);
006f367e
PU		 355}
356
ee4ccac7 357static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
006f367e 358{
ee4ccac7
PU		 359 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
360 int status = -1;
361
362 if (enable) {
363 twl4030->apll_enabled++;
364 if (twl4030->apll_enabled == 1)
365 status = twl4030_codec_enable_resource(
366 TWL4030_CODEC_RES_APLL);
367 } else {
368 twl4030->apll_enabled--;
369 if (!twl4030->apll_enabled)
370 status = twl4030_codec_disable_resource(
371 TWL4030_CODEC_RES_APLL);
372 }
373
374 if (status >= 0)
375 twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
006f367e
PU		 376}
377
5e98a464 378/* Earpiece */
1a787e7a
JS		 379static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
380 SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
381 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
382 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
383 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
384};
5e98a464 385
2a6f5c58 386/* PreDrive Left */
1a787e7a
JS		 387static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
388 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
389 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
390 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
391 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
392};
2a6f5c58
PU		 393
394/* PreDrive Right */
1a787e7a
JS		 395static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
396 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
397 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
398 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
399 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
400};
2a6f5c58 401
dfad21a2 402/* Headset Left */
1a787e7a
JS		 403static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
404 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
405 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
406 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
407};
dfad21a2
PU		 408
409/* Headset Right */
1a787e7a
JS		 410static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
411 SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
412 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
413 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
414};
dfad21a2 415
5152d8c2 416/* Carkit Left */
1a787e7a
JS		 417static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
418 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
419 SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
420 SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
421};
5152d8c2
PU		 422
423/* Carkit Right */
1a787e7a
JS		 424static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
425 SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
426 SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
427 SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
428};
5152d8c2 429
df339804
PU		 430/* Handsfree Left */
431static const char *twl4030_handsfreel_texts[] =
1a787e7a 432 {"Voice", "AudioL1", "AudioL2", "AudioR2"};
df339804
PU		 433
434static const struct soc_enum twl4030_handsfreel_enum =
435 SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
436 ARRAY_SIZE(twl4030_handsfreel_texts),
437 twl4030_handsfreel_texts);
438
439static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
440SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
441
0f89bdca
PU		 442/* Handsfree Left virtual mute */
443static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
444 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
445
df339804
PU		 446/* Handsfree Right */
447static const char *twl4030_handsfreer_texts[] =
1a787e7a 448 {"Voice", "AudioR1", "AudioR2", "AudioL2"};
df339804
PU		 449
450static const struct soc_enum twl4030_handsfreer_enum =
451 SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
452 ARRAY_SIZE(twl4030_handsfreer_texts),
453 twl4030_handsfreer_texts);
454
455static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
456SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
457
0f89bdca
PU		 458/* Handsfree Right virtual mute */
459static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
460 SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
461
376f7839
PU		 462/* Vibra */
463/* Vibra audio path selection */
464static const char *twl4030_vibra_texts[] =
465 {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
466
467static const struct soc_enum twl4030_vibra_enum =
468 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
469 ARRAY_SIZE(twl4030_vibra_texts),
470 twl4030_vibra_texts);
471
472static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
473SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
474
475/* Vibra path selection: local vibrator (PWM) or audio driven */
476static const char *twl4030_vibrapath_texts[] =
477 {"Local vibrator", "Audio"};
478
479static const struct soc_enum twl4030_vibrapath_enum =
480 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
481 ARRAY_SIZE(twl4030_vibrapath_texts),
482 twl4030_vibrapath_texts);
483
484static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
485SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
486
276c6222 487/* Left analog microphone selection */
97b8096d 488static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
9028935d
PU		 489 SOC_DAPM_SINGLE("Main Mic Capture Switch",
490 TWL4030_REG_ANAMICL, 0, 1, 0),
491 SOC_DAPM_SINGLE("Headset Mic Capture Switch",
492 TWL4030_REG_ANAMICL, 1, 1, 0),
493 SOC_DAPM_SINGLE("AUXL Capture Switch",
494 TWL4030_REG_ANAMICL, 2, 1, 0),
495 SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
496 TWL4030_REG_ANAMICL, 3, 1, 0),
97b8096d 497};
276c6222
PU		 498
499/* Right analog microphone selection */
97b8096d 500static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
9028935d
PU		 501 SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
502 SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
97b8096d 503};
276c6222
PU		 504
505/* TX1 L/R Analog/Digital microphone selection */
506static const char *twl4030_micpathtx1_texts[] =
507 {"Analog", "Digimic0"};
508
509static const struct soc_enum twl4030_micpathtx1_enum =
510 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
511 ARRAY_SIZE(twl4030_micpathtx1_texts),
512 twl4030_micpathtx1_texts);
513
514static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
515SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
516
517/* TX2 L/R Analog/Digital microphone selection */
518static const char *twl4030_micpathtx2_texts[] =
519 {"Analog", "Digimic1"};
520
521static const struct soc_enum twl4030_micpathtx2_enum =
522 SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
523 ARRAY_SIZE(twl4030_micpathtx2_texts),
524 twl4030_micpathtx2_texts);
525
526static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
527SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
528
7393958f
PU		 529/* Analog bypass for AudioR1 */
530static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
531 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
532
533/* Analog bypass for AudioL1 */
534static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
535 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
536
537/* Analog bypass for AudioR2 */
538static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
539 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
540
541/* Analog bypass for AudioL2 */
542static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
543 SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
544
fcd274a3
LCM		 545/* Analog bypass for Voice */
546static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
547 SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
548
8b0d3153 549/* Digital bypass gain, mute instead of -30dB */
6bab83fd 550static const unsigned int twl4030_dapm_dbypass_tlv[] = {
8b0d3153
PU		 551 TLV_DB_RANGE_HEAD(3),
552 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
553 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
6bab83fd
PU		 554 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
555};
556
557/* Digital bypass left (TX1L -> RX2L) */
558static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
559 SOC_DAPM_SINGLE_TLV("Volume",
560 TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
561 twl4030_dapm_dbypass_tlv);
562
563/* Digital bypass right (TX1R -> RX2R) */
564static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
565 SOC_DAPM_SINGLE_TLV("Volume",
566 TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
567 twl4030_dapm_dbypass_tlv);
568
ee8f6894
LCM		 569/*
570 * Voice Sidetone GAIN volume control:
571 * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
572 */
573static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
574
575/* Digital bypass voice: sidetone (VUL -> VDL)*/
576static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
577 SOC_DAPM_SINGLE_TLV("Volume",
578 TWL4030_REG_VSTPGA, 0, 0x29, 0,
579 twl4030_dapm_dbypassv_tlv);
580
9008adf9
PU		 581/*
582 * Output PGA builder:
583 * Handle the muting and unmuting of the given output (turning off the
584 * amplifier associated with the output pin)
c96907f2
PU		 585 * On mute bypass the reg_cache and write 0 to the register
586 * On unmute: restore the register content from the reg_cache
9008adf9
PU		 587 * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
588 */
589#define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
590static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
591 struct snd_kcontrol *kcontrol, int event) \
592{ \
b2c812e2 593 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
9008adf9
PU		 594 \
595 switch (event) { \
596 case SND_SOC_DAPM_POST_PMU: \
c96907f2 597 twl4030->pin_name##_enabled = 1; \
9008adf9
PU		 598 twl4030_write(w->codec, reg, \
599 twl4030_read_reg_cache(w->codec, reg)); \
600 break; \
601 case SND_SOC_DAPM_POST_PMD: \
c96907f2
PU		 602 twl4030->pin_name##_enabled = 0; \
603 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
604 0, reg); \
9008adf9
PU		 605 break; \
606 } \
607 return 0; \
608}
609
610TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
611TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
612TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
613TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
614TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
615
5a2e9a48 616static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
49d92c7d 617{
49d92c7d
SM		 618 unsigned char hs_ctl;
619
5a2e9a48 620 hs_ctl = twl4030_read_reg_cache(codec, reg);
49d92c7d 621
5a2e9a48
PU		 622 if (ramp) {
623 /* HF ramp-up */
624 hs_ctl |= TWL4030_HF_CTL_REF_EN;
625 twl4030_write(codec, reg, hs_ctl);
626 udelay(10);
49d92c7d 627 hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
5a2e9a48
PU		 628 twl4030_write(codec, reg, hs_ctl);
629 udelay(40);
49d92c7d 630 hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
49d92c7d 631 hs_ctl |= TWL4030_HF_CTL_HB_EN;
5a2e9a48 632 twl4030_write(codec, reg, hs_ctl);
49d92c7d 633 } else {
5a2e9a48
PU		 634 /* HF ramp-down */
635 hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
636 hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
637 twl4030_write(codec, reg, hs_ctl);
638 hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
639 twl4030_write(codec, reg, hs_ctl);
640 udelay(40);
641 hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
642 twl4030_write(codec, reg, hs_ctl);
49d92c7d 643 }
5a2e9a48 644}
49d92c7d 645
5a2e9a48
PU		 646static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
647 struct snd_kcontrol *kcontrol, int event)
648{
649 switch (event) {
650 case SND_SOC_DAPM_POST_PMU:
651 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
652 break;
653 case SND_SOC_DAPM_POST_PMD:
654 handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
655 break;
656 }
657 return 0;
658}
659
660static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
661 struct snd_kcontrol *kcontrol, int event)
662{
663 switch (event) {
664 case SND_SOC_DAPM_POST_PMU:
665 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
666 break;
667 case SND_SOC_DAPM_POST_PMD:
668 handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
669 break;
670 }
49d92c7d
SM		 671 return 0;
672}
673
86139a13
JV		 674static int vibramux_event(struct snd_soc_dapm_widget *w,
675 struct snd_kcontrol *kcontrol, int event)
676{
677 twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
678 return 0;
679}
680
7729cf74
PU		 681static int apll_event(struct snd_soc_dapm_widget *w,
682 struct snd_kcontrol *kcontrol, int event)
683{
684 switch (event) {
685 case SND_SOC_DAPM_PRE_PMU:
686 twl4030_apll_enable(w->codec, 1);
687 break;
688 case SND_SOC_DAPM_POST_PMD:
689 twl4030_apll_enable(w->codec, 0);
690 break;
691 }
692 return 0;
693}
694
7b4c734e
PU		 695static int aif_event(struct snd_soc_dapm_widget *w,
696 struct snd_kcontrol *kcontrol, int event)
697{
698 u8 audio_if;
699
700 audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
701 switch (event) {
702 case SND_SOC_DAPM_PRE_PMU:
703 /* Enable AIF */
704 /* enable the PLL before we use it to clock the DAI */
705 twl4030_apll_enable(w->codec, 1);
706
707 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
708 audio_if | TWL4030_AIF_EN);
709 break;
710 case SND_SOC_DAPM_POST_PMD:
711 /* disable the DAI before we stop it's source PLL */
712 twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
713 audio_if & ~TWL4030_AIF_EN);
714 twl4030_apll_enable(w->codec, 0);
715 break;
716 }
717 return 0;
718}
719
6943c92e 720static void headset_ramp(struct snd_soc_codec *codec, int ramp)
aad749e5 721{
f0fba2ad 722 struct twl4030_codec_audio_data *pdata = codec->dev->platform_data;
aad749e5 723 unsigned char hs_gain, hs_pop;
b2c812e2 724 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
6943c92e
PU		 725 /* Base values for ramp delay calculation: 2^19 - 2^26 */
726 unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
727 8388608, 16777216, 33554432, 67108864};
aad749e5 728
6943c92e
PU		 729 hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
730 hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
aad749e5 731
4e49ffd1
CVJ		 732 /* Enable external mute control, this dramatically reduces
733 * the pop-noise */
f0fba2ad
LG		 734 if (pdata && pdata->hs_extmute) {
735 if (pdata->set_hs_extmute) {
736 pdata->set_hs_extmute(1);
4e49ffd1
CVJ		 737 } else {
738 hs_pop |= TWL4030_EXTMUTE;
739 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
740 }
741 }
742
6943c92e
PU		 743 if (ramp) {
744 /* Headset ramp-up according to the TRM */
aad749e5 745 hs_pop |= TWL4030_VMID_EN;
6943c92e 746 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
c96907f2
PU		 747 /* Actually write to the register */
748 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
749 hs_gain,
750 TWL4030_REG_HS_GAIN_SET);
aad749e5 751 hs_pop |= TWL4030_RAMP_EN;
6943c92e 752 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
4e49ffd1
CVJ		 753 /* Wait ramp delay time + 1, so the VMID can settle */
754 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
755 twl4030->sysclk) + 1);
6943c92e
PU		 756 } else {
757 /* Headset ramp-down _not_ according to
758 * the TRM, but in a way that it is working */
aad749e5 759 hs_pop &= ~TWL4030_RAMP_EN;
6943c92e
PU		 760 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
761 /* Wait ramp delay time + 1, so the VMID can settle */
762 mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
763 twl4030->sysclk) + 1);
aad749e5 764 /* Bypass the reg_cache to mute the headset */
fc7b92fc 765 twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
aad749e5
PU		 766 hs_gain & (~0x0f),
767 TWL4030_REG_HS_GAIN_SET);
6943c92e 768
aad749e5 769 hs_pop &= ~TWL4030_VMID_EN;
6943c92e
PU		 770 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
771 }
4e49ffd1
CVJ		 772
773 /* Disable external mute */
f0fba2ad
LG		 774 if (pdata && pdata->hs_extmute) {
775 if (pdata->set_hs_extmute) {
776 pdata->set_hs_extmute(0);
4e49ffd1
CVJ		 777 } else {
778 hs_pop &= ~TWL4030_EXTMUTE;
779 twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
780 }
781 }
6943c92e
PU		 782}
783
784static int headsetlpga_event(struct snd_soc_dapm_widget *w,
785 struct snd_kcontrol *kcontrol, int event)
786{
b2c812e2 787 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 788
789 switch (event) {
790 case SND_SOC_DAPM_POST_PMU:
791 /* Do the ramp-up only once */
792 if (!twl4030->hsr_enabled)
793 headset_ramp(w->codec, 1);
794
795 twl4030->hsl_enabled = 1;
796 break;
797 case SND_SOC_DAPM_POST_PMD:
798 /* Do the ramp-down only if both headsetL/R is disabled */
799 if (!twl4030->hsr_enabled)
800 headset_ramp(w->codec, 0);
801
802 twl4030->hsl_enabled = 0;
803 break;
804 }
805 return 0;
806}
807
808static int headsetrpga_event(struct snd_soc_dapm_widget *w,
809 struct snd_kcontrol *kcontrol, int event)
810{
b2c812e2 811 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
6943c92e
PU		 812
813 switch (event) {
814 case SND_SOC_DAPM_POST_PMU:
815 /* Do the ramp-up only once */
816 if (!twl4030->hsl_enabled)
817 headset_ramp(w->codec, 1);
818
819 twl4030->hsr_enabled = 1;
820 break;
821 case SND_SOC_DAPM_POST_PMD:
822 /* Do the ramp-down only if both headsetL/R is disabled */
823 if (!twl4030->hsl_enabled)
824 headset_ramp(w->codec, 0);
825
826 twl4030->hsr_enabled = 0;
aad749e5
PU		 827 break;
828 }
829 return 0;
830}
831
01ea6ba2
PU		 832static int digimic_event(struct snd_soc_dapm_widget *w,
833 struct snd_kcontrol *kcontrol, int event)
834{
835 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
836
837 if (twl4030->digimic_delay)
838 mdelay(twl4030->digimic_delay);
839 return 0;
840}
841
b0bd53a7
PU		 842/*
843 * Some of the gain controls in TWL (mostly those which are associated with
844 * the outputs) are implemented in an interesting way:
845 * 0x0 : Power down (mute)
846 * 0x1 : 6dB
847 * 0x2 : 0 dB
848 * 0x3 : -6 dB
849 * Inverting not going to help with these.
850 * Custom volsw and volsw_2r get/put functions to handle these gain bits.
851 */
852#define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
853 xinvert, tlv_array) \
854{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
855 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
856 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
857 .tlv.p = (tlv_array), \
858 .info = snd_soc_info_volsw, \
859 .get = snd_soc_get_volsw_twl4030, \
860 .put = snd_soc_put_volsw_twl4030, \
861 .private_value = (unsigned long)&(struct soc_mixer_control) \
862 {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
863 .max = xmax, .invert = xinvert} }
864#define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
865 xinvert, tlv_array) \
866{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
867 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
868 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
869 .tlv.p = (tlv_array), \
870 .info = snd_soc_info_volsw_2r, \
871 .get = snd_soc_get_volsw_r2_twl4030,\
872 .put = snd_soc_put_volsw_r2_twl4030, \
873 .private_value = (unsigned long)&(struct soc_mixer_control) \
874 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
64089b84 875 .rshift = xshift, .max = xmax, .invert = xinvert} }
b0bd53a7
PU		 876#define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
877 SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
878 xinvert, tlv_array)
879
880static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
881 struct snd_ctl_elem_value *ucontrol)
882{
883 struct soc_mixer_control *mc =
884 (struct soc_mixer_control *)kcontrol->private_value;
885 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
886 unsigned int reg = mc->reg;
887 unsigned int shift = mc->shift;
888 unsigned int rshift = mc->rshift;
889 int max = mc->max;
890 int mask = (1 << fls(max)) - 1;
891
892 ucontrol->value.integer.value[0] =
893 (snd_soc_read(codec, reg) >> shift) & mask;
894 if (ucontrol->value.integer.value[0])
895 ucontrol->value.integer.value[0] =
896 max + 1 - ucontrol->value.integer.value[0];
897
898 if (shift != rshift) {
899 ucontrol->value.integer.value[1] =
900 (snd_soc_read(codec, reg) >> rshift) & mask;
901 if (ucontrol->value.integer.value[1])
902 ucontrol->value.integer.value[1] =
903 max + 1 - ucontrol->value.integer.value[1];
904 }
905
906 return 0;
907}
908
909static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
910 struct snd_ctl_elem_value *ucontrol)
911{
912 struct soc_mixer_control *mc =
913 (struct soc_mixer_control *)kcontrol->private_value;
914 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
915 unsigned int reg = mc->reg;
916 unsigned int shift = mc->shift;
917 unsigned int rshift = mc->rshift;
918 int max = mc->max;
919 int mask = (1 << fls(max)) - 1;
920 unsigned short val, val2, val_mask;
921
922 val = (ucontrol->value.integer.value[0] & mask);
923
924 val_mask = mask << shift;
925 if (val)
926 val = max + 1 - val;
927 val = val << shift;
928 if (shift != rshift) {
929 val2 = (ucontrol->value.integer.value[1] & mask);
930 val_mask |= mask << rshift;
931 if (val2)
932 val2 = max + 1 - val2;
933 val |= val2 << rshift;
934 }
935 return snd_soc_update_bits(codec, reg, val_mask, val);
936}
937
938static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
939 struct snd_ctl_elem_value *ucontrol)
940{
941 struct soc_mixer_control *mc =
942 (struct soc_mixer_control *)kcontrol->private_value;
943 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
944 unsigned int reg = mc->reg;
945 unsigned int reg2 = mc->rreg;
946 unsigned int shift = mc->shift;
947 int max = mc->max;
948 int mask = (1<<fls(max))-1;
949
950 ucontrol->value.integer.value[0] =
951 (snd_soc_read(codec, reg) >> shift) & mask;
952 ucontrol->value.integer.value[1] =
953 (snd_soc_read(codec, reg2) >> shift) & mask;
954
955 if (ucontrol->value.integer.value[0])
956 ucontrol->value.integer.value[0] =
957 max + 1 - ucontrol->value.integer.value[0];
958 if (ucontrol->value.integer.value[1])
959 ucontrol->value.integer.value[1] =
960 max + 1 - ucontrol->value.integer.value[1];
961
962 return 0;
963}
964
965static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
966 struct snd_ctl_elem_value *ucontrol)
967{
968 struct soc_mixer_control *mc =
969 (struct soc_mixer_control *)kcontrol->private_value;
970 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
971 unsigned int reg = mc->reg;
972 unsigned int reg2 = mc->rreg;
973 unsigned int shift = mc->shift;
974 int max = mc->max;
975 int mask = (1 << fls(max)) - 1;
976 int err;
977 unsigned short val, val2, val_mask;
978
979 val_mask = mask << shift;
980 val = (ucontrol->value.integer.value[0] & mask);
981 val2 = (ucontrol->value.integer.value[1] & mask);
982
983 if (val)
984 val = max + 1 - val;
985 if (val2)
986 val2 = max + 1 - val2;
987
988 val = val << shift;
989 val2 = val2 << shift;
990
991 err = snd_soc_update_bits(codec, reg, val_mask, val);
992 if (err < 0)
993 return err;
994
995 err = snd_soc_update_bits(codec, reg2, val_mask, val2);
996 return err;
997}
998
b74bd40f
LCM		 999/* Codec operation modes */
1000static const char *twl4030_op_modes_texts[] = {
1001 "Option 2 (voice/audio)", "Option 1 (audio)"
1002};
1003
1004static const struct soc_enum twl4030_op_modes_enum =
1005 SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1006 ARRAY_SIZE(twl4030_op_modes_texts),
1007 twl4030_op_modes_texts);
1008
423c238d 1009static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
b74bd40f
LCM		 1010 struct snd_ctl_elem_value *ucontrol)
1011{
1012 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 1013 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
b74bd40f
LCM		 1014 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1015 unsigned short val;
1016 unsigned short mask, bitmask;
1017
1018 if (twl4030->configured) {
1019 printk(KERN_ERR "twl4030 operation mode cannot be "
1020 "changed on-the-fly\n");
1021 return -EBUSY;
1022 }
1023
1024 for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
1025 ;
1026 if (ucontrol->value.enumerated.item[0] > e->max - 1)
1027 return -EINVAL;
1028
1029 val = ucontrol->value.enumerated.item[0] << e->shift_l;
1030 mask = (bitmask - 1) << e->shift_l;
1031 if (e->shift_l != e->shift_r) {
1032 if (ucontrol->value.enumerated.item[1] > e->max - 1)
1033 return -EINVAL;
1034 val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1035 mask |= (bitmask - 1) << e->shift_r;
1036 }
1037
1038 return snd_soc_update_bits(codec, e->reg, mask, val);
1039}
1040
c10b82cf
PU		 1041/*
1042 * FGAIN volume control:
1043 * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1044 */
d889a72c 1045static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
c10b82cf 1046
0d33ea0b
PU		 1047/*
1048 * CGAIN volume control:
1049 * 0 dB to 12 dB in 6 dB steps
1050 * value 2 and 3 means 12 dB
1051 */
d889a72c
PU		 1052static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1053
1a787e7a
JS		 1054/*
1055 * Voice Downlink GAIN volume control:
1056 * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1057 */
1058static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1059
d889a72c
PU		 1060/*
1061 * Analog playback gain
1062 * -24 dB to 12 dB in 2 dB steps
1063 */
1064static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
0d33ea0b 1065
4290239c
PU		 1066/*
1067 * Gain controls tied to outputs
1068 * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1069 */
1070static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1071
18cc8d8d
JS		 1072/*
1073 * Gain control for earpiece amplifier
1074 * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1075 */
1076static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1077
381a22b5
PU		 1078/*
1079 * Capture gain after the ADCs
1080 * from 0 dB to 31 dB in 1 dB steps
1081 */
1082static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1083
5920b453
GI		 1084/*
1085 * Gain control for input amplifiers
1086 * 0 dB to 30 dB in 6 dB steps
1087 */
1088static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1089
328d0a13
LCM		 1090/* AVADC clock priority */
1091static const char *twl4030_avadc_clk_priority_texts[] = {
1092 "Voice high priority", "HiFi high priority"
1093};
1094
1095static const struct soc_enum twl4030_avadc_clk_priority_enum =
1096 SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1097 ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1098 twl4030_avadc_clk_priority_texts);
1099
89492be8
PU		 1100static const char *twl4030_rampdelay_texts[] = {
1101 "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1102 "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1103 "3495/2581/1748 ms"
1104};
1105
1106static const struct soc_enum twl4030_rampdelay_enum =
1107 SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1108 ARRAY_SIZE(twl4030_rampdelay_texts),
1109 twl4030_rampdelay_texts);
1110
376f7839
PU		 1111/* Vibra H-bridge direction mode */
1112static const char *twl4030_vibradirmode_texts[] = {
1113 "Vibra H-bridge direction", "Audio data MSB",
1114};
1115
1116static const struct soc_enum twl4030_vibradirmode_enum =
1117 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1118 ARRAY_SIZE(twl4030_vibradirmode_texts),
1119 twl4030_vibradirmode_texts);
1120
1121/* Vibra H-bridge direction */
1122static const char *twl4030_vibradir_texts[] = {
1123 "Positive polarity", "Negative polarity",
1124};
1125
1126static const struct soc_enum twl4030_vibradir_enum =
1127 SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1128 ARRAY_SIZE(twl4030_vibradir_texts),
1129 twl4030_vibradir_texts);
1130
36aeff61
PU		 1131/* Digimic Left and right swapping */
1132static const char *twl4030_digimicswap_texts[] = {
1133 "Not swapped", "Swapped",
1134};
1135
1136static const struct soc_enum twl4030_digimicswap_enum =
1137 SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1138 ARRAY_SIZE(twl4030_digimicswap_texts),
1139 twl4030_digimicswap_texts);
1140
cc17557e 1141static const struct snd_kcontrol_new twl4030_snd_controls[] = {
b74bd40f
LCM		 1142 /* Codec operation mode control */
1143 SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1144 snd_soc_get_enum_double,
1145 snd_soc_put_twl4030_opmode_enum_double),
1146
d889a72c
PU		 1147 /* Common playback gain controls */
1148 SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1149 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1150 0, 0x3f, 0, digital_fine_tlv),
1151 SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1152 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1153 0, 0x3f, 0, digital_fine_tlv),
1154
1155 SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1156 TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1157 6, 0x2, 0, digital_coarse_tlv),
1158 SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1159 TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1160 6, 0x2, 0, digital_coarse_tlv),
1161
1162 SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1163 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1164 3, 0x12, 1, analog_tlv),
1165 SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1166 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1167 3, 0x12, 1, analog_tlv),
44c55870
PU		 1168 SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1169 TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1170 1, 1, 0),
1171 SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1172 TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1173 1, 1, 0),
381a22b5 1174
1a787e7a
JS		 1175 /* Common voice downlink gain controls */
1176 SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1177 TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1178
1179 SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1180 TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1181
1182 SOC_SINGLE("DAC Voice Analog Downlink Switch",
1183 TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1184
4290239c
PU		 1185 /* Separate output gain controls */
1186 SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
1187 TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1188 4, 3, 0, output_tvl),
1189
1190 SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
1191 TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
1192
1193 SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
1194 TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1195 4, 3, 0, output_tvl),
1196
1197 SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
18cc8d8d 1198 TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
4290239c 1199
381a22b5 1200 /* Common capture gain controls */
276c6222 1201 SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
381a22b5
PU		 1202 TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1203 0, 0x1f, 0, digital_capture_tlv),
276c6222
PU		 1204 SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1205 TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1206 0, 0x1f, 0, digital_capture_tlv),
5920b453 1207
276c6222 1208 SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
5920b453 1209 0, 3, 5, 0, input_gain_tlv),
89492be8 1210
328d0a13
LCM		 1211 SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1212
89492be8 1213 SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
376f7839
PU		 1214
1215 SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1216 SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
36aeff61
PU		 1217
1218 SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
cc17557e
SS		 1219};
1220
cc17557e 1221static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
276c6222
PU		 1222 /* Left channel inputs */
1223 SND_SOC_DAPM_INPUT("MAINMIC"),
1224 SND_SOC_DAPM_INPUT("HSMIC"),
1225 SND_SOC_DAPM_INPUT("AUXL"),
1226 SND_SOC_DAPM_INPUT("CARKITMIC"),
1227 /* Right channel inputs */
1228 SND_SOC_DAPM_INPUT("SUBMIC"),
1229 SND_SOC_DAPM_INPUT("AUXR"),
1230 /* Digital microphones (Stereo) */
1231 SND_SOC_DAPM_INPUT("DIGIMIC0"),
1232 SND_SOC_DAPM_INPUT("DIGIMIC1"),
1233
1234 /* Outputs */
5e98a464 1235 SND_SOC_DAPM_OUTPUT("EARPIECE"),
2a6f5c58
PU		 1236 SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1237 SND_SOC_DAPM_OUTPUT("PREDRIVER"),
dfad21a2
PU		 1238 SND_SOC_DAPM_OUTPUT("HSOL"),
1239 SND_SOC_DAPM_OUTPUT("HSOR"),
6a1bee4a
PU		 1240 SND_SOC_DAPM_OUTPUT("CARKITL"),
1241 SND_SOC_DAPM_OUTPUT("CARKITR"),
df339804
PU		 1242 SND_SOC_DAPM_OUTPUT("HFL"),
1243 SND_SOC_DAPM_OUTPUT("HFR"),
376f7839 1244 SND_SOC_DAPM_OUTPUT("VIBRA"),
cc17557e 1245
7b4c734e
PU		 1246 /* AIF and APLL clocks for running DAIs (including loopback) */
1247 SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1248 SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1249 SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1250
53b5047d 1251 /* DACs */
b4852b79 1252 SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
7393958f 1253 SND_SOC_NOPM, 0, 0),
b4852b79 1254 SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
7393958f 1255 SND_SOC_NOPM, 0, 0),
b4852b79 1256 SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
7393958f 1257 SND_SOC_NOPM, 0, 0),
b4852b79 1258 SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
7393958f 1259 SND_SOC_NOPM, 0, 0),
1a787e7a 1260 SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
fcd274a3 1261 SND_SOC_NOPM, 0, 0),
cc17557e 1262
7393958f 1263 /* Analog bypasses */
78e08e2f
PU		 1264 SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1265 &twl4030_dapm_abypassr1_control),
1266 SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1267 &twl4030_dapm_abypassl1_control),
1268 SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1269 &twl4030_dapm_abypassr2_control),
1270 SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1271 &twl4030_dapm_abypassl2_control),
1272 SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1273 &twl4030_dapm_abypassv_control),
1274
1275 /* Master analog loopback switch */
1276 SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1277 NULL, 0),
7393958f 1278
6bab83fd 1279 /* Digital bypasses */
78e08e2f
PU		 1280 SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1281 &twl4030_dapm_dbypassl_control),
1282 SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1283 &twl4030_dapm_dbypassr_control),
1284 SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1285 &twl4030_dapm_dbypassv_control),
6bab83fd 1286
4005d39a
PU		 1287 /* Digital mixers, power control for the physical DACs */
1288 SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1289 TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1290 SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1291 TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1292 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1293 TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1294 SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1295 TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1296 SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1297 TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1298
1299 /* Analog mixers, power control for the physical PGAs */
1300 SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1301 TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1302 SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1303 TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1304 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1305 TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1306 SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1307 TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1308 SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1309 TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
7393958f 1310
7729cf74
PU		 1311 SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1312 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1313
7b4c734e
PU		 1314 SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1315 SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
c42a59ea 1316
1a787e7a 1317 /* Output MIXER controls */
5e98a464 1318 /* Earpiece */
1a787e7a
JS		 1319 SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1320 &twl4030_dapm_earpiece_controls[0],
1321 ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
9008adf9
PU		 1322 SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1323 0, 0, NULL, 0, earpiecepga_event,
1324 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
2a6f5c58 1325 /* PreDrivL/R */
1a787e7a
JS		 1326 SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1327 &twl4030_dapm_predrivel_controls[0],
1328 ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
9008adf9
PU		 1329 SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1330 0, 0, NULL, 0, predrivelpga_event,
1331 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1332 SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1333 &twl4030_dapm_predriver_controls[0],
1334 ARRAY_SIZE(twl4030_dapm_predriver_controls)),
9008adf9
PU		 1335 SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1336 0, 0, NULL, 0, predriverpga_event,
1337 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
dfad21a2 1338 /* HeadsetL/R */
6943c92e 1339 SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1a787e7a 1340 &twl4030_dapm_hsol_controls[0],
6943c92e
PU		 1341 ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1342 SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1343 0, 0, NULL, 0, headsetlpga_event,
1a787e7a
JS		 1344 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1345 SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1346 &twl4030_dapm_hsor_controls[0],
1347 ARRAY_SIZE(twl4030_dapm_hsor_controls)),
6943c92e
PU		 1348 SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1349 0, 0, NULL, 0, headsetrpga_event,
1350 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
5152d8c2 1351 /* CarkitL/R */
1a787e7a
JS		 1352 SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1353 &twl4030_dapm_carkitl_controls[0],
1354 ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
9008adf9
PU		 1355 SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1356 0, 0, NULL, 0, carkitlpga_event,
1357 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1358 SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1359 &twl4030_dapm_carkitr_controls[0],
1360 ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
9008adf9
PU		 1361 SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1362 0, 0, NULL, 0, carkitrpga_event,
1363 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1a787e7a
JS		 1364
1365 /* Output MUX controls */
df339804 1366 /* HandsfreeL/R */
5a2e9a48
PU		 1367 SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1368 &twl4030_dapm_handsfreel_control),
e3c7dbb0 1369 SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
0f89bdca 1370 &twl4030_dapm_handsfreelmute_control),
5a2e9a48
PU		 1371 SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1372 0, 0, NULL, 0, handsfreelpga_event,
1373 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1374 SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1375 &twl4030_dapm_handsfreer_control),
e3c7dbb0 1376 SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
0f89bdca 1377 &twl4030_dapm_handsfreermute_control),
5a2e9a48
PU		 1378 SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1379 0, 0, NULL, 0, handsfreerpga_event,
1380 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
376f7839 1381 /* Vibra */
86139a13
JV		 1382 SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1383 &twl4030_dapm_vibra_control, vibramux_event,
1384 SND_SOC_DAPM_PRE_PMU),
376f7839
PU		 1385 SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1386 &twl4030_dapm_vibrapath_control),
5e98a464 1387
276c6222
PU		 1388 /* Introducing four virtual ADC, since TWL4030 have four channel for
1389 capture */
1390 SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
1391 SND_SOC_NOPM, 0, 0),
1392 SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
1393 SND_SOC_NOPM, 0, 0),
1394 SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
1395 SND_SOC_NOPM, 0, 0),
1396 SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
1397 SND_SOC_NOPM, 0, 0),
1398
1399 /* Analog/Digital mic path selection.
1400 TX1 Left/Right: either analog Left/Right or Digimic0
1401 TX2 Left/Right: either analog Left/Right or Digimic1 */
bda7d2a8
PU		 1402 SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1403 &twl4030_dapm_micpathtx1_control),
1404 SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1405 &twl4030_dapm_micpathtx2_control),
276c6222 1406
97b8096d 1407 /* Analog input mixers for the capture amplifiers */
9028935d 1408 SND_SOC_DAPM_MIXER("Analog Left",
97b8096d
JS		 1409 TWL4030_REG_ANAMICL, 4, 0,
1410 &twl4030_dapm_analoglmic_controls[0],
1411 ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
9028935d 1412 SND_SOC_DAPM_MIXER("Analog Right",
97b8096d
JS		 1413 TWL4030_REG_ANAMICR, 4, 0,
1414 &twl4030_dapm_analogrmic_controls[0],
1415 ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
276c6222 1416
fb2a2f84
PU		 1417 SND_SOC_DAPM_PGA("ADC Physical Left",
1418 TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1419 SND_SOC_DAPM_PGA("ADC Physical Right",
1420 TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
276c6222 1421
01ea6ba2
PU		 1422 SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1423 TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1424 digimic_event, SND_SOC_DAPM_POST_PMU),
1425 SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1426 TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1427 digimic_event, SND_SOC_DAPM_POST_PMU),
276c6222 1428
bda7d2a8
PU		 1429 SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1430 NULL, 0),
1431 SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1432 NULL, 0),
1433
276c6222
PU		 1434 SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1435 SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1436 SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
7393958f 1437
cc17557e
SS		 1438};
1439
1440static const struct snd_soc_dapm_route intercon[] = {
4005d39a
PU		 1441 {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1442 {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1443 {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1444 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1445 {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1446
7729cf74 1447 /* Supply for the digital part (APLL) */
7729cf74
PU		 1448 {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1449
27eeb1fe
PU		 1450 {"DAC Left1", NULL, "AIF Enable"},
1451 {"DAC Right1", NULL, "AIF Enable"},
1452 {"DAC Left2", NULL, "AIF Enable"},
1453 {"DAC Right1", NULL, "AIF Enable"},
1454
c42a59ea
PU		 1455 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1456 {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1457
4005d39a
PU		 1458 {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1459 {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1460 {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1461 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1462 {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1a787e7a 1463
5e98a464
PU		 1464 /* Internal playback routings */
1465 /* Earpiece */
4005d39a
PU		 1466 {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1467 {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1468 {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1469 {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
9008adf9 1470 {"Earpiece PGA", NULL, "Earpiece Mixer"},
2a6f5c58 1471 /* PreDrivL */
4005d39a
PU		 1472 {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1473 {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1474 {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1475 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1476 {"PredriveL PGA", NULL, "PredriveL Mixer"},
2a6f5c58 1477 /* PreDrivR */
4005d39a
PU		 1478 {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1479 {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1480 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1481 {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1482 {"PredriveR PGA", NULL, "PredriveR Mixer"},
dfad21a2 1483 /* HeadsetL */
4005d39a
PU		 1484 {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1485 {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1486 {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
6943c92e 1487 {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
dfad21a2 1488 /* HeadsetR */
4005d39a
PU		 1489 {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1490 {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1491 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
6943c92e 1492 {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
5152d8c2 1493 /* CarkitL */
4005d39a
PU		 1494 {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1495 {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1496 {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
9008adf9 1497 {"CarkitL PGA", NULL, "CarkitL Mixer"},
5152d8c2 1498 /* CarkitR */
4005d39a
PU		 1499 {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1500 {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1501 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
9008adf9 1502 {"CarkitR PGA", NULL, "CarkitR Mixer"},
df339804 1503 /* HandsfreeL */
4005d39a
PU		 1504 {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1505 {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1506 {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1507 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
e3c7dbb0
LCM		 1508 {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1509 {"HandsfreeL PGA", NULL, "HandsfreeL"},
df339804 1510 /* HandsfreeR */
4005d39a
PU		 1511 {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1512 {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1513 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1514 {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
e3c7dbb0
LCM		 1515 {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1516 {"HandsfreeR PGA", NULL, "HandsfreeR"},
376f7839
PU		 1517 /* Vibra */
1518 {"Vibra Mux", "AudioL1", "DAC Left1"},
1519 {"Vibra Mux", "AudioR1", "DAC Right1"},
1520 {"Vibra Mux", "AudioL2", "DAC Left2"},
1521 {"Vibra Mux", "AudioR2", "DAC Right2"},
5e98a464 1522
cc17557e 1523 /* outputs */
7b4c734e 1524 /* Must be always connected (for AIF and APLL) */
27eeb1fe
PU		 1525 {"Virtual HiFi OUT", NULL, "DAC Left1"},
1526 {"Virtual HiFi OUT", NULL, "DAC Right1"},
1527 {"Virtual HiFi OUT", NULL, "DAC Left2"},
1528 {"Virtual HiFi OUT", NULL, "DAC Right2"},
7b4c734e
PU		 1529 /* Must be always connected (for APLL) */
1530 {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1531 /* Physical outputs */
9008adf9
PU		 1532 {"EARPIECE", NULL, "Earpiece PGA"},
1533 {"PREDRIVEL", NULL, "PredriveL PGA"},
1534 {"PREDRIVER", NULL, "PredriveR PGA"},
6943c92e
PU		 1535 {"HSOL", NULL, "HeadsetL PGA"},
1536 {"HSOR", NULL, "HeadsetR PGA"},
9008adf9
PU		 1537 {"CARKITL", NULL, "CarkitL PGA"},
1538 {"CARKITR", NULL, "CarkitR PGA"},
5a2e9a48
PU		 1539 {"HFL", NULL, "HandsfreeL PGA"},
1540 {"HFR", NULL, "HandsfreeR PGA"},
376f7839
PU		 1541 {"Vibra Route", "Audio", "Vibra Mux"},
1542 {"VIBRA", NULL, "Vibra Route"},
cc17557e 1543
276c6222 1544 /* Capture path */
7b4c734e
PU		 1545 /* Must be always connected (for AIF and APLL) */
1546 {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1547 {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1548 {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1549 {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1550 /* Physical inputs */
9028935d
PU		 1551 {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1552 {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1553 {"Analog Left", "AUXL Capture Switch", "AUXL"},
1554 {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
276c6222 1555
9028935d
PU		 1556 {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1557 {"Analog Right", "AUXR Capture Switch", "AUXR"},
276c6222 1558
9028935d
PU		 1559 {"ADC Physical Left", NULL, "Analog Left"},
1560 {"ADC Physical Right", NULL, "Analog Right"},
276c6222
PU		 1561
1562 {"Digimic0 Enable", NULL, "DIGIMIC0"},
1563 {"Digimic1 Enable", NULL, "DIGIMIC1"},
1564
bda7d2a8
PU		 1565 {"DIGIMIC0", NULL, "micbias1 select"},
1566 {"DIGIMIC1", NULL, "micbias2 select"},
1567
276c6222 1568 /* TX1 Left capture path */
fb2a2f84 1569 {"TX1 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1570 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1571 /* TX1 Right capture path */
fb2a2f84 1572 {"TX1 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1573 {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1574 /* TX2 Left capture path */
fb2a2f84 1575 {"TX2 Capture Route", "Analog", "ADC Physical Left"},
276c6222
PU		 1576 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1577 /* TX2 Right capture path */
fb2a2f84 1578 {"TX2 Capture Route", "Analog", "ADC Physical Right"},
276c6222
PU		 1579 {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1580
1581 {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1582 {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1583 {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1584 {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1585
c42a59ea
PU		 1586 {"ADC Virtual Left1", NULL, "AIF Enable"},
1587 {"ADC Virtual Right1", NULL, "AIF Enable"},
1588 {"ADC Virtual Left2", NULL, "AIF Enable"},
1589 {"ADC Virtual Right2", NULL, "AIF Enable"},
1590
7393958f 1591 /* Analog bypass routes */
9028935d
PU		 1592 {"Right1 Analog Loopback", "Switch", "Analog Right"},
1593 {"Left1 Analog Loopback", "Switch", "Analog Left"},
1594 {"Right2 Analog Loopback", "Switch", "Analog Right"},
1595 {"Left2 Analog Loopback", "Switch", "Analog Left"},
1596 {"Voice Analog Loopback", "Switch", "Analog Left"},
7393958f 1597
78e08e2f
PU		 1598 /* Supply for the Analog loopbacks */
1599 {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1600 {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1601 {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1602 {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1603 {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1604
7393958f
PU		 1605 {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1606 {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1607 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1608 {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
fcd274a3 1609 {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
7393958f 1610
6bab83fd
PU		 1611 /* Digital bypass routes */
1612 {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1613 {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
ee8f6894 1614 {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
6bab83fd 1615
4005d39a
PU		 1616 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1617 {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1618 {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
6bab83fd 1619
cc17557e
SS		 1620};
1621
1622static int twl4030_add_widgets(struct snd_soc_codec *codec)
1623{
1624 snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
1625 ARRAY_SIZE(twl4030_dapm_widgets));
1626
1627 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
1628
cc17557e
SS		 1629 return 0;
1630}
1631
cc17557e
SS		 1632static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1633 enum snd_soc_bias_level level)
1634{
1635 switch (level) {
1636 case SND_SOC_BIAS_ON:
cc17557e
SS		 1637 break;
1638 case SND_SOC_BIAS_PREPARE:
cc17557e
SS		 1639 break;
1640 case SND_SOC_BIAS_STANDBY:
78e08e2f 1641 if (codec->bias_level == SND_SOC_BIAS_OFF)
ee4ccac7 1642 twl4030_codec_enable(codec, 1);
cc17557e
SS		 1643 break;
1644 case SND_SOC_BIAS_OFF:
cbd2db12 1645 twl4030_codec_enable(codec, 0);
cc17557e
SS		 1646 break;
1647 }
1648 codec->bias_level = level;
1649
1650 return 0;
1651}
1652
6b87a91f
PU		 1653static void twl4030_constraints(struct twl4030_priv *twl4030,
1654 struct snd_pcm_substream *mst_substream)
1655{
1656 struct snd_pcm_substream *slv_substream;
1657
1658 /* Pick the stream, which need to be constrained */
1659 if (mst_substream == twl4030->master_substream)
1660 slv_substream = twl4030->slave_substream;
1661 else if (mst_substream == twl4030->slave_substream)
1662 slv_substream = twl4030->master_substream;
1663 else /* This should not happen.. */
1664 return;
1665
1666 /* Set the constraints according to the already configured stream */
1667 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1668 SNDRV_PCM_HW_PARAM_RATE,
1669 twl4030->rate,
1670 twl4030->rate);
1671
1672 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1673 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1674 twl4030->sample_bits,
1675 twl4030->sample_bits);
1676
1677 snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1678 SNDRV_PCM_HW_PARAM_CHANNELS,
1679 twl4030->channels,
1680 twl4030->channels);
1681}
1682
8a1f936a
PU		 1683/* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1684 * capture has to be enabled/disabled. */
1685static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1686 int enable)
1687{
1688 u8 reg, mask;
1689
1690 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1691
1692 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1693 mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1694 else
1695 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1696
1697 if (enable)
1698 reg |= mask;
1699 else
1700 reg &= ~mask;
1701
1702 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1703}
1704
d6648da1
PU		 1705static int twl4030_startup(struct snd_pcm_substream *substream,
1706 struct snd_soc_dai *dai)
7220b9f4
PU		 1707{
1708 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1709 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1710 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4 1711
7220b9f4 1712 if (twl4030->master_substream) {
7220b9f4 1713 twl4030->slave_substream = substream;
6b87a91f
PU		 1714 /* The DAI has one configuration for playback and capture, so
1715 * if the DAI has been already configured then constrain this
1716 * substream to match it. */
1717 if (twl4030->configured)
1718 twl4030_constraints(twl4030, twl4030->master_substream);
1719 } else {
8a1f936a
PU		 1720 if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1721 TWL4030_OPTION_1)) {
1722 /* In option2 4 channel is not supported, set the
1723 * constraint for the first stream for channels, the
1724 * second stream will 'inherit' this cosntraint */
1725 snd_pcm_hw_constraint_minmax(substream->runtime,
1726 SNDRV_PCM_HW_PARAM_CHANNELS,
1727 2, 2);
1728 }
7220b9f4 1729 twl4030->master_substream = substream;
6b87a91f 1730 }
7220b9f4
PU		 1731
1732 return 0;
1733}
1734
d6648da1
PU		 1735static void twl4030_shutdown(struct snd_pcm_substream *substream,
1736 struct snd_soc_dai *dai)
7220b9f4
PU		 1737{
1738 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1739 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1740 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7220b9f4
PU		 1741
1742 if (twl4030->master_substream == substream)
1743 twl4030->master_substream = twl4030->slave_substream;
1744
1745 twl4030->slave_substream = NULL;
6b87a91f
PU		 1746
1747 /* If all streams are closed, or the remaining stream has not yet
1748 * been configured than set the DAI as not configured. */
1749 if (!twl4030->master_substream)
1750 twl4030->configured = 0;
1751 else if (!twl4030->master_substream->runtime->channels)
1752 twl4030->configured = 0;
8a1f936a
PU		 1753
1754 /* If the closing substream had 4 channel, do the necessary cleanup */
1755 if (substream->runtime->channels == 4)
1756 twl4030_tdm_enable(codec, substream->stream, 0);
7220b9f4
PU		 1757}
1758
cc17557e 1759static int twl4030_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1760 struct snd_pcm_hw_params *params,
1761 struct snd_soc_dai *dai)
cc17557e
SS		 1762{
1763 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1764 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1765 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1766 u8 mode, old_mode, format, old_format;
1767
8a1f936a
PU		 1768 /* If the substream has 4 channel, do the necessary setup */
1769 if (params_channels(params) == 4) {
eaf1ac8b
PU		 1770 format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1771 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1772
1773 /* Safety check: are we in the correct operating mode and
1774 * the interface is in TDM mode? */
1775 if ((mode & TWL4030_OPTION_1) &&
1776 ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
8a1f936a
PU		 1777 twl4030_tdm_enable(codec, substream->stream, 1);
1778 else
1779 return -EINVAL;
1780 }
1781
6b87a91f
PU		 1782 if (twl4030->configured)
1783 /* Ignoring hw_params for already configured DAI */
7220b9f4
PU		 1784 return 0;
1785
cc17557e
SS		 1786 /* bit rate */
1787 old_mode = twl4030_read_reg_cache(codec,
1788 TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1789 mode = old_mode & ~TWL4030_APLL_RATE;
1790
1791 switch (params_rate(params)) {
1792 case 8000:
1793 mode |= TWL4030_APLL_RATE_8000;
1794 break;
1795 case 11025:
1796 mode |= TWL4030_APLL_RATE_11025;
1797 break;
1798 case 12000:
1799 mode |= TWL4030_APLL_RATE_12000;
1800 break;
1801 case 16000:
1802 mode |= TWL4030_APLL_RATE_16000;
1803 break;
1804 case 22050:
1805 mode |= TWL4030_APLL_RATE_22050;
1806 break;
1807 case 24000:
1808 mode |= TWL4030_APLL_RATE_24000;
1809 break;
1810 case 32000:
1811 mode |= TWL4030_APLL_RATE_32000;
1812 break;
1813 case 44100:
1814 mode |= TWL4030_APLL_RATE_44100;
1815 break;
1816 case 48000:
1817 mode |= TWL4030_APLL_RATE_48000;
1818 break;
103f211d
PU		 1819 case 96000:
1820 mode |= TWL4030_APLL_RATE_96000;
1821 break;
cc17557e
SS		 1822 default:
1823 printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
1824 params_rate(params));
1825 return -EINVAL;
1826 }
1827
cc17557e
SS		 1828 /* sample size */
1829 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1830 format = old_format;
1831 format &= ~TWL4030_DATA_WIDTH;
1832 switch (params_format(params)) {
1833 case SNDRV_PCM_FORMAT_S16_LE:
1834 format |= TWL4030_DATA_WIDTH_16S_16W;
1835 break;
1836 case SNDRV_PCM_FORMAT_S24_LE:
1837 format |= TWL4030_DATA_WIDTH_32S_24W;
1838 break;
1839 default:
1840 printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
1841 params_format(params));
1842 return -EINVAL;
1843 }
1844
2046f175
PU		 1845 if (format != old_format || mode != old_mode) {
1846 if (twl4030->codec_powered) {
1847 /*
1848 * If the codec is powered, than we need to toggle the
1849 * codec power.
1850 */
1851 twl4030_codec_enable(codec, 0);
1852 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1853 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1854 twl4030_codec_enable(codec, 1);
1855 } else {
1856 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1857 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1858 }
cc17557e 1859 }
6b87a91f
PU		 1860
1861 /* Store the important parameters for the DAI configuration and set
1862 * the DAI as configured */
1863 twl4030->configured = 1;
1864 twl4030->rate = params_rate(params);
1865 twl4030->sample_bits = hw_param_interval(params,
1866 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1867 twl4030->channels = params_channels(params);
1868
1869 /* If both playback and capture streams are open, and one of them
1870 * is setting the hw parameters right now (since we are here), set
1871 * constraints to the other stream to match the current one. */
1872 if (twl4030->slave_substream)
1873 twl4030_constraints(twl4030, substream);
1874
cc17557e
SS		 1875 return 0;
1876}
1877
1878static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1879 int clk_id, unsigned int freq, int dir)
1880{
1881 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1882 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1883
1884 switch (freq) {
1885 case 19200000:
cc17557e 1886 case 26000000:
cc17557e 1887 case 38400000:
cc17557e
SS		 1888 break;
1889 default:
68d01955 1890 dev_err(codec->dev, "Unsupported APLL mclk: %u\n", freq);
cc17557e
SS		 1891 return -EINVAL;
1892 }
1893
68d01955
PU		 1894 if ((freq / 1000) != twl4030->sysclk) {
1895 dev_err(codec->dev,
1896 "Mismatch in APLL mclk: %u (configured: %u)\n",
1897 freq, twl4030->sysclk * 1000);
1898 return -EINVAL;
1899 }
cc17557e
SS		 1900
1901 return 0;
1902}
1903
1904static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1905 unsigned int fmt)
1906{
1907 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 1908 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
cc17557e
SS		 1909 u8 old_format, format;
1910
1911 /* get format */
1912 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1913 format = old_format;
1914
1915 /* set master/slave audio interface */
1916 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1917 case SND_SOC_DAIFMT_CBM_CFM:
1918 format &= ~(TWL4030_AIF_SLAVE_EN);
e18c94d2 1919 format &= ~(TWL4030_CLK256FS_EN);
cc17557e
SS		 1920 break;
1921 case SND_SOC_DAIFMT_CBS_CFS:
cc17557e 1922 format |= TWL4030_AIF_SLAVE_EN;
e18c94d2 1923 format |= TWL4030_CLK256FS_EN;
cc17557e
SS		 1924 break;
1925 default:
1926 return -EINVAL;
1927 }
1928
1929 /* interface format */
1930 format &= ~TWL4030_AIF_FORMAT;
1931 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1932 case SND_SOC_DAIFMT_I2S:
1933 format |= TWL4030_AIF_FORMAT_CODEC;
1934 break;
8a1f936a
PU		 1935 case SND_SOC_DAIFMT_DSP_A:
1936 format |= TWL4030_AIF_FORMAT_TDM;
1937 break;
cc17557e
SS		 1938 default:
1939 return -EINVAL;
1940 }
1941
1942 if (format != old_format) {
2046f175
PU		 1943 if (twl4030->codec_powered) {
1944 /*
1945 * If the codec is powered, than we need to toggle the
1946 * codec power.
1947 */
1948 twl4030_codec_enable(codec, 0);
1949 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1950 twl4030_codec_enable(codec, 1);
1951 } else {
1952 twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1953 }
cc17557e
SS		 1954 }
1955
1956 return 0;
1957}
1958
68140443
LCM		 1959static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
1960{
1961 struct snd_soc_codec *codec = dai->codec;
1962 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1963
1964 if (tristate)
1965 reg |= TWL4030_AIF_TRI_EN;
1966 else
1967 reg &= ~TWL4030_AIF_TRI_EN;
1968
1969 return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
1970}
1971
b7a755a8
MLC		 1972/* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
1973 * (VTXL, VTXR) for uplink has to be enabled/disabled. */
1974static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
1975 int enable)
1976{
1977 u8 reg, mask;
1978
1979 reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1980
1981 if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1982 mask = TWL4030_ARXL1_VRX_EN;
1983 else
1984 mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1985
1986 if (enable)
1987 reg |= mask;
1988 else
1989 reg &= ~mask;
1990
1991 twl4030_write(codec, TWL4030_REG_OPTION, reg);
1992}
1993
7154b3e8
JS		 1994static int twl4030_voice_startup(struct snd_pcm_substream *substream,
1995 struct snd_soc_dai *dai)
1996{
1997 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1998 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1999 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2000 u8 mode;
2001
2002 /* If the system master clock is not 26MHz, the voice PCM interface is
2003 * not avilable.
2004 */
68d01955
PU		 2005 if (twl4030->sysclk != 26000) {
2006 dev_err(codec->dev, "The board is configured for %u Hz, while"
2007 "the Voice interface needs 26MHz APLL mclk\n",
2008 twl4030->sysclk * 1000);
7154b3e8
JS		 2009 return -EINVAL;
2010 }
2011
2012 /* If the codec mode is not option2, the voice PCM interface is not
2013 * avilable.
2014 */
2015 mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2016 & TWL4030_OPT_MODE;
2017
2018 if (mode != TWL4030_OPTION_2) {
2019 printk(KERN_ERR "TWL4030 voice startup: "
2020 "the codec mode is not option2\n");
2021 return -EINVAL;
2022 }
2023
2024 return 0;
2025}
2026
b7a755a8
MLC		 2027static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2028 struct snd_soc_dai *dai)
2029{
2030 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 2031 struct snd_soc_codec *codec = rtd->codec;
b7a755a8
MLC		 2032
2033 /* Enable voice digital filters */
2034 twl4030_voice_enable(codec, substream->stream, 0);
2035}
2036
7154b3e8
JS		 2037static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2038 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2039{
2040 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 2041 struct snd_soc_codec *codec = rtd->codec;
2046f175 2042 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2043 u8 old_mode, mode;
2044
b7a755a8
MLC		 2045 /* Enable voice digital filters */
2046 twl4030_voice_enable(codec, substream->stream, 1);
2047
7154b3e8
JS		 2048 /* bit rate */
2049 old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2050 & ~(TWL4030_CODECPDZ);
2051 mode = old_mode;
2052
2053 switch (params_rate(params)) {
2054 case 8000:
2055 mode &= ~(TWL4030_SEL_16K);
2056 break;
2057 case 16000:
2058 mode |= TWL4030_SEL_16K;
2059 break;
2060 default:
2061 printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
2062 params_rate(params));
2063 return -EINVAL;
2064 }
2065
2066 if (mode != old_mode) {
2046f175
PU		 2067 if (twl4030->codec_powered) {
2068 /*
2069 * If the codec is powered, than we need to toggle the
2070 * codec power.
2071 */
2072 twl4030_codec_enable(codec, 0);
2073 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2074 twl4030_codec_enable(codec, 1);
2075 } else {
2076 twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2077 }
7154b3e8
JS		 2078 }
2079
2080 return 0;
2081}
2082
2083static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2084 int clk_id, unsigned int freq, int dir)
2085{
2086 struct snd_soc_codec *codec = codec_dai->codec;
d4a8ca24 2087 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8 2088
68d01955
PU		 2089 if (freq != 26000000) {
2090 dev_err(codec->dev, "Unsupported APLL mclk: %u, the Voice"
2091 "interface needs 26MHz APLL mclk\n", freq);
2092 return -EINVAL;
2093 }
2094 if ((freq / 1000) != twl4030->sysclk) {
2095 dev_err(codec->dev,
2096 "Mismatch in APLL mclk: %u (configured: %u)\n",
2097 freq, twl4030->sysclk * 1000);
7154b3e8
JS		 2098 return -EINVAL;
2099 }
7154b3e8
JS		 2100 return 0;
2101}
2102
2103static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2104 unsigned int fmt)
2105{
2106 struct snd_soc_codec *codec = codec_dai->codec;
2046f175 2107 struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
7154b3e8
JS		 2108 u8 old_format, format;
2109
2110 /* get format */
2111 old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2112 format = old_format;
2113
2114 /* set master/slave audio interface */
2115 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
c264301c 2116 case SND_SOC_DAIFMT_CBM_CFM:
7154b3e8
JS		 2117 format &= ~(TWL4030_VIF_SLAVE_EN);
2118 break;
2119 case SND_SOC_DAIFMT_CBS_CFS:
2120 format |= TWL4030_VIF_SLAVE_EN;
2121 break;
2122 default:
2123 return -EINVAL;
2124 }
2125
2126 /* clock inversion */
2127 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2128 case SND_SOC_DAIFMT_IB_NF:
2129 format &= ~(TWL4030_VIF_FORMAT);
2130 break;
2131 case SND_SOC_DAIFMT_NB_IF:
2132 format |= TWL4030_VIF_FORMAT;
2133 break;
2134 default:
2135 return -EINVAL;
2136 }
2137
2138 if (format != old_format) {
2046f175
PU		 2139 if (twl4030->codec_powered) {
2140 /*
2141 * If the codec is powered, than we need to toggle the
2142 * codec power.
2143 */
2144 twl4030_codec_enable(codec, 0);
2145 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2146 twl4030_codec_enable(codec, 1);
2147 } else {
2148 twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2149 }
7154b3e8
JS		 2150 }
2151
2152 return 0;
2153}
2154
68140443
LCM		 2155static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2156{
2157 struct snd_soc_codec *codec = dai->codec;
2158 u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2159
2160 if (tristate)
2161 reg |= TWL4030_VIF_TRI_EN;
2162 else
2163 reg &= ~TWL4030_VIF_TRI_EN;
2164
2165 return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2166}
2167
bbba9444 2168#define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
cc17557e
SS		 2169#define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
2170
f0fba2ad 2171static struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
7220b9f4
PU		 2172 .startup = twl4030_startup,
2173 .shutdown = twl4030_shutdown,
10d9e3d9
JS		 2174 .hw_params = twl4030_hw_params,
2175 .set_sysclk = twl4030_set_dai_sysclk,
2176 .set_fmt = twl4030_set_dai_fmt,
68140443 2177 .set_tristate = twl4030_set_tristate,
10d9e3d9
JS		 2178};
2179
7154b3e8
JS		 2180static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2181 .startup = twl4030_voice_startup,
b7a755a8 2182 .shutdown = twl4030_voice_shutdown,
7154b3e8
JS		 2183 .hw_params = twl4030_voice_hw_params,
2184 .set_sysclk = twl4030_voice_set_dai_sysclk,
2185 .set_fmt = twl4030_voice_set_dai_fmt,
68140443 2186 .set_tristate = twl4030_voice_set_tristate,
7154b3e8
JS		 2187};
2188
f0fba2ad 2189static struct snd_soc_dai_driver twl4030_dai[] = {
7154b3e8 2190{
f0fba2ad 2191 .name = "twl4030-hifi",
cc17557e 2192 .playback = {
b4852b79 2193 .stream_name = "HiFi Playback",
cc17557e 2194 .channels_min = 2,
8a1f936a 2195 .channels_max = 4,
31ad0f31 2196 .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
cc17557e
SS		 2197 .formats = TWL4030_FORMATS,},
2198 .capture = {
2199 .stream_name = "Capture",
2200 .channels_min = 2,
8a1f936a 2201 .channels_max = 4,
cc17557e
SS		 2202 .rates = TWL4030_RATES,
2203 .formats = TWL4030_FORMATS,},
f0fba2ad 2204 .ops = &twl4030_dai_hifi_ops,
7154b3e8
JS		 2205},
2206{
f0fba2ad 2207 .name = "twl4030-voice",
7154b3e8 2208 .playback = {
b4852b79 2209 .stream_name = "Voice Playback",
7154b3e8
JS		 2210 .channels_min = 1,
2211 .channels_max = 1,
2212 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2213 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2214 .capture = {
2215 .stream_name = "Capture",
2216 .channels_min = 1,
2217 .channels_max = 2,
2218 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2219 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2220 .ops = &twl4030_dai_voice_ops,
2221},
cc17557e 2222};
cc17557e 2223
f0fba2ad 2224static int twl4030_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
cc17557e 2225{
cc17557e 2226 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
cc17557e
SS		 2227 return 0;
2228}
2229
f0fba2ad 2230static int twl4030_soc_resume(struct snd_soc_codec *codec)
cc17557e 2231{
cc17557e 2232 twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
cc17557e
SS		 2233 return 0;
2234}
2235
f0fba2ad 2236static int twl4030_soc_probe(struct snd_soc_codec *codec)
cc17557e 2237{
f0fba2ad 2238 struct twl4030_priv *twl4030;
9da28c7b 2239
f0fba2ad
LG		 2240 twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
2241 if (twl4030 == NULL) {
2242 printk("Can not allocate memroy\n");
2243 return -ENOMEM;
cc17557e 2244 }
f0fba2ad
LG		 2245 snd_soc_codec_set_drvdata(codec, twl4030);
2246 /* Set the defaults, and power up the codec */
2247 twl4030->sysclk = twl4030_codec_get_mclk() / 1000;
2248 codec->bias_level = SND_SOC_BIAS_OFF;
2249 codec->idle_bias_off = 1;
2250
2251 twl4030_init_chip(codec);
cc17557e 2252
3e8e1952
IM		 2253 snd_soc_add_controls(codec, twl4030_snd_controls,
2254 ARRAY_SIZE(twl4030_snd_controls));
cc17557e 2255 twl4030_add_widgets(codec);
7a1fecf5 2256 return 0;
cc17557e
SS		 2257}
2258
f0fba2ad 2259static int twl4030_soc_remove(struct snd_soc_codec *codec)
cc17557e 2260{
7a1fecf5 2261 twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
7a1fecf5
PU		 2262 return 0;
2263}
2264
f0fba2ad
LG		 2265static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2266 .probe = twl4030_soc_probe,
2267 .remove = twl4030_soc_remove,
2268 .suspend = twl4030_soc_suspend,
2269 .resume = twl4030_soc_resume,
2270 .read = twl4030_read_reg_cache,
2271 .write = twl4030_write,
2272 .set_bias_level = twl4030_set_bias_level,
2273 .reg_cache_size = sizeof(twl4030_reg),
2274 .reg_word_size = sizeof(u8),
2275 .reg_cache_default = twl4030_reg,
2276};
2277
7a1fecf5
PU		 2278static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2279{
2280 struct twl4030_codec_audio_data *pdata = pdev->dev.platform_data;
cc17557e 2281
68d01955
PU		 2282 if (!pdata) {
2283 dev_err(&pdev->dev, "platform_data is missing\n");
7a1fecf5
PU		 2284 return -EINVAL;
2285 }
cc17557e 2286
f0fba2ad
LG		 2287 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
2288 twl4030_dai, ARRAY_SIZE(twl4030_dai));
cc17557e
SS		 2289}
2290
7a1fecf5 2291static int __devexit twl4030_codec_remove(struct platform_device *pdev)
cc17557e 2292{
f0fba2ad 2293 struct twl4030_priv *twl4030 = dev_get_drvdata(&pdev->dev);
cc17557e 2294
f0fba2ad 2295 snd_soc_unregister_codec(&pdev->dev);
7a1fecf5 2296 kfree(twl4030);
cc17557e
SS		 2297 return 0;
2298}
2299
f0fba2ad 2300MODULE_ALIAS("platform:twl4030-codec");
7a1fecf5
PU		 2301
2302static struct platform_driver twl4030_codec_driver = {
2303 .probe = twl4030_codec_probe,
2304 .remove = __devexit_p(twl4030_codec_remove),
2305 .driver = {
f0fba2ad 2306 .name = "twl4030-codec",
7a1fecf5
PU		 2307 .owner = THIS_MODULE,
2308 },
cc17557e 2309};
cc17557e 2310
24e07db8 2311static int __init twl4030_modinit(void)
64089b84 2312{
7a1fecf5 2313 return platform_driver_register(&twl4030_codec_driver);
64089b84 2314}
24e07db8 2315module_init(twl4030_modinit);
64089b84
MB		 2316
2317static void __exit twl4030_exit(void)
2318{
7a1fecf5 2319 platform_driver_unregister(&twl4030_codec_driver);
64089b84
MB		 2320}
2321module_exit(twl4030_exit);
2322
cc17557e
SS		 2323MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2324MODULE_AUTHOR("Steve Sakoman");
2325MODULE_LICENSE("GPL");
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