Commit | Line | Data |
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cc17557e SS |
1 | /* |
2 | * ALSA SoC TWL4030 codec driver | |
3 | * | |
4 | * Author: Steve Sakoman, <steve@sakoman.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
18 | * 02110-1301 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/pm.h> | |
27 | #include <linux/i2c.h> | |
28 | #include <linux/platform_device.h> | |
2d6d649a PU |
29 | #include <linux/of.h> |
30 | #include <linux/of_gpio.h> | |
b07682b6 | 31 | #include <linux/i2c/twl.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
281ecd16 | 33 | #include <linux/gpio.h> |
cc17557e SS |
34 | #include <sound/core.h> |
35 | #include <sound/pcm.h> | |
36 | #include <sound/pcm_params.h> | |
37 | #include <sound/soc.h> | |
cc17557e | 38 | #include <sound/initval.h> |
c10b82cf | 39 | #include <sound/tlv.h> |
cc17557e | 40 | |
f0fba2ad | 41 | /* Register descriptions are here */ |
57fe7251 | 42 | #include <linux/mfd/twl4030-audio.h> |
f0fba2ad | 43 | |
5712ded9 PU |
44 | /* TWL4030 PMBR1 Register */ |
45 | #define TWL4030_PMBR1_REG 0x0D | |
46 | /* TWL4030 PMBR1 Register GPIO6 mux bits */ | |
47 | #define TWL4030_GPIO6_PWM0_MUTE(value) ((value & 0x03) << 2) | |
48 | ||
052901f4 | 49 | #define TWL4030_CACHEREGNUM (TWL4030_REG_MISC_SET_2 + 1) |
cc17557e | 50 | |
7393958f PU |
51 | /* codec private data */ |
52 | struct twl4030_priv { | |
7393958f | 53 | unsigned int codec_powered; |
7b4c734e PU |
54 | |
55 | /* reference counts of AIF/APLL users */ | |
2845fa13 | 56 | unsigned int apll_enabled; |
7220b9f4 PU |
57 | |
58 | struct snd_pcm_substream *master_substream; | |
59 | struct snd_pcm_substream *slave_substream; | |
6b87a91f PU |
60 | |
61 | unsigned int configured; | |
62 | unsigned int rate; | |
63 | unsigned int sample_bits; | |
64 | unsigned int channels; | |
6943c92e PU |
65 | |
66 | unsigned int sysclk; | |
67 | ||
c96907f2 PU |
68 | /* Output (with associated amp) states */ |
69 | u8 hsl_enabled, hsr_enabled; | |
70 | u8 earpiece_enabled; | |
71 | u8 predrivel_enabled, predriver_enabled; | |
72 | u8 carkitl_enabled, carkitr_enabled; | |
8b3bca29 | 73 | u8 ctl_cache[TWL4030_REG_PRECKR_CTL - TWL4030_REG_EAR_CTL + 1]; |
01ea6ba2 | 74 | |
182f73f6 | 75 | struct twl4030_codec_data *pdata; |
7393958f PU |
76 | }; |
77 | ||
8b3bca29 PU |
78 | static void tw4030_init_ctl_cache(struct twl4030_priv *twl4030) |
79 | { | |
80 | int i; | |
81 | u8 byte; | |
82 | ||
83 | for (i = TWL4030_REG_EAR_CTL; i <= TWL4030_REG_PRECKR_CTL; i++) { | |
84 | twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, i); | |
85 | twl4030->ctl_cache[i - TWL4030_REG_EAR_CTL] = byte; | |
86 | } | |
87 | } | |
88 | ||
efc8acff | 89 | static unsigned int twl4030_read(struct snd_soc_codec *codec, unsigned int reg) |
cc17557e | 90 | { |
efc8acff PU |
91 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
92 | u8 value = 0; | |
cc17557e SS |
93 | |
94 | if (reg >= TWL4030_CACHEREGNUM) | |
efc8acff PU |
95 | return -EIO; |
96 | ||
97 | switch (reg) { | |
98 | case TWL4030_REG_EAR_CTL: | |
99 | case TWL4030_REG_PREDL_CTL: | |
100 | case TWL4030_REG_PREDR_CTL: | |
101 | case TWL4030_REG_PRECKL_CTL: | |
102 | case TWL4030_REG_PRECKR_CTL: | |
103 | case TWL4030_REG_HS_GAIN_SET: | |
104 | value = twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL]; | |
105 | break; | |
106 | default: | |
107 | twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &value, reg); | |
108 | break; | |
109 | } | |
110 | ||
111 | return value; | |
cc17557e SS |
112 | } |
113 | ||
b703b504 | 114 | static bool twl4030_can_write_to_chip(struct twl4030_priv *twl4030, |
a8fc415c | 115 | unsigned int reg) |
cc17557e | 116 | { |
a8fc415c | 117 | bool write_to_reg = false; |
c96907f2 | 118 | |
052901f4 LPC |
119 | /* Decide if the given register can be written */ |
120 | switch (reg) { | |
121 | case TWL4030_REG_EAR_CTL: | |
122 | if (twl4030->earpiece_enabled) | |
a8fc415c | 123 | write_to_reg = true; |
052901f4 LPC |
124 | break; |
125 | case TWL4030_REG_PREDL_CTL: | |
126 | if (twl4030->predrivel_enabled) | |
a8fc415c | 127 | write_to_reg = true; |
052901f4 LPC |
128 | break; |
129 | case TWL4030_REG_PREDR_CTL: | |
130 | if (twl4030->predriver_enabled) | |
a8fc415c | 131 | write_to_reg = true; |
052901f4 LPC |
132 | break; |
133 | case TWL4030_REG_PRECKL_CTL: | |
134 | if (twl4030->carkitl_enabled) | |
a8fc415c | 135 | write_to_reg = true; |
052901f4 LPC |
136 | break; |
137 | case TWL4030_REG_PRECKR_CTL: | |
138 | if (twl4030->carkitr_enabled) | |
a8fc415c | 139 | write_to_reg = true; |
052901f4 LPC |
140 | break; |
141 | case TWL4030_REG_HS_GAIN_SET: | |
142 | if (twl4030->hsl_enabled || twl4030->hsr_enabled) | |
a8fc415c | 143 | write_to_reg = true; |
052901f4 LPC |
144 | break; |
145 | default: | |
146 | /* All other register can be written */ | |
a8fc415c | 147 | write_to_reg = true; |
052901f4 | 148 | break; |
c96907f2 | 149 | } |
a8fc415c PU |
150 | |
151 | return write_to_reg; | |
152 | } | |
153 | ||
7ded5fe0 PU |
154 | static int twl4030_write(struct snd_soc_codec *codec, unsigned int reg, |
155 | unsigned int value) | |
a8fc415c | 156 | { |
a450aa6f PU |
157 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
158 | ||
159 | /* Update the ctl cache */ | |
160 | switch (reg) { | |
161 | case TWL4030_REG_EAR_CTL: | |
162 | case TWL4030_REG_PREDL_CTL: | |
163 | case TWL4030_REG_PREDR_CTL: | |
164 | case TWL4030_REG_PRECKL_CTL: | |
165 | case TWL4030_REG_PRECKR_CTL: | |
166 | case TWL4030_REG_HS_GAIN_SET: | |
167 | twl4030->ctl_cache[reg - TWL4030_REG_EAR_CTL] = value; | |
168 | break; | |
169 | default: | |
170 | break; | |
171 | } | |
172 | ||
b703b504 | 173 | if (twl4030_can_write_to_chip(twl4030, reg)) |
a8fc415c | 174 | return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg); |
052901f4 | 175 | |
c96907f2 | 176 | return 0; |
cc17557e SS |
177 | } |
178 | ||
7e6120c5 PU |
179 | static inline void twl4030_wait_ms(int time) |
180 | { | |
181 | if (time < 60) { | |
182 | time *= 1000; | |
183 | usleep_range(time, time + 500); | |
184 | } else { | |
185 | msleep(time); | |
186 | } | |
187 | } | |
188 | ||
db04e2c5 | 189 | static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable) |
cc17557e | 190 | { |
b2c812e2 | 191 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7a1fecf5 | 192 | int mode; |
cc17557e | 193 | |
7393958f PU |
194 | if (enable == twl4030->codec_powered) |
195 | return; | |
196 | ||
db04e2c5 | 197 | if (enable) |
57fe7251 | 198 | mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER); |
db04e2c5 | 199 | else |
57fe7251 | 200 | mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER); |
cc17557e | 201 | |
efc8acff | 202 | if (mode >= 0) |
7a1fecf5 | 203 | twl4030->codec_powered = enable; |
cc17557e SS |
204 | |
205 | /* REVISIT: this delay is present in TI sample drivers */ | |
206 | /* but there seems to be no TRM requirement for it */ | |
207 | udelay(10); | |
208 | } | |
209 | ||
2d6d649a PU |
210 | static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata, |
211 | struct device_node *node) | |
212 | { | |
213 | int value; | |
214 | ||
215 | of_property_read_u32(node, "ti,digimic_delay", | |
216 | &pdata->digimic_delay); | |
217 | of_property_read_u32(node, "ti,ramp_delay_value", | |
218 | &pdata->ramp_delay_value); | |
219 | of_property_read_u32(node, "ti,offset_cncl_path", | |
220 | &pdata->offset_cncl_path); | |
221 | if (!of_property_read_u32(node, "ti,hs_extmute", &value)) | |
222 | pdata->hs_extmute = value; | |
223 | ||
224 | pdata->hs_extmute_gpio = of_get_named_gpio(node, | |
225 | "ti,hs_extmute_gpio", 0); | |
226 | if (gpio_is_valid(pdata->hs_extmute_gpio)) | |
227 | pdata->hs_extmute = 1; | |
228 | } | |
229 | ||
230 | static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec) | |
7393958f | 231 | { |
4ae6df5e | 232 | struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev); |
2d6d649a PU |
233 | struct device_node *twl4030_codec_node = NULL; |
234 | ||
235 | twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node, | |
236 | "codec"); | |
237 | ||
238 | if (!pdata && twl4030_codec_node) { | |
239 | pdata = devm_kzalloc(codec->dev, | |
240 | sizeof(struct twl4030_codec_data), | |
241 | GFP_KERNEL); | |
242 | if (!pdata) { | |
243 | dev_err(codec->dev, "Can not allocate memory\n"); | |
244 | return NULL; | |
245 | } | |
246 | twl4030_setup_pdata_of(pdata, twl4030_codec_node); | |
247 | } | |
248 | ||
249 | return pdata; | |
250 | } | |
251 | ||
252 | static void twl4030_init_chip(struct snd_soc_codec *codec) | |
253 | { | |
254 | struct twl4030_codec_data *pdata; | |
b2c812e2 | 255 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
ee4ccac7 PU |
256 | u8 reg, byte; |
257 | int i = 0; | |
7393958f | 258 | |
2d6d649a PU |
259 | pdata = twl4030_get_pdata(codec); |
260 | ||
5712ded9 PU |
261 | if (pdata && pdata->hs_extmute) { |
262 | if (gpio_is_valid(pdata->hs_extmute_gpio)) { | |
263 | int ret; | |
264 | ||
265 | if (!pdata->hs_extmute_gpio) | |
266 | dev_warn(codec->dev, | |
267 | "Extmute GPIO is 0 is this correct?\n"); | |
268 | ||
269 | ret = gpio_request_one(pdata->hs_extmute_gpio, | |
270 | GPIOF_OUT_INIT_LOW, | |
271 | "hs_extmute"); | |
272 | if (ret) { | |
273 | dev_err(codec->dev, | |
274 | "Failed to get hs_extmute GPIO\n"); | |
275 | pdata->hs_extmute_gpio = -1; | |
276 | } | |
277 | } else { | |
278 | u8 pin_mux; | |
279 | ||
280 | /* Set TWL4030 GPIO6 as EXTMUTE signal */ | |
281 | twl_i2c_read_u8(TWL4030_MODULE_INTBR, &pin_mux, | |
282 | TWL4030_PMBR1_REG); | |
283 | pin_mux &= ~TWL4030_GPIO6_PWM0_MUTE(0x03); | |
284 | pin_mux |= TWL4030_GPIO6_PWM0_MUTE(0x02); | |
285 | twl_i2c_write_u8(TWL4030_MODULE_INTBR, pin_mux, | |
286 | TWL4030_PMBR1_REG); | |
281ecd16 PU |
287 | } |
288 | } | |
289 | ||
8b3bca29 PU |
290 | /* Initialize the local ctl register cache */ |
291 | tw4030_init_ctl_cache(twl4030); | |
292 | ||
ee4ccac7 | 293 | /* anti-pop when changing analog gain */ |
efc8acff | 294 | reg = twl4030_read(codec, TWL4030_REG_MISC_SET_1); |
ee4ccac7 | 295 | twl4030_write(codec, TWL4030_REG_MISC_SET_1, |
7ded5fe0 | 296 | reg | TWL4030_SMOOTH_ANAVOL_EN); |
7393958f | 297 | |
ee4ccac7 | 298 | twl4030_write(codec, TWL4030_REG_OPTION, |
7ded5fe0 PU |
299 | TWL4030_ATXL1_EN | TWL4030_ATXR1_EN | |
300 | TWL4030_ARXL2_EN | TWL4030_ARXR2_EN); | |
006f367e | 301 | |
3c36cc68 PU |
302 | /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */ |
303 | twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32); | |
304 | ||
ee4ccac7 | 305 | /* Machine dependent setup */ |
f0fba2ad | 306 | if (!pdata) |
7393958f PU |
307 | return; |
308 | ||
182f73f6 | 309 | twl4030->pdata = pdata; |
ee4ccac7 | 310 | |
efc8acff | 311 | reg = twl4030_read(codec, TWL4030_REG_HS_POPN_SET); |
ee4ccac7 | 312 | reg &= ~TWL4030_RAMP_DELAY; |
f0fba2ad | 313 | reg |= (pdata->ramp_delay_value << 2); |
efc8acff | 314 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, reg); |
006f367e PU |
315 | |
316 | /* initiate offset cancellation */ | |
ee4ccac7 PU |
317 | twl4030_codec_enable(codec, 1); |
318 | ||
efc8acff | 319 | reg = twl4030_read(codec, TWL4030_REG_ANAMICL); |
ee4ccac7 | 320 | reg &= ~TWL4030_OFFSET_CNCL_SEL; |
f0fba2ad | 321 | reg |= pdata->offset_cncl_path; |
006f367e | 322 | twl4030_write(codec, TWL4030_REG_ANAMICL, |
7ded5fe0 | 323 | reg | TWL4030_CNCL_OFFSET_START); |
006f367e | 324 | |
7e6120c5 PU |
325 | /* |
326 | * Wait for offset cancellation to complete. | |
327 | * Since this takes a while, do not slam the i2c. | |
328 | * Start polling the status after ~20ms. | |
329 | */ | |
330 | msleep(20); | |
006f367e | 331 | do { |
7e6120c5 | 332 | usleep_range(1000, 2000); |
efc8acff | 333 | twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, true); |
fc7b92fc | 334 | twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte, |
7ded5fe0 | 335 | TWL4030_REG_ANAMICL); |
efc8acff | 336 | twl_set_regcache_bypass(TWL4030_MODULE_AUDIO_VOICE, false); |
006f367e PU |
337 | } while ((i++ < 100) && |
338 | ((byte & TWL4030_CNCL_OFFSET_START) == | |
339 | TWL4030_CNCL_OFFSET_START)); | |
340 | ||
006f367e | 341 | twl4030_codec_enable(codec, 0); |
006f367e PU |
342 | } |
343 | ||
ee4ccac7 | 344 | static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable) |
006f367e | 345 | { |
ee4ccac7 | 346 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
ee4ccac7 PU |
347 | |
348 | if (enable) { | |
349 | twl4030->apll_enabled++; | |
350 | if (twl4030->apll_enabled == 1) | |
bb17bc78 | 351 | twl4030_audio_enable_resource( |
57fe7251 | 352 | TWL4030_AUDIO_RES_APLL); |
ee4ccac7 PU |
353 | } else { |
354 | twl4030->apll_enabled--; | |
355 | if (!twl4030->apll_enabled) | |
bb17bc78 | 356 | twl4030_audio_disable_resource( |
57fe7251 | 357 | TWL4030_AUDIO_RES_APLL); |
ee4ccac7 | 358 | } |
006f367e PU |
359 | } |
360 | ||
5e98a464 | 361 | /* Earpiece */ |
1a787e7a JS |
362 | static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = { |
363 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0), | |
364 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0), | |
365 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0), | |
366 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0), | |
367 | }; | |
5e98a464 | 368 | |
2a6f5c58 | 369 | /* PreDrive Left */ |
1a787e7a JS |
370 | static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = { |
371 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0), | |
372 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0), | |
373 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0), | |
374 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0), | |
375 | }; | |
2a6f5c58 PU |
376 | |
377 | /* PreDrive Right */ | |
1a787e7a JS |
378 | static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = { |
379 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0), | |
380 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0), | |
381 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0), | |
382 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0), | |
383 | }; | |
2a6f5c58 | 384 | |
dfad21a2 | 385 | /* Headset Left */ |
1a787e7a JS |
386 | static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = { |
387 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0), | |
388 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0), | |
389 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0), | |
390 | }; | |
dfad21a2 PU |
391 | |
392 | /* Headset Right */ | |
1a787e7a JS |
393 | static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = { |
394 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0), | |
395 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0), | |
396 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0), | |
397 | }; | |
dfad21a2 | 398 | |
5152d8c2 | 399 | /* Carkit Left */ |
1a787e7a JS |
400 | static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = { |
401 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0), | |
402 | SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0), | |
403 | SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0), | |
404 | }; | |
5152d8c2 PU |
405 | |
406 | /* Carkit Right */ | |
1a787e7a JS |
407 | static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = { |
408 | SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0), | |
409 | SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0), | |
410 | SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0), | |
411 | }; | |
5152d8c2 | 412 | |
df339804 PU |
413 | /* Handsfree Left */ |
414 | static const char *twl4030_handsfreel_texts[] = | |
1a787e7a | 415 | {"Voice", "AudioL1", "AudioL2", "AudioR2"}; |
df339804 | 416 | |
9f04fba7 TI |
417 | static SOC_ENUM_SINGLE_DECL(twl4030_handsfreel_enum, |
418 | TWL4030_REG_HFL_CTL, 0, | |
419 | twl4030_handsfreel_texts); | |
df339804 PU |
420 | |
421 | static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control = | |
422 | SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum); | |
423 | ||
0f89bdca PU |
424 | /* Handsfree Left virtual mute */ |
425 | static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control = | |
052901f4 | 426 | SOC_DAPM_SINGLE_VIRT("Switch", 1); |
0f89bdca | 427 | |
df339804 PU |
428 | /* Handsfree Right */ |
429 | static const char *twl4030_handsfreer_texts[] = | |
1a787e7a | 430 | {"Voice", "AudioR1", "AudioR2", "AudioL2"}; |
df339804 | 431 | |
9f04fba7 TI |
432 | static SOC_ENUM_SINGLE_DECL(twl4030_handsfreer_enum, |
433 | TWL4030_REG_HFR_CTL, 0, | |
434 | twl4030_handsfreer_texts); | |
df339804 PU |
435 | |
436 | static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control = | |
437 | SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum); | |
438 | ||
0f89bdca PU |
439 | /* Handsfree Right virtual mute */ |
440 | static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control = | |
052901f4 | 441 | SOC_DAPM_SINGLE_VIRT("Switch", 1); |
0f89bdca | 442 | |
376f7839 PU |
443 | /* Vibra */ |
444 | /* Vibra audio path selection */ | |
445 | static const char *twl4030_vibra_texts[] = | |
446 | {"AudioL1", "AudioR1", "AudioL2", "AudioR2"}; | |
447 | ||
9f04fba7 TI |
448 | static SOC_ENUM_SINGLE_DECL(twl4030_vibra_enum, |
449 | TWL4030_REG_VIBRA_CTL, 2, | |
450 | twl4030_vibra_texts); | |
376f7839 PU |
451 | |
452 | static const struct snd_kcontrol_new twl4030_dapm_vibra_control = | |
453 | SOC_DAPM_ENUM("Route", twl4030_vibra_enum); | |
454 | ||
455 | /* Vibra path selection: local vibrator (PWM) or audio driven */ | |
456 | static const char *twl4030_vibrapath_texts[] = | |
457 | {"Local vibrator", "Audio"}; | |
458 | ||
9f04fba7 TI |
459 | static SOC_ENUM_SINGLE_DECL(twl4030_vibrapath_enum, |
460 | TWL4030_REG_VIBRA_CTL, 4, | |
461 | twl4030_vibrapath_texts); | |
376f7839 PU |
462 | |
463 | static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control = | |
464 | SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum); | |
465 | ||
276c6222 | 466 | /* Left analog microphone selection */ |
97b8096d | 467 | static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = { |
9028935d PU |
468 | SOC_DAPM_SINGLE("Main Mic Capture Switch", |
469 | TWL4030_REG_ANAMICL, 0, 1, 0), | |
470 | SOC_DAPM_SINGLE("Headset Mic Capture Switch", | |
471 | TWL4030_REG_ANAMICL, 1, 1, 0), | |
472 | SOC_DAPM_SINGLE("AUXL Capture Switch", | |
473 | TWL4030_REG_ANAMICL, 2, 1, 0), | |
474 | SOC_DAPM_SINGLE("Carkit Mic Capture Switch", | |
475 | TWL4030_REG_ANAMICL, 3, 1, 0), | |
97b8096d | 476 | }; |
276c6222 PU |
477 | |
478 | /* Right analog microphone selection */ | |
97b8096d | 479 | static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = { |
9028935d PU |
480 | SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0), |
481 | SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0), | |
97b8096d | 482 | }; |
276c6222 PU |
483 | |
484 | /* TX1 L/R Analog/Digital microphone selection */ | |
485 | static const char *twl4030_micpathtx1_texts[] = | |
486 | {"Analog", "Digimic0"}; | |
487 | ||
9f04fba7 TI |
488 | static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx1_enum, |
489 | TWL4030_REG_ADCMICSEL, 0, | |
490 | twl4030_micpathtx1_texts); | |
276c6222 PU |
491 | |
492 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control = | |
493 | SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum); | |
494 | ||
495 | /* TX2 L/R Analog/Digital microphone selection */ | |
496 | static const char *twl4030_micpathtx2_texts[] = | |
497 | {"Analog", "Digimic1"}; | |
498 | ||
9f04fba7 TI |
499 | static SOC_ENUM_SINGLE_DECL(twl4030_micpathtx2_enum, |
500 | TWL4030_REG_ADCMICSEL, 2, | |
501 | twl4030_micpathtx2_texts); | |
276c6222 PU |
502 | |
503 | static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control = | |
504 | SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum); | |
505 | ||
7393958f PU |
506 | /* Analog bypass for AudioR1 */ |
507 | static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control = | |
508 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0); | |
509 | ||
510 | /* Analog bypass for AudioL1 */ | |
511 | static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control = | |
512 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0); | |
513 | ||
514 | /* Analog bypass for AudioR2 */ | |
515 | static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control = | |
516 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0); | |
517 | ||
518 | /* Analog bypass for AudioL2 */ | |
519 | static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control = | |
520 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0); | |
521 | ||
fcd274a3 LCM |
522 | /* Analog bypass for Voice */ |
523 | static const struct snd_kcontrol_new twl4030_dapm_abypassv_control = | |
524 | SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0); | |
525 | ||
8b0d3153 | 526 | /* Digital bypass gain, mute instead of -30dB */ |
6bab83fd | 527 | static const unsigned int twl4030_dapm_dbypass_tlv[] = { |
8b0d3153 PU |
528 | TLV_DB_RANGE_HEAD(3), |
529 | 0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1), | |
530 | 2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0), | |
6bab83fd PU |
531 | 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0), |
532 | }; | |
533 | ||
534 | /* Digital bypass left (TX1L -> RX2L) */ | |
535 | static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control = | |
536 | SOC_DAPM_SINGLE_TLV("Volume", | |
537 | TWL4030_REG_ATX2ARXPGA, 3, 7, 0, | |
538 | twl4030_dapm_dbypass_tlv); | |
539 | ||
540 | /* Digital bypass right (TX1R -> RX2R) */ | |
541 | static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control = | |
542 | SOC_DAPM_SINGLE_TLV("Volume", | |
543 | TWL4030_REG_ATX2ARXPGA, 0, 7, 0, | |
544 | twl4030_dapm_dbypass_tlv); | |
545 | ||
ee8f6894 LCM |
546 | /* |
547 | * Voice Sidetone GAIN volume control: | |
548 | * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB) | |
549 | */ | |
550 | static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1); | |
551 | ||
552 | /* Digital bypass voice: sidetone (VUL -> VDL)*/ | |
553 | static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control = | |
554 | SOC_DAPM_SINGLE_TLV("Volume", | |
555 | TWL4030_REG_VSTPGA, 0, 0x29, 0, | |
556 | twl4030_dapm_dbypassv_tlv); | |
557 | ||
9008adf9 PU |
558 | /* |
559 | * Output PGA builder: | |
560 | * Handle the muting and unmuting of the given output (turning off the | |
561 | * amplifier associated with the output pin) | |
c96907f2 PU |
562 | * On mute bypass the reg_cache and write 0 to the register |
563 | * On unmute: restore the register content from the reg_cache | |
9008adf9 PU |
564 | * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R |
565 | */ | |
566 | #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \ | |
567 | static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \ | |
7ded5fe0 | 568 | struct snd_kcontrol *kcontrol, int event) \ |
9008adf9 | 569 | { \ |
a36ac9b3 LPC |
570 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); \ |
571 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); \ | |
9008adf9 PU |
572 | \ |
573 | switch (event) { \ | |
574 | case SND_SOC_DAPM_POST_PMU: \ | |
c96907f2 | 575 | twl4030->pin_name##_enabled = 1; \ |
a36ac9b3 | 576 | twl4030_write(codec, reg, twl4030_read(codec, reg)); \ |
9008adf9 PU |
577 | break; \ |
578 | case SND_SOC_DAPM_POST_PMD: \ | |
c96907f2 | 579 | twl4030->pin_name##_enabled = 0; \ |
7ded5fe0 | 580 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, 0, reg); \ |
9008adf9 PU |
581 | break; \ |
582 | } \ | |
583 | return 0; \ | |
584 | } | |
585 | ||
586 | TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN); | |
587 | TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN); | |
588 | TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN); | |
589 | TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN); | |
590 | TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN); | |
591 | ||
5a2e9a48 | 592 | static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp) |
49d92c7d | 593 | { |
49d92c7d SM |
594 | unsigned char hs_ctl; |
595 | ||
efc8acff | 596 | hs_ctl = twl4030_read(codec, reg); |
49d92c7d | 597 | |
5a2e9a48 PU |
598 | if (ramp) { |
599 | /* HF ramp-up */ | |
600 | hs_ctl |= TWL4030_HF_CTL_REF_EN; | |
601 | twl4030_write(codec, reg, hs_ctl); | |
602 | udelay(10); | |
49d92c7d | 603 | hs_ctl |= TWL4030_HF_CTL_RAMP_EN; |
5a2e9a48 PU |
604 | twl4030_write(codec, reg, hs_ctl); |
605 | udelay(40); | |
49d92c7d | 606 | hs_ctl |= TWL4030_HF_CTL_LOOP_EN; |
49d92c7d | 607 | hs_ctl |= TWL4030_HF_CTL_HB_EN; |
5a2e9a48 | 608 | twl4030_write(codec, reg, hs_ctl); |
49d92c7d | 609 | } else { |
5a2e9a48 PU |
610 | /* HF ramp-down */ |
611 | hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN; | |
612 | hs_ctl &= ~TWL4030_HF_CTL_HB_EN; | |
613 | twl4030_write(codec, reg, hs_ctl); | |
614 | hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN; | |
615 | twl4030_write(codec, reg, hs_ctl); | |
616 | udelay(40); | |
617 | hs_ctl &= ~TWL4030_HF_CTL_REF_EN; | |
618 | twl4030_write(codec, reg, hs_ctl); | |
49d92c7d | 619 | } |
5a2e9a48 | 620 | } |
49d92c7d | 621 | |
5a2e9a48 | 622 | static int handsfreelpga_event(struct snd_soc_dapm_widget *w, |
7ded5fe0 | 623 | struct snd_kcontrol *kcontrol, int event) |
5a2e9a48 | 624 | { |
a36ac9b3 LPC |
625 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
626 | ||
5a2e9a48 PU |
627 | switch (event) { |
628 | case SND_SOC_DAPM_POST_PMU: | |
a36ac9b3 | 629 | handsfree_ramp(codec, TWL4030_REG_HFL_CTL, 1); |
5a2e9a48 PU |
630 | break; |
631 | case SND_SOC_DAPM_POST_PMD: | |
a36ac9b3 | 632 | handsfree_ramp(codec, TWL4030_REG_HFL_CTL, 0); |
5a2e9a48 PU |
633 | break; |
634 | } | |
635 | return 0; | |
636 | } | |
637 | ||
638 | static int handsfreerpga_event(struct snd_soc_dapm_widget *w, | |
7ded5fe0 | 639 | struct snd_kcontrol *kcontrol, int event) |
5a2e9a48 | 640 | { |
a36ac9b3 LPC |
641 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
642 | ||
5a2e9a48 PU |
643 | switch (event) { |
644 | case SND_SOC_DAPM_POST_PMU: | |
a36ac9b3 | 645 | handsfree_ramp(codec, TWL4030_REG_HFR_CTL, 1); |
5a2e9a48 PU |
646 | break; |
647 | case SND_SOC_DAPM_POST_PMD: | |
a36ac9b3 | 648 | handsfree_ramp(codec, TWL4030_REG_HFR_CTL, 0); |
5a2e9a48 PU |
649 | break; |
650 | } | |
49d92c7d SM |
651 | return 0; |
652 | } | |
653 | ||
86139a13 | 654 | static int vibramux_event(struct snd_soc_dapm_widget *w, |
7ded5fe0 | 655 | struct snd_kcontrol *kcontrol, int event) |
86139a13 | 656 | { |
a36ac9b3 LPC |
657 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
658 | ||
659 | twl4030_write(codec, TWL4030_REG_VIBRA_SET, 0xff); | |
86139a13 JV |
660 | return 0; |
661 | } | |
662 | ||
7729cf74 | 663 | static int apll_event(struct snd_soc_dapm_widget *w, |
7ded5fe0 | 664 | struct snd_kcontrol *kcontrol, int event) |
7729cf74 | 665 | { |
a36ac9b3 LPC |
666 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
667 | ||
7729cf74 PU |
668 | switch (event) { |
669 | case SND_SOC_DAPM_PRE_PMU: | |
a36ac9b3 | 670 | twl4030_apll_enable(codec, 1); |
7729cf74 PU |
671 | break; |
672 | case SND_SOC_DAPM_POST_PMD: | |
a36ac9b3 | 673 | twl4030_apll_enable(codec, 0); |
7729cf74 PU |
674 | break; |
675 | } | |
676 | return 0; | |
677 | } | |
678 | ||
7b4c734e | 679 | static int aif_event(struct snd_soc_dapm_widget *w, |
7ded5fe0 | 680 | struct snd_kcontrol *kcontrol, int event) |
7b4c734e | 681 | { |
a36ac9b3 | 682 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
7b4c734e PU |
683 | u8 audio_if; |
684 | ||
a36ac9b3 | 685 | audio_if = twl4030_read(codec, TWL4030_REG_AUDIO_IF); |
7b4c734e PU |
686 | switch (event) { |
687 | case SND_SOC_DAPM_PRE_PMU: | |
688 | /* Enable AIF */ | |
689 | /* enable the PLL before we use it to clock the DAI */ | |
a36ac9b3 | 690 | twl4030_apll_enable(codec, 1); |
7b4c734e | 691 | |
a36ac9b3 | 692 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, |
7ded5fe0 | 693 | audio_if | TWL4030_AIF_EN); |
7b4c734e PU |
694 | break; |
695 | case SND_SOC_DAPM_POST_PMD: | |
696 | /* disable the DAI before we stop it's source PLL */ | |
a36ac9b3 | 697 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, |
7ded5fe0 | 698 | audio_if & ~TWL4030_AIF_EN); |
a36ac9b3 | 699 | twl4030_apll_enable(codec, 0); |
7b4c734e PU |
700 | break; |
701 | } | |
702 | return 0; | |
703 | } | |
704 | ||
6943c92e | 705 | static void headset_ramp(struct snd_soc_codec *codec, int ramp) |
aad749e5 PU |
706 | { |
707 | unsigned char hs_gain, hs_pop; | |
b2c812e2 | 708 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
182f73f6 | 709 | struct twl4030_codec_data *pdata = twl4030->pdata; |
6943c92e PU |
710 | /* Base values for ramp delay calculation: 2^19 - 2^26 */ |
711 | unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304, | |
712 | 8388608, 16777216, 33554432, 67108864}; | |
7e6120c5 | 713 | unsigned int delay; |
aad749e5 | 714 | |
efc8acff PU |
715 | hs_gain = twl4030_read(codec, TWL4030_REG_HS_GAIN_SET); |
716 | hs_pop = twl4030_read(codec, TWL4030_REG_HS_POPN_SET); | |
7e6120c5 PU |
717 | delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] / |
718 | twl4030->sysclk) + 1; | |
aad749e5 | 719 | |
4e49ffd1 CVJ |
720 | /* Enable external mute control, this dramatically reduces |
721 | * the pop-noise */ | |
f0fba2ad | 722 | if (pdata && pdata->hs_extmute) { |
281ecd16 PU |
723 | if (gpio_is_valid(pdata->hs_extmute_gpio)) { |
724 | gpio_set_value(pdata->hs_extmute_gpio, 1); | |
4e49ffd1 CVJ |
725 | } else { |
726 | hs_pop |= TWL4030_EXTMUTE; | |
727 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
728 | } | |
729 | } | |
730 | ||
6943c92e PU |
731 | if (ramp) { |
732 | /* Headset ramp-up according to the TRM */ | |
aad749e5 | 733 | hs_pop |= TWL4030_VMID_EN; |
6943c92e | 734 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
c96907f2 | 735 | /* Actually write to the register */ |
7ded5fe0 PU |
736 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain, |
737 | TWL4030_REG_HS_GAIN_SET); | |
aad749e5 | 738 | hs_pop |= TWL4030_RAMP_EN; |
6943c92e | 739 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
4e49ffd1 | 740 | /* Wait ramp delay time + 1, so the VMID can settle */ |
7e6120c5 | 741 | twl4030_wait_ms(delay); |
6943c92e PU |
742 | } else { |
743 | /* Headset ramp-down _not_ according to | |
744 | * the TRM, but in a way that it is working */ | |
aad749e5 | 745 | hs_pop &= ~TWL4030_RAMP_EN; |
6943c92e PU |
746 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
747 | /* Wait ramp delay time + 1, so the VMID can settle */ | |
7e6120c5 | 748 | twl4030_wait_ms(delay); |
aad749e5 | 749 | /* Bypass the reg_cache to mute the headset */ |
7ded5fe0 PU |
750 | twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, hs_gain & (~0x0f), |
751 | TWL4030_REG_HS_GAIN_SET); | |
6943c92e | 752 | |
aad749e5 | 753 | hs_pop &= ~TWL4030_VMID_EN; |
6943c92e PU |
754 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); |
755 | } | |
4e49ffd1 CVJ |
756 | |
757 | /* Disable external mute */ | |
f0fba2ad | 758 | if (pdata && pdata->hs_extmute) { |
281ecd16 PU |
759 | if (gpio_is_valid(pdata->hs_extmute_gpio)) { |
760 | gpio_set_value(pdata->hs_extmute_gpio, 0); | |
4e49ffd1 CVJ |
761 | } else { |
762 | hs_pop &= ~TWL4030_EXTMUTE; | |
763 | twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop); | |
764 | } | |
765 | } | |
6943c92e PU |
766 | } |
767 | ||
768 | static int headsetlpga_event(struct snd_soc_dapm_widget *w, | |
7ded5fe0 | 769 | struct snd_kcontrol *kcontrol, int event) |
6943c92e | 770 | { |
a36ac9b3 LPC |
771 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
772 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); | |
6943c92e PU |
773 | |
774 | switch (event) { | |
775 | case SND_SOC_DAPM_POST_PMU: | |
776 | /* Do the ramp-up only once */ | |
777 | if (!twl4030->hsr_enabled) | |
a36ac9b3 | 778 | headset_ramp(codec, 1); |
6943c92e PU |
779 | |
780 | twl4030->hsl_enabled = 1; | |
781 | break; | |
782 | case SND_SOC_DAPM_POST_PMD: | |
783 | /* Do the ramp-down only if both headsetL/R is disabled */ | |
784 | if (!twl4030->hsr_enabled) | |
a36ac9b3 | 785 | headset_ramp(codec, 0); |
6943c92e PU |
786 | |
787 | twl4030->hsl_enabled = 0; | |
788 | break; | |
789 | } | |
790 | return 0; | |
791 | } | |
792 | ||
793 | static int headsetrpga_event(struct snd_soc_dapm_widget *w, | |
7ded5fe0 | 794 | struct snd_kcontrol *kcontrol, int event) |
6943c92e | 795 | { |
a36ac9b3 LPC |
796 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
797 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); | |
6943c92e PU |
798 | |
799 | switch (event) { | |
800 | case SND_SOC_DAPM_POST_PMU: | |
801 | /* Do the ramp-up only once */ | |
802 | if (!twl4030->hsl_enabled) | |
a36ac9b3 | 803 | headset_ramp(codec, 1); |
6943c92e PU |
804 | |
805 | twl4030->hsr_enabled = 1; | |
806 | break; | |
807 | case SND_SOC_DAPM_POST_PMD: | |
808 | /* Do the ramp-down only if both headsetL/R is disabled */ | |
809 | if (!twl4030->hsl_enabled) | |
a36ac9b3 | 810 | headset_ramp(codec, 0); |
6943c92e PU |
811 | |
812 | twl4030->hsr_enabled = 0; | |
aad749e5 PU |
813 | break; |
814 | } | |
815 | return 0; | |
816 | } | |
817 | ||
01ea6ba2 | 818 | static int digimic_event(struct snd_soc_dapm_widget *w, |
7ded5fe0 | 819 | struct snd_kcontrol *kcontrol, int event) |
01ea6ba2 | 820 | { |
a36ac9b3 LPC |
821 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
822 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); | |
182f73f6 | 823 | struct twl4030_codec_data *pdata = twl4030->pdata; |
01ea6ba2 | 824 | |
182f73f6 PU |
825 | if (pdata && pdata->digimic_delay) |
826 | twl4030_wait_ms(pdata->digimic_delay); | |
01ea6ba2 PU |
827 | return 0; |
828 | } | |
829 | ||
b0bd53a7 PU |
830 | /* |
831 | * Some of the gain controls in TWL (mostly those which are associated with | |
832 | * the outputs) are implemented in an interesting way: | |
833 | * 0x0 : Power down (mute) | |
834 | * 0x1 : 6dB | |
835 | * 0x2 : 0 dB | |
836 | * 0x3 : -6 dB | |
837 | * Inverting not going to help with these. | |
838 | * Custom volsw and volsw_2r get/put functions to handle these gain bits. | |
839 | */ | |
b0bd53a7 | 840 | static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol, |
7ded5fe0 | 841 | struct snd_ctl_elem_value *ucontrol) |
b0bd53a7 PU |
842 | { |
843 | struct soc_mixer_control *mc = | |
844 | (struct soc_mixer_control *)kcontrol->private_value; | |
ea53bf77 | 845 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
b0bd53a7 PU |
846 | unsigned int reg = mc->reg; |
847 | unsigned int shift = mc->shift; | |
848 | unsigned int rshift = mc->rshift; | |
849 | int max = mc->max; | |
850 | int mask = (1 << fls(max)) - 1; | |
851 | ||
852 | ucontrol->value.integer.value[0] = | |
853 | (snd_soc_read(codec, reg) >> shift) & mask; | |
854 | if (ucontrol->value.integer.value[0]) | |
855 | ucontrol->value.integer.value[0] = | |
856 | max + 1 - ucontrol->value.integer.value[0]; | |
857 | ||
858 | if (shift != rshift) { | |
859 | ucontrol->value.integer.value[1] = | |
860 | (snd_soc_read(codec, reg) >> rshift) & mask; | |
861 | if (ucontrol->value.integer.value[1]) | |
862 | ucontrol->value.integer.value[1] = | |
863 | max + 1 - ucontrol->value.integer.value[1]; | |
864 | } | |
865 | ||
866 | return 0; | |
867 | } | |
868 | ||
869 | static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol, | |
7ded5fe0 | 870 | struct snd_ctl_elem_value *ucontrol) |
b0bd53a7 PU |
871 | { |
872 | struct soc_mixer_control *mc = | |
873 | (struct soc_mixer_control *)kcontrol->private_value; | |
ea53bf77 | 874 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
b0bd53a7 PU |
875 | unsigned int reg = mc->reg; |
876 | unsigned int shift = mc->shift; | |
877 | unsigned int rshift = mc->rshift; | |
878 | int max = mc->max; | |
879 | int mask = (1 << fls(max)) - 1; | |
880 | unsigned short val, val2, val_mask; | |
881 | ||
882 | val = (ucontrol->value.integer.value[0] & mask); | |
883 | ||
884 | val_mask = mask << shift; | |
885 | if (val) | |
886 | val = max + 1 - val; | |
887 | val = val << shift; | |
888 | if (shift != rshift) { | |
889 | val2 = (ucontrol->value.integer.value[1] & mask); | |
890 | val_mask |= mask << rshift; | |
891 | if (val2) | |
892 | val2 = max + 1 - val2; | |
893 | val |= val2 << rshift; | |
894 | } | |
895 | return snd_soc_update_bits(codec, reg, val_mask, val); | |
896 | } | |
897 | ||
898 | static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
7ded5fe0 | 899 | struct snd_ctl_elem_value *ucontrol) |
b0bd53a7 PU |
900 | { |
901 | struct soc_mixer_control *mc = | |
902 | (struct soc_mixer_control *)kcontrol->private_value; | |
ea53bf77 | 903 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
b0bd53a7 PU |
904 | unsigned int reg = mc->reg; |
905 | unsigned int reg2 = mc->rreg; | |
906 | unsigned int shift = mc->shift; | |
907 | int max = mc->max; | |
908 | int mask = (1<<fls(max))-1; | |
909 | ||
910 | ucontrol->value.integer.value[0] = | |
911 | (snd_soc_read(codec, reg) >> shift) & mask; | |
912 | ucontrol->value.integer.value[1] = | |
913 | (snd_soc_read(codec, reg2) >> shift) & mask; | |
914 | ||
915 | if (ucontrol->value.integer.value[0]) | |
916 | ucontrol->value.integer.value[0] = | |
917 | max + 1 - ucontrol->value.integer.value[0]; | |
918 | if (ucontrol->value.integer.value[1]) | |
919 | ucontrol->value.integer.value[1] = | |
920 | max + 1 - ucontrol->value.integer.value[1]; | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
925 | static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol, | |
7ded5fe0 | 926 | struct snd_ctl_elem_value *ucontrol) |
b0bd53a7 PU |
927 | { |
928 | struct soc_mixer_control *mc = | |
929 | (struct soc_mixer_control *)kcontrol->private_value; | |
ea53bf77 | 930 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
b0bd53a7 PU |
931 | unsigned int reg = mc->reg; |
932 | unsigned int reg2 = mc->rreg; | |
933 | unsigned int shift = mc->shift; | |
934 | int max = mc->max; | |
935 | int mask = (1 << fls(max)) - 1; | |
936 | int err; | |
937 | unsigned short val, val2, val_mask; | |
938 | ||
939 | val_mask = mask << shift; | |
940 | val = (ucontrol->value.integer.value[0] & mask); | |
941 | val2 = (ucontrol->value.integer.value[1] & mask); | |
942 | ||
943 | if (val) | |
944 | val = max + 1 - val; | |
945 | if (val2) | |
946 | val2 = max + 1 - val2; | |
947 | ||
948 | val = val << shift; | |
949 | val2 = val2 << shift; | |
950 | ||
951 | err = snd_soc_update_bits(codec, reg, val_mask, val); | |
952 | if (err < 0) | |
953 | return err; | |
954 | ||
955 | err = snd_soc_update_bits(codec, reg2, val_mask, val2); | |
956 | return err; | |
957 | } | |
958 | ||
b74bd40f LCM |
959 | /* Codec operation modes */ |
960 | static const char *twl4030_op_modes_texts[] = { | |
961 | "Option 2 (voice/audio)", "Option 1 (audio)" | |
962 | }; | |
963 | ||
9f04fba7 TI |
964 | static SOC_ENUM_SINGLE_DECL(twl4030_op_modes_enum, |
965 | TWL4030_REG_CODEC_MODE, 0, | |
966 | twl4030_op_modes_texts); | |
b74bd40f | 967 | |
423c238d | 968 | static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol, |
b74bd40f LCM |
969 | struct snd_ctl_elem_value *ucontrol) |
970 | { | |
ea53bf77 | 971 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
b2c812e2 | 972 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
b74bd40f LCM |
973 | |
974 | if (twl4030->configured) { | |
3b8a0795 PU |
975 | dev_err(codec->dev, |
976 | "operation mode cannot be changed on-the-fly\n"); | |
b74bd40f LCM |
977 | return -EBUSY; |
978 | } | |
979 | ||
6b207c0f | 980 | return snd_soc_put_enum_double(kcontrol, ucontrol); |
b74bd40f LCM |
981 | } |
982 | ||
c10b82cf PU |
983 | /* |
984 | * FGAIN volume control: | |
985 | * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB) | |
986 | */ | |
d889a72c | 987 | static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1); |
c10b82cf | 988 | |
0d33ea0b PU |
989 | /* |
990 | * CGAIN volume control: | |
991 | * 0 dB to 12 dB in 6 dB steps | |
992 | * value 2 and 3 means 12 dB | |
993 | */ | |
d889a72c PU |
994 | static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0); |
995 | ||
1a787e7a JS |
996 | /* |
997 | * Voice Downlink GAIN volume control: | |
998 | * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB) | |
999 | */ | |
1000 | static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1); | |
1001 | ||
d889a72c PU |
1002 | /* |
1003 | * Analog playback gain | |
1004 | * -24 dB to 12 dB in 2 dB steps | |
1005 | */ | |
1006 | static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0); | |
0d33ea0b | 1007 | |
4290239c PU |
1008 | /* |
1009 | * Gain controls tied to outputs | |
1010 | * -6 dB to 6 dB in 6 dB steps (mute instead of -12) | |
1011 | */ | |
1012 | static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1); | |
1013 | ||
18cc8d8d JS |
1014 | /* |
1015 | * Gain control for earpiece amplifier | |
1016 | * 0 dB to 12 dB in 6 dB steps (mute instead of -6) | |
1017 | */ | |
1018 | static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1); | |
1019 | ||
381a22b5 PU |
1020 | /* |
1021 | * Capture gain after the ADCs | |
1022 | * from 0 dB to 31 dB in 1 dB steps | |
1023 | */ | |
1024 | static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0); | |
1025 | ||
5920b453 GI |
1026 | /* |
1027 | * Gain control for input amplifiers | |
1028 | * 0 dB to 30 dB in 6 dB steps | |
1029 | */ | |
1030 | static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0); | |
1031 | ||
328d0a13 LCM |
1032 | /* AVADC clock priority */ |
1033 | static const char *twl4030_avadc_clk_priority_texts[] = { | |
1034 | "Voice high priority", "HiFi high priority" | |
1035 | }; | |
1036 | ||
9f04fba7 TI |
1037 | static SOC_ENUM_SINGLE_DECL(twl4030_avadc_clk_priority_enum, |
1038 | TWL4030_REG_AVADC_CTL, 2, | |
1039 | twl4030_avadc_clk_priority_texts); | |
328d0a13 | 1040 | |
89492be8 PU |
1041 | static const char *twl4030_rampdelay_texts[] = { |
1042 | "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms", | |
1043 | "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms", | |
1044 | "3495/2581/1748 ms" | |
1045 | }; | |
1046 | ||
9f04fba7 TI |
1047 | static SOC_ENUM_SINGLE_DECL(twl4030_rampdelay_enum, |
1048 | TWL4030_REG_HS_POPN_SET, 2, | |
1049 | twl4030_rampdelay_texts); | |
89492be8 | 1050 | |
376f7839 PU |
1051 | /* Vibra H-bridge direction mode */ |
1052 | static const char *twl4030_vibradirmode_texts[] = { | |
1053 | "Vibra H-bridge direction", "Audio data MSB", | |
1054 | }; | |
1055 | ||
9f04fba7 TI |
1056 | static SOC_ENUM_SINGLE_DECL(twl4030_vibradirmode_enum, |
1057 | TWL4030_REG_VIBRA_CTL, 5, | |
1058 | twl4030_vibradirmode_texts); | |
376f7839 PU |
1059 | |
1060 | /* Vibra H-bridge direction */ | |
1061 | static const char *twl4030_vibradir_texts[] = { | |
1062 | "Positive polarity", "Negative polarity", | |
1063 | }; | |
1064 | ||
9f04fba7 TI |
1065 | static SOC_ENUM_SINGLE_DECL(twl4030_vibradir_enum, |
1066 | TWL4030_REG_VIBRA_CTL, 1, | |
1067 | twl4030_vibradir_texts); | |
376f7839 | 1068 | |
36aeff61 PU |
1069 | /* Digimic Left and right swapping */ |
1070 | static const char *twl4030_digimicswap_texts[] = { | |
1071 | "Not swapped", "Swapped", | |
1072 | }; | |
1073 | ||
9f04fba7 TI |
1074 | static SOC_ENUM_SINGLE_DECL(twl4030_digimicswap_enum, |
1075 | TWL4030_REG_MISC_SET_1, 0, | |
1076 | twl4030_digimicswap_texts); | |
36aeff61 | 1077 | |
cc17557e | 1078 | static const struct snd_kcontrol_new twl4030_snd_controls[] = { |
b74bd40f LCM |
1079 | /* Codec operation mode control */ |
1080 | SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum, | |
1081 | snd_soc_get_enum_double, | |
1082 | snd_soc_put_twl4030_opmode_enum_double), | |
1083 | ||
d889a72c PU |
1084 | /* Common playback gain controls */ |
1085 | SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume", | |
1086 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
1087 | 0, 0x3f, 0, digital_fine_tlv), | |
1088 | SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume", | |
1089 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
1090 | 0, 0x3f, 0, digital_fine_tlv), | |
1091 | ||
1092 | SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume", | |
1093 | TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA, | |
1094 | 6, 0x2, 0, digital_coarse_tlv), | |
1095 | SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume", | |
1096 | TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA, | |
1097 | 6, 0x2, 0, digital_coarse_tlv), | |
1098 | ||
1099 | SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume", | |
1100 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
1101 | 3, 0x12, 1, analog_tlv), | |
1102 | SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume", | |
1103 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
1104 | 3, 0x12, 1, analog_tlv), | |
44c55870 PU |
1105 | SOC_DOUBLE_R("DAC1 Analog Playback Switch", |
1106 | TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL, | |
1107 | 1, 1, 0), | |
1108 | SOC_DOUBLE_R("DAC2 Analog Playback Switch", | |
1109 | TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL, | |
1110 | 1, 1, 0), | |
381a22b5 | 1111 | |
1a787e7a JS |
1112 | /* Common voice downlink gain controls */ |
1113 | SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume", | |
1114 | TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv), | |
1115 | ||
1116 | SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume", | |
1117 | TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv), | |
1118 | ||
1119 | SOC_SINGLE("DAC Voice Analog Downlink Switch", | |
1120 | TWL4030_REG_VDL_APGA_CTL, 1, 1, 0), | |
1121 | ||
4290239c | 1122 | /* Separate output gain controls */ |
0f9887d1 | 1123 | SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume", |
4290239c | 1124 | TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL, |
0f9887d1 PU |
1125 | 4, 3, 0, snd_soc_get_volsw_r2_twl4030, |
1126 | snd_soc_put_volsw_r2_twl4030, output_tvl), | |
4290239c | 1127 | |
0f9887d1 PU |
1128 | SOC_DOUBLE_EXT_TLV("Headset Playback Volume", |
1129 | TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030, | |
1130 | snd_soc_put_volsw_twl4030, output_tvl), | |
4290239c | 1131 | |
0f9887d1 | 1132 | SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume", |
4290239c | 1133 | TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL, |
0f9887d1 PU |
1134 | 4, 3, 0, snd_soc_get_volsw_r2_twl4030, |
1135 | snd_soc_put_volsw_r2_twl4030, output_tvl), | |
4290239c | 1136 | |
0f9887d1 PU |
1137 | SOC_SINGLE_EXT_TLV("Earpiece Playback Volume", |
1138 | TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030, | |
1139 | snd_soc_put_volsw_twl4030, output_ear_tvl), | |
4290239c | 1140 | |
381a22b5 | 1141 | /* Common capture gain controls */ |
276c6222 | 1142 | SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume", |
381a22b5 PU |
1143 | TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA, |
1144 | 0, 0x1f, 0, digital_capture_tlv), | |
276c6222 PU |
1145 | SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume", |
1146 | TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA, | |
1147 | 0, 0x1f, 0, digital_capture_tlv), | |
5920b453 | 1148 | |
276c6222 | 1149 | SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN, |
5920b453 | 1150 | 0, 3, 5, 0, input_gain_tlv), |
89492be8 | 1151 | |
328d0a13 LCM |
1152 | SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum), |
1153 | ||
89492be8 | 1154 | SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum), |
376f7839 PU |
1155 | |
1156 | SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum), | |
1157 | SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum), | |
36aeff61 PU |
1158 | |
1159 | SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum), | |
cc17557e SS |
1160 | }; |
1161 | ||
cc17557e | 1162 | static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = { |
276c6222 PU |
1163 | /* Left channel inputs */ |
1164 | SND_SOC_DAPM_INPUT("MAINMIC"), | |
1165 | SND_SOC_DAPM_INPUT("HSMIC"), | |
1166 | SND_SOC_DAPM_INPUT("AUXL"), | |
1167 | SND_SOC_DAPM_INPUT("CARKITMIC"), | |
1168 | /* Right channel inputs */ | |
1169 | SND_SOC_DAPM_INPUT("SUBMIC"), | |
1170 | SND_SOC_DAPM_INPUT("AUXR"), | |
1171 | /* Digital microphones (Stereo) */ | |
1172 | SND_SOC_DAPM_INPUT("DIGIMIC0"), | |
1173 | SND_SOC_DAPM_INPUT("DIGIMIC1"), | |
1174 | ||
1175 | /* Outputs */ | |
5e98a464 | 1176 | SND_SOC_DAPM_OUTPUT("EARPIECE"), |
2a6f5c58 PU |
1177 | SND_SOC_DAPM_OUTPUT("PREDRIVEL"), |
1178 | SND_SOC_DAPM_OUTPUT("PREDRIVER"), | |
dfad21a2 PU |
1179 | SND_SOC_DAPM_OUTPUT("HSOL"), |
1180 | SND_SOC_DAPM_OUTPUT("HSOR"), | |
6a1bee4a PU |
1181 | SND_SOC_DAPM_OUTPUT("CARKITL"), |
1182 | SND_SOC_DAPM_OUTPUT("CARKITR"), | |
df339804 PU |
1183 | SND_SOC_DAPM_OUTPUT("HFL"), |
1184 | SND_SOC_DAPM_OUTPUT("HFR"), | |
376f7839 | 1185 | SND_SOC_DAPM_OUTPUT("VIBRA"), |
cc17557e | 1186 | |
7b4c734e PU |
1187 | /* AIF and APLL clocks for running DAIs (including loopback) */ |
1188 | SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"), | |
1189 | SND_SOC_DAPM_INPUT("Virtual HiFi IN"), | |
1190 | SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"), | |
1191 | ||
53b5047d | 1192 | /* DACs */ |
7f51e7d3 PU |
1193 | SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0), |
1194 | SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0), | |
1195 | SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0), | |
1196 | SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0), | |
1197 | SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0), | |
cc17557e | 1198 | |
927a7747 PU |
1199 | SND_SOC_DAPM_AIF_IN("VAIFIN", "Voice Playback", 0, |
1200 | TWL4030_REG_VOICE_IF, 6, 0), | |
1201 | ||
7393958f | 1202 | /* Analog bypasses */ |
78e08e2f PU |
1203 | SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0, |
1204 | &twl4030_dapm_abypassr1_control), | |
1205 | SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1206 | &twl4030_dapm_abypassl1_control), | |
1207 | SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1208 | &twl4030_dapm_abypassr2_control), | |
1209 | SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1210 | &twl4030_dapm_abypassl2_control), | |
1211 | SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0, | |
1212 | &twl4030_dapm_abypassv_control), | |
1213 | ||
1214 | /* Master analog loopback switch */ | |
1215 | SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0, | |
1216 | NULL, 0), | |
7393958f | 1217 | |
6bab83fd | 1218 | /* Digital bypasses */ |
78e08e2f PU |
1219 | SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0, |
1220 | &twl4030_dapm_dbypassl_control), | |
1221 | SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0, | |
1222 | &twl4030_dapm_dbypassr_control), | |
1223 | SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0, | |
1224 | &twl4030_dapm_dbypassv_control), | |
6bab83fd | 1225 | |
4005d39a PU |
1226 | /* Digital mixers, power control for the physical DACs */ |
1227 | SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer", | |
1228 | TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0), | |
1229 | SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer", | |
1230 | TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0), | |
1231 | SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer", | |
1232 | TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0), | |
1233 | SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer", | |
1234 | TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0), | |
1235 | SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer", | |
1236 | TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0), | |
1237 | ||
1238 | /* Analog mixers, power control for the physical PGAs */ | |
1239 | SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", | |
1240 | TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0), | |
1241 | SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", | |
1242 | TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0), | |
1243 | SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", | |
1244 | TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0), | |
1245 | SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", | |
1246 | TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0), | |
1247 | SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer", | |
1248 | TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0), | |
7393958f | 1249 | |
7729cf74 PU |
1250 | SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event, |
1251 | SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD), | |
1252 | ||
7b4c734e PU |
1253 | SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event, |
1254 | SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD), | |
c42a59ea | 1255 | |
1a787e7a | 1256 | /* Output MIXER controls */ |
5e98a464 | 1257 | /* Earpiece */ |
1a787e7a JS |
1258 | SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0, |
1259 | &twl4030_dapm_earpiece_controls[0], | |
1260 | ARRAY_SIZE(twl4030_dapm_earpiece_controls)), | |
9008adf9 PU |
1261 | SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM, |
1262 | 0, 0, NULL, 0, earpiecepga_event, | |
1263 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
2a6f5c58 | 1264 | /* PreDrivL/R */ |
1a787e7a JS |
1265 | SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0, |
1266 | &twl4030_dapm_predrivel_controls[0], | |
1267 | ARRAY_SIZE(twl4030_dapm_predrivel_controls)), | |
9008adf9 PU |
1268 | SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM, |
1269 | 0, 0, NULL, 0, predrivelpga_event, | |
1270 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1271 | SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0, |
1272 | &twl4030_dapm_predriver_controls[0], | |
1273 | ARRAY_SIZE(twl4030_dapm_predriver_controls)), | |
9008adf9 PU |
1274 | SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM, |
1275 | 0, 0, NULL, 0, predriverpga_event, | |
1276 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
dfad21a2 | 1277 | /* HeadsetL/R */ |
6943c92e | 1278 | SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0, |
1a787e7a | 1279 | &twl4030_dapm_hsol_controls[0], |
6943c92e PU |
1280 | ARRAY_SIZE(twl4030_dapm_hsol_controls)), |
1281 | SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM, | |
1282 | 0, 0, NULL, 0, headsetlpga_event, | |
1a787e7a JS |
1283 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), |
1284 | SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0, | |
1285 | &twl4030_dapm_hsor_controls[0], | |
1286 | ARRAY_SIZE(twl4030_dapm_hsor_controls)), | |
6943c92e PU |
1287 | SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM, |
1288 | 0, 0, NULL, 0, headsetrpga_event, | |
1289 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
5152d8c2 | 1290 | /* CarkitL/R */ |
1a787e7a JS |
1291 | SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0, |
1292 | &twl4030_dapm_carkitl_controls[0], | |
1293 | ARRAY_SIZE(twl4030_dapm_carkitl_controls)), | |
9008adf9 PU |
1294 | SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM, |
1295 | 0, 0, NULL, 0, carkitlpga_event, | |
1296 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1297 | SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0, |
1298 | &twl4030_dapm_carkitr_controls[0], | |
1299 | ARRAY_SIZE(twl4030_dapm_carkitr_controls)), | |
9008adf9 PU |
1300 | SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM, |
1301 | 0, 0, NULL, 0, carkitrpga_event, | |
1302 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1a787e7a JS |
1303 | |
1304 | /* Output MUX controls */ | |
df339804 | 1305 | /* HandsfreeL/R */ |
5a2e9a48 PU |
1306 | SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0, |
1307 | &twl4030_dapm_handsfreel_control), | |
e3c7dbb0 | 1308 | SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0, |
0f89bdca | 1309 | &twl4030_dapm_handsfreelmute_control), |
5a2e9a48 PU |
1310 | SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM, |
1311 | 0, 0, NULL, 0, handsfreelpga_event, | |
1312 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
1313 | SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0, | |
1314 | &twl4030_dapm_handsfreer_control), | |
e3c7dbb0 | 1315 | SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0, |
0f89bdca | 1316 | &twl4030_dapm_handsfreermute_control), |
5a2e9a48 PU |
1317 | SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM, |
1318 | 0, 0, NULL, 0, handsfreerpga_event, | |
1319 | SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD), | |
376f7839 | 1320 | /* Vibra */ |
86139a13 JV |
1321 | SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0, |
1322 | &twl4030_dapm_vibra_control, vibramux_event, | |
1323 | SND_SOC_DAPM_PRE_PMU), | |
376f7839 PU |
1324 | SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0, |
1325 | &twl4030_dapm_vibrapath_control), | |
5e98a464 | 1326 | |
276c6222 PU |
1327 | /* Introducing four virtual ADC, since TWL4030 have four channel for |
1328 | capture */ | |
7f51e7d3 PU |
1329 | SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0), |
1330 | SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0), | |
1331 | SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0), | |
1332 | SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0), | |
276c6222 | 1333 | |
927a7747 PU |
1334 | SND_SOC_DAPM_AIF_OUT("VAIFOUT", "Voice Capture", 0, |
1335 | TWL4030_REG_VOICE_IF, 5, 0), | |
1336 | ||
276c6222 PU |
1337 | /* Analog/Digital mic path selection. |
1338 | TX1 Left/Right: either analog Left/Right or Digimic0 | |
1339 | TX2 Left/Right: either analog Left/Right or Digimic1 */ | |
bda7d2a8 PU |
1340 | SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0, |
1341 | &twl4030_dapm_micpathtx1_control), | |
1342 | SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0, | |
1343 | &twl4030_dapm_micpathtx2_control), | |
276c6222 | 1344 | |
97b8096d | 1345 | /* Analog input mixers for the capture amplifiers */ |
9028935d | 1346 | SND_SOC_DAPM_MIXER("Analog Left", |
97b8096d JS |
1347 | TWL4030_REG_ANAMICL, 4, 0, |
1348 | &twl4030_dapm_analoglmic_controls[0], | |
1349 | ARRAY_SIZE(twl4030_dapm_analoglmic_controls)), | |
9028935d | 1350 | SND_SOC_DAPM_MIXER("Analog Right", |
97b8096d JS |
1351 | TWL4030_REG_ANAMICR, 4, 0, |
1352 | &twl4030_dapm_analogrmic_controls[0], | |
1353 | ARRAY_SIZE(twl4030_dapm_analogrmic_controls)), | |
276c6222 | 1354 | |
fb2a2f84 PU |
1355 | SND_SOC_DAPM_PGA("ADC Physical Left", |
1356 | TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0), | |
1357 | SND_SOC_DAPM_PGA("ADC Physical Right", | |
1358 | TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0), | |
276c6222 | 1359 | |
01ea6ba2 PU |
1360 | SND_SOC_DAPM_PGA_E("Digimic0 Enable", |
1361 | TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0, | |
1362 | digimic_event, SND_SOC_DAPM_POST_PMU), | |
1363 | SND_SOC_DAPM_PGA_E("Digimic1 Enable", | |
1364 | TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0, | |
1365 | digimic_event, SND_SOC_DAPM_POST_PMU), | |
276c6222 | 1366 | |
bda7d2a8 PU |
1367 | SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0, |
1368 | NULL, 0), | |
1369 | SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0, | |
1370 | NULL, 0), | |
1371 | ||
e04d6e55 PU |
1372 | /* Microphone bias */ |
1373 | SND_SOC_DAPM_SUPPLY("Mic Bias 1", | |
1374 | TWL4030_REG_MICBIAS_CTL, 0, 0, NULL, 0), | |
1375 | SND_SOC_DAPM_SUPPLY("Mic Bias 2", | |
1376 | TWL4030_REG_MICBIAS_CTL, 1, 0, NULL, 0), | |
1377 | SND_SOC_DAPM_SUPPLY("Headset Mic Bias", | |
1378 | TWL4030_REG_MICBIAS_CTL, 2, 0, NULL, 0), | |
7393958f | 1379 | |
927a7747 | 1380 | SND_SOC_DAPM_SUPPLY("VIF Enable", TWL4030_REG_VOICE_IF, 0, 0, NULL, 0), |
cc17557e SS |
1381 | }; |
1382 | ||
1383 | static const struct snd_soc_dapm_route intercon[] = { | |
7f51e7d3 PU |
1384 | /* Stream -> DAC mapping */ |
1385 | {"DAC Right1", NULL, "HiFi Playback"}, | |
1386 | {"DAC Left1", NULL, "HiFi Playback"}, | |
1387 | {"DAC Right2", NULL, "HiFi Playback"}, | |
1388 | {"DAC Left2", NULL, "HiFi Playback"}, | |
927a7747 | 1389 | {"DAC Voice", NULL, "VAIFIN"}, |
7f51e7d3 PU |
1390 | |
1391 | /* ADC -> Stream mapping */ | |
1392 | {"HiFi Capture", NULL, "ADC Virtual Left1"}, | |
1393 | {"HiFi Capture", NULL, "ADC Virtual Right1"}, | |
1394 | {"HiFi Capture", NULL, "ADC Virtual Left2"}, | |
1395 | {"HiFi Capture", NULL, "ADC Virtual Right2"}, | |
927a7747 PU |
1396 | {"VAIFOUT", NULL, "ADC Virtual Left2"}, |
1397 | {"VAIFOUT", NULL, "ADC Virtual Right2"}, | |
1398 | {"VAIFOUT", NULL, "VIF Enable"}, | |
7f51e7d3 | 1399 | |
4005d39a PU |
1400 | {"Digital L1 Playback Mixer", NULL, "DAC Left1"}, |
1401 | {"Digital R1 Playback Mixer", NULL, "DAC Right1"}, | |
1402 | {"Digital L2 Playback Mixer", NULL, "DAC Left2"}, | |
1403 | {"Digital R2 Playback Mixer", NULL, "DAC Right2"}, | |
1404 | {"Digital Voice Playback Mixer", NULL, "DAC Voice"}, | |
1405 | ||
7729cf74 | 1406 | /* Supply for the digital part (APLL) */ |
7729cf74 PU |
1407 | {"Digital Voice Playback Mixer", NULL, "APLL Enable"}, |
1408 | ||
27eeb1fe PU |
1409 | {"DAC Left1", NULL, "AIF Enable"}, |
1410 | {"DAC Right1", NULL, "AIF Enable"}, | |
1411 | {"DAC Left2", NULL, "AIF Enable"}, | |
1412 | {"DAC Right1", NULL, "AIF Enable"}, | |
927a7747 | 1413 | {"DAC Voice", NULL, "VIF Enable"}, |
27eeb1fe | 1414 | |
c42a59ea PU |
1415 | {"Digital R2 Playback Mixer", NULL, "AIF Enable"}, |
1416 | {"Digital L2 Playback Mixer", NULL, "AIF Enable"}, | |
1417 | ||
4005d39a PU |
1418 | {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"}, |
1419 | {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"}, | |
1420 | {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"}, | |
1421 | {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"}, | |
1422 | {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"}, | |
1a787e7a | 1423 | |
5e98a464 PU |
1424 | /* Internal playback routings */ |
1425 | /* Earpiece */ | |
4005d39a PU |
1426 | {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1427 | {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1428 | {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
1429 | {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
9008adf9 | 1430 | {"Earpiece PGA", NULL, "Earpiece Mixer"}, |
2a6f5c58 | 1431 | /* PreDrivL */ |
4005d39a PU |
1432 | {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1433 | {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1434 | {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
1435 | {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
9008adf9 | 1436 | {"PredriveL PGA", NULL, "PredriveL Mixer"}, |
2a6f5c58 | 1437 | /* PreDrivR */ |
4005d39a PU |
1438 | {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1439 | {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1440 | {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
1441 | {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
9008adf9 | 1442 | {"PredriveR PGA", NULL, "PredriveR Mixer"}, |
dfad21a2 | 1443 | /* HeadsetL */ |
4005d39a PU |
1444 | {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1445 | {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1446 | {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
6943c92e | 1447 | {"HeadsetL PGA", NULL, "HeadsetL Mixer"}, |
dfad21a2 | 1448 | /* HeadsetR */ |
4005d39a PU |
1449 | {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1450 | {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1451 | {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
6943c92e | 1452 | {"HeadsetR PGA", NULL, "HeadsetR Mixer"}, |
5152d8c2 | 1453 | /* CarkitL */ |
4005d39a PU |
1454 | {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1455 | {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"}, | |
1456 | {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"}, | |
9008adf9 | 1457 | {"CarkitL PGA", NULL, "CarkitL Mixer"}, |
5152d8c2 | 1458 | /* CarkitR */ |
4005d39a PU |
1459 | {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"}, |
1460 | {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"}, | |
1461 | {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"}, | |
9008adf9 | 1462 | {"CarkitR PGA", NULL, "CarkitR Mixer"}, |
df339804 | 1463 | /* HandsfreeL */ |
4005d39a PU |
1464 | {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"}, |
1465 | {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"}, | |
1466 | {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"}, | |
1467 | {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"}, | |
e3c7dbb0 LCM |
1468 | {"HandsfreeL", "Switch", "HandsfreeL Mux"}, |
1469 | {"HandsfreeL PGA", NULL, "HandsfreeL"}, | |
df339804 | 1470 | /* HandsfreeR */ |
4005d39a PU |
1471 | {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"}, |
1472 | {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"}, | |
1473 | {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"}, | |
1474 | {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"}, | |
e3c7dbb0 LCM |
1475 | {"HandsfreeR", "Switch", "HandsfreeR Mux"}, |
1476 | {"HandsfreeR PGA", NULL, "HandsfreeR"}, | |
376f7839 PU |
1477 | /* Vibra */ |
1478 | {"Vibra Mux", "AudioL1", "DAC Left1"}, | |
1479 | {"Vibra Mux", "AudioR1", "DAC Right1"}, | |
1480 | {"Vibra Mux", "AudioL2", "DAC Left2"}, | |
1481 | {"Vibra Mux", "AudioR2", "DAC Right2"}, | |
5e98a464 | 1482 | |
cc17557e | 1483 | /* outputs */ |
7b4c734e | 1484 | /* Must be always connected (for AIF and APLL) */ |
27eeb1fe PU |
1485 | {"Virtual HiFi OUT", NULL, "DAC Left1"}, |
1486 | {"Virtual HiFi OUT", NULL, "DAC Right1"}, | |
1487 | {"Virtual HiFi OUT", NULL, "DAC Left2"}, | |
1488 | {"Virtual HiFi OUT", NULL, "DAC Right2"}, | |
7b4c734e PU |
1489 | /* Must be always connected (for APLL) */ |
1490 | {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"}, | |
1491 | /* Physical outputs */ | |
9008adf9 PU |
1492 | {"EARPIECE", NULL, "Earpiece PGA"}, |
1493 | {"PREDRIVEL", NULL, "PredriveL PGA"}, | |
1494 | {"PREDRIVER", NULL, "PredriveR PGA"}, | |
6943c92e PU |
1495 | {"HSOL", NULL, "HeadsetL PGA"}, |
1496 | {"HSOR", NULL, "HeadsetR PGA"}, | |
9008adf9 PU |
1497 | {"CARKITL", NULL, "CarkitL PGA"}, |
1498 | {"CARKITR", NULL, "CarkitR PGA"}, | |
5a2e9a48 PU |
1499 | {"HFL", NULL, "HandsfreeL PGA"}, |
1500 | {"HFR", NULL, "HandsfreeR PGA"}, | |
376f7839 PU |
1501 | {"Vibra Route", "Audio", "Vibra Mux"}, |
1502 | {"VIBRA", NULL, "Vibra Route"}, | |
cc17557e | 1503 | |
276c6222 | 1504 | /* Capture path */ |
7b4c734e PU |
1505 | /* Must be always connected (for AIF and APLL) */ |
1506 | {"ADC Virtual Left1", NULL, "Virtual HiFi IN"}, | |
1507 | {"ADC Virtual Right1", NULL, "Virtual HiFi IN"}, | |
1508 | {"ADC Virtual Left2", NULL, "Virtual HiFi IN"}, | |
1509 | {"ADC Virtual Right2", NULL, "Virtual HiFi IN"}, | |
1510 | /* Physical inputs */ | |
9028935d PU |
1511 | {"Analog Left", "Main Mic Capture Switch", "MAINMIC"}, |
1512 | {"Analog Left", "Headset Mic Capture Switch", "HSMIC"}, | |
1513 | {"Analog Left", "AUXL Capture Switch", "AUXL"}, | |
1514 | {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"}, | |
276c6222 | 1515 | |
9028935d PU |
1516 | {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"}, |
1517 | {"Analog Right", "AUXR Capture Switch", "AUXR"}, | |
276c6222 | 1518 | |
9028935d PU |
1519 | {"ADC Physical Left", NULL, "Analog Left"}, |
1520 | {"ADC Physical Right", NULL, "Analog Right"}, | |
276c6222 PU |
1521 | |
1522 | {"Digimic0 Enable", NULL, "DIGIMIC0"}, | |
1523 | {"Digimic1 Enable", NULL, "DIGIMIC1"}, | |
1524 | ||
bda7d2a8 PU |
1525 | {"DIGIMIC0", NULL, "micbias1 select"}, |
1526 | {"DIGIMIC1", NULL, "micbias2 select"}, | |
1527 | ||
276c6222 | 1528 | /* TX1 Left capture path */ |
fb2a2f84 | 1529 | {"TX1 Capture Route", "Analog", "ADC Physical Left"}, |
276c6222 PU |
1530 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, |
1531 | /* TX1 Right capture path */ | |
fb2a2f84 | 1532 | {"TX1 Capture Route", "Analog", "ADC Physical Right"}, |
276c6222 PU |
1533 | {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"}, |
1534 | /* TX2 Left capture path */ | |
fb2a2f84 | 1535 | {"TX2 Capture Route", "Analog", "ADC Physical Left"}, |
276c6222 PU |
1536 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, |
1537 | /* TX2 Right capture path */ | |
fb2a2f84 | 1538 | {"TX2 Capture Route", "Analog", "ADC Physical Right"}, |
276c6222 PU |
1539 | {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"}, |
1540 | ||
1541 | {"ADC Virtual Left1", NULL, "TX1 Capture Route"}, | |
1542 | {"ADC Virtual Right1", NULL, "TX1 Capture Route"}, | |
1543 | {"ADC Virtual Left2", NULL, "TX2 Capture Route"}, | |
1544 | {"ADC Virtual Right2", NULL, "TX2 Capture Route"}, | |
1545 | ||
c42a59ea PU |
1546 | {"ADC Virtual Left1", NULL, "AIF Enable"}, |
1547 | {"ADC Virtual Right1", NULL, "AIF Enable"}, | |
1548 | {"ADC Virtual Left2", NULL, "AIF Enable"}, | |
1549 | {"ADC Virtual Right2", NULL, "AIF Enable"}, | |
1550 | ||
7393958f | 1551 | /* Analog bypass routes */ |
9028935d PU |
1552 | {"Right1 Analog Loopback", "Switch", "Analog Right"}, |
1553 | {"Left1 Analog Loopback", "Switch", "Analog Left"}, | |
1554 | {"Right2 Analog Loopback", "Switch", "Analog Right"}, | |
1555 | {"Left2 Analog Loopback", "Switch", "Analog Left"}, | |
1556 | {"Voice Analog Loopback", "Switch", "Analog Left"}, | |
7393958f | 1557 | |
78e08e2f PU |
1558 | /* Supply for the Analog loopbacks */ |
1559 | {"Right1 Analog Loopback", NULL, "FM Loop Enable"}, | |
1560 | {"Left1 Analog Loopback", NULL, "FM Loop Enable"}, | |
1561 | {"Right2 Analog Loopback", NULL, "FM Loop Enable"}, | |
1562 | {"Left2 Analog Loopback", NULL, "FM Loop Enable"}, | |
1563 | {"Voice Analog Loopback", NULL, "FM Loop Enable"}, | |
1564 | ||
7393958f PU |
1565 | {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"}, |
1566 | {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"}, | |
1567 | {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"}, | |
1568 | {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"}, | |
fcd274a3 | 1569 | {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"}, |
7393958f | 1570 | |
6bab83fd PU |
1571 | /* Digital bypass routes */ |
1572 | {"Right Digital Loopback", "Volume", "TX1 Capture Route"}, | |
1573 | {"Left Digital Loopback", "Volume", "TX1 Capture Route"}, | |
ee8f6894 | 1574 | {"Voice Digital Loopback", "Volume", "TX2 Capture Route"}, |
6bab83fd | 1575 | |
4005d39a PU |
1576 | {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"}, |
1577 | {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"}, | |
1578 | {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"}, | |
6bab83fd | 1579 | |
cc17557e SS |
1580 | }; |
1581 | ||
cc17557e SS |
1582 | static int twl4030_set_bias_level(struct snd_soc_codec *codec, |
1583 | enum snd_soc_bias_level level) | |
1584 | { | |
1585 | switch (level) { | |
1586 | case SND_SOC_BIAS_ON: | |
cc17557e SS |
1587 | break; |
1588 | case SND_SOC_BIAS_PREPARE: | |
cc17557e SS |
1589 | break; |
1590 | case SND_SOC_BIAS_STANDBY: | |
1682c8e5 | 1591 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) |
ee4ccac7 | 1592 | twl4030_codec_enable(codec, 1); |
cc17557e SS |
1593 | break; |
1594 | case SND_SOC_BIAS_OFF: | |
cbd2db12 | 1595 | twl4030_codec_enable(codec, 0); |
cc17557e SS |
1596 | break; |
1597 | } | |
cc17557e SS |
1598 | |
1599 | return 0; | |
1600 | } | |
1601 | ||
6b87a91f PU |
1602 | static void twl4030_constraints(struct twl4030_priv *twl4030, |
1603 | struct snd_pcm_substream *mst_substream) | |
1604 | { | |
1605 | struct snd_pcm_substream *slv_substream; | |
1606 | ||
1607 | /* Pick the stream, which need to be constrained */ | |
1608 | if (mst_substream == twl4030->master_substream) | |
1609 | slv_substream = twl4030->slave_substream; | |
1610 | else if (mst_substream == twl4030->slave_substream) | |
1611 | slv_substream = twl4030->master_substream; | |
1612 | else /* This should not happen.. */ | |
1613 | return; | |
1614 | ||
1615 | /* Set the constraints according to the already configured stream */ | |
1616 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1617 | SNDRV_PCM_HW_PARAM_RATE, | |
1618 | twl4030->rate, | |
1619 | twl4030->rate); | |
1620 | ||
1621 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1622 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS, | |
1623 | twl4030->sample_bits, | |
1624 | twl4030->sample_bits); | |
1625 | ||
1626 | snd_pcm_hw_constraint_minmax(slv_substream->runtime, | |
1627 | SNDRV_PCM_HW_PARAM_CHANNELS, | |
1628 | twl4030->channels, | |
1629 | twl4030->channels); | |
1630 | } | |
1631 | ||
8a1f936a PU |
1632 | /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for |
1633 | * capture has to be enabled/disabled. */ | |
1634 | static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction, | |
7ded5fe0 | 1635 | int enable) |
8a1f936a PU |
1636 | { |
1637 | u8 reg, mask; | |
1638 | ||
efc8acff | 1639 | reg = twl4030_read(codec, TWL4030_REG_OPTION); |
8a1f936a PU |
1640 | |
1641 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1642 | mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN; | |
1643 | else | |
1644 | mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; | |
1645 | ||
1646 | if (enable) | |
1647 | reg |= mask; | |
1648 | else | |
1649 | reg &= ~mask; | |
1650 | ||
1651 | twl4030_write(codec, TWL4030_REG_OPTION, reg); | |
1652 | } | |
1653 | ||
d6648da1 PU |
1654 | static int twl4030_startup(struct snd_pcm_substream *substream, |
1655 | struct snd_soc_dai *dai) | |
7220b9f4 | 1656 | { |
e6968a17 | 1657 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 1658 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7220b9f4 | 1659 | |
7220b9f4 | 1660 | if (twl4030->master_substream) { |
7220b9f4 | 1661 | twl4030->slave_substream = substream; |
6b87a91f PU |
1662 | /* The DAI has one configuration for playback and capture, so |
1663 | * if the DAI has been already configured then constrain this | |
1664 | * substream to match it. */ | |
1665 | if (twl4030->configured) | |
1666 | twl4030_constraints(twl4030, twl4030->master_substream); | |
1667 | } else { | |
efc8acff | 1668 | if (!(twl4030_read(codec, TWL4030_REG_CODEC_MODE) & |
8a1f936a PU |
1669 | TWL4030_OPTION_1)) { |
1670 | /* In option2 4 channel is not supported, set the | |
1671 | * constraint for the first stream for channels, the | |
1672 | * second stream will 'inherit' this cosntraint */ | |
1673 | snd_pcm_hw_constraint_minmax(substream->runtime, | |
7ded5fe0 PU |
1674 | SNDRV_PCM_HW_PARAM_CHANNELS, |
1675 | 2, 2); | |
8a1f936a | 1676 | } |
7220b9f4 | 1677 | twl4030->master_substream = substream; |
6b87a91f | 1678 | } |
7220b9f4 PU |
1679 | |
1680 | return 0; | |
1681 | } | |
1682 | ||
d6648da1 PU |
1683 | static void twl4030_shutdown(struct snd_pcm_substream *substream, |
1684 | struct snd_soc_dai *dai) | |
7220b9f4 | 1685 | { |
e6968a17 | 1686 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 1687 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7220b9f4 PU |
1688 | |
1689 | if (twl4030->master_substream == substream) | |
1690 | twl4030->master_substream = twl4030->slave_substream; | |
1691 | ||
1692 | twl4030->slave_substream = NULL; | |
6b87a91f PU |
1693 | |
1694 | /* If all streams are closed, or the remaining stream has not yet | |
1695 | * been configured than set the DAI as not configured. */ | |
1696 | if (!twl4030->master_substream) | |
1697 | twl4030->configured = 0; | |
1698 | else if (!twl4030->master_substream->runtime->channels) | |
1699 | twl4030->configured = 0; | |
8a1f936a PU |
1700 | |
1701 | /* If the closing substream had 4 channel, do the necessary cleanup */ | |
1702 | if (substream->runtime->channels == 4) | |
1703 | twl4030_tdm_enable(codec, substream->stream, 0); | |
7220b9f4 PU |
1704 | } |
1705 | ||
cc17557e | 1706 | static int twl4030_hw_params(struct snd_pcm_substream *substream, |
7ded5fe0 PU |
1707 | struct snd_pcm_hw_params *params, |
1708 | struct snd_soc_dai *dai) | |
cc17557e | 1709 | { |
e6968a17 | 1710 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 1711 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
cc17557e SS |
1712 | u8 mode, old_mode, format, old_format; |
1713 | ||
8a1f936a PU |
1714 | /* If the substream has 4 channel, do the necessary setup */ |
1715 | if (params_channels(params) == 4) { | |
efc8acff PU |
1716 | format = twl4030_read(codec, TWL4030_REG_AUDIO_IF); |
1717 | mode = twl4030_read(codec, TWL4030_REG_CODEC_MODE); | |
eaf1ac8b PU |
1718 | |
1719 | /* Safety check: are we in the correct operating mode and | |
1720 | * the interface is in TDM mode? */ | |
1721 | if ((mode & TWL4030_OPTION_1) && | |
1722 | ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM)) | |
8a1f936a PU |
1723 | twl4030_tdm_enable(codec, substream->stream, 1); |
1724 | else | |
1725 | return -EINVAL; | |
1726 | } | |
1727 | ||
6b87a91f PU |
1728 | if (twl4030->configured) |
1729 | /* Ignoring hw_params for already configured DAI */ | |
7220b9f4 PU |
1730 | return 0; |
1731 | ||
cc17557e | 1732 | /* bit rate */ |
efc8acff PU |
1733 | old_mode = twl4030_read(codec, |
1734 | TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; | |
cc17557e SS |
1735 | mode = old_mode & ~TWL4030_APLL_RATE; |
1736 | ||
1737 | switch (params_rate(params)) { | |
1738 | case 8000: | |
1739 | mode |= TWL4030_APLL_RATE_8000; | |
1740 | break; | |
1741 | case 11025: | |
1742 | mode |= TWL4030_APLL_RATE_11025; | |
1743 | break; | |
1744 | case 12000: | |
1745 | mode |= TWL4030_APLL_RATE_12000; | |
1746 | break; | |
1747 | case 16000: | |
1748 | mode |= TWL4030_APLL_RATE_16000; | |
1749 | break; | |
1750 | case 22050: | |
1751 | mode |= TWL4030_APLL_RATE_22050; | |
1752 | break; | |
1753 | case 24000: | |
1754 | mode |= TWL4030_APLL_RATE_24000; | |
1755 | break; | |
1756 | case 32000: | |
1757 | mode |= TWL4030_APLL_RATE_32000; | |
1758 | break; | |
1759 | case 44100: | |
1760 | mode |= TWL4030_APLL_RATE_44100; | |
1761 | break; | |
1762 | case 48000: | |
1763 | mode |= TWL4030_APLL_RATE_48000; | |
1764 | break; | |
103f211d PU |
1765 | case 96000: |
1766 | mode |= TWL4030_APLL_RATE_96000; | |
1767 | break; | |
cc17557e | 1768 | default: |
3b8a0795 | 1769 | dev_err(codec->dev, "%s: unknown rate %d\n", __func__, |
cc17557e SS |
1770 | params_rate(params)); |
1771 | return -EINVAL; | |
1772 | } | |
1773 | ||
cc17557e | 1774 | /* sample size */ |
efc8acff | 1775 | old_format = twl4030_read(codec, TWL4030_REG_AUDIO_IF); |
cc17557e SS |
1776 | format = old_format; |
1777 | format &= ~TWL4030_DATA_WIDTH; | |
04f630d8 MB |
1778 | switch (params_width(params)) { |
1779 | case 16: | |
cc17557e SS |
1780 | format |= TWL4030_DATA_WIDTH_16S_16W; |
1781 | break; | |
04f630d8 | 1782 | case 32: |
cc17557e SS |
1783 | format |= TWL4030_DATA_WIDTH_32S_24W; |
1784 | break; | |
1785 | default: | |
04f630d8 MB |
1786 | dev_err(codec->dev, "%s: unsupported bits/sample %d\n", |
1787 | __func__, params_width(params)); | |
cc17557e SS |
1788 | return -EINVAL; |
1789 | } | |
1790 | ||
2046f175 PU |
1791 | if (format != old_format || mode != old_mode) { |
1792 | if (twl4030->codec_powered) { | |
1793 | /* | |
1794 | * If the codec is powered, than we need to toggle the | |
1795 | * codec power. | |
1796 | */ | |
1797 | twl4030_codec_enable(codec, 0); | |
1798 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
1799 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1800 | twl4030_codec_enable(codec, 1); | |
1801 | } else { | |
1802 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
1803 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1804 | } | |
cc17557e | 1805 | } |
6b87a91f PU |
1806 | |
1807 | /* Store the important parameters for the DAI configuration and set | |
1808 | * the DAI as configured */ | |
1809 | twl4030->configured = 1; | |
1810 | twl4030->rate = params_rate(params); | |
1811 | twl4030->sample_bits = hw_param_interval(params, | |
1812 | SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; | |
1813 | twl4030->channels = params_channels(params); | |
1814 | ||
1815 | /* If both playback and capture streams are open, and one of them | |
1816 | * is setting the hw parameters right now (since we are here), set | |
1817 | * constraints to the other stream to match the current one. */ | |
1818 | if (twl4030->slave_substream) | |
1819 | twl4030_constraints(twl4030, substream); | |
1820 | ||
cc17557e SS |
1821 | return 0; |
1822 | } | |
1823 | ||
7ded5fe0 PU |
1824 | static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, |
1825 | unsigned int freq, int dir) | |
cc17557e SS |
1826 | { |
1827 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1828 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
cc17557e SS |
1829 | |
1830 | switch (freq) { | |
1831 | case 19200000: | |
cc17557e | 1832 | case 26000000: |
cc17557e | 1833 | case 38400000: |
cc17557e SS |
1834 | break; |
1835 | default: | |
3b8a0795 | 1836 | dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq); |
cc17557e SS |
1837 | return -EINVAL; |
1838 | } | |
1839 | ||
68d01955 PU |
1840 | if ((freq / 1000) != twl4030->sysclk) { |
1841 | dev_err(codec->dev, | |
3b8a0795 | 1842 | "Mismatch in HFCLKIN: %u (configured: %u)\n", |
68d01955 PU |
1843 | freq, twl4030->sysclk * 1000); |
1844 | return -EINVAL; | |
1845 | } | |
cc17557e SS |
1846 | |
1847 | return 0; | |
1848 | } | |
1849 | ||
7ded5fe0 | 1850 | static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) |
cc17557e SS |
1851 | { |
1852 | struct snd_soc_codec *codec = codec_dai->codec; | |
2046f175 | 1853 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
cc17557e SS |
1854 | u8 old_format, format; |
1855 | ||
1856 | /* get format */ | |
efc8acff | 1857 | old_format = twl4030_read(codec, TWL4030_REG_AUDIO_IF); |
cc17557e SS |
1858 | format = old_format; |
1859 | ||
1860 | /* set master/slave audio interface */ | |
1861 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1862 | case SND_SOC_DAIFMT_CBM_CFM: | |
1863 | format &= ~(TWL4030_AIF_SLAVE_EN); | |
e18c94d2 | 1864 | format &= ~(TWL4030_CLK256FS_EN); |
cc17557e SS |
1865 | break; |
1866 | case SND_SOC_DAIFMT_CBS_CFS: | |
cc17557e | 1867 | format |= TWL4030_AIF_SLAVE_EN; |
e18c94d2 | 1868 | format |= TWL4030_CLK256FS_EN; |
cc17557e SS |
1869 | break; |
1870 | default: | |
1871 | return -EINVAL; | |
1872 | } | |
1873 | ||
1874 | /* interface format */ | |
1875 | format &= ~TWL4030_AIF_FORMAT; | |
1876 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1877 | case SND_SOC_DAIFMT_I2S: | |
1878 | format |= TWL4030_AIF_FORMAT_CODEC; | |
1879 | break; | |
8a1f936a PU |
1880 | case SND_SOC_DAIFMT_DSP_A: |
1881 | format |= TWL4030_AIF_FORMAT_TDM; | |
1882 | break; | |
cc17557e SS |
1883 | default: |
1884 | return -EINVAL; | |
1885 | } | |
1886 | ||
1887 | if (format != old_format) { | |
2046f175 PU |
1888 | if (twl4030->codec_powered) { |
1889 | /* | |
1890 | * If the codec is powered, than we need to toggle the | |
1891 | * codec power. | |
1892 | */ | |
1893 | twl4030_codec_enable(codec, 0); | |
1894 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1895 | twl4030_codec_enable(codec, 1); | |
1896 | } else { | |
1897 | twl4030_write(codec, TWL4030_REG_AUDIO_IF, format); | |
1898 | } | |
cc17557e SS |
1899 | } |
1900 | ||
1901 | return 0; | |
1902 | } | |
1903 | ||
68140443 LCM |
1904 | static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate) |
1905 | { | |
1906 | struct snd_soc_codec *codec = dai->codec; | |
efc8acff | 1907 | u8 reg = twl4030_read(codec, TWL4030_REG_AUDIO_IF); |
68140443 LCM |
1908 | |
1909 | if (tristate) | |
1910 | reg |= TWL4030_AIF_TRI_EN; | |
1911 | else | |
1912 | reg &= ~TWL4030_AIF_TRI_EN; | |
1913 | ||
1914 | return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg); | |
1915 | } | |
1916 | ||
b7a755a8 MLC |
1917 | /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R |
1918 | * (VTXL, VTXR) for uplink has to be enabled/disabled. */ | |
1919 | static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction, | |
7ded5fe0 | 1920 | int enable) |
b7a755a8 MLC |
1921 | { |
1922 | u8 reg, mask; | |
1923 | ||
efc8acff | 1924 | reg = twl4030_read(codec, TWL4030_REG_OPTION); |
b7a755a8 MLC |
1925 | |
1926 | if (direction == SNDRV_PCM_STREAM_PLAYBACK) | |
1927 | mask = TWL4030_ARXL1_VRX_EN; | |
1928 | else | |
1929 | mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN; | |
1930 | ||
1931 | if (enable) | |
1932 | reg |= mask; | |
1933 | else | |
1934 | reg &= ~mask; | |
1935 | ||
1936 | twl4030_write(codec, TWL4030_REG_OPTION, reg); | |
1937 | } | |
1938 | ||
7154b3e8 | 1939 | static int twl4030_voice_startup(struct snd_pcm_substream *substream, |
7ded5fe0 | 1940 | struct snd_soc_dai *dai) |
7154b3e8 | 1941 | { |
e6968a17 | 1942 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 1943 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7154b3e8 JS |
1944 | u8 mode; |
1945 | ||
1946 | /* If the system master clock is not 26MHz, the voice PCM interface is | |
25985edc | 1947 | * not available. |
7154b3e8 | 1948 | */ |
68d01955 | 1949 | if (twl4030->sysclk != 26000) { |
3b8a0795 PU |
1950 | dev_err(codec->dev, |
1951 | "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n", | |
1952 | __func__, twl4030->sysclk); | |
7154b3e8 JS |
1953 | return -EINVAL; |
1954 | } | |
1955 | ||
1956 | /* If the codec mode is not option2, the voice PCM interface is not | |
25985edc | 1957 | * available. |
7154b3e8 | 1958 | */ |
efc8acff | 1959 | mode = twl4030_read(codec, TWL4030_REG_CODEC_MODE) |
7154b3e8 JS |
1960 | & TWL4030_OPT_MODE; |
1961 | ||
1962 | if (mode != TWL4030_OPTION_2) { | |
3b8a0795 PU |
1963 | dev_err(codec->dev, "%s: the codec mode is not option2\n", |
1964 | __func__); | |
7154b3e8 JS |
1965 | return -EINVAL; |
1966 | } | |
1967 | ||
1968 | return 0; | |
1969 | } | |
1970 | ||
b7a755a8 | 1971 | static void twl4030_voice_shutdown(struct snd_pcm_substream *substream, |
7ded5fe0 | 1972 | struct snd_soc_dai *dai) |
b7a755a8 | 1973 | { |
e6968a17 | 1974 | struct snd_soc_codec *codec = dai->codec; |
b7a755a8 MLC |
1975 | |
1976 | /* Enable voice digital filters */ | |
1977 | twl4030_voice_enable(codec, substream->stream, 0); | |
1978 | } | |
1979 | ||
7154b3e8 | 1980 | static int twl4030_voice_hw_params(struct snd_pcm_substream *substream, |
7ded5fe0 PU |
1981 | struct snd_pcm_hw_params *params, |
1982 | struct snd_soc_dai *dai) | |
7154b3e8 | 1983 | { |
e6968a17 | 1984 | struct snd_soc_codec *codec = dai->codec; |
2046f175 | 1985 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7154b3e8 JS |
1986 | u8 old_mode, mode; |
1987 | ||
b7a755a8 MLC |
1988 | /* Enable voice digital filters */ |
1989 | twl4030_voice_enable(codec, substream->stream, 1); | |
1990 | ||
7154b3e8 | 1991 | /* bit rate */ |
7ded5fe0 PU |
1992 | old_mode = twl4030_read(codec, |
1993 | TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ; | |
7154b3e8 JS |
1994 | mode = old_mode; |
1995 | ||
1996 | switch (params_rate(params)) { | |
1997 | case 8000: | |
1998 | mode &= ~(TWL4030_SEL_16K); | |
1999 | break; | |
2000 | case 16000: | |
2001 | mode |= TWL4030_SEL_16K; | |
2002 | break; | |
2003 | default: | |
3b8a0795 | 2004 | dev_err(codec->dev, "%s: unknown rate %d\n", __func__, |
7154b3e8 JS |
2005 | params_rate(params)); |
2006 | return -EINVAL; | |
2007 | } | |
2008 | ||
2009 | if (mode != old_mode) { | |
2046f175 PU |
2010 | if (twl4030->codec_powered) { |
2011 | /* | |
2012 | * If the codec is powered, than we need to toggle the | |
2013 | * codec power. | |
2014 | */ | |
2015 | twl4030_codec_enable(codec, 0); | |
2016 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
2017 | twl4030_codec_enable(codec, 1); | |
2018 | } else { | |
2019 | twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode); | |
2020 | } | |
7154b3e8 JS |
2021 | } |
2022 | ||
2023 | return 0; | |
2024 | } | |
2025 | ||
2026 | static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
7ded5fe0 | 2027 | int clk_id, unsigned int freq, int dir) |
7154b3e8 JS |
2028 | { |
2029 | struct snd_soc_codec *codec = codec_dai->codec; | |
d4a8ca24 | 2030 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7154b3e8 | 2031 | |
68d01955 | 2032 | if (freq != 26000000) { |
3b8a0795 PU |
2033 | dev_err(codec->dev, |
2034 | "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n", | |
2035 | __func__, freq / 1000); | |
68d01955 PU |
2036 | return -EINVAL; |
2037 | } | |
2038 | if ((freq / 1000) != twl4030->sysclk) { | |
2039 | dev_err(codec->dev, | |
3b8a0795 | 2040 | "Mismatch in HFCLKIN: %u (configured: %u)\n", |
68d01955 | 2041 | freq, twl4030->sysclk * 1000); |
7154b3e8 JS |
2042 | return -EINVAL; |
2043 | } | |
7154b3e8 JS |
2044 | return 0; |
2045 | } | |
2046 | ||
2047 | static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
7ded5fe0 | 2048 | unsigned int fmt) |
7154b3e8 JS |
2049 | { |
2050 | struct snd_soc_codec *codec = codec_dai->codec; | |
2046f175 | 2051 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
7154b3e8 JS |
2052 | u8 old_format, format; |
2053 | ||
2054 | /* get format */ | |
efc8acff | 2055 | old_format = twl4030_read(codec, TWL4030_REG_VOICE_IF); |
7154b3e8 JS |
2056 | format = old_format; |
2057 | ||
2058 | /* set master/slave audio interface */ | |
2059 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
c264301c | 2060 | case SND_SOC_DAIFMT_CBM_CFM: |
7154b3e8 JS |
2061 | format &= ~(TWL4030_VIF_SLAVE_EN); |
2062 | break; | |
2063 | case SND_SOC_DAIFMT_CBS_CFS: | |
2064 | format |= TWL4030_VIF_SLAVE_EN; | |
2065 | break; | |
2066 | default: | |
2067 | return -EINVAL; | |
2068 | } | |
2069 | ||
2070 | /* clock inversion */ | |
2071 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2072 | case SND_SOC_DAIFMT_IB_NF: | |
2073 | format &= ~(TWL4030_VIF_FORMAT); | |
2074 | break; | |
2075 | case SND_SOC_DAIFMT_NB_IF: | |
2076 | format |= TWL4030_VIF_FORMAT; | |
2077 | break; | |
2078 | default: | |
2079 | return -EINVAL; | |
2080 | } | |
2081 | ||
2082 | if (format != old_format) { | |
2046f175 PU |
2083 | if (twl4030->codec_powered) { |
2084 | /* | |
2085 | * If the codec is powered, than we need to toggle the | |
2086 | * codec power. | |
2087 | */ | |
2088 | twl4030_codec_enable(codec, 0); | |
2089 | twl4030_write(codec, TWL4030_REG_VOICE_IF, format); | |
2090 | twl4030_codec_enable(codec, 1); | |
2091 | } else { | |
2092 | twl4030_write(codec, TWL4030_REG_VOICE_IF, format); | |
2093 | } | |
7154b3e8 JS |
2094 | } |
2095 | ||
2096 | return 0; | |
2097 | } | |
2098 | ||
68140443 LCM |
2099 | static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate) |
2100 | { | |
2101 | struct snd_soc_codec *codec = dai->codec; | |
efc8acff | 2102 | u8 reg = twl4030_read(codec, TWL4030_REG_VOICE_IF); |
68140443 LCM |
2103 | |
2104 | if (tristate) | |
2105 | reg |= TWL4030_VIF_TRI_EN; | |
2106 | else | |
2107 | reg &= ~TWL4030_VIF_TRI_EN; | |
2108 | ||
2109 | return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg); | |
2110 | } | |
2111 | ||
bbba9444 | 2112 | #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000) |
dcdeda4a | 2113 | #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) |
cc17557e | 2114 | |
85e7652d | 2115 | static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = { |
7220b9f4 PU |
2116 | .startup = twl4030_startup, |
2117 | .shutdown = twl4030_shutdown, | |
10d9e3d9 JS |
2118 | .hw_params = twl4030_hw_params, |
2119 | .set_sysclk = twl4030_set_dai_sysclk, | |
2120 | .set_fmt = twl4030_set_dai_fmt, | |
68140443 | 2121 | .set_tristate = twl4030_set_tristate, |
10d9e3d9 JS |
2122 | }; |
2123 | ||
85e7652d | 2124 | static const struct snd_soc_dai_ops twl4030_dai_voice_ops = { |
7154b3e8 | 2125 | .startup = twl4030_voice_startup, |
b7a755a8 | 2126 | .shutdown = twl4030_voice_shutdown, |
7154b3e8 JS |
2127 | .hw_params = twl4030_voice_hw_params, |
2128 | .set_sysclk = twl4030_voice_set_dai_sysclk, | |
2129 | .set_fmt = twl4030_voice_set_dai_fmt, | |
68140443 | 2130 | .set_tristate = twl4030_voice_set_tristate, |
7154b3e8 JS |
2131 | }; |
2132 | ||
f0fba2ad | 2133 | static struct snd_soc_dai_driver twl4030_dai[] = { |
7154b3e8 | 2134 | { |
f0fba2ad | 2135 | .name = "twl4030-hifi", |
cc17557e | 2136 | .playback = { |
b4852b79 | 2137 | .stream_name = "HiFi Playback", |
cc17557e | 2138 | .channels_min = 2, |
8a1f936a | 2139 | .channels_max = 4, |
31ad0f31 | 2140 | .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000, |
8819f65c PU |
2141 | .formats = TWL4030_FORMATS, |
2142 | .sig_bits = 24,}, | |
cc17557e | 2143 | .capture = { |
7f51e7d3 | 2144 | .stream_name = "HiFi Capture", |
cc17557e | 2145 | .channels_min = 2, |
8a1f936a | 2146 | .channels_max = 4, |
cc17557e | 2147 | .rates = TWL4030_RATES, |
8819f65c PU |
2148 | .formats = TWL4030_FORMATS, |
2149 | .sig_bits = 24,}, | |
f0fba2ad | 2150 | .ops = &twl4030_dai_hifi_ops, |
7154b3e8 JS |
2151 | }, |
2152 | { | |
f0fba2ad | 2153 | .name = "twl4030-voice", |
7154b3e8 | 2154 | .playback = { |
b4852b79 | 2155 | .stream_name = "Voice Playback", |
7154b3e8 JS |
2156 | .channels_min = 1, |
2157 | .channels_max = 1, | |
2158 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, | |
2159 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
2160 | .capture = { | |
7f51e7d3 | 2161 | .stream_name = "Voice Capture", |
7154b3e8 JS |
2162 | .channels_min = 1, |
2163 | .channels_max = 2, | |
2164 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000, | |
2165 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
2166 | .ops = &twl4030_dai_voice_ops, | |
2167 | }, | |
cc17557e | 2168 | }; |
cc17557e | 2169 | |
f0fba2ad | 2170 | static int twl4030_soc_probe(struct snd_soc_codec *codec) |
cc17557e | 2171 | { |
f0fba2ad | 2172 | struct twl4030_priv *twl4030; |
9da28c7b | 2173 | |
f2b1ce49 PU |
2174 | twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv), |
2175 | GFP_KERNEL); | |
04cc41a8 | 2176 | if (!twl4030) |
f0fba2ad | 2177 | return -ENOMEM; |
f0fba2ad LG |
2178 | snd_soc_codec_set_drvdata(codec, twl4030); |
2179 | /* Set the defaults, and power up the codec */ | |
57fe7251 | 2180 | twl4030->sysclk = twl4030_audio_get_mclk() / 1000; |
f0fba2ad LG |
2181 | |
2182 | twl4030_init_chip(codec); | |
cc17557e | 2183 | |
7a1fecf5 | 2184 | return 0; |
cc17557e SS |
2185 | } |
2186 | ||
f0fba2ad | 2187 | static int twl4030_soc_remove(struct snd_soc_codec *codec) |
cc17557e | 2188 | { |
5b3b0fa8 | 2189 | struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec); |
182f73f6 | 2190 | struct twl4030_codec_data *pdata = twl4030->pdata; |
5b3b0fa8 | 2191 | |
281ecd16 PU |
2192 | if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio)) |
2193 | gpio_free(pdata->hs_extmute_gpio); | |
2194 | ||
7a1fecf5 PU |
2195 | return 0; |
2196 | } | |
2197 | ||
f0fba2ad LG |
2198 | static struct snd_soc_codec_driver soc_codec_dev_twl4030 = { |
2199 | .probe = twl4030_soc_probe, | |
2200 | .remove = twl4030_soc_remove, | |
efc8acff | 2201 | .read = twl4030_read, |
f0fba2ad LG |
2202 | .write = twl4030_write, |
2203 | .set_bias_level = twl4030_set_bias_level, | |
eb3032f8 | 2204 | .idle_bias_off = true, |
f7c93f01 PU |
2205 | |
2206 | .controls = twl4030_snd_controls, | |
2207 | .num_controls = ARRAY_SIZE(twl4030_snd_controls), | |
2208 | .dapm_widgets = twl4030_dapm_widgets, | |
2209 | .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets), | |
2210 | .dapm_routes = intercon, | |
2211 | .num_dapm_routes = ARRAY_SIZE(intercon), | |
f0fba2ad LG |
2212 | }; |
2213 | ||
05c4c6f7 | 2214 | static int twl4030_codec_probe(struct platform_device *pdev) |
7a1fecf5 | 2215 | { |
f0fba2ad | 2216 | return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030, |
7ded5fe0 | 2217 | twl4030_dai, ARRAY_SIZE(twl4030_dai)); |
cc17557e SS |
2218 | } |
2219 | ||
05c4c6f7 | 2220 | static int twl4030_codec_remove(struct platform_device *pdev) |
cc17557e | 2221 | { |
f0fba2ad | 2222 | snd_soc_unregister_codec(&pdev->dev); |
cc17557e SS |
2223 | return 0; |
2224 | } | |
2225 | ||
f0fba2ad | 2226 | MODULE_ALIAS("platform:twl4030-codec"); |
7a1fecf5 PU |
2227 | |
2228 | static struct platform_driver twl4030_codec_driver = { | |
2229 | .probe = twl4030_codec_probe, | |
05c4c6f7 | 2230 | .remove = twl4030_codec_remove, |
7a1fecf5 | 2231 | .driver = { |
f0fba2ad | 2232 | .name = "twl4030-codec", |
7a1fecf5 | 2233 | }, |
cc17557e | 2234 | }; |
cc17557e | 2235 | |
5bbcc3c0 | 2236 | module_platform_driver(twl4030_codec_driver); |
64089b84 | 2237 | |
cc17557e SS |
2238 | MODULE_DESCRIPTION("ASoC TWL4030 codec driver"); |
2239 | MODULE_AUTHOR("Steve Sakoman"); | |
2240 | MODULE_LICENSE("GPL"); |