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ASoC: tlv320dac33: Clean up the hardware configuration code
[linux-block.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
c8bf93f0
PU		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/soc-dapm.h>
39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
45#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47#define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49#define NSAMPLE_MAX 5700
50
51#define LATENCY_TIME_MS 20
52
53static struct snd_soc_codec *tlv320dac33_codec;
54
55enum dac33_state {
56 DAC33_IDLE = 0,
57 DAC33_PREFILL,
58 DAC33_PLAYBACK,
59 DAC33_FLUSH,
60};
61
7427b4b9
PU		 62enum dac33_fifo_modes {
63 DAC33_FIFO_BYPASS = 0,
64 DAC33_FIFO_MODE1,
65 DAC33_FIFO_LAST_MODE,
66};
67
3a7aaed7
IK		 68#define DAC33_NUM_SUPPLIES 3
69static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
70 "AVDD",
71 "DVDD",
72 "IOVDD",
73};
74
c8bf93f0
PU		 75struct tlv320dac33_priv {
76 struct mutex mutex;
77 struct workqueue_struct *dac33_wq;
78 struct work_struct work;
79 struct snd_soc_codec codec;
3a7aaed7 80 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
c8bf93f0
PU		 81 int power_gpio;
82 int chip_power;
83 int irq;
84 unsigned int refclk;
85
86 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
87 unsigned int nsample_min; /* nsample should not be lower than
88 * this */
89 unsigned int nsample_max; /* nsample should not be higher than
90 * this */
7427b4b9 91 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0
PU		 92 unsigned int nsample; /* burst read amount from host */
93
94 enum dac33_state state;
95};
96
97static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
980x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
990x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1000x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1010x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1020x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1030x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1040x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1050x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1060x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1070x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1080x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1090x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1100x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1110x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1120x00, 0x00, /* 0x38 - 0x39 */
113/* Registers 0x3a - 0x3f are reserved */
114 0x00, 0x00, /* 0x3a - 0x3b */
1150x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
116
1170x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1180x00, 0x80, /* 0x44 - 0x45 */
119/* Registers 0x46 - 0x47 are reserved */
120 0x80, 0x80, /* 0x46 - 0x47 */
121
1220x80, 0x00, 0x00, /* 0x48 - 0x4a */
123/* Registers 0x4b - 0x7c are reserved */
124 0x00, /* 0x4b */
1250x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1260x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1270x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1280x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1290x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1300x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1310x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1320x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1330x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1340x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1350x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1360x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1370x00, /* 0x7c */
138
139 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
140};
141
142/* Register read and write */
143static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
144 unsigned reg)
145{
146 u8 *cache = codec->reg_cache;
147 if (reg >= DAC33_CACHEREGNUM)
148 return 0;
149
150 return cache[reg];
151}
152
153static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
154 u8 reg, u8 value)
155{
156 u8 *cache = codec->reg_cache;
157 if (reg >= DAC33_CACHEREGNUM)
158 return;
159
160 cache[reg] = value;
161}
162
163static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
164 u8 *value)
165{
166 struct tlv320dac33_priv *dac33 = codec->private_data;
167 int val;
168
169 *value = reg & 0xff;
170
171 /* If powered off, return the cached value */
172 if (dac33->chip_power) {
173 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
174 if (val < 0) {
175 dev_err(codec->dev, "Read failed (%d)\n", val);
176 value[0] = dac33_read_reg_cache(codec, reg);
177 } else {
178 value[0] = val;
179 dac33_write_reg_cache(codec, reg, val);
180 }
181 } else {
182 value[0] = dac33_read_reg_cache(codec, reg);
183 }
184
185 return 0;
186}
187
188static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
189 unsigned int value)
190{
191 struct tlv320dac33_priv *dac33 = codec->private_data;
192 u8 data[2];
193 int ret = 0;
194
195 /*
196 * data is
197 * D15..D8 dac33 register offset
198 * D7...D0 register data
199 */
200 data[0] = reg & 0xff;
201 data[1] = value & 0xff;
202
203 dac33_write_reg_cache(codec, data[0], data[1]);
204 if (dac33->chip_power) {
205 ret = codec->hw_write(codec->control_data, data, 2);
206 if (ret != 2)
207 dev_err(codec->dev, "Write failed (%d)\n", ret);
208 else
209 ret = 0;
210 }
211
212 return ret;
213}
214
215static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
216 unsigned int value)
217{
218 struct tlv320dac33_priv *dac33 = codec->private_data;
219 int ret;
220
221 mutex_lock(&dac33->mutex);
222 ret = dac33_write(codec, reg, value);
223 mutex_unlock(&dac33->mutex);
224
225 return ret;
226}
227
228#define DAC33_I2C_ADDR_AUTOINC 0x80
229static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
230 unsigned int value)
231{
232 struct tlv320dac33_priv *dac33 = codec->private_data;
233 u8 data[3];
234 int ret = 0;
235
236 /*
237 * data is
238 * D23..D16 dac33 register offset
239 * D15..D8 register data MSB
240 * D7...D0 register data LSB
241 */
242 data[0] = reg & 0xff;
243 data[1] = (value >> 8) & 0xff;
244 data[2] = value & 0xff;
245
246 dac33_write_reg_cache(codec, data[0], data[1]);
247 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
248
249 if (dac33->chip_power) {
250 /* We need to set autoincrement mode for 16 bit writes */
251 data[0] |= DAC33_I2C_ADDR_AUTOINC;
252 ret = codec->hw_write(codec->control_data, data, 3);
253 if (ret != 3)
254 dev_err(codec->dev, "Write failed (%d)\n", ret);
255 else
256 ret = 0;
257 }
258
259 return ret;
260}
261
262static void dac33_restore_regs(struct snd_soc_codec *codec)
263{
264 struct tlv320dac33_priv *dac33 = codec->private_data;
265 u8 *cache = codec->reg_cache;
266 u8 data[2];
267 int i, ret;
268
269 if (!dac33->chip_power)
270 return;
271
272 for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {
273 data[0] = i;
274 data[1] = cache[i];
275 /* Skip the read only registers */
276 if ((i >= DAC33_INT_OSC_STATUS &&
277 i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||
278 (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||
279 i == DAC33_DAC_STATUS_FLAGS ||
280 i == DAC33_SRC_EST_REF_CLK_RATIO_A ||
281 i == DAC33_SRC_EST_REF_CLK_RATIO_B)
282 continue;
283 ret = codec->hw_write(codec->control_data, data, 2);
284 if (ret != 2)
285 dev_err(codec->dev, "Write failed (%d)\n", ret);
286 }
287 for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {
288 data[0] = i;
289 data[1] = cache[i];
290 ret = codec->hw_write(codec->control_data, data, 2);
291 if (ret != 2)
292 dev_err(codec->dev, "Write failed (%d)\n", ret);
293 }
294 for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {
295 data[0] = i;
296 data[1] = cache[i];
297 ret = codec->hw_write(codec->control_data, data, 2);
298 if (ret != 2)
299 dev_err(codec->dev, "Write failed (%d)\n", ret);
300 }
301}
302
303static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
304{
305 u8 reg;
306
307 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
308 if (power)
309 reg |= DAC33_PDNALLB;
310 else
311 reg &= ~DAC33_PDNALLB;
312 dac33_write(codec, DAC33_PWR_CTRL, reg);
313}
314
3a7aaed7 315static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0
PU		 316{
317 struct tlv320dac33_priv *dac33 = codec->private_data;
3a7aaed7 318 int ret;
c8bf93f0
PU		 319
320 mutex_lock(&dac33->mutex);
321 if (power) {
3a7aaed7
IK		 322 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
323 dac33->supplies);
324 if (ret != 0) {
325 dev_err(codec->dev,
326 "Failed to enable supplies: %d\n", ret);
327 goto exit;
c8bf93f0 328 }
3a7aaed7
IK		 329
330 if (dac33->power_gpio >= 0)
331 gpio_set_value(dac33->power_gpio, 1);
332
333 dac33->chip_power = 1;
334
335 /* Restore registers */
336 dac33_restore_regs(codec);
337
c8bf93f0
PU		 338 dac33_soft_power(codec, 1);
339 } else {
340 dac33_soft_power(codec, 0);
3a7aaed7 341 if (dac33->power_gpio >= 0)
c8bf93f0 342 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 343
344 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
345 dac33->supplies);
346 if (ret != 0) {
347 dev_err(codec->dev,
348 "Failed to disable supplies: %d\n", ret);
349 goto exit;
c8bf93f0 350 }
3a7aaed7
IK		 351
352 dac33->chip_power = 0;
c8bf93f0 353 }
c8bf93f0 354
3a7aaed7
IK		 355exit:
356 mutex_unlock(&dac33->mutex);
357 return ret;
c8bf93f0
PU		 358}
359
360static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
361 struct snd_ctl_elem_value *ucontrol)
362{
363 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
364 struct tlv320dac33_priv *dac33 = codec->private_data;
365
366 ucontrol->value.integer.value[0] = dac33->nsample;
367
368 return 0;
369}
370
371static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
372 struct snd_ctl_elem_value *ucontrol)
373{
374 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
375 struct tlv320dac33_priv *dac33 = codec->private_data;
376 int ret = 0;
377
378 if (dac33->nsample == ucontrol->value.integer.value[0])
379 return 0;
380
381 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
382 ucontrol->value.integer.value[0] > dac33->nsample_max)
383 ret = -EINVAL;
384 else
385 dac33->nsample = ucontrol->value.integer.value[0];
386
387 return ret;
388}
389
7427b4b9 390static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 391 struct snd_ctl_elem_value *ucontrol)
392{
393 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
394 struct tlv320dac33_priv *dac33 = codec->private_data;
395
7427b4b9 396 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 397
398 return 0;
399}
400
7427b4b9 401static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 402 struct snd_ctl_elem_value *ucontrol)
403{
404 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
405 struct tlv320dac33_priv *dac33 = codec->private_data;
406 int ret = 0;
407
7427b4b9 408 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 409 return 0;
410 /* Do not allow changes while stream is running*/
411 if (codec->active)
412 return -EPERM;
413
414 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 415 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 416 ret = -EINVAL;
417 else
7427b4b9 418 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 419
420 return ret;
421}
422
7427b4b9
PU		 423/* Codec operation modes */
424static const char *dac33_fifo_mode_texts[] = {
425 "Bypass", "Mode 1"
426};
427
428static const struct soc_enum dac33_fifo_mode_enum =
429 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
430 dac33_fifo_mode_texts);
431
c8bf93f0
PU		 432/*
433 * DACL/R digital volume control:
434 * from 0 dB to -63.5 in 0.5 dB steps
435 * Need to be inverted later on:
436 * 0x00 == 0 dB
437 * 0x7f == -63.5 dB
438 */
439static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
440
441static const struct snd_kcontrol_new dac33_snd_controls[] = {
442 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
443 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
444 0, 0x7f, 1, dac_digivol_tlv),
445 SOC_DOUBLE_R("DAC Digital Playback Switch",
446 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
447 SOC_DOUBLE_R("Line to Line Out Volume",
448 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
449};
450
451static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
452 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
453 dac33_get_nsample, dac33_set_nsample),
7427b4b9
PU		 454 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
455 dac33_get_fifo_mode, dac33_set_fifo_mode),
c8bf93f0
PU		 456};
457
458/* Analog bypass */
459static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
460 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
461
462static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
463 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
464
465static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
466 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
467 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
468
469 SND_SOC_DAPM_INPUT("LINEL"),
470 SND_SOC_DAPM_INPUT("LINER"),
471
472 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
473 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
474
475 /* Analog bypass */
476 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
477 &dac33_dapm_abypassl_control),
478 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
479 &dac33_dapm_abypassr_control),
480
481 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
482 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
483 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
484 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
485};
486
487static const struct snd_soc_dapm_route audio_map[] = {
488 /* Analog bypass */
489 {"Analog Left Bypass", "Switch", "LINEL"},
490 {"Analog Right Bypass", "Switch", "LINER"},
491
492 {"Output Left Amp Power", NULL, "DACL"},
493 {"Output Right Amp Power", NULL, "DACR"},
494
495 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
496 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
497
498 /* output */
499 {"LEFT_LO", NULL, "Output Left Amp Power"},
500 {"RIGHT_LO", NULL, "Output Right Amp Power"},
501};
502
503static int dac33_add_widgets(struct snd_soc_codec *codec)
504{
505 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
506 ARRAY_SIZE(dac33_dapm_widgets));
507
508 /* set up audio path interconnects */
509 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 510
511 return 0;
512}
513
514static int dac33_set_bias_level(struct snd_soc_codec *codec,
515 enum snd_soc_bias_level level)
516{
3a7aaed7
IK		 517 int ret;
518
c8bf93f0
PU		 519 switch (level) {
520 case SND_SOC_BIAS_ON:
521 dac33_soft_power(codec, 1);
522 break;
523 case SND_SOC_BIAS_PREPARE:
524 break;
525 case SND_SOC_BIAS_STANDBY:
3a7aaed7
IK		 526 if (codec->bias_level == SND_SOC_BIAS_OFF) {
527 ret = dac33_hard_power(codec, 1);
528 if (ret != 0)
529 return ret;
530 }
531
c8bf93f0
PU		 532 dac33_soft_power(codec, 0);
533 break;
534 case SND_SOC_BIAS_OFF:
3a7aaed7
IK		 535 ret = dac33_hard_power(codec, 0);
536 if (ret != 0)
537 return ret;
538
c8bf93f0
PU		 539 break;
540 }
541 codec->bias_level = level;
542
543 return 0;
544}
545
d4f102d4
PU		 546static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
547{
548 struct snd_soc_codec *codec;
549
550 codec = &dac33->codec;
551
552 switch (dac33->fifo_mode) {
553 case DAC33_FIFO_MODE1:
554 dac33_write16(codec, DAC33_NSAMPLE_MSB,
555 DAC33_THRREG(dac33->nsample));
556 dac33_write16(codec, DAC33_PREFILL_MSB,
557 DAC33_THRREG(dac33->alarm_threshold));
558 break;
559 default:
560 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
561 dac33->fifo_mode);
562 break;
563 }
564}
565
566static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
567{
568 struct snd_soc_codec *codec;
569
570 codec = &dac33->codec;
571
572 switch (dac33->fifo_mode) {
573 case DAC33_FIFO_MODE1:
574 dac33_write16(codec, DAC33_NSAMPLE_MSB,
575 DAC33_THRREG(dac33->nsample));
576 break;
577 default:
578 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
579 dac33->fifo_mode);
580 break;
581 }
582}
583
c8bf93f0
PU		 584static void dac33_work(struct work_struct *work)
585{
586 struct snd_soc_codec *codec;
587 struct tlv320dac33_priv *dac33;
588 u8 reg;
589
590 dac33 = container_of(work, struct tlv320dac33_priv, work);
591 codec = &dac33->codec;
592
593 mutex_lock(&dac33->mutex);
594 switch (dac33->state) {
595 case DAC33_PREFILL:
596 dac33->state = DAC33_PLAYBACK;
d4f102d4 597 dac33_prefill_handler(dac33);
c8bf93f0
PU		 598 break;
599 case DAC33_PLAYBACK:
d4f102d4 600 dac33_playback_handler(dac33);
c8bf93f0
PU		 601 break;
602 case DAC33_IDLE:
603 break;
604 case DAC33_FLUSH:
605 dac33->state = DAC33_IDLE;
606 /* Mask all interrupts from dac33 */
607 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
608
609 /* flush fifo */
610 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
611 reg |= DAC33_FIFOFLUSH;
612 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
613 break;
614 }
615 mutex_unlock(&dac33->mutex);
616}
617
618static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
619{
620 struct snd_soc_codec *codec = dev;
621 struct tlv320dac33_priv *dac33 = codec->private_data;
622
623 queue_work(dac33->dac33_wq, &dac33->work);
624
625 return IRQ_HANDLED;
626}
627
628static void dac33_shutdown(struct snd_pcm_substream *substream,
629 struct snd_soc_dai *dai)
630{
631 struct snd_soc_pcm_runtime *rtd = substream->private_data;
632 struct snd_soc_device *socdev = rtd->socdev;
633 struct snd_soc_codec *codec = socdev->card->codec;
634 struct tlv320dac33_priv *dac33 = codec->private_data;
635 unsigned int pwr_ctrl;
636
637 /* Stop pending workqueue */
7427b4b9 638 if (dac33->fifo_mode)
c8bf93f0
PU		 639 cancel_work_sync(&dac33->work);
640
641 mutex_lock(&dac33->mutex);
642 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
643 pwr_ctrl &= ~(DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB);
644 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
645 mutex_unlock(&dac33->mutex);
646}
647
648static void dac33_oscwait(struct snd_soc_codec *codec)
649{
650 int timeout = 20;
651 u8 reg;
652
653 do {
654 msleep(1);
655 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
656 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
657 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
658 dev_err(codec->dev,
659 "internal oscillator calibration failed\n");
660}
661
662static int dac33_hw_params(struct snd_pcm_substream *substream,
663 struct snd_pcm_hw_params *params,
664 struct snd_soc_dai *dai)
665{
666 struct snd_soc_pcm_runtime *rtd = substream->private_data;
667 struct snd_soc_device *socdev = rtd->socdev;
668 struct snd_soc_codec *codec = socdev->card->codec;
669
670 /* Check parameters for validity */
671 switch (params_rate(params)) {
672 case 44100:
673 case 48000:
674 break;
675 default:
676 dev_err(codec->dev, "unsupported rate %d\n",
677 params_rate(params));
678 return -EINVAL;
679 }
680
681 switch (params_format(params)) {
682 case SNDRV_PCM_FORMAT_S16_LE:
683 break;
684 default:
685 dev_err(codec->dev, "unsupported format %d\n",
686 params_format(params));
687 return -EINVAL;
688 }
689
690 return 0;
691}
692
693#define CALC_OSCSET(rate, refclk) ( \
694 ((((rate * 10000) / refclk) * 4096) + 5000) / 10000)
695#define CALC_RATIOSET(rate, refclk) ( \
696 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
697
698/*
699 * tlv320dac33 is strict on the sequence of the register writes, if the register
700 * writes happens in different order, than dac33 might end up in unknown state.
701 * Use the known, working sequence of register writes to initialize the dac33.
702 */
703static int dac33_prepare_chip(struct snd_pcm_substream *substream)
704{
705 struct snd_soc_pcm_runtime *rtd = substream->private_data;
706 struct snd_soc_device *socdev = rtd->socdev;
707 struct snd_soc_codec *codec = socdev->card->codec;
708 struct tlv320dac33_priv *dac33 = codec->private_data;
709 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 710 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 711
712 switch (substream->runtime->rate) {
713 case 44100:
714 case 48000:
715 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
716 ratioset = CALC_RATIOSET(substream->runtime->rate,
717 dac33->refclk);
718 break;
719 default:
720 dev_err(codec->dev, "unsupported rate %d\n",
721 substream->runtime->rate);
722 return -EINVAL;
723 }
724
725
726 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
727 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
728 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
729 fifoctrl_a &= ~DAC33_WIDTH;
730 switch (substream->runtime->format) {
731 case SNDRV_PCM_FORMAT_S16_LE:
732 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
733 fifoctrl_a |= DAC33_WIDTH;
734 break;
735 default:
736 dev_err(codec->dev, "unsupported format %d\n",
737 substream->runtime->format);
738 return -EINVAL;
739 }
740
741 mutex_lock(&dac33->mutex);
742 dac33_soft_power(codec, 1);
743
744 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
745 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
746
747 /* Write registers 0x08 and 0x09 (MSB, LSB) */
748 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
749
750 /* calib time: 128 is a nice number ;) */
751 dac33_write(codec, DAC33_CALIB_TIME, 128);
752
753 /* adjustment treshold & step */
754 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
755 DAC33_ADJSTEP(1));
756
757 /* div=4 / gain=1 / div */
758 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
759
760 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
761 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
762 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
763
764 dac33_oscwait(codec);
765
7427b4b9 766 if (dac33->fifo_mode) {
aec242dc 767 /* Generic for all FIFO modes */
c8bf93f0
PU		 768 /* 50-51 : ASRC Control registers */
769 dac33_write(codec, DAC33_ASRC_CTRL_A, (1 << 4)); /* div=2 */
770 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
771
772 /* Write registers 0x34 and 0x35 (MSB, LSB) */
773 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
774
775 /* Set interrupts to high active */
776 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 777 } else {
aec242dc 778 /* FIFO bypass mode */
c8bf93f0
PU		 779 /* 50-51 : ASRC Control registers */
780 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
781 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
782 }
783
aec242dc
PU		 784 /* Interrupt behaviour configuration */
785 switch (dac33->fifo_mode) {
786 case DAC33_FIFO_MODE1:
787 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
788 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
789 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
790 break;
791 default:
792 /* in FIFO bypass mode, the interrupts are not used */
793 break;
794 }
795
796 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
797
798 switch (dac33->fifo_mode) {
799 case DAC33_FIFO_MODE1:
800 /*
801 * For mode1:
802 * Disable the FIFO bypass (Enable the use of FIFO)
803 * Select nSample mode
804 * BCLK is only running when data is needed by DAC33
805 */
c8bf93f0 806 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc
PU		 807 fifoctrl_a &= ~DAC33_FAUTO;
808 aictrl_b &= ~DAC33_BCLKON;
809 break;
810 default:
811 /*
812 * For FIFO bypass mode:
813 * Enable the FIFO bypass (Disable the FIFO use)
814 * Set the BCLK as continous
815 */
c8bf93f0 816 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 817 aictrl_b |= DAC33_BCLKON;
818 break;
819 }
c8bf93f0 820
aec242dc 821 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 822 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 823 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 824
aec242dc
PU		 825 switch (dac33->fifo_mode) {
826 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 827 /* 20: BCLK divide ratio */
828 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 3);
829
830 dac33_write16(codec, DAC33_ATHR_MSB,
831 DAC33_THRREG(dac33->alarm_threshold));
aec242dc
PU		 832 break;
833 default:
834 /* BYPASS mode */
c8bf93f0 835 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
aec242dc 836 break;
c8bf93f0
PU		 837 }
838
839 mutex_unlock(&dac33->mutex);
840
841 return 0;
842}
843
844static void dac33_calculate_times(struct snd_pcm_substream *substream)
845{
846 struct snd_soc_pcm_runtime *rtd = substream->private_data;
847 struct snd_soc_device *socdev = rtd->socdev;
848 struct snd_soc_codec *codec = socdev->card->codec;
849 struct tlv320dac33_priv *dac33 = codec->private_data;
850 unsigned int nsample_limit;
851
852 /* Number of samples (16bit, stereo) in one period */
853 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
854
855 /* Number of samples (16bit, stereo) in ALSA buffer */
856 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
857 /* Subtract one period from the total */
858 dac33->nsample_max -= dac33->nsample_min;
859
860 /* Number of samples for LATENCY_TIME_MS / 2 */
861 dac33->alarm_threshold = substream->runtime->rate /
862 (1000 / (LATENCY_TIME_MS / 2));
863
864 /* Find and fix up the lowest nsmaple limit */
865 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
866
867 if (dac33->nsample_min < nsample_limit)
868 dac33->nsample_min = nsample_limit;
869
870 if (dac33->nsample < dac33->nsample_min)
871 dac33->nsample = dac33->nsample_min;
872
873 /*
874 * Find and fix up the highest nsmaple limit
875 * In order to not overflow the DAC33 buffer substract the
876 * alarm_threshold value from the size of the DAC33 buffer
877 */
878 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
879
880 if (dac33->nsample_max > nsample_limit)
881 dac33->nsample_max = nsample_limit;
882
883 if (dac33->nsample > dac33->nsample_max)
884 dac33->nsample = dac33->nsample_max;
885}
886
887static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
888 struct snd_soc_dai *dai)
889{
890 dac33_calculate_times(substream);
891 dac33_prepare_chip(substream);
892
893 return 0;
894}
895
896static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
897 struct snd_soc_dai *dai)
898{
899 struct snd_soc_pcm_runtime *rtd = substream->private_data;
900 struct snd_soc_device *socdev = rtd->socdev;
901 struct snd_soc_codec *codec = socdev->card->codec;
902 struct tlv320dac33_priv *dac33 = codec->private_data;
903 int ret = 0;
904
905 switch (cmd) {
906 case SNDRV_PCM_TRIGGER_START:
907 case SNDRV_PCM_TRIGGER_RESUME:
908 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 909 if (dac33->fifo_mode) {
c8bf93f0
PU		 910 dac33->state = DAC33_PREFILL;
911 queue_work(dac33->dac33_wq, &dac33->work);
912 }
913 break;
914 case SNDRV_PCM_TRIGGER_STOP:
915 case SNDRV_PCM_TRIGGER_SUSPEND:
916 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 917 if (dac33->fifo_mode) {
c8bf93f0
PU		 918 dac33->state = DAC33_FLUSH;
919 queue_work(dac33->dac33_wq, &dac33->work);
920 }
921 break;
922 default:
923 ret = -EINVAL;
924 }
925
926 return ret;
927}
928
929static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
930 int clk_id, unsigned int freq, int dir)
931{
932 struct snd_soc_codec *codec = codec_dai->codec;
933 struct tlv320dac33_priv *dac33 = codec->private_data;
934 u8 ioc_reg, asrcb_reg;
935
936 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
937 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
938 switch (clk_id) {
939 case TLV320DAC33_MCLK:
940 ioc_reg |= DAC33_REFSEL;
941 asrcb_reg |= DAC33_SRCREFSEL;
942 break;
943 case TLV320DAC33_SLEEPCLK:
944 ioc_reg &= ~DAC33_REFSEL;
945 asrcb_reg &= ~DAC33_SRCREFSEL;
946 break;
947 default:
948 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
949 break;
950 }
951 dac33->refclk = freq;
952
953 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
954 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
955
956 return 0;
957}
958
959static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
960 unsigned int fmt)
961{
962 struct snd_soc_codec *codec = codec_dai->codec;
963 u8 aictrl_a, aictrl_b;
964
965 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
966 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
967 /* set master/slave audio interface */
968 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
969 case SND_SOC_DAIFMT_CBM_CFM:
970 /* Codec Master */
971 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
972 break;
973 case SND_SOC_DAIFMT_CBS_CFS:
974 /* Codec Slave */
975 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
976 break;
977 default:
978 return -EINVAL;
979 }
980
981 aictrl_a &= ~DAC33_AFMT_MASK;
982 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
983 case SND_SOC_DAIFMT_I2S:
984 aictrl_a |= DAC33_AFMT_I2S;
985 break;
986 case SND_SOC_DAIFMT_DSP_A:
987 aictrl_a |= DAC33_AFMT_DSP;
988 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
989 aictrl_b |= DAC33_DATA_DELAY(1); /* 1 bit delay */
990 break;
991 case SND_SOC_DAIFMT_DSP_B:
992 aictrl_a |= DAC33_AFMT_DSP;
993 aictrl_b &= ~DAC33_DATA_DELAY_MASK; /* No delay */
994 break;
995 case SND_SOC_DAIFMT_RIGHT_J:
996 aictrl_a |= DAC33_AFMT_RIGHT_J;
997 break;
998 case SND_SOC_DAIFMT_LEFT_J:
999 aictrl_a |= DAC33_AFMT_LEFT_J;
1000 break;
1001 default:
1002 dev_err(codec->dev, "Unsupported format (%u)\n",
1003 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1004 return -EINVAL;
1005 }
1006
1007 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1008 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1009
1010 return 0;
1011}
1012
1013static void dac33_init_chip(struct snd_soc_codec *codec)
1014{
1015 /* 44-46: DAC Control Registers */
1016 /* A : DAC sample rate Fsref/1.5 */
1017 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(1));
1018 /* B : DAC src=normal, not muted */
1019 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
1020 DAC33_DACSRCL_LEFT);
1021 /* C : (defaults) */
1022 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
1023
1024 /* 64-65 : L&R DAC power control
1025 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
1026 dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1027 dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1028
1029 /* 73 : volume soft stepping control,
1030 clock source = internal osc (?) */
1031 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
1032
1033 /* 66 : LOP/LOM Modes */
1034 dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
1035
1036 /* 68 : LOM inverted from LOP */
1037 dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
1038
1039 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
1040}
1041
1042static int dac33_soc_probe(struct platform_device *pdev)
1043{
1044 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1045 struct snd_soc_codec *codec;
1046 struct tlv320dac33_priv *dac33;
1047 int ret = 0;
1048
1049 BUG_ON(!tlv320dac33_codec);
1050
1051 codec = tlv320dac33_codec;
1052 socdev->card->codec = codec;
1053 dac33 = codec->private_data;
1054
1055 /* Power up the codec */
1056 dac33_hard_power(codec, 1);
1057 /* Set default configuration */
1058 dac33_init_chip(codec);
1059
1060 /* register pcms */
1061 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1062 if (ret < 0) {
1063 dev_err(codec->dev, "failed to create pcms\n");
1064 goto pcm_err;
1065 }
1066
1067 snd_soc_add_controls(codec, dac33_snd_controls,
1068 ARRAY_SIZE(dac33_snd_controls));
1069 /* Only add the nSample controls, if we have valid IRQ number */
1070 if (dac33->irq >= 0)
1071 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1072 ARRAY_SIZE(dac33_nsample_snd_controls));
1073
1074 dac33_add_widgets(codec);
1075
1076 /* power on device */
1077 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1078
3a7aaed7
IK		 1079 /* Bias level configuration has enabled regulator an extra time */
1080 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1081
c8bf93f0 1082 return 0;
fe3e78e0 1083
c8bf93f0
PU		 1084pcm_err:
1085 dac33_hard_power(codec, 0);
1086 return ret;
1087}
1088
1089static int dac33_soc_remove(struct platform_device *pdev)
1090{
1091 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1092 struct snd_soc_codec *codec = socdev->card->codec;
1093
1094 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1095
1096 snd_soc_free_pcms(socdev);
1097 snd_soc_dapm_free(socdev);
1098
1099 return 0;
1100}
1101
1102static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1103{
1104 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1105 struct snd_soc_codec *codec = socdev->card->codec;
1106
1107 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1108
1109 return 0;
1110}
1111
1112static int dac33_soc_resume(struct platform_device *pdev)
1113{
1114 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1115 struct snd_soc_codec *codec = socdev->card->codec;
1116
1117 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1118 dac33_set_bias_level(codec, codec->suspend_bias_level);
1119
1120 return 0;
1121}
1122
1123struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1124 .probe = dac33_soc_probe,
1125 .remove = dac33_soc_remove,
1126 .suspend = dac33_soc_suspend,
1127 .resume = dac33_soc_resume,
1128};
1129EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1130
1131#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1132 SNDRV_PCM_RATE_48000)
1133#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1134
1135static struct snd_soc_dai_ops dac33_dai_ops = {
1136 .shutdown = dac33_shutdown,
1137 .hw_params = dac33_hw_params,
1138 .prepare = dac33_pcm_prepare,
1139 .trigger = dac33_pcm_trigger,
1140 .set_sysclk = dac33_set_dai_sysclk,
1141 .set_fmt = dac33_set_dai_fmt,
1142};
1143
1144struct snd_soc_dai dac33_dai = {
1145 .name = "tlv320dac33",
1146 .playback = {
1147 .stream_name = "Playback",
1148 .channels_min = 2,
1149 .channels_max = 2,
1150 .rates = DAC33_RATES,
1151 .formats = DAC33_FORMATS,},
1152 .ops = &dac33_dai_ops,
1153};
1154EXPORT_SYMBOL_GPL(dac33_dai);
1155
1156static int dac33_i2c_probe(struct i2c_client *client,
1157 const struct i2c_device_id *id)
1158{
1159 struct tlv320dac33_platform_data *pdata;
1160 struct tlv320dac33_priv *dac33;
1161 struct snd_soc_codec *codec;
3a7aaed7 1162 int ret, i;
c8bf93f0
PU		 1163
1164 if (client->dev.platform_data == NULL) {
1165 dev_err(&client->dev, "Platform data not set\n");
1166 return -ENODEV;
1167 }
1168 pdata = client->dev.platform_data;
1169
1170 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1171 if (dac33 == NULL)
1172 return -ENOMEM;
1173
1174 codec = &dac33->codec;
1175 codec->private_data = dac33;
1176 codec->control_data = client;
1177
1178 mutex_init(&codec->mutex);
1179 mutex_init(&dac33->mutex);
1180 INIT_LIST_HEAD(&codec->dapm_widgets);
1181 INIT_LIST_HEAD(&codec->dapm_paths);
1182
1183 codec->name = "tlv320dac33";
1184 codec->owner = THIS_MODULE;
1185 codec->read = dac33_read_reg_cache;
1186 codec->write = dac33_write_locked;
1187 codec->hw_write = (hw_write_t) i2c_master_send;
1188 codec->bias_level = SND_SOC_BIAS_OFF;
1189 codec->set_bias_level = dac33_set_bias_level;
1190 codec->dai = &dac33_dai;
1191 codec->num_dai = 1;
1192 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1193 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1194 GFP_KERNEL);
1195 if (codec->reg_cache == NULL) {
1196 ret = -ENOMEM;
1197 goto error_reg;
1198 }
1199
1200 i2c_set_clientdata(client, dac33);
1201
1202 dac33->power_gpio = pdata->power_gpio;
1203 dac33->irq = client->irq;
1204 dac33->nsample = NSAMPLE_MAX;
1205 /* Disable FIFO use by default */
7427b4b9 1206 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0
PU		 1207
1208 tlv320dac33_codec = codec;
1209
1210 codec->dev = &client->dev;
1211 dac33_dai.dev = codec->dev;
1212
1213 /* Check if the reset GPIO number is valid and request it */
1214 if (dac33->power_gpio >= 0) {
1215 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1216 if (ret < 0) {
1217 dev_err(codec->dev,
1218 "Failed to request reset GPIO (%d)\n",
1219 dac33->power_gpio);
1220 snd_soc_unregister_dai(&dac33_dai);
1221 snd_soc_unregister_codec(codec);
1222 goto error_gpio;
1223 }
1224 gpio_direction_output(dac33->power_gpio, 0);
1225 } else {
1226 dac33->chip_power = 1;
1227 }
1228
1229 /* Check if the IRQ number is valid and request it */
1230 if (dac33->irq >= 0) {
1231 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1232 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1233 codec->name, codec);
1234 if (ret < 0) {
1235 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1236 dac33->irq, ret);
1237 dac33->irq = -1;
1238 }
1239 if (dac33->irq != -1) {
1240 /* Setup work queue */
74ea23aa
PU		 1241 dac33->dac33_wq =
1242 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1243 if (dac33->dac33_wq == NULL) {
1244 free_irq(dac33->irq, &dac33->codec);
1245 ret = -ENOMEM;
1246 goto error_wq;
1247 }
1248
1249 INIT_WORK(&dac33->work, dac33_work);
1250 }
1251 }
1252
3a7aaed7
IK		 1253 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1254 dac33->supplies[i].supply = dac33_supply_names[i];
1255
1256 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1257 dac33->supplies);
1258
1259 if (ret != 0) {
1260 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1261 goto err_get;
1262 }
1263
1264 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
1265 dac33->supplies);
1266 if (ret != 0) {
1267 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1268 goto err_enable;
1269 }
1270
c8bf93f0
PU		 1271 ret = snd_soc_register_codec(codec);
1272 if (ret != 0) {
1273 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1274 goto error_codec;
1275 }
1276
1277 ret = snd_soc_register_dai(&dac33_dai);
1278 if (ret != 0) {
1279 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1280 snd_soc_unregister_codec(codec);
1281 goto error_codec;
1282 }
1283
1284 /* Shut down the codec for now */
1285 dac33_hard_power(codec, 0);
1286
1287 return ret;
1288
1289error_codec:
3a7aaed7
IK		 1290 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1291err_enable:
1292 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1293err_get:
c8bf93f0
PU		 1294 if (dac33->irq >= 0) {
1295 free_irq(dac33->irq, &dac33->codec);
1296 destroy_workqueue(dac33->dac33_wq);
1297 }
1298error_wq:
1299 if (dac33->power_gpio >= 0)
1300 gpio_free(dac33->power_gpio);
1301error_gpio:
1302 kfree(codec->reg_cache);
1303error_reg:
1304 tlv320dac33_codec = NULL;
1305 kfree(dac33);
1306
1307 return ret;
1308}
1309
1310static int dac33_i2c_remove(struct i2c_client *client)
1311{
1312 struct tlv320dac33_priv *dac33;
1313
1314 dac33 = i2c_get_clientdata(client);
1315 dac33_hard_power(&dac33->codec, 0);
1316
1317 if (dac33->power_gpio >= 0)
1318 gpio_free(dac33->power_gpio);
1319 if (dac33->irq >= 0)
1320 free_irq(dac33->irq, &dac33->codec);
1321
3a7aaed7
IK		 1322 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1323
c8bf93f0
PU		 1324 destroy_workqueue(dac33->dac33_wq);
1325 snd_soc_unregister_dai(&dac33_dai);
1326 snd_soc_unregister_codec(&dac33->codec);
1327 kfree(dac33->codec.reg_cache);
1328 kfree(dac33);
1329 tlv320dac33_codec = NULL;
1330
1331 return 0;
1332}
1333
1334static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1335 {
1336 .name = "tlv320dac33",
1337 .driver_data = 0,
1338 },
1339 { },
1340};
1341
1342static struct i2c_driver tlv320dac33_i2c_driver = {
1343 .driver = {
1344 .name = "tlv320dac33",
1345 .owner = THIS_MODULE,
1346 },
1347 .probe = dac33_i2c_probe,
1348 .remove = __devexit_p(dac33_i2c_remove),
1349 .id_table = tlv320dac33_i2c_id,
1350};
1351
1352static int __init dac33_module_init(void)
1353{
1354 int r;
1355 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1356 if (r < 0) {
1357 printk(KERN_ERR "DAC33: driver registration failed\n");
1358 return r;
1359 }
1360 return 0;
1361}
1362module_init(dac33_module_init);
1363
1364static void __exit dac33_module_exit(void)
1365{
1366 i2c_del_driver(&tlv320dac33_i2c_driver);
1367}
1368module_exit(dac33_module_exit);
1369
1370
1371MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1372MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1373MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)