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ASoC: tlv320dac33: Change magic numbers used in Mode7
[linux-block.git] / sound / soc / codecs / tlv320dac33.c
CommitLineData
c8bf93f0
PU		 1/*
2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
3 *
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
5 *
6 * Copyright: (C) 2009 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/init.h>
27#include <linux/delay.h>
28#include <linux/pm.h>
29#include <linux/i2c.h>
30#include <linux/platform_device.h>
31#include <linux/interrupt.h>
32#include <linux/gpio.h>
3a7aaed7 33#include <linux/regulator/consumer.h>
c8bf93f0
PU		 34#include <sound/core.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/soc.h>
38#include <sound/soc-dapm.h>
39#include <sound/initval.h>
40#include <sound/tlv.h>
41
42#include <sound/tlv320dac33-plat.h>
43#include "tlv320dac33.h"
44
45#define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
46 * 6144 stereo */
47#define DAC33_BUFFER_SIZE_SAMPLES 6144
48
49#define NSAMPLE_MAX 5700
50
51#define LATENCY_TIME_MS 20
52
4260393e
PU		 53#define MODE7_LTHR 10
54#define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
55
c8bf93f0
PU		 56static struct snd_soc_codec *tlv320dac33_codec;
57
58enum dac33_state {
59 DAC33_IDLE = 0,
60 DAC33_PREFILL,
61 DAC33_PLAYBACK,
62 DAC33_FLUSH,
63};
64
7427b4b9
PU		 65enum dac33_fifo_modes {
66 DAC33_FIFO_BYPASS = 0,
67 DAC33_FIFO_MODE1,
28e05d98 68 DAC33_FIFO_MODE7,
7427b4b9
PU		 69 DAC33_FIFO_LAST_MODE,
70};
71
3a7aaed7
IK		 72#define DAC33_NUM_SUPPLIES 3
73static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
74 "AVDD",
75 "DVDD",
76 "IOVDD",
77};
78
c8bf93f0
PU		 79struct tlv320dac33_priv {
80 struct mutex mutex;
81 struct workqueue_struct *dac33_wq;
82 struct work_struct work;
83 struct snd_soc_codec codec;
3a7aaed7 84 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
c8bf93f0
PU		 85 int power_gpio;
86 int chip_power;
87 int irq;
88 unsigned int refclk;
89
90 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
91 unsigned int nsample_min; /* nsample should not be lower than
92 * this */
93 unsigned int nsample_max; /* nsample should not be higher than
94 * this */
7427b4b9 95 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
c8bf93f0 96 unsigned int nsample; /* burst read amount from host */
6aceabb4 97 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
c8bf93f0 98
eeb309a8
PU		 99 int keep_bclk; /* Keep the BCLK continuously running
100 * in FIFO modes */
c8bf93f0
PU		 101 enum dac33_state state;
102};
103
104static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
1050x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
1060x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
1070x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
1080x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
1090x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
1100x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
1110x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
1120x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
1130x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
1140x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
1150x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
1160x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
1170x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
1180x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
1190x00, 0x00, /* 0x38 - 0x39 */
120/* Registers 0x3a - 0x3f are reserved */
121 0x00, 0x00, /* 0x3a - 0x3b */
1220x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
123
1240x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
1250x00, 0x80, /* 0x44 - 0x45 */
126/* Registers 0x46 - 0x47 are reserved */
127 0x80, 0x80, /* 0x46 - 0x47 */
128
1290x80, 0x00, 0x00, /* 0x48 - 0x4a */
130/* Registers 0x4b - 0x7c are reserved */
131 0x00, /* 0x4b */
1320x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
1330x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
1340x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
1350x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
1360x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
1370x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
1380x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
1390x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
1400x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
1410x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
1420x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
1430x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
1440x00, /* 0x7c */
145
146 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
147};
148
149/* Register read and write */
150static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
151 unsigned reg)
152{
153 u8 *cache = codec->reg_cache;
154 if (reg >= DAC33_CACHEREGNUM)
155 return 0;
156
157 return cache[reg];
158}
159
160static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
161 u8 reg, u8 value)
162{
163 u8 *cache = codec->reg_cache;
164 if (reg >= DAC33_CACHEREGNUM)
165 return;
166
167 cache[reg] = value;
168}
169
170static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
171 u8 *value)
172{
b2c812e2 173 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 174 int val;
175
176 *value = reg & 0xff;
177
178 /* If powered off, return the cached value */
179 if (dac33->chip_power) {
180 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
181 if (val < 0) {
182 dev_err(codec->dev, "Read failed (%d)\n", val);
183 value[0] = dac33_read_reg_cache(codec, reg);
184 } else {
185 value[0] = val;
186 dac33_write_reg_cache(codec, reg, val);
187 }
188 } else {
189 value[0] = dac33_read_reg_cache(codec, reg);
190 }
191
192 return 0;
193}
194
195static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
196 unsigned int value)
197{
b2c812e2 198 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 199 u8 data[2];
200 int ret = 0;
201
202 /*
203 * data is
204 * D15..D8 dac33 register offset
205 * D7...D0 register data
206 */
207 data[0] = reg & 0xff;
208 data[1] = value & 0xff;
209
210 dac33_write_reg_cache(codec, data[0], data[1]);
211 if (dac33->chip_power) {
212 ret = codec->hw_write(codec->control_data, data, 2);
213 if (ret != 2)
214 dev_err(codec->dev, "Write failed (%d)\n", ret);
215 else
216 ret = 0;
217 }
218
219 return ret;
220}
221
222static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
223 unsigned int value)
224{
b2c812e2 225 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 226 int ret;
227
228 mutex_lock(&dac33->mutex);
229 ret = dac33_write(codec, reg, value);
230 mutex_unlock(&dac33->mutex);
231
232 return ret;
233}
234
235#define DAC33_I2C_ADDR_AUTOINC 0x80
236static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
237 unsigned int value)
238{
b2c812e2 239 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 240 u8 data[3];
241 int ret = 0;
242
243 /*
244 * data is
245 * D23..D16 dac33 register offset
246 * D15..D8 register data MSB
247 * D7...D0 register data LSB
248 */
249 data[0] = reg & 0xff;
250 data[1] = (value >> 8) & 0xff;
251 data[2] = value & 0xff;
252
253 dac33_write_reg_cache(codec, data[0], data[1]);
254 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
255
256 if (dac33->chip_power) {
257 /* We need to set autoincrement mode for 16 bit writes */
258 data[0] |= DAC33_I2C_ADDR_AUTOINC;
259 ret = codec->hw_write(codec->control_data, data, 3);
260 if (ret != 3)
261 dev_err(codec->dev, "Write failed (%d)\n", ret);
262 else
263 ret = 0;
264 }
265
266 return ret;
267}
268
269static void dac33_restore_regs(struct snd_soc_codec *codec)
270{
b2c812e2 271 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 272 u8 *cache = codec->reg_cache;
273 u8 data[2];
274 int i, ret;
275
276 if (!dac33->chip_power)
277 return;
278
279 for (i = DAC33_PWR_CTRL; i <= DAC33_INTP_CTRL_B; i++) {
280 data[0] = i;
281 data[1] = cache[i];
282 /* Skip the read only registers */
283 if ((i >= DAC33_INT_OSC_STATUS &&
284 i <= DAC33_INT_OSC_FREQ_RAT_READ_B) ||
285 (i >= DAC33_FIFO_WPTR_MSB && i <= DAC33_FIFO_IRQ_FLAG) ||
286 i == DAC33_DAC_STATUS_FLAGS ||
287 i == DAC33_SRC_EST_REF_CLK_RATIO_A ||
288 i == DAC33_SRC_EST_REF_CLK_RATIO_B)
289 continue;
290 ret = codec->hw_write(codec->control_data, data, 2);
291 if (ret != 2)
292 dev_err(codec->dev, "Write failed (%d)\n", ret);
293 }
294 for (i = DAC33_LDAC_PWR_CTRL; i <= DAC33_LINEL_TO_LLO_VOL; i++) {
295 data[0] = i;
296 data[1] = cache[i];
297 ret = codec->hw_write(codec->control_data, data, 2);
298 if (ret != 2)
299 dev_err(codec->dev, "Write failed (%d)\n", ret);
300 }
301 for (i = DAC33_LINER_TO_RLO_VOL; i <= DAC33_OSC_TRIM; i++) {
302 data[0] = i;
303 data[1] = cache[i];
304 ret = codec->hw_write(codec->control_data, data, 2);
305 if (ret != 2)
306 dev_err(codec->dev, "Write failed (%d)\n", ret);
307 }
308}
309
310static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
311{
312 u8 reg;
313
314 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
315 if (power)
316 reg |= DAC33_PDNALLB;
317 else
c3746a07
PU		 318 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
319 DAC33_DACRPDNB | DAC33_DACLPDNB);
c8bf93f0
PU		 320 dac33_write(codec, DAC33_PWR_CTRL, reg);
321}
322
3a7aaed7 323static int dac33_hard_power(struct snd_soc_codec *codec, int power)
c8bf93f0 324{
b2c812e2 325 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
3a7aaed7 326 int ret;
c8bf93f0
PU		 327
328 mutex_lock(&dac33->mutex);
329 if (power) {
3a7aaed7
IK		 330 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
331 dac33->supplies);
332 if (ret != 0) {
333 dev_err(codec->dev,
334 "Failed to enable supplies: %d\n", ret);
335 goto exit;
c8bf93f0 336 }
3a7aaed7
IK		 337
338 if (dac33->power_gpio >= 0)
339 gpio_set_value(dac33->power_gpio, 1);
340
341 dac33->chip_power = 1;
342
343 /* Restore registers */
344 dac33_restore_regs(codec);
345
c8bf93f0
PU		 346 dac33_soft_power(codec, 1);
347 } else {
348 dac33_soft_power(codec, 0);
3a7aaed7 349 if (dac33->power_gpio >= 0)
c8bf93f0 350 gpio_set_value(dac33->power_gpio, 0);
3a7aaed7
IK		 351
352 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
353 dac33->supplies);
354 if (ret != 0) {
355 dev_err(codec->dev,
356 "Failed to disable supplies: %d\n", ret);
357 goto exit;
c8bf93f0 358 }
3a7aaed7
IK		 359
360 dac33->chip_power = 0;
c8bf93f0 361 }
c8bf93f0 362
3a7aaed7
IK		 363exit:
364 mutex_unlock(&dac33->mutex);
365 return ret;
c8bf93f0
PU		 366}
367
368static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
369 struct snd_ctl_elem_value *ucontrol)
370{
371 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 372 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 373
374 ucontrol->value.integer.value[0] = dac33->nsample;
375
376 return 0;
377}
378
379static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
380 struct snd_ctl_elem_value *ucontrol)
381{
382 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 383 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 384 int ret = 0;
385
386 if (dac33->nsample == ucontrol->value.integer.value[0])
387 return 0;
388
389 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
390 ucontrol->value.integer.value[0] > dac33->nsample_max)
391 ret = -EINVAL;
392 else
393 dac33->nsample = ucontrol->value.integer.value[0];
394
395 return ret;
396}
397
7427b4b9 398static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 399 struct snd_ctl_elem_value *ucontrol)
400{
401 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 402 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 403
7427b4b9 404 ucontrol->value.integer.value[0] = dac33->fifo_mode;
c8bf93f0
PU		 405
406 return 0;
407}
408
7427b4b9 409static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
c8bf93f0
PU		 410 struct snd_ctl_elem_value *ucontrol)
411{
412 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 413 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 414 int ret = 0;
415
7427b4b9 416 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
c8bf93f0
PU		 417 return 0;
418 /* Do not allow changes while stream is running*/
419 if (codec->active)
420 return -EPERM;
421
422 if (ucontrol->value.integer.value[0] < 0 ||
7427b4b9 423 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
c8bf93f0
PU		 424 ret = -EINVAL;
425 else
7427b4b9 426 dac33->fifo_mode = ucontrol->value.integer.value[0];
c8bf93f0
PU		 427
428 return ret;
429}
430
7427b4b9
PU		 431/* Codec operation modes */
432static const char *dac33_fifo_mode_texts[] = {
28e05d98 433 "Bypass", "Mode 1", "Mode 7"
7427b4b9
PU		 434};
435
436static const struct soc_enum dac33_fifo_mode_enum =
437 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
438 dac33_fifo_mode_texts);
439
c8bf93f0
PU		 440/*
441 * DACL/R digital volume control:
442 * from 0 dB to -63.5 in 0.5 dB steps
443 * Need to be inverted later on:
444 * 0x00 == 0 dB
445 * 0x7f == -63.5 dB
446 */
447static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
448
449static const struct snd_kcontrol_new dac33_snd_controls[] = {
450 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
451 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
452 0, 0x7f, 1, dac_digivol_tlv),
453 SOC_DOUBLE_R("DAC Digital Playback Switch",
454 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
455 SOC_DOUBLE_R("Line to Line Out Volume",
456 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
457};
458
459static const struct snd_kcontrol_new dac33_nsample_snd_controls[] = {
460 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
461 dac33_get_nsample, dac33_set_nsample),
7427b4b9
PU		 462 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
463 dac33_get_fifo_mode, dac33_set_fifo_mode),
c8bf93f0
PU		 464};
465
466/* Analog bypass */
467static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
468 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
469
470static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
471 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
472
473static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
474 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
475 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
476
477 SND_SOC_DAPM_INPUT("LINEL"),
478 SND_SOC_DAPM_INPUT("LINER"),
479
480 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
481 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
482
483 /* Analog bypass */
484 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
485 &dac33_dapm_abypassl_control),
486 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
487 &dac33_dapm_abypassr_control),
488
489 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
490 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
491 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
492 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
493};
494
495static const struct snd_soc_dapm_route audio_map[] = {
496 /* Analog bypass */
497 {"Analog Left Bypass", "Switch", "LINEL"},
498 {"Analog Right Bypass", "Switch", "LINER"},
499
500 {"Output Left Amp Power", NULL, "DACL"},
501 {"Output Right Amp Power", NULL, "DACR"},
502
503 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
504 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
505
506 /* output */
507 {"LEFT_LO", NULL, "Output Left Amp Power"},
508 {"RIGHT_LO", NULL, "Output Right Amp Power"},
509};
510
511static int dac33_add_widgets(struct snd_soc_codec *codec)
512{
513 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
514 ARRAY_SIZE(dac33_dapm_widgets));
515
516 /* set up audio path interconnects */
517 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
c8bf93f0
PU		 518
519 return 0;
520}
521
522static int dac33_set_bias_level(struct snd_soc_codec *codec,
523 enum snd_soc_bias_level level)
524{
3a7aaed7
IK		 525 int ret;
526
c8bf93f0
PU		 527 switch (level) {
528 case SND_SOC_BIAS_ON:
529 dac33_soft_power(codec, 1);
530 break;
531 case SND_SOC_BIAS_PREPARE:
532 break;
533 case SND_SOC_BIAS_STANDBY:
3a7aaed7
IK		 534 if (codec->bias_level == SND_SOC_BIAS_OFF) {
535 ret = dac33_hard_power(codec, 1);
536 if (ret != 0)
537 return ret;
538 }
539
c8bf93f0
PU		 540 dac33_soft_power(codec, 0);
541 break;
542 case SND_SOC_BIAS_OFF:
3a7aaed7
IK		 543 ret = dac33_hard_power(codec, 0);
544 if (ret != 0)
545 return ret;
546
c8bf93f0
PU		 547 break;
548 }
549 codec->bias_level = level;
550
551 return 0;
552}
553
d4f102d4
PU		 554static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
555{
556 struct snd_soc_codec *codec;
557
558 codec = &dac33->codec;
559
560 switch (dac33->fifo_mode) {
561 case DAC33_FIFO_MODE1:
562 dac33_write16(codec, DAC33_NSAMPLE_MSB,
f4d59328 563 DAC33_THRREG(dac33->nsample + dac33->alarm_threshold));
d4f102d4
PU		 564 dac33_write16(codec, DAC33_PREFILL_MSB,
565 DAC33_THRREG(dac33->alarm_threshold));
f4d59328
PU		 566 /* Enable Alarm Threshold IRQ with a delay */
567 udelay(SAMPLES_TO_US(dac33->burst_rate,
568 dac33->alarm_threshold));
569 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
d4f102d4 570 break;
28e05d98
PU		 571 case DAC33_FIFO_MODE7:
572 dac33_write16(codec, DAC33_PREFILL_MSB,
4260393e 573 DAC33_THRREG(MODE7_LTHR));
28e05d98 574 break;
d4f102d4
PU		 575 default:
576 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
577 dac33->fifo_mode);
578 break;
579 }
580}
581
582static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
583{
584 struct snd_soc_codec *codec;
585
586 codec = &dac33->codec;
587
588 switch (dac33->fifo_mode) {
589 case DAC33_FIFO_MODE1:
590 dac33_write16(codec, DAC33_NSAMPLE_MSB,
591 DAC33_THRREG(dac33->nsample));
592 break;
28e05d98
PU		 593 case DAC33_FIFO_MODE7:
594 /* At the moment we are not using interrupts in mode7 */
595 break;
d4f102d4
PU		 596 default:
597 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
598 dac33->fifo_mode);
599 break;
600 }
601}
602
c8bf93f0
PU		 603static void dac33_work(struct work_struct *work)
604{
605 struct snd_soc_codec *codec;
606 struct tlv320dac33_priv *dac33;
607 u8 reg;
608
609 dac33 = container_of(work, struct tlv320dac33_priv, work);
610 codec = &dac33->codec;
611
612 mutex_lock(&dac33->mutex);
613 switch (dac33->state) {
614 case DAC33_PREFILL:
615 dac33->state = DAC33_PLAYBACK;
d4f102d4 616 dac33_prefill_handler(dac33);
c8bf93f0
PU		 617 break;
618 case DAC33_PLAYBACK:
d4f102d4 619 dac33_playback_handler(dac33);
c8bf93f0
PU		 620 break;
621 case DAC33_IDLE:
622 break;
623 case DAC33_FLUSH:
624 dac33->state = DAC33_IDLE;
625 /* Mask all interrupts from dac33 */
626 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
627
628 /* flush fifo */
629 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
630 reg |= DAC33_FIFOFLUSH;
631 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
632 break;
633 }
634 mutex_unlock(&dac33->mutex);
635}
636
637static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
638{
639 struct snd_soc_codec *codec = dev;
b2c812e2 640 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 641
642 queue_work(dac33->dac33_wq, &dac33->work);
643
644 return IRQ_HANDLED;
645}
646
c8bf93f0
PU		 647static void dac33_oscwait(struct snd_soc_codec *codec)
648{
649 int timeout = 20;
650 u8 reg;
651
652 do {
653 msleep(1);
654 dac33_read(codec, DAC33_INT_OSC_STATUS, &reg);
655 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
656 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
657 dev_err(codec->dev,
658 "internal oscillator calibration failed\n");
659}
660
661static int dac33_hw_params(struct snd_pcm_substream *substream,
662 struct snd_pcm_hw_params *params,
663 struct snd_soc_dai *dai)
664{
665 struct snd_soc_pcm_runtime *rtd = substream->private_data;
666 struct snd_soc_device *socdev = rtd->socdev;
667 struct snd_soc_codec *codec = socdev->card->codec;
668
669 /* Check parameters for validity */
670 switch (params_rate(params)) {
671 case 44100:
672 case 48000:
673 break;
674 default:
675 dev_err(codec->dev, "unsupported rate %d\n",
676 params_rate(params));
677 return -EINVAL;
678 }
679
680 switch (params_format(params)) {
681 case SNDRV_PCM_FORMAT_S16_LE:
682 break;
683 default:
684 dev_err(codec->dev, "unsupported format %d\n",
685 params_format(params));
686 return -EINVAL;
687 }
688
689 return 0;
690}
691
692#define CALC_OSCSET(rate, refclk) ( \
7833ae0e 693 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
c8bf93f0
PU		 694#define CALC_RATIOSET(rate, refclk) ( \
695 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
696
697/*
698 * tlv320dac33 is strict on the sequence of the register writes, if the register
699 * writes happens in different order, than dac33 might end up in unknown state.
700 * Use the known, working sequence of register writes to initialize the dac33.
701 */
702static int dac33_prepare_chip(struct snd_pcm_substream *substream)
703{
704 struct snd_soc_pcm_runtime *rtd = substream->private_data;
705 struct snd_soc_device *socdev = rtd->socdev;
706 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 707 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0 708 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
aec242dc 709 u8 aictrl_a, aictrl_b, fifoctrl_a;
c8bf93f0
PU		 710
711 switch (substream->runtime->rate) {
712 case 44100:
713 case 48000:
714 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
715 ratioset = CALC_RATIOSET(substream->runtime->rate,
716 dac33->refclk);
717 break;
718 default:
719 dev_err(codec->dev, "unsupported rate %d\n",
720 substream->runtime->rate);
721 return -EINVAL;
722 }
723
724
725 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
726 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
e5e878c1 727 /* Read FIFO control A, and clear FIFO flush bit */
c8bf93f0 728 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
e5e878c1
PU		 729 fifoctrl_a &= ~DAC33_FIFOFLUSH;
730
c8bf93f0
PU		 731 fifoctrl_a &= ~DAC33_WIDTH;
732 switch (substream->runtime->format) {
733 case SNDRV_PCM_FORMAT_S16_LE:
734 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
735 fifoctrl_a |= DAC33_WIDTH;
736 break;
737 default:
738 dev_err(codec->dev, "unsupported format %d\n",
739 substream->runtime->format);
740 return -EINVAL;
741 }
742
743 mutex_lock(&dac33->mutex);
c3746a07 744 dac33_soft_power(codec, 0);
c8bf93f0
PU		 745 dac33_soft_power(codec, 1);
746
747 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
748 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
749
750 /* Write registers 0x08 and 0x09 (MSB, LSB) */
751 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
752
753 /* calib time: 128 is a nice number ;) */
754 dac33_write(codec, DAC33_CALIB_TIME, 128);
755
756 /* adjustment treshold & step */
757 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
758 DAC33_ADJSTEP(1));
759
760 /* div=4 / gain=1 / div */
761 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
762
763 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
764 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
765 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
766
767 dac33_oscwait(codec);
768
7427b4b9 769 if (dac33->fifo_mode) {
aec242dc 770 /* Generic for all FIFO modes */
c8bf93f0 771 /* 50-51 : ASRC Control registers */
fdb6b1e1 772 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
c8bf93f0
PU		 773 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
774
775 /* Write registers 0x34 and 0x35 (MSB, LSB) */
776 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
777
778 /* Set interrupts to high active */
779 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
c8bf93f0 780 } else {
aec242dc 781 /* FIFO bypass mode */
c8bf93f0
PU		 782 /* 50-51 : ASRC Control registers */
783 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
784 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
785 }
786
aec242dc
PU		 787 /* Interrupt behaviour configuration */
788 switch (dac33->fifo_mode) {
789 case DAC33_FIFO_MODE1:
790 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
791 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
aec242dc 792 break;
28e05d98
PU		 793 case DAC33_FIFO_MODE7:
794 /* Disable all interrupts */
795 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
796 break;
aec242dc
PU		 797 default:
798 /* in FIFO bypass mode, the interrupts are not used */
799 break;
800 }
801
802 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
803
804 switch (dac33->fifo_mode) {
805 case DAC33_FIFO_MODE1:
806 /*
807 * For mode1:
808 * Disable the FIFO bypass (Enable the use of FIFO)
809 * Select nSample mode
810 * BCLK is only running when data is needed by DAC33
811 */
c8bf93f0 812 fifoctrl_a &= ~DAC33_FBYPAS;
aec242dc 813 fifoctrl_a &= ~DAC33_FAUTO;
eeb309a8
PU		 814 if (dac33->keep_bclk)
815 aictrl_b |= DAC33_BCLKON;
816 else
817 aictrl_b &= ~DAC33_BCLKON;
aec242dc 818 break;
28e05d98
PU		 819 case DAC33_FIFO_MODE7:
820 /*
821 * For mode1:
822 * Disable the FIFO bypass (Enable the use of FIFO)
823 * Select Threshold mode
824 * BCLK is only running when data is needed by DAC33
825 */
826 fifoctrl_a &= ~DAC33_FBYPAS;
827 fifoctrl_a |= DAC33_FAUTO;
eeb309a8
PU		 828 if (dac33->keep_bclk)
829 aictrl_b |= DAC33_BCLKON;
830 else
831 aictrl_b &= ~DAC33_BCLKON;
28e05d98 832 break;
aec242dc
PU		 833 default:
834 /*
835 * For FIFO bypass mode:
836 * Enable the FIFO bypass (Disable the FIFO use)
837 * Set the BCLK as continous
838 */
c8bf93f0 839 fifoctrl_a |= DAC33_FBYPAS;
aec242dc
PU		 840 aictrl_b |= DAC33_BCLKON;
841 break;
842 }
c8bf93f0 843
aec242dc 844 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
c8bf93f0 845 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
aec242dc 846 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
c8bf93f0 847
6aceabb4
PU		 848 /*
849 * BCLK divide ratio
850 * 0: 1.5
851 * 1: 1
852 * 2: 2
853 * ...
854 * 254: 254
855 * 255: 255
856 */
6cd6cede 857 if (dac33->fifo_mode)
6aceabb4
PU		 858 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
859 dac33->burst_bclkdiv);
6cd6cede
PU		 860 else
861 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
c8bf93f0 862
6cd6cede
PU		 863 switch (dac33->fifo_mode) {
864 case DAC33_FIFO_MODE1:
c8bf93f0
PU		 865 dac33_write16(codec, DAC33_ATHR_MSB,
866 DAC33_THRREG(dac33->alarm_threshold));
aec242dc 867 break;
28e05d98
PU		 868 case DAC33_FIFO_MODE7:
869 /*
870 * Configure the threshold levels, and leave 10 sample space
871 * at the bottom, and also at the top of the FIFO
872 */
4260393e
PU		 873 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(MODE7_UTHR));
874 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
28e05d98 875 break;
aec242dc 876 default:
aec242dc 877 break;
c8bf93f0
PU		 878 }
879
880 mutex_unlock(&dac33->mutex);
881
882 return 0;
883}
884
885static void dac33_calculate_times(struct snd_pcm_substream *substream)
886{
887 struct snd_soc_pcm_runtime *rtd = substream->private_data;
888 struct snd_soc_device *socdev = rtd->socdev;
889 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 890 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 891 unsigned int nsample_limit;
892
55abb59c
PU		 893 /* In bypass mode we don't need to calculate */
894 if (!dac33->fifo_mode)
895 return;
896
c8bf93f0
PU		 897 /* Number of samples (16bit, stereo) in one period */
898 dac33->nsample_min = snd_pcm_lib_period_bytes(substream) / 4;
899
900 /* Number of samples (16bit, stereo) in ALSA buffer */
901 dac33->nsample_max = snd_pcm_lib_buffer_bytes(substream) / 4;
902 /* Subtract one period from the total */
903 dac33->nsample_max -= dac33->nsample_min;
904
905 /* Number of samples for LATENCY_TIME_MS / 2 */
906 dac33->alarm_threshold = substream->runtime->rate /
907 (1000 / (LATENCY_TIME_MS / 2));
908
909 /* Find and fix up the lowest nsmaple limit */
910 nsample_limit = substream->runtime->rate / (1000 / LATENCY_TIME_MS);
911
912 if (dac33->nsample_min < nsample_limit)
913 dac33->nsample_min = nsample_limit;
914
915 if (dac33->nsample < dac33->nsample_min)
916 dac33->nsample = dac33->nsample_min;
917
918 /*
919 * Find and fix up the highest nsmaple limit
920 * In order to not overflow the DAC33 buffer substract the
921 * alarm_threshold value from the size of the DAC33 buffer
922 */
923 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES - dac33->alarm_threshold;
924
925 if (dac33->nsample_max > nsample_limit)
926 dac33->nsample_max = nsample_limit;
927
928 if (dac33->nsample > dac33->nsample_max)
929 dac33->nsample = dac33->nsample_max;
930}
931
932static int dac33_pcm_prepare(struct snd_pcm_substream *substream,
933 struct snd_soc_dai *dai)
934{
935 dac33_calculate_times(substream);
936 dac33_prepare_chip(substream);
937
938 return 0;
939}
940
941static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
942 struct snd_soc_dai *dai)
943{
944 struct snd_soc_pcm_runtime *rtd = substream->private_data;
945 struct snd_soc_device *socdev = rtd->socdev;
946 struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2 947 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 948 int ret = 0;
949
950 switch (cmd) {
951 case SNDRV_PCM_TRIGGER_START:
952 case SNDRV_PCM_TRIGGER_RESUME:
953 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
7427b4b9 954 if (dac33->fifo_mode) {
c8bf93f0
PU		 955 dac33->state = DAC33_PREFILL;
956 queue_work(dac33->dac33_wq, &dac33->work);
957 }
958 break;
959 case SNDRV_PCM_TRIGGER_STOP:
960 case SNDRV_PCM_TRIGGER_SUSPEND:
961 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
7427b4b9 962 if (dac33->fifo_mode) {
c8bf93f0
PU		 963 dac33->state = DAC33_FLUSH;
964 queue_work(dac33->dac33_wq, &dac33->work);
965 }
966 break;
967 default:
968 ret = -EINVAL;
969 }
970
971 return ret;
972}
973
974static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
975 int clk_id, unsigned int freq, int dir)
976{
977 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 978 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 979 u8 ioc_reg, asrcb_reg;
980
981 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
982 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
983 switch (clk_id) {
984 case TLV320DAC33_MCLK:
985 ioc_reg |= DAC33_REFSEL;
986 asrcb_reg |= DAC33_SRCREFSEL;
987 break;
988 case TLV320DAC33_SLEEPCLK:
989 ioc_reg &= ~DAC33_REFSEL;
990 asrcb_reg &= ~DAC33_SRCREFSEL;
991 break;
992 default:
993 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
994 break;
995 }
996 dac33->refclk = freq;
997
998 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
999 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1000
1001 return 0;
1002}
1003
1004static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1005 unsigned int fmt)
1006{
1007 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1008 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1009 u8 aictrl_a, aictrl_b;
1010
1011 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1012 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1013 /* set master/slave audio interface */
1014 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1015 case SND_SOC_DAIFMT_CBM_CFM:
1016 /* Codec Master */
1017 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1018 break;
1019 case SND_SOC_DAIFMT_CBS_CFS:
1020 /* Codec Slave */
adcb8bc0
PU		 1021 if (dac33->fifo_mode) {
1022 dev_err(codec->dev, "FIFO mode requires master mode\n");
1023 return -EINVAL;
1024 } else
1025 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
c8bf93f0
PU		 1026 break;
1027 default:
1028 return -EINVAL;
1029 }
1030
1031 aictrl_a &= ~DAC33_AFMT_MASK;
1032 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1033 case SND_SOC_DAIFMT_I2S:
1034 aictrl_a |= DAC33_AFMT_I2S;
1035 break;
1036 case SND_SOC_DAIFMT_DSP_A:
1037 aictrl_a |= DAC33_AFMT_DSP;
1038 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
44f497b4 1039 aictrl_b |= DAC33_DATA_DELAY(0);
c8bf93f0
PU		 1040 break;
1041 case SND_SOC_DAIFMT_RIGHT_J:
1042 aictrl_a |= DAC33_AFMT_RIGHT_J;
1043 break;
1044 case SND_SOC_DAIFMT_LEFT_J:
1045 aictrl_a |= DAC33_AFMT_LEFT_J;
1046 break;
1047 default:
1048 dev_err(codec->dev, "Unsupported format (%u)\n",
1049 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1050 return -EINVAL;
1051 }
1052
1053 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1054 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1055
1056 return 0;
1057}
1058
1059static void dac33_init_chip(struct snd_soc_codec *codec)
1060{
1061 /* 44-46: DAC Control Registers */
1062 /* A : DAC sample rate Fsref/1.5 */
fdb6b1e1 1063 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
c8bf93f0
PU		 1064 /* B : DAC src=normal, not muted */
1065 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
1066 DAC33_DACSRCL_LEFT);
1067 /* C : (defaults) */
1068 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
1069
1070 /* 64-65 : L&R DAC power control
1071 Line In -> OUT 1V/V Gain, DAC -> OUT 4V/V Gain*/
1072 dac33_write(codec, DAC33_LDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1073 dac33_write(codec, DAC33_RDAC_PWR_CTRL, DAC33_LROUT_GAIN(2));
1074
1075 /* 73 : volume soft stepping control,
1076 clock source = internal osc (?) */
1077 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
1078
1079 /* 66 : LOP/LOM Modes */
1080 dac33_write(codec, DAC33_OUT_AMP_CM_CTRL, 0xff);
1081
1082 /* 68 : LOM inverted from LOP */
1083 dac33_write(codec, DAC33_OUT_AMP_CTRL, (3<<2));
1084
1085 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
1086}
1087
1088static int dac33_soc_probe(struct platform_device *pdev)
1089{
1090 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1091 struct snd_soc_codec *codec;
1092 struct tlv320dac33_priv *dac33;
1093 int ret = 0;
1094
1095 BUG_ON(!tlv320dac33_codec);
1096
1097 codec = tlv320dac33_codec;
1098 socdev->card->codec = codec;
b2c812e2 1099 dac33 = snd_soc_codec_get_drvdata(codec);
c8bf93f0
PU		 1100
1101 /* Power up the codec */
1102 dac33_hard_power(codec, 1);
1103 /* Set default configuration */
1104 dac33_init_chip(codec);
1105
1106 /* register pcms */
1107 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1108 if (ret < 0) {
1109 dev_err(codec->dev, "failed to create pcms\n");
1110 goto pcm_err;
1111 }
1112
1113 snd_soc_add_controls(codec, dac33_snd_controls,
1114 ARRAY_SIZE(dac33_snd_controls));
1115 /* Only add the nSample controls, if we have valid IRQ number */
1116 if (dac33->irq >= 0)
1117 snd_soc_add_controls(codec, dac33_nsample_snd_controls,
1118 ARRAY_SIZE(dac33_nsample_snd_controls));
1119
1120 dac33_add_widgets(codec);
1121
1122 /* power on device */
1123 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1124
3a7aaed7
IK		 1125 /* Bias level configuration has enabled regulator an extra time */
1126 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1127
c8bf93f0 1128 return 0;
fe3e78e0 1129
c8bf93f0
PU		 1130pcm_err:
1131 dac33_hard_power(codec, 0);
1132 return ret;
1133}
1134
1135static int dac33_soc_remove(struct platform_device *pdev)
1136{
1137 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1138 struct snd_soc_codec *codec = socdev->card->codec;
1139
1140 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1141
1142 snd_soc_free_pcms(socdev);
1143 snd_soc_dapm_free(socdev);
1144
1145 return 0;
1146}
1147
1148static int dac33_soc_suspend(struct platform_device *pdev, pm_message_t state)
1149{
1150 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1151 struct snd_soc_codec *codec = socdev->card->codec;
1152
1153 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1154
1155 return 0;
1156}
1157
1158static int dac33_soc_resume(struct platform_device *pdev)
1159{
1160 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1161 struct snd_soc_codec *codec = socdev->card->codec;
1162
1163 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1164 dac33_set_bias_level(codec, codec->suspend_bias_level);
1165
1166 return 0;
1167}
1168
1169struct snd_soc_codec_device soc_codec_dev_tlv320dac33 = {
1170 .probe = dac33_soc_probe,
1171 .remove = dac33_soc_remove,
1172 .suspend = dac33_soc_suspend,
1173 .resume = dac33_soc_resume,
1174};
1175EXPORT_SYMBOL_GPL(soc_codec_dev_tlv320dac33);
1176
1177#define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1178 SNDRV_PCM_RATE_48000)
1179#define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1180
1181static struct snd_soc_dai_ops dac33_dai_ops = {
c8bf93f0
PU		 1182 .hw_params = dac33_hw_params,
1183 .prepare = dac33_pcm_prepare,
1184 .trigger = dac33_pcm_trigger,
1185 .set_sysclk = dac33_set_dai_sysclk,
1186 .set_fmt = dac33_set_dai_fmt,
1187};
1188
1189struct snd_soc_dai dac33_dai = {
1190 .name = "tlv320dac33",
1191 .playback = {
1192 .stream_name = "Playback",
1193 .channels_min = 2,
1194 .channels_max = 2,
1195 .rates = DAC33_RATES,
1196 .formats = DAC33_FORMATS,},
1197 .ops = &dac33_dai_ops,
1198};
1199EXPORT_SYMBOL_GPL(dac33_dai);
1200
735fe4cf
MB		 1201static int __devinit dac33_i2c_probe(struct i2c_client *client,
1202 const struct i2c_device_id *id)
c8bf93f0
PU		 1203{
1204 struct tlv320dac33_platform_data *pdata;
1205 struct tlv320dac33_priv *dac33;
1206 struct snd_soc_codec *codec;
3a7aaed7 1207 int ret, i;
c8bf93f0
PU		 1208
1209 if (client->dev.platform_data == NULL) {
1210 dev_err(&client->dev, "Platform data not set\n");
1211 return -ENODEV;
1212 }
1213 pdata = client->dev.platform_data;
1214
1215 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1216 if (dac33 == NULL)
1217 return -ENOMEM;
1218
1219 codec = &dac33->codec;
b2c812e2 1220 snd_soc_codec_set_drvdata(codec, dac33);
c8bf93f0
PU		 1221 codec->control_data = client;
1222
1223 mutex_init(&codec->mutex);
1224 mutex_init(&dac33->mutex);
1225 INIT_LIST_HEAD(&codec->dapm_widgets);
1226 INIT_LIST_HEAD(&codec->dapm_paths);
1227
1228 codec->name = "tlv320dac33";
1229 codec->owner = THIS_MODULE;
1230 codec->read = dac33_read_reg_cache;
1231 codec->write = dac33_write_locked;
1232 codec->hw_write = (hw_write_t) i2c_master_send;
1233 codec->bias_level = SND_SOC_BIAS_OFF;
1234 codec->set_bias_level = dac33_set_bias_level;
1235 codec->dai = &dac33_dai;
1236 codec->num_dai = 1;
1237 codec->reg_cache_size = ARRAY_SIZE(dac33_reg);
1238 codec->reg_cache = kmemdup(dac33_reg, ARRAY_SIZE(dac33_reg),
1239 GFP_KERNEL);
1240 if (codec->reg_cache == NULL) {
1241 ret = -ENOMEM;
1242 goto error_reg;
1243 }
1244
1245 i2c_set_clientdata(client, dac33);
1246
1247 dac33->power_gpio = pdata->power_gpio;
6aceabb4 1248 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
eeb309a8 1249 dac33->keep_bclk = pdata->keep_bclk;
c8bf93f0
PU		 1250 dac33->irq = client->irq;
1251 dac33->nsample = NSAMPLE_MAX;
55abb59c 1252 dac33->nsample_max = NSAMPLE_MAX;
c8bf93f0 1253 /* Disable FIFO use by default */
7427b4b9 1254 dac33->fifo_mode = DAC33_FIFO_BYPASS;
c8bf93f0
PU		 1255
1256 tlv320dac33_codec = codec;
1257
1258 codec->dev = &client->dev;
1259 dac33_dai.dev = codec->dev;
1260
1261 /* Check if the reset GPIO number is valid and request it */
1262 if (dac33->power_gpio >= 0) {
1263 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1264 if (ret < 0) {
1265 dev_err(codec->dev,
1266 "Failed to request reset GPIO (%d)\n",
1267 dac33->power_gpio);
1268 snd_soc_unregister_dai(&dac33_dai);
1269 snd_soc_unregister_codec(codec);
1270 goto error_gpio;
1271 }
1272 gpio_direction_output(dac33->power_gpio, 0);
1273 } else {
1274 dac33->chip_power = 1;
1275 }
1276
1277 /* Check if the IRQ number is valid and request it */
1278 if (dac33->irq >= 0) {
1279 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1280 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1281 codec->name, codec);
1282 if (ret < 0) {
1283 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1284 dac33->irq, ret);
1285 dac33->irq = -1;
1286 }
1287 if (dac33->irq != -1) {
1288 /* Setup work queue */
74ea23aa
PU		 1289 dac33->dac33_wq =
1290 create_singlethread_workqueue("tlv320dac33");
c8bf93f0
PU		 1291 if (dac33->dac33_wq == NULL) {
1292 free_irq(dac33->irq, &dac33->codec);
1293 ret = -ENOMEM;
1294 goto error_wq;
1295 }
1296
1297 INIT_WORK(&dac33->work, dac33_work);
1298 }
1299 }
1300
3a7aaed7
IK		 1301 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1302 dac33->supplies[i].supply = dac33_supply_names[i];
1303
1304 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(dac33->supplies),
1305 dac33->supplies);
1306
1307 if (ret != 0) {
1308 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1309 goto err_get;
1310 }
1311
1312 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
1313 dac33->supplies);
1314 if (ret != 0) {
1315 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1316 goto err_enable;
1317 }
1318
c8bf93f0
PU		 1319 ret = snd_soc_register_codec(codec);
1320 if (ret != 0) {
1321 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1322 goto error_codec;
1323 }
1324
1325 ret = snd_soc_register_dai(&dac33_dai);
1326 if (ret != 0) {
1327 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1328 snd_soc_unregister_codec(codec);
1329 goto error_codec;
1330 }
1331
1332 /* Shut down the codec for now */
1333 dac33_hard_power(codec, 0);
1334
1335 return ret;
1336
1337error_codec:
3a7aaed7
IK		 1338 regulator_bulk_disable(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1339err_enable:
1340 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1341err_get:
c8bf93f0
PU		 1342 if (dac33->irq >= 0) {
1343 free_irq(dac33->irq, &dac33->codec);
1344 destroy_workqueue(dac33->dac33_wq);
1345 }
1346error_wq:
1347 if (dac33->power_gpio >= 0)
1348 gpio_free(dac33->power_gpio);
1349error_gpio:
1350 kfree(codec->reg_cache);
1351error_reg:
1352 tlv320dac33_codec = NULL;
1353 kfree(dac33);
1354
1355 return ret;
1356}
1357
735fe4cf 1358static int __devexit dac33_i2c_remove(struct i2c_client *client)
c8bf93f0
PU		 1359{
1360 struct tlv320dac33_priv *dac33;
1361
1362 dac33 = i2c_get_clientdata(client);
1363 dac33_hard_power(&dac33->codec, 0);
1364
1365 if (dac33->power_gpio >= 0)
1366 gpio_free(dac33->power_gpio);
1367 if (dac33->irq >= 0)
1368 free_irq(dac33->irq, &dac33->codec);
1369
3a7aaed7
IK		 1370 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1371
c8bf93f0
PU		 1372 destroy_workqueue(dac33->dac33_wq);
1373 snd_soc_unregister_dai(&dac33_dai);
1374 snd_soc_unregister_codec(&dac33->codec);
1375 kfree(dac33->codec.reg_cache);
1376 kfree(dac33);
1377 tlv320dac33_codec = NULL;
1378
1379 return 0;
1380}
1381
1382static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1383 {
1384 .name = "tlv320dac33",
1385 .driver_data = 0,
1386 },
1387 { },
1388};
1389
1390static struct i2c_driver tlv320dac33_i2c_driver = {
1391 .driver = {
1392 .name = "tlv320dac33",
1393 .owner = THIS_MODULE,
1394 },
1395 .probe = dac33_i2c_probe,
1396 .remove = __devexit_p(dac33_i2c_remove),
1397 .id_table = tlv320dac33_i2c_id,
1398};
1399
1400static int __init dac33_module_init(void)
1401{
1402 int r;
1403 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1404 if (r < 0) {
1405 printk(KERN_ERR "DAC33: driver registration failed\n");
1406 return r;
1407 }
1408 return 0;
1409}
1410module_init(dac33_module_init);
1411
1412static void __exit dac33_module_exit(void)
1413{
1414 i2c_del_driver(&tlv320dac33_i2c_driver);
1415}
1416module_exit(dac33_module_exit);
1417
1418
1419MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1420MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1421MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)