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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-block.git] / sound / soc / codecs / tlv320aic3x.c
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44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
15 * codecs aic31, aic32, aic33.
16 *
17 * It supports full aic33 codec functionality.
18 * The compatibility with aic32, aic31 is as follows:
19 * aic32 | aic31
20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
41#include <linux/platform_device.h>
5a0e3ad6 42#include <linux/slab.h>
44d0a879
VB		 43#include <sound/core.h>
44#include <sound/pcm.h>
45#include <sound/pcm_params.h>
46#include <sound/soc.h>
47#include <sound/soc-dapm.h>
48#include <sound/initval.h>
7565fc38 49#include <sound/tlv.h>
44d0a879
VB		 50
51#include "tlv320aic3x.h"
52
4f9c16cc 53#define AIC3X_VERSION "0.2"
44d0a879
VB		 54
55/* codec private data */
56struct aic3x_priv {
cb3826f5 57 struct snd_soc_codec codec;
44d0a879
VB		 58 unsigned int sysclk;
59 int master;
60};
61
62/*
63 * AIC3X register cache
64 * We can't read the AIC3X register space when we are
65 * using 2 wire for device control, so we cache them instead.
66 * There is no point in caching the reset register
67 */
68static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
69 0x00, 0x00, 0x00, 0x10, /* 0 */
70 0x04, 0x00, 0x00, 0x00, /* 4 */
71 0x00, 0x00, 0x00, 0x01, /* 8 */
72 0x00, 0x00, 0x00, 0x80, /* 12 */
73 0x80, 0xff, 0xff, 0x78, /* 16 */
74 0x78, 0x78, 0x78, 0x78, /* 20 */
75 0x78, 0x00, 0x00, 0xfe, /* 24 */
76 0x00, 0x00, 0xfe, 0x00, /* 28 */
77 0x18, 0x18, 0x00, 0x00, /* 32 */
78 0x00, 0x00, 0x00, 0x00, /* 36 */
79 0x00, 0x00, 0x00, 0x80, /* 40 */
80 0x80, 0x00, 0x00, 0x00, /* 44 */
81 0x00, 0x00, 0x00, 0x04, /* 48 */
82 0x00, 0x00, 0x00, 0x00, /* 52 */
83 0x00, 0x00, 0x04, 0x00, /* 56 */
84 0x00, 0x00, 0x00, 0x00, /* 60 */
85 0x00, 0x04, 0x00, 0x00, /* 64 */
86 0x00, 0x00, 0x00, 0x00, /* 68 */
87 0x04, 0x00, 0x00, 0x00, /* 72 */
88 0x00, 0x00, 0x00, 0x00, /* 76 */
89 0x00, 0x00, 0x00, 0x00, /* 80 */
90 0x00, 0x00, 0x00, 0x00, /* 84 */
91 0x00, 0x00, 0x00, 0x00, /* 88 */
92 0x00, 0x00, 0x00, 0x00, /* 92 */
93 0x00, 0x00, 0x00, 0x00, /* 96 */
94 0x00, 0x00, 0x02, /* 100 */
95};
96
97/*
98 * read aic3x register cache
99 */
100static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
101 unsigned int reg)
102{
103 u8 *cache = codec->reg_cache;
104 if (reg >= AIC3X_CACHEREGNUM)
105 return -1;
106 return cache[reg];
107}
108
109/*
110 * write aic3x register cache
111 */
112static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
113 u8 reg, u8 value)
114{
115 u8 *cache = codec->reg_cache;
116 if (reg >= AIC3X_CACHEREGNUM)
117 return;
118 cache[reg] = value;
119}
120
121/*
122 * write to the aic3x register space
123 */
124static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
125 unsigned int value)
126{
127 u8 data[2];
128
129 /* data is
130 * D15..D8 aic3x register offset
131 * D7...D0 register data
132 */
133 data[0] = reg & 0xff;
134 data[1] = value & 0xff;
135
136 aic3x_write_reg_cache(codec, data[0], data[1]);
137 if (codec->hw_write(codec->control_data, data, 2) == 2)
138 return 0;
139 else
140 return -EIO;
141}
142
54e7e616
DM		 143/*
144 * read from the aic3x register space
145 */
146static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
147 u8 *value)
148{
149 *value = reg & 0xff;
5f345346
MB		 150
151 value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
54e7e616
DM		 152
153 aic3x_write_reg_cache(codec, reg, *value);
154 return 0;
155}
156
44d0a879
VB		 157#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
158{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
159 .info = snd_soc_info_volsw, \
160 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
161 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
162
163/*
164 * All input lines are connected when !0xf and disconnected with 0xf bit field,
165 * so we have to use specific dapm_put call for input mixer
166 */
167static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
168 struct snd_ctl_elem_value *ucontrol)
169{
170 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
4453dba5
EN		 171 struct soc_mixer_control *mc =
172 (struct soc_mixer_control *)kcontrol->private_value;
173 unsigned int reg = mc->reg;
174 unsigned int shift = mc->shift;
175 int max = mc->max;
176 unsigned int mask = (1 << fls(max)) - 1;
177 unsigned int invert = mc->invert;
44d0a879
VB		 178 unsigned short val, val_mask;
179 int ret;
180 struct snd_soc_dapm_path *path;
181 int found = 0;
182
183 val = (ucontrol->value.integer.value[0] & mask);
184
185 mask = 0xf;
186 if (val)
187 val = mask;
188
189 if (invert)
190 val = mask - val;
191 val_mask = mask << shift;
192 val = val << shift;
193
194 mutex_lock(&widget->codec->mutex);
195
196 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
197 /* find dapm widget path assoc with kcontrol */
198 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
199 if (path->kcontrol != kcontrol)
200 continue;
201
202 /* found, now check type */
203 found = 1;
204 if (val)
205 /* new connection */
206 path->connect = invert ? 0 : 1;
207 else
208 /* old connection must be powered down */
209 path->connect = invert ? 1 : 0;
210 break;
211 }
212
213 if (found)
a5302181 214 snd_soc_dapm_sync(widget->codec);
44d0a879
VB		 215 }
216
217 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
218
219 mutex_unlock(&widget->codec->mutex);
220 return ret;
221}
222
223static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
224static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
225static const char *aic3x_left_hpcom_mux[] =
226 { "differential of HPLOUT", "constant VCM", "single-ended" };
227static const char *aic3x_right_hpcom_mux[] =
228 { "differential of HPROUT", "constant VCM", "single-ended",
229 "differential of HPLCOM", "external feedback" };
230static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 231static const char *aic3x_adc_hpf[] =
232 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 233
234#define LDAC_ENUM 0
235#define RDAC_ENUM 1
236#define LHPCOM_ENUM 2
237#define RHPCOM_ENUM 3
238#define LINE1L_ENUM 4
239#define LINE1R_ENUM 5
240#define LINE2L_ENUM 6
241#define LINE2R_ENUM 7
4d20f70a 242#define ADC_HPF_ENUM 8
44d0a879
VB		 243
244static const struct soc_enum aic3x_enum[] = {
245 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
246 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
247 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
248 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
249 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
250 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
251 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
252 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 253 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 254};
255
7565fc38
JN		 256/*
257 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
258 */
259static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
260/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
261static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
262/*
263 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
264 * Step size is approximately 0.5 dB over most of the scale but increasing
265 * near the very low levels.
266 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
267 * but having increasing dB difference below that (and where it doesn't count
268 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
269 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
270 */
271static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
272
44d0a879
VB		 273static const struct snd_kcontrol_new aic3x_snd_controls[] = {
274 /* Output */
7565fc38
JN		 275 SOC_DOUBLE_R_TLV("PCM Playback Volume",
276 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 277
7565fc38
JN		 278 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
279 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
280 0, 118, 1, output_stage_tlv),
28a1d869
DM		 281 SOC_SINGLE("LineL Playback Switch", LLOPM_CTRL, 3, 0x01, 0),
282 SOC_SINGLE("LineR Playback Switch", RLOPM_CTRL, 3, 0x01, 0),
7565fc38
JN		 283 SOC_DOUBLE_R_TLV("LineL DAC Playback Volume",
284 DACL1_2_LLOPM_VOL, DACR1_2_LLOPM_VOL,
285 0, 118, 1, output_stage_tlv),
286 SOC_SINGLE_TLV("LineL Left PGA Bypass Playback Volume",
287 PGAL_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
288 SOC_SINGLE_TLV("LineR Right PGA Bypass Playback Volume",
289 PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
290 SOC_DOUBLE_R_TLV("LineL Line2 Bypass Playback Volume",
291 LINE2L_2_LLOPM_VOL, LINE2R_2_LLOPM_VOL,
292 0, 118, 1, output_stage_tlv),
293 SOC_DOUBLE_R_TLV("LineR Line2 Bypass Playback Volume",
294 LINE2L_2_RLOPM_VOL, LINE2R_2_RLOPM_VOL,
295 0, 118, 1, output_stage_tlv),
296
297 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
298 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
299 0, 118, 1, output_stage_tlv),
44d0a879 300 SOC_SINGLE("Mono DAC Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
7565fc38
JN		 301 SOC_DOUBLE_R_TLV("Mono PGA Bypass Playback Volume",
302 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
303 0, 118, 1, output_stage_tlv),
304 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Playback Volume",
305 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
306 0, 118, 1, output_stage_tlv),
307
308 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
309 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
310 0, 118, 1, output_stage_tlv),
44d0a879
VB		 311 SOC_DOUBLE_R("HP DAC Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
312 0x01, 0),
7565fc38
JN		 313 SOC_DOUBLE_R_TLV("HP Right PGA Bypass Playback Volume",
314 PGAR_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
315 0, 118, 1, output_stage_tlv),
316 SOC_SINGLE_TLV("HPL PGA Bypass Playback Volume",
317 PGAL_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
318 SOC_SINGLE_TLV("HPR PGA Bypass Playback Volume",
319 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
320 SOC_DOUBLE_R_TLV("HP Line2 Bypass Playback Volume",
321 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
322 0, 118, 1, output_stage_tlv),
323
324 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
325 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
326 0, 118, 1, output_stage_tlv),
44d0a879
VB		 327 SOC_DOUBLE_R("HPCOM DAC Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
328 0x01, 0),
7565fc38
JN		 329 SOC_SINGLE_TLV("HPLCOM PGA Bypass Playback Volume",
330 PGAL_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
331 SOC_SINGLE_TLV("HPRCOM PGA Bypass Playback Volume",
332 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
333 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Playback Volume",
334 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
335 0, 118, 1, output_stage_tlv),
44d0a879
VB		 336
337 /*
338 * Note: enable Automatic input Gain Controller with care. It can
339 * adjust PGA to max value when ADC is on and will never go back.
340 */
341 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
342
343 /* Input */
7565fc38
JN		 344 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
345 0, 119, 0, adc_tlv),
44d0a879 346 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 347
348 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 349};
350
44d0a879
VB		 351/* Left DAC Mux */
352static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
353SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
354
355/* Right DAC Mux */
356static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
357SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
358
359/* Left HPCOM Mux */
360static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
361SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
362
363/* Right HPCOM Mux */
364static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
365SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
366
367/* Left DAC_L1 Mixer */
368static const struct snd_kcontrol_new aic3x_left_dac_mixer_controls[] = {
54f01916
DM		 369 SOC_DAPM_SINGLE("LineL Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
370 SOC_DAPM_SINGLE("LineR Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 371 SOC_DAPM_SINGLE("Mono Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
372 SOC_DAPM_SINGLE("HP Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
373 SOC_DAPM_SINGLE("HPCOM Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
374};
375
376/* Right DAC_R1 Mixer */
377static const struct snd_kcontrol_new aic3x_right_dac_mixer_controls[] = {
54f01916
DM		 378 SOC_DAPM_SINGLE("LineL Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
379 SOC_DAPM_SINGLE("LineR Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 380 SOC_DAPM_SINGLE("Mono Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
381 SOC_DAPM_SINGLE("HP Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
382 SOC_DAPM_SINGLE("HPCOM Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
383};
384
385/* Left PGA Mixer */
386static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
387 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 388 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 389 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
390 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 391 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 392};
393
394/* Right PGA Mixer */
395static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
396 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 397 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 398 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 399 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 400 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
401};
402
403/* Left Line1 Mux */
404static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
405SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
406
407/* Right Line1 Mux */
408static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
409SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
410
411/* Left Line2 Mux */
412static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
413SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
414
415/* Right Line2 Mux */
416static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
417SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
418
419/* Left PGA Bypass Mixer */
420static const struct snd_kcontrol_new aic3x_left_pga_bp_mixer_controls[] = {
54f01916
DM		 421 SOC_DAPM_SINGLE("LineL Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
422 SOC_DAPM_SINGLE("LineR Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
44d0a879 423 SOC_DAPM_SINGLE("Mono Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
54f01916
DM		 424 SOC_DAPM_SINGLE("HPL Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
425 SOC_DAPM_SINGLE("HPR Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
426 SOC_DAPM_SINGLE("HPLCOM Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
427 SOC_DAPM_SINGLE("HPRCOM Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 428};
429
430/* Right PGA Bypass Mixer */
431static const struct snd_kcontrol_new aic3x_right_pga_bp_mixer_controls[] = {
54f01916
DM		 432 SOC_DAPM_SINGLE("LineL Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("LineR Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
44d0a879 434 SOC_DAPM_SINGLE("Mono Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
54f01916
DM		 435 SOC_DAPM_SINGLE("HPL Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("HPR Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("HPLCOM Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
438 SOC_DAPM_SINGLE("HPRCOM Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 439};
440
441/* Left Line2 Bypass Mixer */
442static const struct snd_kcontrol_new aic3x_left_line2_bp_mixer_controls[] = {
54f01916
DM		 443 SOC_DAPM_SINGLE("LineL Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("LineR Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 445 SOC_DAPM_SINGLE("Mono Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("HP Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
54f01916 447 SOC_DAPM_SINGLE("HPLCOM Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
44d0a879
VB		 448};
449
450/* Right Line2 Bypass Mixer */
451static const struct snd_kcontrol_new aic3x_right_line2_bp_mixer_controls[] = {
54f01916
DM		 452 SOC_DAPM_SINGLE("LineL Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("LineR Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
44d0a879
VB		 454 SOC_DAPM_SINGLE("Mono Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("HP Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
54f01916 456 SOC_DAPM_SINGLE("HPRCOM Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 457};
458
459static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
460 /* Left DAC to Left Outputs */
461 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
462 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
463 &aic3x_left_dac_mux_controls),
464 SND_SOC_DAPM_MIXER("Left DAC_L1 Mixer", SND_SOC_NOPM, 0, 0,
465 &aic3x_left_dac_mixer_controls[0],
466 ARRAY_SIZE(aic3x_left_dac_mixer_controls)),
467 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
468 &aic3x_left_hpcom_mux_controls),
469 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
470 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
471 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
472
473 /* Right DAC to Right Outputs */
474 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
475 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
476 &aic3x_right_dac_mux_controls),
477 SND_SOC_DAPM_MIXER("Right DAC_R1 Mixer", SND_SOC_NOPM, 0, 0,
478 &aic3x_right_dac_mixer_controls[0],
479 ARRAY_SIZE(aic3x_right_dac_mixer_controls)),
480 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
481 &aic3x_right_hpcom_mux_controls),
482 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
483 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
484 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
485
486 /* Mono Output */
487 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
488
54f01916 489 /* Inputs to Left ADC */
44d0a879
VB		 490 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
491 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
492 &aic3x_left_pga_mixer_controls[0],
493 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
494 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
495 &aic3x_left_line1_mux_controls),
54f01916
DM		 496 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
497 &aic3x_left_line1_mux_controls),
44d0a879
VB		 498 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
499 &aic3x_left_line2_mux_controls),
500
54f01916 501 /* Inputs to Right ADC */
44d0a879
VB		 502 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
503 LINE1R_2_RADC_CTRL, 2, 0),
504 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
505 &aic3x_right_pga_mixer_controls[0],
506 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916
DM		 507 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
508 &aic3x_right_line1_mux_controls),
44d0a879
VB		 509 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
510 &aic3x_right_line1_mux_controls),
511 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
512 &aic3x_right_line2_mux_controls),
513
ee15ffdb
JN		 514 /*
515 * Not a real mic bias widget but similar function. This is for dynamic
516 * control of GPIO1 digital mic modulator clock output function when
517 * using digital mic.
518 */
519 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
520 AIC3X_GPIO1_REG, 4, 0xf,
521 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
522 AIC3X_GPIO1_FUNC_DISABLED),
523
524 /*
525 * Also similar function like mic bias. Selects digital mic with
526 * configurable oversampling rate instead of ADC converter.
527 */
528 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
529 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
530 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
531 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
532 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
533 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
534
44d0a879 535 /* Mic Bias */
0bd72a3d
JN		 536 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
537 MICBIAS_CTRL, 6, 3, 1, 0),
538 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
539 MICBIAS_CTRL, 6, 3, 2, 0),
540 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
541 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879
VB		 542
543 /* Left PGA to Left Output bypass */
544 SND_SOC_DAPM_MIXER("Left PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
545 &aic3x_left_pga_bp_mixer_controls[0],
546 ARRAY_SIZE(aic3x_left_pga_bp_mixer_controls)),
547
548 /* Right PGA to Right Output bypass */
549 SND_SOC_DAPM_MIXER("Right PGA Bypass Mixer", SND_SOC_NOPM, 0, 0,
550 &aic3x_right_pga_bp_mixer_controls[0],
551 ARRAY_SIZE(aic3x_right_pga_bp_mixer_controls)),
552
553 /* Left Line2 to Left Output bypass */
554 SND_SOC_DAPM_MIXER("Left Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
555 &aic3x_left_line2_bp_mixer_controls[0],
556 ARRAY_SIZE(aic3x_left_line2_bp_mixer_controls)),
557
558 /* Right Line2 to Right Output bypass */
559 SND_SOC_DAPM_MIXER("Right Line2 Bypass Mixer", SND_SOC_NOPM, 0, 0,
560 &aic3x_right_line2_bp_mixer_controls[0],
561 ARRAY_SIZE(aic3x_right_line2_bp_mixer_controls)),
562
563 SND_SOC_DAPM_OUTPUT("LLOUT"),
564 SND_SOC_DAPM_OUTPUT("RLOUT"),
565 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
566 SND_SOC_DAPM_OUTPUT("HPLOUT"),
567 SND_SOC_DAPM_OUTPUT("HPROUT"),
568 SND_SOC_DAPM_OUTPUT("HPLCOM"),
569 SND_SOC_DAPM_OUTPUT("HPRCOM"),
570
571 SND_SOC_DAPM_INPUT("MIC3L"),
572 SND_SOC_DAPM_INPUT("MIC3R"),
573 SND_SOC_DAPM_INPUT("LINE1L"),
574 SND_SOC_DAPM_INPUT("LINE1R"),
575 SND_SOC_DAPM_INPUT("LINE2L"),
576 SND_SOC_DAPM_INPUT("LINE2R"),
577};
578
d0cc0d3a 579static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 580 /* Left Output */
581 {"Left DAC Mux", "DAC_L1", "Left DAC"},
582 {"Left DAC Mux", "DAC_L2", "Left DAC"},
583 {"Left DAC Mux", "DAC_L3", "Left DAC"},
584
54f01916
DM		 585 {"Left DAC_L1 Mixer", "LineL Switch", "Left DAC Mux"},
586 {"Left DAC_L1 Mixer", "LineR Switch", "Left DAC Mux"},
44d0a879
VB		 587 {"Left DAC_L1 Mixer", "Mono Switch", "Left DAC Mux"},
588 {"Left DAC_L1 Mixer", "HP Switch", "Left DAC Mux"},
589 {"Left DAC_L1 Mixer", "HPCOM Switch", "Left DAC Mux"},
590 {"Left Line Out", NULL, "Left DAC Mux"},
591 {"Left HP Out", NULL, "Left DAC Mux"},
592
593 {"Left HPCOM Mux", "differential of HPLOUT", "Left DAC_L1 Mixer"},
594 {"Left HPCOM Mux", "constant VCM", "Left DAC_L1 Mixer"},
595 {"Left HPCOM Mux", "single-ended", "Left DAC_L1 Mixer"},
596
597 {"Left Line Out", NULL, "Left DAC_L1 Mixer"},
598 {"Mono Out", NULL, "Left DAC_L1 Mixer"},
599 {"Left HP Out", NULL, "Left DAC_L1 Mixer"},
600 {"Left HP Com", NULL, "Left HPCOM Mux"},
601
602 {"LLOUT", NULL, "Left Line Out"},
603 {"LLOUT", NULL, "Left Line Out"},
604 {"HPLOUT", NULL, "Left HP Out"},
605 {"HPLCOM", NULL, "Left HP Com"},
606
607 /* Right Output */
608 {"Right DAC Mux", "DAC_R1", "Right DAC"},
609 {"Right DAC Mux", "DAC_R2", "Right DAC"},
610 {"Right DAC Mux", "DAC_R3", "Right DAC"},
611
54f01916
DM		 612 {"Right DAC_R1 Mixer", "LineL Switch", "Right DAC Mux"},
613 {"Right DAC_R1 Mixer", "LineR Switch", "Right DAC Mux"},
44d0a879
VB		 614 {"Right DAC_R1 Mixer", "Mono Switch", "Right DAC Mux"},
615 {"Right DAC_R1 Mixer", "HP Switch", "Right DAC Mux"},
616 {"Right DAC_R1 Mixer", "HPCOM Switch", "Right DAC Mux"},
617 {"Right Line Out", NULL, "Right DAC Mux"},
618 {"Right HP Out", NULL, "Right DAC Mux"},
619
620 {"Right HPCOM Mux", "differential of HPROUT", "Right DAC_R1 Mixer"},
621 {"Right HPCOM Mux", "constant VCM", "Right DAC_R1 Mixer"},
622 {"Right HPCOM Mux", "single-ended", "Right DAC_R1 Mixer"},
623 {"Right HPCOM Mux", "differential of HPLCOM", "Right DAC_R1 Mixer"},
624 {"Right HPCOM Mux", "external feedback", "Right DAC_R1 Mixer"},
625
626 {"Right Line Out", NULL, "Right DAC_R1 Mixer"},
627 {"Mono Out", NULL, "Right DAC_R1 Mixer"},
628 {"Right HP Out", NULL, "Right DAC_R1 Mixer"},
629 {"Right HP Com", NULL, "Right HPCOM Mux"},
630
631 {"RLOUT", NULL, "Right Line Out"},
632 {"RLOUT", NULL, "Right Line Out"},
633 {"HPROUT", NULL, "Right HP Out"},
634 {"HPRCOM", NULL, "Right HP Com"},
635
636 /* Mono Output */
5b006137
JN		 637 {"MONO_LOUT", NULL, "Mono Out"},
638 {"MONO_LOUT", NULL, "Mono Out"},
44d0a879
VB		 639
640 /* Left Input */
641 {"Left Line1L Mux", "single-ended", "LINE1L"},
642 {"Left Line1L Mux", "differential", "LINE1L"},
643
644 {"Left Line2L Mux", "single-ended", "LINE2L"},
645 {"Left Line2L Mux", "differential", "LINE2L"},
646
647 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 648 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 649 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
650 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 651 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 652
653 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 654 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 655
656 /* Right Input */
657 {"Right Line1R Mux", "single-ended", "LINE1R"},
658 {"Right Line1R Mux", "differential", "LINE1R"},
659
660 {"Right Line2R Mux", "single-ended", "LINE2R"},
661 {"Right Line2R Mux", "differential", "LINE2R"},
662
54f01916 663 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 664 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
665 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 666 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 667 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
668
669 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 670 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 671
672 /* Left PGA Bypass */
54f01916
DM		 673 {"Left PGA Bypass Mixer", "LineL Switch", "Left PGA Mixer"},
674 {"Left PGA Bypass Mixer", "LineR Switch", "Left PGA Mixer"},
44d0a879 675 {"Left PGA Bypass Mixer", "Mono Switch", "Left PGA Mixer"},
54f01916
DM		 676 {"Left PGA Bypass Mixer", "HPL Switch", "Left PGA Mixer"},
677 {"Left PGA Bypass Mixer", "HPR Switch", "Left PGA Mixer"},
678 {"Left PGA Bypass Mixer", "HPLCOM Switch", "Left PGA Mixer"},
679 {"Left PGA Bypass Mixer", "HPRCOM Switch", "Left PGA Mixer"},
44d0a879
VB		 680
681 {"Left HPCOM Mux", "differential of HPLOUT", "Left PGA Bypass Mixer"},
682 {"Left HPCOM Mux", "constant VCM", "Left PGA Bypass Mixer"},
683 {"Left HPCOM Mux", "single-ended", "Left PGA Bypass Mixer"},
684
685 {"Left Line Out", NULL, "Left PGA Bypass Mixer"},
686 {"Mono Out", NULL, "Left PGA Bypass Mixer"},
687 {"Left HP Out", NULL, "Left PGA Bypass Mixer"},
688
689 /* Right PGA Bypass */
54f01916
DM		 690 {"Right PGA Bypass Mixer", "LineL Switch", "Right PGA Mixer"},
691 {"Right PGA Bypass Mixer", "LineR Switch", "Right PGA Mixer"},
44d0a879 692 {"Right PGA Bypass Mixer", "Mono Switch", "Right PGA Mixer"},
54f01916
DM		 693 {"Right PGA Bypass Mixer", "HPL Switch", "Right PGA Mixer"},
694 {"Right PGA Bypass Mixer", "HPR Switch", "Right PGA Mixer"},
695 {"Right PGA Bypass Mixer", "HPLCOM Switch", "Right PGA Mixer"},
696 {"Right PGA Bypass Mixer", "HPRCOM Switch", "Right PGA Mixer"},
44d0a879
VB		 697
698 {"Right HPCOM Mux", "differential of HPROUT", "Right PGA Bypass Mixer"},
699 {"Right HPCOM Mux", "constant VCM", "Right PGA Bypass Mixer"},
700 {"Right HPCOM Mux", "single-ended", "Right PGA Bypass Mixer"},
701 {"Right HPCOM Mux", "differential of HPLCOM", "Right PGA Bypass Mixer"},
702 {"Right HPCOM Mux", "external feedback", "Right PGA Bypass Mixer"},
703
704 {"Right Line Out", NULL, "Right PGA Bypass Mixer"},
705 {"Mono Out", NULL, "Right PGA Bypass Mixer"},
706 {"Right HP Out", NULL, "Right PGA Bypass Mixer"},
707
708 /* Left Line2 Bypass */
54f01916
DM		 709 {"Left Line2 Bypass Mixer", "LineL Switch", "Left Line2L Mux"},
710 {"Left Line2 Bypass Mixer", "LineR Switch", "Left Line2L Mux"},
44d0a879
VB		 711 {"Left Line2 Bypass Mixer", "Mono Switch", "Left Line2L Mux"},
712 {"Left Line2 Bypass Mixer", "HP Switch", "Left Line2L Mux"},
54f01916 713 {"Left Line2 Bypass Mixer", "HPLCOM Switch", "Left Line2L Mux"},
44d0a879
VB		 714
715 {"Left HPCOM Mux", "differential of HPLOUT", "Left Line2 Bypass Mixer"},
716 {"Left HPCOM Mux", "constant VCM", "Left Line2 Bypass Mixer"},
717 {"Left HPCOM Mux", "single-ended", "Left Line2 Bypass Mixer"},
718
719 {"Left Line Out", NULL, "Left Line2 Bypass Mixer"},
720 {"Mono Out", NULL, "Left Line2 Bypass Mixer"},
721 {"Left HP Out", NULL, "Left Line2 Bypass Mixer"},
722
723 /* Right Line2 Bypass */
54f01916
DM		 724 {"Right Line2 Bypass Mixer", "LineL Switch", "Right Line2R Mux"},
725 {"Right Line2 Bypass Mixer", "LineR Switch", "Right Line2R Mux"},
44d0a879
VB		 726 {"Right Line2 Bypass Mixer", "Mono Switch", "Right Line2R Mux"},
727 {"Right Line2 Bypass Mixer", "HP Switch", "Right Line2R Mux"},
54f01916 728 {"Right Line2 Bypass Mixer", "HPRCOM Switch", "Right Line2R Mux"},
44d0a879
VB		 729
730 {"Right HPCOM Mux", "differential of HPROUT", "Right Line2 Bypass Mixer"},
731 {"Right HPCOM Mux", "constant VCM", "Right Line2 Bypass Mixer"},
732 {"Right HPCOM Mux", "single-ended", "Right Line2 Bypass Mixer"},
733 {"Right HPCOM Mux", "differential of HPLCOM", "Right Line2 Bypass Mixer"},
734 {"Right HPCOM Mux", "external feedback", "Right Line2 Bypass Mixer"},
735
736 {"Right Line Out", NULL, "Right Line2 Bypass Mixer"},
737 {"Mono Out", NULL, "Right Line2 Bypass Mixer"},
738 {"Right HP Out", NULL, "Right Line2 Bypass Mixer"},
ee15ffdb
JN		 739
740 /*
741 * Logical path between digital mic enable and GPIO1 modulator clock
742 * output function
743 */
744 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
745 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
746 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
44d0a879
VB		 747};
748
749static int aic3x_add_widgets(struct snd_soc_codec *codec)
750{
d0cc0d3a
MB		 751 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
752 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 753
754 /* set up audio path interconnects */
d0cc0d3a 755 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
44d0a879 756
44d0a879
VB		 757 return 0;
758}
759
44d0a879 760static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 761 struct snd_pcm_hw_params *params,
762 struct snd_soc_dai *dai)
44d0a879
VB		 763{
764 struct snd_soc_pcm_runtime *rtd = substream->private_data;
765 struct snd_soc_device *socdev = rtd->socdev;
6627a653 766 struct snd_soc_codec *codec = socdev->card->codec;
44d0a879 767 struct aic3x_priv *aic3x = codec->private_data;
4f9c16cc 768 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 769 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
770 u16 d, pll_d = 1;
06c71282 771 u8 reg;
255173b4 772 int clk;
44d0a879 773
4f9c16cc
DM		 774 /* select data word length */
775 data =
776 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
777 switch (params_format(params)) {
778 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 779 break;
4f9c16cc
DM		 780 case SNDRV_PCM_FORMAT_S20_3LE:
781 data |= (0x01 << 4);
44d0a879 782 break;
4f9c16cc
DM		 783 case SNDRV_PCM_FORMAT_S24_LE:
784 data |= (0x02 << 4);
44d0a879 785 break;
4f9c16cc
DM		 786 case SNDRV_PCM_FORMAT_S32_LE:
787 data |= (0x03 << 4);
44d0a879
VB		 788 break;
789 }
4f9c16cc
DM		 790 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
791
792 /* Fsref can be 44100 or 48000 */
793 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
794
795 /* Try to find a value for Q which allows us to bypass the PLL and
796 * generate CODEC_CLK directly. */
797 for (pll_q = 2; pll_q < 18; pll_q++)
798 if (aic3x->sysclk / (128 * pll_q) == fsref) {
799 bypass_pll = 1;
800 break;
801 }
802
803 if (bypass_pll) {
804 pll_q &= 0xf;
805 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
806 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282
C		 807 /* disable PLL if it is bypassed */
808 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
809 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
810
811 } else {
4f9c16cc 812 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282
C		 813 /* enable PLL when it is used */
814 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
815 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
816 }
4f9c16cc
DM		 817
818 /* Route Left DAC to left channel input and
819 * right DAC to right channel input */
820 data = (LDAC2LCH | RDAC2RCH);
821 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
822 if (params_rate(params) >= 64000)
823 data |= DUAL_RATE_MODE;
44d0a879
VB		 824 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
825
826 /* codec sample rate select */
4f9c16cc
DM		 827 data = (fsref * 20) / params_rate(params);
828 if (params_rate(params) < 64000)
829 data /= 2;
830 data /= 5;
831 data -= 2;
44d0a879
VB		 832 data |= (data << 4);
833 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
834
4f9c16cc
DM		 835 if (bypass_pll)
836 return 0;
837
255173b4
PM		 838 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
839 * one wins the game. Try with d==0 first, next with d!=0.
840 * Constraints for j are according to the datasheet.
4f9c16cc 841 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 842 */
255173b4 843
4f9c16cc
DM		 844 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
845
846 for (r = 1; r <= 16; r++)
847 for (p = 1; p <= 8; p++) {
255173b4
PM		 848 for (j = 4; j <= 55; j++) {
849 /* This is actually 1000*((j+(d/10000))*r)/p
850 * The term had to be converted to get
851 * rid of the division by 10000; d = 0 here
852 */
5baf8315 853 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 854
855 /* Check whether this values get closer than
856 * the best ones we had before
857 */
5baf8315 858 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 859 abs(codec_clk - last_clk)) {
860 pll_j = j; pll_d = 0;
861 pll_r = r; pll_p = p;
5baf8315 862 last_clk = tmp_clk;
255173b4
PM		 863 }
864
865 /* Early exit for exact matches */
5baf8315 866 if (tmp_clk == codec_clk)
255173b4
PM		 867 goto found;
868 }
869 }
4f9c16cc 870
255173b4
PM		 871 /* try with d != 0 */
872 for (p = 1; p <= 8; p++) {
873 j = codec_clk * p / 1000;
4f9c16cc 874
255173b4
PM		 875 if (j < 4 || j > 11)
876 continue;
4f9c16cc 877
255173b4
PM		 878 /* do not use codec_clk here since we'd loose precision */
879 d = ((2048 * p * fsref) - j * aic3x->sysclk)
880 * 100 / (aic3x->sysclk/100);
4f9c16cc 881
255173b4 882 clk = (10000 * j + d) / (10 * p);
4f9c16cc 883
255173b4
PM		 884 /* check whether this values get closer than the best
885 * ones we had before */
886 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
887 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
888 last_clk = clk;
4f9c16cc
DM		 889 }
890
255173b4
PM		 891 /* Early exit for exact matches */
892 if (clk == codec_clk)
893 goto found;
894 }
895
4f9c16cc
DM		 896 if (last_clk == 0) {
897 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
898 return -EINVAL;
899 }
44d0a879 900
255173b4 901found:
44d0a879
VB		 902 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
903 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
904 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
905 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
906 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
907 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
908 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
909
44d0a879
VB		 910 return 0;
911}
912
e550e17f 913static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 914{
915 struct snd_soc_codec *codec = dai->codec;
916 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
917 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
918
919 if (mute) {
920 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
921 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
922 } else {
923 aic3x_write(codec, LDAC_VOL, ldac_reg);
924 aic3x_write(codec, RDAC_VOL, rdac_reg);
925 }
926
927 return 0;
928}
929
e550e17f 930static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 931 int clk_id, unsigned int freq, int dir)
932{
933 struct snd_soc_codec *codec = codec_dai->codec;
934 struct aic3x_priv *aic3x = codec->private_data;
935
4f9c16cc
DM		 936 aic3x->sysclk = freq;
937 return 0;
44d0a879
VB		 938}
939
e550e17f 940static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 941 unsigned int fmt)
942{
943 struct snd_soc_codec *codec = codec_dai->codec;
944 struct aic3x_priv *aic3x = codec->private_data;
81971a14 945 u8 iface_areg, iface_breg;
a24f4f68 946 int delay = 0;
81971a14
JN		 947
948 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
949 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 950
951 /* set master/slave audio interface */
952 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
953 case SND_SOC_DAIFMT_CBM_CFM:
954 aic3x->master = 1;
955 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
956 break;
957 case SND_SOC_DAIFMT_CBS_CFS:
958 aic3x->master = 0;
959 break;
960 default:
961 return -EINVAL;
962 }
963
4b7d2831
JN		 964 /*
965 * match both interface format and signal polarities since they
966 * are fixed
967 */
968 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
969 SND_SOC_DAIFMT_INV_MASK)) {
970 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 971 break;
a24f4f68
TK		 972 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
973 delay = 1;
4b7d2831 974 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 975 iface_breg |= (0x01 << 6);
976 break;
4b7d2831 977 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 978 iface_breg |= (0x02 << 6);
979 break;
4b7d2831 980 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 981 iface_breg |= (0x03 << 6);
982 break;
983 default:
984 return -EINVAL;
985 }
986
987 /* set iface */
988 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
989 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
a24f4f68 990 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 991
992 return 0;
993}
994
0be9898a
MB		 995static int aic3x_set_bias_level(struct snd_soc_codec *codec,
996 enum snd_soc_bias_level level)
44d0a879
VB		 997{
998 struct aic3x_priv *aic3x = codec->private_data;
999 u8 reg;
1000
0be9898a
MB		 1001 switch (level) {
1002 case SND_SOC_BIAS_ON:
44d0a879
VB		 1003 /* all power is driven by DAPM system */
1004 if (aic3x->master) {
1005 /* enable pll */
1006 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1007 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1008 reg | PLL_ENABLE);
1009 }
1010 break;
0be9898a 1011 case SND_SOC_BIAS_PREPARE:
44d0a879 1012 break;
0be9898a 1013 case SND_SOC_BIAS_STANDBY:
44d0a879
VB		 1014 /*
1015 * all power is driven by DAPM system,
1016 * so output power is safe if bypass was set
1017 */
1018 if (aic3x->master) {
1019 /* disable pll */
1020 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1021 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1022 reg & ~PLL_ENABLE);
1023 }
1024 break;
0be9898a 1025 case SND_SOC_BIAS_OFF:
44d0a879
VB		 1026 /* force all power off */
1027 reg = aic3x_read_reg_cache(codec, LINE1L_2_LADC_CTRL);
1028 aic3x_write(codec, LINE1L_2_LADC_CTRL, reg & ~LADC_PWR_ON);
1029 reg = aic3x_read_reg_cache(codec, LINE1R_2_RADC_CTRL);
1030 aic3x_write(codec, LINE1R_2_RADC_CTRL, reg & ~RADC_PWR_ON);
1031
1032 reg = aic3x_read_reg_cache(codec, DAC_PWR);
1033 aic3x_write(codec, DAC_PWR, reg & ~(LDAC_PWR_ON | RDAC_PWR_ON));
1034
1035 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1036 aic3x_write(codec, HPLOUT_CTRL, reg & ~HPLOUT_PWR_ON);
1037 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1038 aic3x_write(codec, HPROUT_CTRL, reg & ~HPROUT_PWR_ON);
1039
1040 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1041 aic3x_write(codec, HPLCOM_CTRL, reg & ~HPLCOM_PWR_ON);
1042 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1043 aic3x_write(codec, HPRCOM_CTRL, reg & ~HPRCOM_PWR_ON);
1044
1045 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1046 aic3x_write(codec, MONOLOPM_CTRL, reg & ~MONOLOPM_PWR_ON);
1047
1048 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1049 aic3x_write(codec, LLOPM_CTRL, reg & ~LLOPM_PWR_ON);
1050 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1051 aic3x_write(codec, RLOPM_CTRL, reg & ~RLOPM_PWR_ON);
1052
1053 if (aic3x->master) {
1054 /* disable pll */
1055 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1056 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1057 reg & ~PLL_ENABLE);
1058 }
1059 break;
1060 }
0be9898a 1061 codec->bias_level = level;
44d0a879
VB		 1062
1063 return 0;
1064}
1065
54e7e616
DM		 1066void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1067{
1068 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1069 u8 bit = gpio ? 3: 0;
1070 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1071 aic3x_write(codec, reg, val | (!!state << bit));
1072}
1073EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1074
1075int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1076{
1077 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1078 u8 val, bit = gpio ? 2: 1;
1079
1080 aic3x_read(codec, reg, &val);
1081 return (val >> bit) & 1;
1082}
1083EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1084
6f2a974b
DM		 1085void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1086 int headset_debounce, int button_debounce)
1087{
1088 u8 val;
1089
1090 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1091 << AIC3X_HEADSET_DETECT_SHIFT) |
1092 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1093 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1094 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1095 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1096
1097 if (detect & AIC3X_HEADSET_DETECT_MASK)
1098 val |= AIC3X_HEADSET_DETECT_ENABLED;
1099
1100 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1101}
1102EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1103
54e7e616
DM		 1104int aic3x_headset_detected(struct snd_soc_codec *codec)
1105{
1106 u8 val;
6f2a974b
DM		 1107 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1108 return (val >> 4) & 1;
54e7e616
DM		 1109}
1110EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1111
6f2a974b
DM		 1112int aic3x_button_pressed(struct snd_soc_codec *codec)
1113{
1114 u8 val;
1115 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1116 return (val >> 5) & 1;
1117}
1118EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1119
44d0a879
VB		 1120#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1121#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1122 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1123
6335d055
EM		 1124static struct snd_soc_dai_ops aic3x_dai_ops = {
1125 .hw_params = aic3x_hw_params,
1126 .digital_mute = aic3x_mute,
1127 .set_sysclk = aic3x_set_dai_sysclk,
1128 .set_fmt = aic3x_set_dai_fmt,
1129};
1130
e550e17f 1131struct snd_soc_dai aic3x_dai = {
e78cc18d 1132 .name = "tlv320aic3x",
44d0a879
VB		 1133 .playback = {
1134 .stream_name = "Playback",
1135 .channels_min = 1,
1136 .channels_max = 2,
1137 .rates = AIC3X_RATES,
1138 .formats = AIC3X_FORMATS,},
1139 .capture = {
1140 .stream_name = "Capture",
1141 .channels_min = 1,
1142 .channels_max = 2,
1143 .rates = AIC3X_RATES,
1144 .formats = AIC3X_FORMATS,},
6335d055 1145 .ops = &aic3x_dai_ops,
44d0a879
VB		 1146};
1147EXPORT_SYMBOL_GPL(aic3x_dai);
1148
1149static int aic3x_suspend(struct platform_device *pdev, pm_message_t state)
1150{
1151 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1152 struct snd_soc_codec *codec = socdev->card->codec;
44d0a879 1153
0be9898a 1154 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1155
1156 return 0;
1157}
1158
1159static int aic3x_resume(struct platform_device *pdev)
1160{
1161 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1162 struct snd_soc_codec *codec = socdev->card->codec;
44d0a879
VB		 1163 int i;
1164 u8 data[2];
1165 u8 *cache = codec->reg_cache;
1166
1167 /* Sync reg_cache with the hardware */
1168 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1169 data[0] = i;
1170 data[1] = cache[i];
1171 codec->hw_write(codec->control_data, data, 2);
1172 }
1173
0be9898a 1174 aic3x_set_bias_level(codec, codec->suspend_bias_level);
44d0a879
VB		 1175
1176 return 0;
1177}
1178
1179/*
1180 * initialise the AIC3X driver
1181 * register the mixer and dsp interfaces with the kernel
1182 */
cb3826f5 1183static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1184{
cb3826f5
BD		 1185 int reg;
1186
1187 mutex_init(&codec->mutex);
1188 INIT_LIST_HEAD(&codec->dapm_widgets);
1189 INIT_LIST_HEAD(&codec->dapm_paths);
44d0a879 1190
e78cc18d 1191 codec->name = "tlv320aic3x";
44d0a879
VB		 1192 codec->owner = THIS_MODULE;
1193 codec->read = aic3x_read_reg_cache;
1194 codec->write = aic3x_write;
0be9898a 1195 codec->set_bias_level = aic3x_set_bias_level;
44d0a879
VB		 1196 codec->dai = &aic3x_dai;
1197 codec->num_dai = 1;
ae2ff191 1198 codec->reg_cache_size = ARRAY_SIZE(aic3x_reg);
44d0a879
VB		 1199 codec->reg_cache = kmemdup(aic3x_reg, sizeof(aic3x_reg), GFP_KERNEL);
1200 if (codec->reg_cache == NULL)
1201 return -ENOMEM;
1202
1203 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1204 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1205
44d0a879
VB		 1206 /* DAC default volume and mute */
1207 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1208 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1209
1210 /* DAC to HP default volume and route to Output mixer */
1211 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1212 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1213 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1214 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1215 /* DAC to Line Out default volume and route to Output mixer */
1216 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1217 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1218 /* DAC to Mono Line Out default volume and route to Output mixer */
1219 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1220 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1221
1222 /* unmute all outputs */
1223 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1224 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1225 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1226 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1227 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1228 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1229 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1230 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1231 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1232 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1233 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1234 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1235 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1236 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1237
1238 /* ADC default volume and unmute */
1239 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1240 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1241 /* By default route Line1 to ADC PGA mixer */
1242 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1243 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1244
1245 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1246 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1247 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1248 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1249 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1250 /* PGA to Line Out default volume, disconnect from Output Mixer */
1251 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1252 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1253 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1254 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1255 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1256
1257 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1258 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1259 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1260 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1261 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1262 /* Line2 Line Out default volume, disconnect from Output Mixer */
1263 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1264 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1265 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1266 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1267 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1268
1269 /* off, with power on */
0be9898a 1270 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879 1271
cb3826f5
BD		 1272 return 0;
1273}
54e7e616 1274
cb3826f5
BD		 1275static struct snd_soc_codec *aic3x_codec;
1276
1277static int aic3x_register(struct snd_soc_codec *codec)
1278{
1279 int ret;
1280
1281 ret = aic3x_init(codec);
44d0a879 1282 if (ret < 0) {
cb3826f5
BD		 1283 dev_err(codec->dev, "Failed to initialise device\n");
1284 return ret;
44d0a879
VB		 1285 }
1286
cb3826f5 1287 aic3x_codec = codec;
44d0a879 1288
cb3826f5
BD		 1289 ret = snd_soc_register_codec(codec);
1290 if (ret) {
1291 dev_err(codec->dev, "Failed to register codec\n");
1292 return ret;
1293 }
1294
1295 ret = snd_soc_register_dai(&aic3x_dai);
1296 if (ret) {
1297 dev_err(codec->dev, "Failed to register dai\n");
1298 snd_soc_unregister_codec(codec);
1299 return ret;
1300 }
1301
1302 return 0;
44d0a879
VB		 1303}
1304
cb3826f5
BD		 1305static int aic3x_unregister(struct aic3x_priv *aic3x)
1306{
1307 aic3x_set_bias_level(&aic3x->codec, SND_SOC_BIAS_OFF);
1308
1309 snd_soc_unregister_dai(&aic3x_dai);
1310 snd_soc_unregister_codec(&aic3x->codec);
1311
1312 kfree(aic3x);
1313 aic3x_codec = NULL;
1314
1315 return 0;
1316}
44d0a879
VB		 1317
1318#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1319/*
1320 * AIC3X 2 wire address can be up to 4 devices with device addresses
1321 * 0x18, 0x19, 0x1A, 0x1B
1322 */
44d0a879
VB		 1323
1324/*
1325 * If the i2c layer weren't so broken, we could pass this kind of data
1326 * around
1327 */
ba8ed121
JD		 1328static int aic3x_i2c_probe(struct i2c_client *i2c,
1329 const struct i2c_device_id *id)
44d0a879 1330{
cb3826f5
BD		 1331 struct snd_soc_codec *codec;
1332 struct aic3x_priv *aic3x;
44d0a879 1333
cb3826f5
BD		 1334 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1335 if (aic3x == NULL) {
1336 dev_err(&i2c->dev, "failed to create private data\n");
1337 return -ENOMEM;
1338 }
1339
1340 codec = &aic3x->codec;
1341 codec->dev = &i2c->dev;
1342 codec->private_data = aic3x;
44d0a879 1343 codec->control_data = i2c;
cb3826f5 1344 codec->hw_write = (hw_write_t) i2c_master_send;
44d0a879 1345
cb3826f5
BD		 1346 i2c_set_clientdata(i2c, aic3x);
1347
1348 return aic3x_register(codec);
44d0a879
VB		 1349}
1350
ba8ed121 1351static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1352{
cb3826f5
BD		 1353 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1354
1355 return aic3x_unregister(aic3x);
44d0a879
VB		 1356}
1357
ba8ed121
JD		 1358static const struct i2c_device_id aic3x_i2c_id[] = {
1359 { "tlv320aic3x", 0 },
cb3826f5 1360 { "tlv320aic33", 0 },
ba8ed121
JD		 1361 { }
1362};
1363MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
44d0a879
VB		 1364
1365/* machine i2c codec control layer */
1366static struct i2c_driver aic3x_i2c_driver = {
1367 .driver = {
1368 .name = "aic3x I2C Codec",
1369 .owner = THIS_MODULE,
1370 },
cb3826f5 1371 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1372 .remove = aic3x_i2c_remove,
1373 .id_table = aic3x_i2c_id,
44d0a879 1374};
54e7e616 1375
cb3826f5 1376static inline void aic3x_i2c_init(void)
ba8ed121 1377{
ba8ed121
JD		 1378 int ret;
1379
1380 ret = i2c_add_driver(&aic3x_i2c_driver);
cb3826f5
BD		 1381 if (ret)
1382 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1383 __func__, ret);
1384}
ba8ed121 1385
cb3826f5
BD		 1386static inline void aic3x_i2c_exit(void)
1387{
ba8ed121 1388 i2c_del_driver(&aic3x_i2c_driver);
ba8ed121 1389}
cb3826f5
BD		 1390#else
1391static inline void aic3x_i2c_init(void) { }
1392static inline void aic3x_i2c_exit(void) { }
44d0a879
VB		 1393#endif
1394
1395static int aic3x_probe(struct platform_device *pdev)
1396{
1397 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1398 struct aic3x_setup_data *setup;
1399 struct snd_soc_codec *codec;
44d0a879
VB		 1400 int ret = 0;
1401
cb3826f5
BD		 1402 codec = aic3x_codec;
1403 if (!codec) {
1404 dev_err(&pdev->dev, "Codec not registered\n");
1405 return -ENODEV;
1406 }
44d0a879 1407
cb3826f5 1408 socdev->card->codec = codec;
44d0a879 1409 setup = socdev->codec_data;
44d0a879 1410
977d49e0
MB		 1411 if (setup) {
1412 /* setup GPIO functions */
1413 aic3x_write(codec, AIC3X_GPIO1_REG,
1414 (setup->gpio_func[0] & 0xf) << 4);
1415 aic3x_write(codec, AIC3X_GPIO2_REG,
1416 (setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1417 }
1418
cb3826f5
BD		 1419 /* register pcms */
1420 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1421 if (ret < 0) {
1422 printk(KERN_ERR "aic3x: failed to create pcms\n");
1423 goto pcm_err;
44d0a879 1424 }
3051e41a 1425
cb3826f5
BD		 1426 snd_soc_add_controls(codec, aic3x_snd_controls,
1427 ARRAY_SIZE(aic3x_snd_controls));
1428
1429 aic3x_add_widgets(codec);
1430
cb3826f5
BD		 1431 return ret;
1432
cb3826f5
BD		 1433pcm_err:
1434 kfree(codec->reg_cache);
44d0a879
VB		 1435 return ret;
1436}
1437
1438static int aic3x_remove(struct platform_device *pdev)
1439{
1440 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1441 struct snd_soc_codec *codec = socdev->card->codec;
44d0a879
VB		 1442
1443 /* power down chip */
1444 if (codec->control_data)
0be9898a 1445 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1446
1447 snd_soc_free_pcms(socdev);
1448 snd_soc_dapm_free(socdev);
cb3826f5
BD		 1449
1450 kfree(codec->reg_cache);
44d0a879
VB		 1451
1452 return 0;
1453}
1454
1455struct snd_soc_codec_device soc_codec_dev_aic3x = {
1456 .probe = aic3x_probe,
1457 .remove = aic3x_remove,
1458 .suspend = aic3x_suspend,
1459 .resume = aic3x_resume,
1460};
1461EXPORT_SYMBOL_GPL(soc_codec_dev_aic3x);
1462
c9b3a40f 1463static int __init aic3x_modinit(void)
64089b84 1464{
cb3826f5
BD		 1465 aic3x_i2c_init();
1466
1467 return 0;
64089b84
MB		 1468}
1469module_init(aic3x_modinit);
1470
1471static void __exit aic3x_exit(void)
1472{
cb3826f5 1473 aic3x_i2c_exit();
64089b84
MB		 1474}
1475module_exit(aic3x_exit);
1476
44d0a879
VB		 1477MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1478MODULE_AUTHOR("Vladimir Barinov");
1479MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)