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ASoC: tlv320aic3x: Don't sync first two registers from register cache
[linux-2.6-block.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
44d0a879 43#include <linux/platform_device.h>
5a0e3ad6 44#include <linux/slab.h>
44d0a879
VB		 45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
44d0a879 49#include <sound/initval.h>
7565fc38 50#include <sound/tlv.h>
5193d62f 51#include <sound/tlv320aic3x.h>
44d0a879
VB		 52
53#include "tlv320aic3x.h"
54
07779fdd
JN		 55#define AIC3X_NUM_SUPPLIES 4
56static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
57 "IOVDD", /* I/O Voltage */
58 "DVDD", /* Digital Core Voltage */
59 "AVDD", /* Analog DAC Voltage */
60 "DRVDD", /* ADC Analog and Output Driver Voltage */
61};
44d0a879 62
414c73ab
JN		 63static LIST_HEAD(reset_list);
64
5a895f8a
JN		 65struct aic3x_priv;
66
67struct aic3x_disable_nb {
68 struct notifier_block nb;
69 struct aic3x_priv *aic3x;
70};
71
44d0a879
VB		 72/* codec private data */
73struct aic3x_priv {
5a895f8a 74 struct snd_soc_codec *codec;
07779fdd 75 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
5a895f8a 76 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
f0fba2ad
LG		 77 enum snd_soc_control_type control_type;
78 struct aic3x_setup_data *setup;
79 void *control_data;
44d0a879 80 unsigned int sysclk;
414c73ab 81 struct list_head list;
44d0a879 82 int master;
5193d62f 83 int gpio_reset;
6c1a7d40 84 int power;
6184f105
RC		 85#define AIC3X_MODEL_3X 0
86#define AIC3X_MODEL_33 1
87#define AIC3X_MODEL_3007 2
88 u16 model;
44d0a879
VB		 89};
90
91/*
92 * AIC3X register cache
93 * We can't read the AIC3X register space when we are
94 * using 2 wire for device control, so we cache them instead.
95 * There is no point in caching the reset register
96 */
97static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
98 0x00, 0x00, 0x00, 0x10, /* 0 */
99 0x04, 0x00, 0x00, 0x00, /* 4 */
100 0x00, 0x00, 0x00, 0x01, /* 8 */
101 0x00, 0x00, 0x00, 0x80, /* 12 */
102 0x80, 0xff, 0xff, 0x78, /* 16 */
103 0x78, 0x78, 0x78, 0x78, /* 20 */
104 0x78, 0x00, 0x00, 0xfe, /* 24 */
105 0x00, 0x00, 0xfe, 0x00, /* 28 */
106 0x18, 0x18, 0x00, 0x00, /* 32 */
107 0x00, 0x00, 0x00, 0x00, /* 36 */
108 0x00, 0x00, 0x00, 0x80, /* 40 */
109 0x80, 0x00, 0x00, 0x00, /* 44 */
110 0x00, 0x00, 0x00, 0x04, /* 48 */
111 0x00, 0x00, 0x00, 0x00, /* 52 */
112 0x00, 0x00, 0x04, 0x00, /* 56 */
113 0x00, 0x00, 0x00, 0x00, /* 60 */
114 0x00, 0x04, 0x00, 0x00, /* 64 */
115 0x00, 0x00, 0x00, 0x00, /* 68 */
116 0x04, 0x00, 0x00, 0x00, /* 72 */
117 0x00, 0x00, 0x00, 0x00, /* 76 */
118 0x00, 0x00, 0x00, 0x00, /* 80 */
119 0x00, 0x00, 0x00, 0x00, /* 84 */
120 0x00, 0x00, 0x00, 0x00, /* 88 */
121 0x00, 0x00, 0x00, 0x00, /* 92 */
122 0x00, 0x00, 0x00, 0x00, /* 96 */
123 0x00, 0x00, 0x02, /* 100 */
124};
125
126/*
9900daa8
JN		 127 * read from the aic3x register space. Only use for this function is if
128 * wanting to read volatile bits from those registers that has both read-only
129 * and read/write bits. All other cases should use snd_soc_read.
44d0a879 130 */
54e7e616
DM		 131static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
132 u8 *value)
44d0a879
VB		 133{
134 u8 *cache = codec->reg_cache;
44d0a879 135
5a895f8a
JN		 136 if (codec->cache_only)
137 return -EINVAL;
44d0a879 138 if (reg >= AIC3X_CACHEREGNUM)
9900daa8 139 return -1;
5f345346 140
9900daa8
JN		 141 *value = codec->hw_read(codec, reg);
142 cache[reg] = *value;
54e7e616 143
54e7e616
DM		 144 return 0;
145}
146
44d0a879
VB		 147#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
148{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
149 .info = snd_soc_info_volsw, \
150 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
151 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
152
153/*
154 * All input lines are connected when !0xf and disconnected with 0xf bit field,
155 * so we have to use specific dapm_put call for input mixer
156 */
157static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
158 struct snd_ctl_elem_value *ucontrol)
159{
9d03545d
JN		 160 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
161 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
4453dba5
EN		 162 struct soc_mixer_control *mc =
163 (struct soc_mixer_control *)kcontrol->private_value;
164 unsigned int reg = mc->reg;
165 unsigned int shift = mc->shift;
166 int max = mc->max;
167 unsigned int mask = (1 << fls(max)) - 1;
168 unsigned int invert = mc->invert;
44d0a879
VB		 169 unsigned short val, val_mask;
170 int ret;
171 struct snd_soc_dapm_path *path;
172 int found = 0;
173
174 val = (ucontrol->value.integer.value[0] & mask);
175
176 mask = 0xf;
177 if (val)
178 val = mask;
179
180 if (invert)
181 val = mask - val;
182 val_mask = mask << shift;
183 val = val << shift;
184
185 mutex_lock(&widget->codec->mutex);
186
187 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
188 /* find dapm widget path assoc with kcontrol */
8ddab3f5 189 list_for_each_entry(path, &widget->dapm->card->paths, list) {
44d0a879
VB		 190 if (path->kcontrol != kcontrol)
191 continue;
192
193 /* found, now check type */
194 found = 1;
195 if (val)
196 /* new connection */
197 path->connect = invert ? 0 : 1;
198 else
199 /* old connection must be powered down */
200 path->connect = invert ? 1 : 0;
201 break;
202 }
203
204 if (found)
ce6120cc 205 snd_soc_dapm_sync(widget->dapm);
44d0a879
VB		 206 }
207
208 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
209
210 mutex_unlock(&widget->codec->mutex);
211 return ret;
212}
213
214static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
215static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
216static const char *aic3x_left_hpcom_mux[] =
217 { "differential of HPLOUT", "constant VCM", "single-ended" };
218static const char *aic3x_right_hpcom_mux[] =
219 { "differential of HPROUT", "constant VCM", "single-ended",
220 "differential of HPLCOM", "external feedback" };
221static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 222static const char *aic3x_adc_hpf[] =
223 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 224
225#define LDAC_ENUM 0
226#define RDAC_ENUM 1
227#define LHPCOM_ENUM 2
228#define RHPCOM_ENUM 3
229#define LINE1L_ENUM 4
230#define LINE1R_ENUM 5
231#define LINE2L_ENUM 6
232#define LINE2R_ENUM 7
4d20f70a 233#define ADC_HPF_ENUM 8
44d0a879
VB		 234
235static const struct soc_enum aic3x_enum[] = {
236 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
237 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
238 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
239 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
240 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
241 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
242 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
243 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 244 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 245};
246
7565fc38
JN		 247/*
248 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
249 */
250static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
251/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
252static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
253/*
254 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
255 * Step size is approximately 0.5 dB over most of the scale but increasing
256 * near the very low levels.
257 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
258 * but having increasing dB difference below that (and where it doesn't count
259 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
260 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
261 */
262static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
263
44d0a879
VB		 264static const struct snd_kcontrol_new aic3x_snd_controls[] = {
265 /* Output */
7565fc38
JN		 266 SOC_DOUBLE_R_TLV("PCM Playback Volume",
267 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 268
098b1718
JN		 269 /*
270 * Output controls that map to output mixer switches. Note these are
271 * only for swapped L-to-R and R-to-L routes. See below stereo controls
272 * for direct L-to-L and R-to-R routes.
273 */
274 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
275 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
276 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
277 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
278 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
279 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
280
281 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
282 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
283 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
284 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
285 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
286 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
287
288 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
289 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
290 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
291 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
292 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
293 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
294
295 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
296 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
297 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
298 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
299 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
300 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
301
302 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
303 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
304 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
305 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
306 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
307 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
308
309 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
310 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
311 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
312 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
313 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
314 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
315
316 /* Stereo output controls for direct L-to-L and R-to-R routes */
317 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
318 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
319 0, 118, 1, output_stage_tlv),
320 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
321 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
322 0, 118, 1, output_stage_tlv),
7565fc38
JN		 323 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
324 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
325 0, 118, 1, output_stage_tlv),
098b1718
JN		 326
327 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
328 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 329 0, 118, 1, output_stage_tlv),
098b1718
JN		 330 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
331 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 332 0, 118, 1, output_stage_tlv),
7565fc38
JN		 333 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
334 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
335 0, 118, 1, output_stage_tlv),
098b1718
JN		 336
337 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
338 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 339 0, 118, 1, output_stage_tlv),
098b1718
JN		 340 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
341 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 342 0, 118, 1, output_stage_tlv),
7565fc38
JN		 343 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
344 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
345 0, 118, 1, output_stage_tlv),
098b1718
JN		 346
347 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
348 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 349 0, 118, 1, output_stage_tlv),
098b1718
JN		 350 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
351 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 352 0, 118, 1, output_stage_tlv),
7565fc38
JN		 353 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
354 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
355 0, 118, 1, output_stage_tlv),
098b1718
JN		 356
357 /* Output pin mute controls */
358 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
359 0x01, 0),
360 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
361 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
362 0x01, 0),
f9bc0297 363 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 364 0x01, 0),
44d0a879
VB		 365
366 /*
367 * Note: enable Automatic input Gain Controller with care. It can
368 * adjust PGA to max value when ADC is on and will never go back.
369 */
370 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
371
372 /* Input */
7565fc38
JN		 373 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
374 0, 119, 0, adc_tlv),
44d0a879 375 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 376
377 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 378};
379
6184f105
RC		 380/*
381 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
382 */
383static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
384
385static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
386 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
387
44d0a879
VB		 388/* Left DAC Mux */
389static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
390SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
391
392/* Right DAC Mux */
393static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
394SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
395
396/* Left HPCOM Mux */
397static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
398SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
399
400/* Right HPCOM Mux */
401static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
402SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
403
c3b79e05
JN		 404/* Left Line Mixer */
405static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
406 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
407 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
408 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
409 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
410 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
411 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 412};
413
c3b79e05
JN		 414/* Right Line Mixer */
415static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
416 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
417 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
418 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
419 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
420 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
421 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
422};
423
424/* Mono Mixer */
425static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
426 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
427 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
428 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
429 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
430 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
431 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
432};
433
434/* Left HP Mixer */
435static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
436 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
438 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
439 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
440 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
441 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
442};
443
444/* Right HP Mixer */
445static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
446 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
448 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
449 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
450 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
451 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
452};
453
454/* Left HPCOM Mixer */
455static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
456 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
460 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
461 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
462};
463
464/* Right HPCOM Mixer */
465static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
466 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
470 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
471 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 472};
473
474/* Left PGA Mixer */
475static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
476 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 477 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 478 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
479 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 480 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 481};
482
483/* Right PGA Mixer */
484static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
485 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 486 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 487 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 488 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 489 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
490};
491
492/* Left Line1 Mux */
493static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
494SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
495
496/* Right Line1 Mux */
497static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
498SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
499
500/* Left Line2 Mux */
501static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
502SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
503
504/* Right Line2 Mux */
505static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
506SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
507
44d0a879
VB		 508static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
509 /* Left DAC to Left Outputs */
510 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
511 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
512 &aic3x_left_dac_mux_controls),
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VB		 513 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
514 &aic3x_left_hpcom_mux_controls),
515 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
516 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
517 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
518
519 /* Right DAC to Right Outputs */
520 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
521 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
522 &aic3x_right_dac_mux_controls),
44d0a879
VB		 523 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
524 &aic3x_right_hpcom_mux_controls),
525 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
526 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
527 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
528
529 /* Mono Output */
530 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
531
54f01916 532 /* Inputs to Left ADC */
44d0a879
VB		 533 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
534 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
535 &aic3x_left_pga_mixer_controls[0],
536 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
537 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
538 &aic3x_left_line1_mux_controls),
54f01916
DM		 539 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
540 &aic3x_left_line1_mux_controls),
44d0a879
VB		 541 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
542 &aic3x_left_line2_mux_controls),
543
54f01916 544 /* Inputs to Right ADC */
44d0a879
VB		 545 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
546 LINE1R_2_RADC_CTRL, 2, 0),
547 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
548 &aic3x_right_pga_mixer_controls[0],
549 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916
DM		 550 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
551 &aic3x_right_line1_mux_controls),
44d0a879
VB		 552 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
553 &aic3x_right_line1_mux_controls),
554 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
555 &aic3x_right_line2_mux_controls),
556
ee15ffdb
JN		 557 /*
558 * Not a real mic bias widget but similar function. This is for dynamic
559 * control of GPIO1 digital mic modulator clock output function when
560 * using digital mic.
561 */
562 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
563 AIC3X_GPIO1_REG, 4, 0xf,
564 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
565 AIC3X_GPIO1_FUNC_DISABLED),
566
567 /*
568 * Also similar function like mic bias. Selects digital mic with
569 * configurable oversampling rate instead of ADC converter.
570 */
571 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
572 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
573 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
574 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
575 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
576 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
577
44d0a879 578 /* Mic Bias */
0bd72a3d
JN		 579 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
580 MICBIAS_CTRL, 6, 3, 1, 0),
581 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
582 MICBIAS_CTRL, 6, 3, 2, 0),
583 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
584 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879 585
c3b79e05
JN		 586 /* Output mixers */
587 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
588 &aic3x_left_line_mixer_controls[0],
589 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
590 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
591 &aic3x_right_line_mixer_controls[0],
592 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
593 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
594 &aic3x_mono_mixer_controls[0],
595 ARRAY_SIZE(aic3x_mono_mixer_controls)),
596 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
597 &aic3x_left_hp_mixer_controls[0],
598 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
599 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
600 &aic3x_right_hp_mixer_controls[0],
601 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
602 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
603 &aic3x_left_hpcom_mixer_controls[0],
604 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
605 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
606 &aic3x_right_hpcom_mixer_controls[0],
607 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879
VB		 608
609 SND_SOC_DAPM_OUTPUT("LLOUT"),
610 SND_SOC_DAPM_OUTPUT("RLOUT"),
611 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
612 SND_SOC_DAPM_OUTPUT("HPLOUT"),
613 SND_SOC_DAPM_OUTPUT("HPROUT"),
614 SND_SOC_DAPM_OUTPUT("HPLCOM"),
615 SND_SOC_DAPM_OUTPUT("HPRCOM"),
616
617 SND_SOC_DAPM_INPUT("MIC3L"),
618 SND_SOC_DAPM_INPUT("MIC3R"),
619 SND_SOC_DAPM_INPUT("LINE1L"),
620 SND_SOC_DAPM_INPUT("LINE1R"),
621 SND_SOC_DAPM_INPUT("LINE2L"),
622 SND_SOC_DAPM_INPUT("LINE2R"),
19f7ac50
JN		 623
624 /*
625 * Virtual output pin to detection block inside codec. This can be
626 * used to keep codec bias on if gpio or detection features are needed.
627 * Force pin on or construct a path with an input jack and mic bias
628 * widgets.
629 */
630 SND_SOC_DAPM_OUTPUT("Detection"),
44d0a879
VB		 631};
632
6184f105
RC		 633static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
634 /* Class-D outputs */
635 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
636 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
637
638 SND_SOC_DAPM_OUTPUT("SPOP"),
639 SND_SOC_DAPM_OUTPUT("SPOM"),
640};
641
d0cc0d3a 642static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 643 /* Left Input */
644 {"Left Line1L Mux", "single-ended", "LINE1L"},
645 {"Left Line1L Mux", "differential", "LINE1L"},
646
647 {"Left Line2L Mux", "single-ended", "LINE2L"},
648 {"Left Line2L Mux", "differential", "LINE2L"},
649
650 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 651 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 652 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
653 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 654 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 655
656 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 657 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 658
659 /* Right Input */
660 {"Right Line1R Mux", "single-ended", "LINE1R"},
661 {"Right Line1R Mux", "differential", "LINE1R"},
662
663 {"Right Line2R Mux", "single-ended", "LINE2R"},
664 {"Right Line2R Mux", "differential", "LINE2R"},
665
54f01916 666 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 667 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
668 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 669 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 670 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
671
672 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 673 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 674
ee15ffdb
JN		 675 /*
676 * Logical path between digital mic enable and GPIO1 modulator clock
677 * output function
678 */
679 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
680 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
681 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 682
683 /* Left DAC Output */
684 {"Left DAC Mux", "DAC_L1", "Left DAC"},
685 {"Left DAC Mux", "DAC_L2", "Left DAC"},
686 {"Left DAC Mux", "DAC_L3", "Left DAC"},
687
688 /* Right DAC Output */
689 {"Right DAC Mux", "DAC_R1", "Right DAC"},
690 {"Right DAC Mux", "DAC_R2", "Right DAC"},
691 {"Right DAC Mux", "DAC_R3", "Right DAC"},
692
693 /* Left Line Output */
694 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
695 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
696 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
697 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
698 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
699 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
700
701 {"Left Line Out", NULL, "Left Line Mixer"},
702 {"Left Line Out", NULL, "Left DAC Mux"},
703 {"LLOUT", NULL, "Left Line Out"},
704
705 /* Right Line Output */
706 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
707 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
708 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
709 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
710 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
711 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
712
713 {"Right Line Out", NULL, "Right Line Mixer"},
714 {"Right Line Out", NULL, "Right DAC Mux"},
715 {"RLOUT", NULL, "Right Line Out"},
716
717 /* Mono Output */
718 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
719 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
720 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
721 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
722 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
723 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
724
725 {"Mono Out", NULL, "Mono Mixer"},
726 {"MONO_LOUT", NULL, "Mono Out"},
727
728 /* Left HP Output */
729 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
730 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
731 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
732 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
733 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
734 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
735
736 {"Left HP Out", NULL, "Left HP Mixer"},
737 {"Left HP Out", NULL, "Left DAC Mux"},
738 {"HPLOUT", NULL, "Left HP Out"},
739
740 /* Right HP Output */
741 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
742 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
743 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
744 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
745 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
746 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
747
748 {"Right HP Out", NULL, "Right HP Mixer"},
749 {"Right HP Out", NULL, "Right DAC Mux"},
750 {"HPROUT", NULL, "Right HP Out"},
751
752 /* Left HPCOM Output */
753 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
754 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
755 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
756 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
757 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
758 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
759
760 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
761 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
762 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
763 {"Left HP Com", NULL, "Left HPCOM Mux"},
764 {"HPLCOM", NULL, "Left HP Com"},
765
766 /* Right HPCOM Output */
767 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
768 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
769 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
770 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
771 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
772 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
773
774 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
775 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
776 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
777 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
778 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
779 {"Right HP Com", NULL, "Right HPCOM Mux"},
780 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 781};
782
6184f105
RC		 783static const struct snd_soc_dapm_route intercon_3007[] = {
784 /* Class-D outputs */
785 {"Left Class-D Out", NULL, "Left Line Out"},
786 {"Right Class-D Out", NULL, "Left Line Out"},
787 {"SPOP", NULL, "Left Class-D Out"},
788 {"SPOM", NULL, "Right Class-D Out"},
789};
790
44d0a879
VB		 791static int aic3x_add_widgets(struct snd_soc_codec *codec)
792{
6184f105 793 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
ce6120cc 794 struct snd_soc_dapm_context *dapm = &codec->dapm;
6184f105 795
ce6120cc 796 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
d0cc0d3a 797 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 798
799 /* set up audio path interconnects */
ce6120cc 800 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
44d0a879 801
6184f105 802 if (aic3x->model == AIC3X_MODEL_3007) {
ce6120cc 803 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
6184f105 804 ARRAY_SIZE(aic3007_dapm_widgets));
ce6120cc
LG		 805 snd_soc_dapm_add_routes(dapm, intercon_3007,
806 ARRAY_SIZE(intercon_3007));
6184f105
RC		 807 }
808
44d0a879
VB		 809 return 0;
810}
811
44d0a879 812static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 813 struct snd_pcm_hw_params *params,
814 struct snd_soc_dai *dai)
44d0a879
VB		 815{
816 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 817 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 818 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 819 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 820 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
821 u16 d, pll_d = 1;
06c71282 822 u8 reg;
255173b4 823 int clk;
44d0a879 824
4f9c16cc 825 /* select data word length */
e18eca43 826 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
4f9c16cc
DM		 827 switch (params_format(params)) {
828 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 829 break;
4f9c16cc
DM		 830 case SNDRV_PCM_FORMAT_S20_3LE:
831 data |= (0x01 << 4);
44d0a879 832 break;
4f9c16cc
DM		 833 case SNDRV_PCM_FORMAT_S24_LE:
834 data |= (0x02 << 4);
44d0a879 835 break;
4f9c16cc
DM		 836 case SNDRV_PCM_FORMAT_S32_LE:
837 data |= (0x03 << 4);
44d0a879
VB		 838 break;
839 }
e18eca43 840 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
4f9c16cc
DM		 841
842 /* Fsref can be 44100 or 48000 */
843 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
844
845 /* Try to find a value for Q which allows us to bypass the PLL and
846 * generate CODEC_CLK directly. */
847 for (pll_q = 2; pll_q < 18; pll_q++)
848 if (aic3x->sysclk / (128 * pll_q) == fsref) {
849 bypass_pll = 1;
850 break;
851 }
852
853 if (bypass_pll) {
854 pll_q &= 0xf;
e18eca43
JN		 855 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
856 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282 857 /* disable PLL if it is bypassed */
e18eca43
JN		 858 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
859 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
06c71282
C		 860
861 } else {
e18eca43 862 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282 863 /* enable PLL when it is used */
e18eca43
JN		 864 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
865 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
06c71282 866 }
4f9c16cc
DM		 867
868 /* Route Left DAC to left channel input and
869 * right DAC to right channel input */
870 data = (LDAC2LCH | RDAC2RCH);
871 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
872 if (params_rate(params) >= 64000)
873 data |= DUAL_RATE_MODE;
e18eca43 874 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
44d0a879
VB		 875
876 /* codec sample rate select */
4f9c16cc
DM		 877 data = (fsref * 20) / params_rate(params);
878 if (params_rate(params) < 64000)
879 data /= 2;
880 data /= 5;
881 data -= 2;
44d0a879 882 data |= (data << 4);
e18eca43 883 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
44d0a879 884
4f9c16cc
DM		 885 if (bypass_pll)
886 return 0;
887
25985edc 888 /* Use PLL, compute appropriate setup for j, d, r and p, the closest
255173b4
PM		 889 * one wins the game. Try with d==0 first, next with d!=0.
890 * Constraints for j are according to the datasheet.
4f9c16cc 891 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 892 */
255173b4 893
4f9c16cc
DM		 894 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
895
896 for (r = 1; r <= 16; r++)
897 for (p = 1; p <= 8; p++) {
255173b4
PM		 898 for (j = 4; j <= 55; j++) {
899 /* This is actually 1000*((j+(d/10000))*r)/p
900 * The term had to be converted to get
901 * rid of the division by 10000; d = 0 here
902 */
5baf8315 903 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 904
905 /* Check whether this values get closer than
906 * the best ones we had before
907 */
5baf8315 908 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 909 abs(codec_clk - last_clk)) {
910 pll_j = j; pll_d = 0;
911 pll_r = r; pll_p = p;
5baf8315 912 last_clk = tmp_clk;
255173b4
PM		 913 }
914
915 /* Early exit for exact matches */
5baf8315 916 if (tmp_clk == codec_clk)
255173b4
PM		 917 goto found;
918 }
919 }
4f9c16cc 920
255173b4
PM		 921 /* try with d != 0 */
922 for (p = 1; p <= 8; p++) {
923 j = codec_clk * p / 1000;
4f9c16cc 924
255173b4
PM		 925 if (j < 4 || j > 11)
926 continue;
4f9c16cc 927
255173b4
PM		 928 /* do not use codec_clk here since we'd loose precision */
929 d = ((2048 * p * fsref) - j * aic3x->sysclk)
930 * 100 / (aic3x->sysclk/100);
4f9c16cc 931
255173b4 932 clk = (10000 * j + d) / (10 * p);
4f9c16cc 933
255173b4
PM		 934 /* check whether this values get closer than the best
935 * ones we had before */
936 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
937 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
938 last_clk = clk;
4f9c16cc
DM		 939 }
940
255173b4
PM		 941 /* Early exit for exact matches */
942 if (clk == codec_clk)
943 goto found;
944 }
945
4f9c16cc
DM		 946 if (last_clk == 0) {
947 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
948 return -EINVAL;
949 }
44d0a879 950
255173b4 951found:
e18eca43
JN		 952 data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
953 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
954 data | (pll_p << PLLP_SHIFT));
955 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
956 pll_r << PLLR_SHIFT);
957 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
958 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
959 (pll_d >> 6) << PLLD_MSB_SHIFT);
960 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
961 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
44d0a879 962
44d0a879
VB		 963 return 0;
964}
965
e550e17f 966static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 967{
968 struct snd_soc_codec *codec = dai->codec;
e18eca43
JN		 969 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
970 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
44d0a879
VB		 971
972 if (mute) {
e18eca43
JN		 973 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
974 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
44d0a879 975 } else {
e18eca43
JN		 976 snd_soc_write(codec, LDAC_VOL, ldac_reg);
977 snd_soc_write(codec, RDAC_VOL, rdac_reg);
44d0a879
VB		 978 }
979
980 return 0;
981}
982
e550e17f 983static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 984 int clk_id, unsigned int freq, int dir)
985{
986 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 987 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 988
4f9c16cc
DM		 989 aic3x->sysclk = freq;
990 return 0;
44d0a879
VB		 991}
992
e550e17f 993static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 994 unsigned int fmt)
995{
996 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 997 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 998 u8 iface_areg, iface_breg;
a24f4f68 999 int delay = 0;
81971a14 1000
e18eca43
JN		 1001 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1002 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 1003
1004 /* set master/slave audio interface */
1005 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1006 case SND_SOC_DAIFMT_CBM_CFM:
1007 aic3x->master = 1;
1008 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1009 break;
1010 case SND_SOC_DAIFMT_CBS_CFS:
1011 aic3x->master = 0;
1012 break;
1013 default:
1014 return -EINVAL;
1015 }
1016
4b7d2831
JN		 1017 /*
1018 * match both interface format and signal polarities since they
1019 * are fixed
1020 */
1021 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1022 SND_SOC_DAIFMT_INV_MASK)) {
1023 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1024 break;
a24f4f68
TK		 1025 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1026 delay = 1;
4b7d2831 1027 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1028 iface_breg |= (0x01 << 6);
1029 break;
4b7d2831 1030 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1031 iface_breg |= (0x02 << 6);
1032 break;
4b7d2831 1033 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1034 iface_breg |= (0x03 << 6);
1035 break;
1036 default:
1037 return -EINVAL;
1038 }
1039
1040 /* set iface */
e18eca43
JN		 1041 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1042 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1043 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1044
1045 return 0;
1046}
1047
6c1a7d40
JN		 1048static int aic3x_init_3007(struct snd_soc_codec *codec)
1049{
1050 u8 tmp1, tmp2, *cache = codec->reg_cache;
1051
1052 /*
1053 * There is no need to cache writes to undocumented page 0xD but
1054 * respective page 0 register cache entries must be preserved
1055 */
1056 tmp1 = cache[0xD];
1057 tmp2 = cache[0x8];
1058 /* Class-D speaker driver init; datasheet p. 46 */
1059 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1060 snd_soc_write(codec, 0xD, 0x0D);
1061 snd_soc_write(codec, 0x8, 0x5C);
1062 snd_soc_write(codec, 0x8, 0x5D);
1063 snd_soc_write(codec, 0x8, 0x5C);
1064 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1065 cache[0xD] = tmp1;
1066 cache[0x8] = tmp2;
1067
1068 return 0;
1069}
1070
5a895f8a
JN		 1071static int aic3x_regulator_event(struct notifier_block *nb,
1072 unsigned long event, void *data)
1073{
1074 struct aic3x_disable_nb *disable_nb =
1075 container_of(nb, struct aic3x_disable_nb, nb);
1076 struct aic3x_priv *aic3x = disable_nb->aic3x;
1077
1078 if (event & REGULATOR_EVENT_DISABLE) {
1079 /*
1080 * Put codec to reset and require cache sync as at least one
1081 * of the supplies was disabled
1082 */
79ee820d 1083 if (gpio_is_valid(aic3x->gpio_reset))
5a895f8a
JN		 1084 gpio_set_value(aic3x->gpio_reset, 0);
1085 aic3x->codec->cache_sync = 1;
1086 }
1087
1088 return 0;
1089}
1090
6c1a7d40
JN		 1091static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1092{
1093 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1094 int i, ret;
1095 u8 *cache = codec->reg_cache;
1096
1097 if (power) {
1098 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1099 aic3x->supplies);
1100 if (ret)
1101 goto out;
1102 aic3x->power = 1;
5a895f8a
JN		 1103 /*
1104 * Reset release and cache sync is necessary only if some
1105 * supply was off or if there were cached writes
1106 */
1107 if (!codec->cache_sync)
1108 goto out;
1109
79ee820d 1110 if (gpio_is_valid(aic3x->gpio_reset)) {
6c1a7d40
JN		 1111 udelay(1);
1112 gpio_set_value(aic3x->gpio_reset, 1);
1113 }
1114
1115 /* Sync reg_cache with the hardware */
1116 codec->cache_only = 0;
508b7686 1117 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
6c1a7d40
JN		 1118 snd_soc_write(codec, i, cache[i]);
1119 if (aic3x->model == AIC3X_MODEL_3007)
1120 aic3x_init_3007(codec);
1121 codec->cache_sync = 0;
1122 } else {
1123 aic3x->power = 0;
5a895f8a
JN		 1124 /* HW writes are needless when bias is off */
1125 codec->cache_only = 1;
6c1a7d40
JN		 1126 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1127 aic3x->supplies);
1128 }
1129out:
1130 return ret;
1131}
1132
0be9898a
MB		 1133static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1134 enum snd_soc_bias_level level)
44d0a879 1135{
b2c812e2 1136 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879
VB		 1137 u8 reg;
1138
0be9898a
MB		 1139 switch (level) {
1140 case SND_SOC_BIAS_ON:
db13802e
JN		 1141 break;
1142 case SND_SOC_BIAS_PREPARE:
ce6120cc 1143 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
c23fd751 1144 aic3x->master) {
44d0a879 1145 /* enable pll */
e18eca43
JN		 1146 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1147 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1148 reg | PLL_ENABLE);
44d0a879
VB		 1149 }
1150 break;
0be9898a 1151 case SND_SOC_BIAS_STANDBY:
6c1a7d40
JN		 1152 if (!aic3x->power)
1153 aic3x_set_power(codec, 1);
ce6120cc 1154 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
c23fd751 1155 aic3x->master) {
44d0a879 1156 /* disable pll */
e18eca43
JN		 1157 reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
1158 snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
1159 reg & ~PLL_ENABLE);
44d0a879
VB		 1160 }
1161 break;
c23fd751 1162 case SND_SOC_BIAS_OFF:
6c1a7d40
JN		 1163 if (aic3x->power)
1164 aic3x_set_power(codec, 0);
c23fd751 1165 break;
44d0a879 1166 }
ce6120cc 1167 codec->dapm.bias_level = level;
44d0a879
VB		 1168
1169 return 0;
1170}
1171
54e7e616
DM		 1172void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1173{
1174 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1175 u8 bit = gpio ? 3: 0;
e18eca43
JN		 1176 u8 val = snd_soc_read(codec, reg) & ~(1 << bit);
1177 snd_soc_write(codec, reg, val | (!!state << bit));
54e7e616
DM		 1178}
1179EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1180
1181int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1182{
1183 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
fe99b559 1184 u8 val = 0, bit = gpio ? 2 : 1;
54e7e616
DM		 1185
1186 aic3x_read(codec, reg, &val);
1187 return (val >> bit) & 1;
1188}
1189EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1190
6f2a974b
DM		 1191void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1192 int headset_debounce, int button_debounce)
1193{
1194 u8 val;
1195
1196 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1197 << AIC3X_HEADSET_DETECT_SHIFT) |
1198 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1199 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1200 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1201 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1202
1203 if (detect & AIC3X_HEADSET_DETECT_MASK)
1204 val |= AIC3X_HEADSET_DETECT_ENABLED;
1205
e18eca43 1206 snd_soc_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
6f2a974b
DM		 1207}
1208EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1209
54e7e616
DM		 1210int aic3x_headset_detected(struct snd_soc_codec *codec)
1211{
fe99b559 1212 u8 val = 0;
6f2a974b
DM		 1213 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1214 return (val >> 4) & 1;
54e7e616
DM		 1215}
1216EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1217
6f2a974b
DM		 1218int aic3x_button_pressed(struct snd_soc_codec *codec)
1219{
fe99b559 1220 u8 val = 0;
6f2a974b
DM		 1221 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1222 return (val >> 5) & 1;
1223}
1224EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1225
44d0a879
VB		 1226#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1227#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1228 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1229
6335d055
EM		 1230static struct snd_soc_dai_ops aic3x_dai_ops = {
1231 .hw_params = aic3x_hw_params,
1232 .digital_mute = aic3x_mute,
1233 .set_sysclk = aic3x_set_dai_sysclk,
1234 .set_fmt = aic3x_set_dai_fmt,
1235};
1236
f0fba2ad
LG		 1237static struct snd_soc_dai_driver aic3x_dai = {
1238 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1239 .playback = {
1240 .stream_name = "Playback",
1241 .channels_min = 1,
1242 .channels_max = 2,
1243 .rates = AIC3X_RATES,
1244 .formats = AIC3X_FORMATS,},
1245 .capture = {
1246 .stream_name = "Capture",
1247 .channels_min = 1,
1248 .channels_max = 2,
1249 .rates = AIC3X_RATES,
1250 .formats = AIC3X_FORMATS,},
6335d055 1251 .ops = &aic3x_dai_ops,
14017615 1252 .symmetric_rates = 1,
44d0a879 1253};
44d0a879 1254
f0fba2ad 1255static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
44d0a879 1256{
0be9898a 1257 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1258
1259 return 0;
1260}
1261
f0fba2ad 1262static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1263{
29e189c2 1264 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1265
1266 return 0;
1267}
1268
1269/*
1270 * initialise the AIC3X driver
1271 * register the mixer and dsp interfaces with the kernel
1272 */
cb3826f5 1273static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1274{
6184f105 1275 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5
BD		 1276 int reg;
1277
e18eca43
JN		 1278 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1279 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
44d0a879 1280
44d0a879 1281 /* DAC default volume and mute */
e18eca43
JN		 1282 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1283 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
44d0a879
VB		 1284
1285 /* DAC to HP default volume and route to Output mixer */
e18eca43
JN		 1286 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1287 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1288 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1289 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1290 /* DAC to Line Out default volume and route to Output mixer */
e18eca43
JN		 1291 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1292 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879 1293 /* DAC to Mono Line Out default volume and route to Output mixer */
e18eca43
JN		 1294 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1295 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
44d0a879
VB		 1296
1297 /* unmute all outputs */
e18eca43
JN		 1298 reg = snd_soc_read(codec, LLOPM_CTRL);
1299 snd_soc_write(codec, LLOPM_CTRL, reg | UNMUTE);
1300 reg = snd_soc_read(codec, RLOPM_CTRL);
1301 snd_soc_write(codec, RLOPM_CTRL, reg | UNMUTE);
1302 reg = snd_soc_read(codec, MONOLOPM_CTRL);
1303 snd_soc_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1304 reg = snd_soc_read(codec, HPLOUT_CTRL);
1305 snd_soc_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1306 reg = snd_soc_read(codec, HPROUT_CTRL);
1307 snd_soc_write(codec, HPROUT_CTRL, reg | UNMUTE);
1308 reg = snd_soc_read(codec, HPLCOM_CTRL);
1309 snd_soc_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1310 reg = snd_soc_read(codec, HPRCOM_CTRL);
1311 snd_soc_write(codec, HPRCOM_CTRL, reg | UNMUTE);
44d0a879
VB		 1312
1313 /* ADC default volume and unmute */
e18eca43
JN		 1314 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1315 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
44d0a879 1316 /* By default route Line1 to ADC PGA mixer */
e18eca43
JN		 1317 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1318 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
44d0a879
VB		 1319
1320 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1321 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1322 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1323 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1324 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1325 /* PGA to Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1326 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1327 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1328 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1329 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1330 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879
VB		 1331
1332 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
e18eca43
JN		 1333 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1334 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1335 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1336 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
44d0a879 1337 /* Line2 Line Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1338 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1339 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
44d0a879 1340 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
e18eca43
JN		 1341 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1342 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
44d0a879 1343
6184f105 1344 if (aic3x->model == AIC3X_MODEL_3007) {
6c1a7d40 1345 aic3x_init_3007(codec);
e18eca43 1346 snd_soc_write(codec, CLASSD_CTRL, 0);
6184f105
RC		 1347 }
1348
cb3826f5
BD		 1349 return 0;
1350}
54e7e616 1351
414c73ab
JN		 1352static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1353{
1354 struct aic3x_priv *a;
1355
1356 list_for_each_entry(a, &reset_list, list) {
1357 if (gpio_is_valid(aic3x->gpio_reset) &&
1358 aic3x->gpio_reset == a->gpio_reset)
1359 return true;
1360 }
1361
1362 return false;
1363}
1364
f0fba2ad 1365static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1366{
f0fba2ad 1367 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
2f24111a 1368 int ret, i;
f0fba2ad 1369
414c73ab 1370 INIT_LIST_HEAD(&aic3x->list);
f0fba2ad 1371 codec->control_data = aic3x->control_data;
5a895f8a 1372 aic3x->codec = codec;
ce6120cc 1373 codec->dapm.idle_bias_off = 1;
cb3826f5 1374
a84a441b
JN		 1375 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1376 if (ret != 0) {
1377 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1378 return ret;
1379 }
1380
414c73ab
JN		 1381 if (gpio_is_valid(aic3x->gpio_reset) &&
1382 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1383 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1384 if (ret != 0)
1385 goto err_gpio;
1386 gpio_direction_output(aic3x->gpio_reset, 0);
1387 }
1388
1389 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1390 aic3x->supplies[i].supply = aic3x_supply_names[i];
1391
1392 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1393 aic3x->supplies);
1394 if (ret != 0) {
1395 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1396 goto err_get;
1397 }
5a895f8a
JN		 1398 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1399 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1400 aic3x->disable_nb[i].aic3x = aic3x;
1401 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1402 &aic3x->disable_nb[i].nb);
1403 if (ret) {
1404 dev_err(codec->dev,
1405 "Failed to request regulator notifier: %d\n",
1406 ret);
1407 goto err_notif;
1408 }
1409 }
2f24111a 1410
7d1be0a6 1411 codec->cache_only = 1;
37b47656
JN		 1412 aic3x_init(codec);
1413
f0fba2ad
LG		 1414 if (aic3x->setup) {
1415 /* setup GPIO functions */
e18eca43
JN		 1416 snd_soc_write(codec, AIC3X_GPIO1_REG,
1417 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1418 snd_soc_write(codec, AIC3X_GPIO2_REG,
1419 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1420 }
1421
f0fba2ad
LG		 1422 snd_soc_add_controls(codec, aic3x_snd_controls,
1423 ARRAY_SIZE(aic3x_snd_controls));
6184f105
RC		 1424 if (aic3x->model == AIC3X_MODEL_3007)
1425 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1426
f0fba2ad 1427 aic3x_add_widgets(codec);
414c73ab 1428 list_add(&aic3x->list, &reset_list);
cb3826f5
BD		 1429
1430 return 0;
2f24111a 1431
5a895f8a
JN		 1432err_notif:
1433 while (i--)
1434 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1435 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1436 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1437err_get:
414c73ab
JN		 1438 if (gpio_is_valid(aic3x->gpio_reset) &&
1439 !aic3x_is_shared_reset(aic3x))
2f24111a
JN		 1440 gpio_free(aic3x->gpio_reset);
1441err_gpio:
2f24111a 1442 return ret;
44d0a879
VB		 1443}
1444
f0fba2ad 1445static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1446{
2f24111a 1447 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
5a895f8a 1448 int i;
2f24111a 1449
f0fba2ad 1450 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
414c73ab
JN		 1451 list_del(&aic3x->list);
1452 if (gpio_is_valid(aic3x->gpio_reset) &&
1453 !aic3x_is_shared_reset(aic3x)) {
2f24111a
JN		 1454 gpio_set_value(aic3x->gpio_reset, 0);
1455 gpio_free(aic3x->gpio_reset);
1456 }
5a895f8a
JN		 1457 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1458 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1459 &aic3x->disable_nb[i].nb);
2f24111a
JN		 1460 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1461
cb3826f5
BD		 1462 return 0;
1463}
44d0a879 1464
f0fba2ad 1465static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
f0fba2ad
LG		 1466 .set_bias_level = aic3x_set_bias_level,
1467 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1468 .reg_word_size = sizeof(u8),
1469 .reg_cache_default = aic3x_reg,
1470 .probe = aic3x_probe,
1471 .remove = aic3x_remove,
1472 .suspend = aic3x_suspend,
1473 .resume = aic3x_resume,
1474};
1475
44d0a879
VB		 1476#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1477/*
1478 * AIC3X 2 wire address can be up to 4 devices with device addresses
1479 * 0x18, 0x19, 0x1A, 0x1B
1480 */
44d0a879 1481
6184f105
RC		 1482static const struct i2c_device_id aic3x_i2c_id[] = {
1483 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
1484 [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
1485 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
1486 { }
1487};
1488MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1489
44d0a879
VB		 1490/*
1491 * If the i2c layer weren't so broken, we could pass this kind of data
1492 * around
1493 */
ba8ed121
JD		 1494static int aic3x_i2c_probe(struct i2c_client *i2c,
1495 const struct i2c_device_id *id)
44d0a879 1496{
5193d62f 1497 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1498 struct aic3x_priv *aic3x;
2f24111a 1499 int ret;
6184f105 1500 const struct i2c_device_id *tbl;
44d0a879 1501
cb3826f5
BD		 1502 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1503 if (aic3x == NULL) {
1504 dev_err(&i2c->dev, "failed to create private data\n");
1505 return -ENOMEM;
1506 }
1507
f0fba2ad 1508 aic3x->control_data = i2c;
a84a441b
JN		 1509 aic3x->control_type = SND_SOC_I2C;
1510
cb3826f5 1511 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1512 if (pdata) {
1513 aic3x->gpio_reset = pdata->gpio_reset;
1514 aic3x->setup = pdata->setup;
1515 } else {
1516 aic3x->gpio_reset = -1;
1517 }
cb3826f5 1518
6184f105
RC		 1519 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
1520 if (!strcmp(tbl->name, id->name))
1521 break;
1522 }
1523 aic3x->model = tbl - aic3x_i2c_id;
1524
f0fba2ad
LG		 1525 ret = snd_soc_register_codec(&i2c->dev,
1526 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1527 if (ret < 0)
2f24111a 1528 kfree(aic3x);
07779fdd 1529 return ret;
44d0a879
VB		 1530}
1531
ba8ed121 1532static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1533{
f0fba2ad
LG		 1534 snd_soc_unregister_codec(&client->dev);
1535 kfree(i2c_get_clientdata(client));
1536 return 0;
44d0a879
VB		 1537}
1538
44d0a879
VB		 1539/* machine i2c codec control layer */
1540static struct i2c_driver aic3x_i2c_driver = {
1541 .driver = {
f0fba2ad 1542 .name = "tlv320aic3x-codec",
44d0a879
VB		 1543 .owner = THIS_MODULE,
1544 },
cb3826f5 1545 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1546 .remove = aic3x_i2c_remove,
1547 .id_table = aic3x_i2c_id,
44d0a879
VB		 1548};
1549#endif
1550
f0fba2ad 1551static int __init aic3x_modinit(void)
44d0a879 1552{
44d0a879 1553 int ret = 0;
f0fba2ad
LG		 1554#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1555 ret = i2c_add_driver(&aic3x_i2c_driver);
1556 if (ret != 0) {
1557 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1558 ret);
44d0a879 1559 }
f0fba2ad 1560#endif
44d0a879
VB		 1561 return ret;
1562}
64089b84
MB		 1563module_init(aic3x_modinit);
1564
1565static void __exit aic3x_exit(void)
1566{
f0fba2ad
LG		 1567#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1568 i2c_del_driver(&aic3x_i2c_driver);
1569#endif
64089b84
MB		 1570}
1571module_exit(aic3x_exit);
1572
44d0a879
VB		 1573MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1574MODULE_AUTHOR("Vladimir Barinov");
1575MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)