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OMAP: McBSP: Fix static function warning
[linux-2.6-block.git] / sound / soc / codecs / tlv320aic3x.c
CommitLineData
44d0a879
VB		 1/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
d6b52039 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
44d0a879
VB		 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Notes:
14 * The AIC3X is a driver for a low power stereo audio
6184f105 15 * codecs aic31, aic32, aic33, aic3007.
44d0a879
VB		 16 *
17 * It supports full aic33 codec functionality.
6184f105
RC		 18 * The compatibility with aic32, aic31 and aic3007 is as follows:
19 * aic32/aic3007 | aic31
44d0a879
VB		 20 * ---------------------------------------
21 * MONO_LOUT -> N/A | MONO_LOUT -> N/A
22 * | IN1L -> LINE1L
23 * | IN1R -> LINE1R
24 * | IN2L -> LINE2L
25 * | IN2R -> LINE2R
26 * | MIC3L/R -> N/A
27 * truncated internal functionality in
28 * accordance with documentation
29 * ---------------------------------------
30 *
31 * Hence the machine layer should disable unsupported inputs/outputs by
a5302181 32 * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
44d0a879
VB		 33 */
34
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
5193d62f 41#include <linux/gpio.h>
07779fdd 42#include <linux/regulator/consumer.h>
44d0a879 43#include <linux/platform_device.h>
5a0e3ad6 44#include <linux/slab.h>
44d0a879
VB		 45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
49#include <sound/soc-dapm.h>
50#include <sound/initval.h>
7565fc38 51#include <sound/tlv.h>
5193d62f 52#include <sound/tlv320aic3x.h>
44d0a879
VB		 53
54#include "tlv320aic3x.h"
55
07779fdd
JN		 56#define AIC3X_NUM_SUPPLIES 4
57static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
58 "IOVDD", /* I/O Voltage */
59 "DVDD", /* Digital Core Voltage */
60 "AVDD", /* Analog DAC Voltage */
61 "DRVDD", /* ADC Analog and Output Driver Voltage */
62};
44d0a879
VB		 63
64/* codec private data */
65struct aic3x_priv {
07779fdd 66 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
f0fba2ad
LG		 67 enum snd_soc_control_type control_type;
68 struct aic3x_setup_data *setup;
69 void *control_data;
44d0a879
VB		 70 unsigned int sysclk;
71 int master;
5193d62f 72 int gpio_reset;
6184f105
RC		 73#define AIC3X_MODEL_3X 0
74#define AIC3X_MODEL_33 1
75#define AIC3X_MODEL_3007 2
76 u16 model;
44d0a879
VB		 77};
78
79/*
80 * AIC3X register cache
81 * We can't read the AIC3X register space when we are
82 * using 2 wire for device control, so we cache them instead.
83 * There is no point in caching the reset register
84 */
85static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
86 0x00, 0x00, 0x00, 0x10, /* 0 */
87 0x04, 0x00, 0x00, 0x00, /* 4 */
88 0x00, 0x00, 0x00, 0x01, /* 8 */
89 0x00, 0x00, 0x00, 0x80, /* 12 */
90 0x80, 0xff, 0xff, 0x78, /* 16 */
91 0x78, 0x78, 0x78, 0x78, /* 20 */
92 0x78, 0x00, 0x00, 0xfe, /* 24 */
93 0x00, 0x00, 0xfe, 0x00, /* 28 */
94 0x18, 0x18, 0x00, 0x00, /* 32 */
95 0x00, 0x00, 0x00, 0x00, /* 36 */
96 0x00, 0x00, 0x00, 0x80, /* 40 */
97 0x80, 0x00, 0x00, 0x00, /* 44 */
98 0x00, 0x00, 0x00, 0x04, /* 48 */
99 0x00, 0x00, 0x00, 0x00, /* 52 */
100 0x00, 0x00, 0x04, 0x00, /* 56 */
101 0x00, 0x00, 0x00, 0x00, /* 60 */
102 0x00, 0x04, 0x00, 0x00, /* 64 */
103 0x00, 0x00, 0x00, 0x00, /* 68 */
104 0x04, 0x00, 0x00, 0x00, /* 72 */
105 0x00, 0x00, 0x00, 0x00, /* 76 */
106 0x00, 0x00, 0x00, 0x00, /* 80 */
107 0x00, 0x00, 0x00, 0x00, /* 84 */
108 0x00, 0x00, 0x00, 0x00, /* 88 */
109 0x00, 0x00, 0x00, 0x00, /* 92 */
110 0x00, 0x00, 0x00, 0x00, /* 96 */
111 0x00, 0x00, 0x02, /* 100 */
112};
113
114/*
115 * read aic3x register cache
116 */
117static inline unsigned int aic3x_read_reg_cache(struct snd_soc_codec *codec,
118 unsigned int reg)
119{
120 u8 *cache = codec->reg_cache;
121 if (reg >= AIC3X_CACHEREGNUM)
122 return -1;
123 return cache[reg];
124}
125
126/*
127 * write aic3x register cache
128 */
129static inline void aic3x_write_reg_cache(struct snd_soc_codec *codec,
130 u8 reg, u8 value)
131{
132 u8 *cache = codec->reg_cache;
133 if (reg >= AIC3X_CACHEREGNUM)
134 return;
135 cache[reg] = value;
136}
137
138/*
139 * write to the aic3x register space
140 */
141static int aic3x_write(struct snd_soc_codec *codec, unsigned int reg,
142 unsigned int value)
143{
144 u8 data[2];
145
146 /* data is
147 * D15..D8 aic3x register offset
148 * D7...D0 register data
149 */
150 data[0] = reg & 0xff;
151 data[1] = value & 0xff;
152
153 aic3x_write_reg_cache(codec, data[0], data[1]);
154 if (codec->hw_write(codec->control_data, data, 2) == 2)
155 return 0;
156 else
157 return -EIO;
158}
159
54e7e616
DM		 160/*
161 * read from the aic3x register space
162 */
163static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg,
164 u8 *value)
165{
166 *value = reg & 0xff;
5f345346
MB		 167
168 value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
54e7e616
DM		 169
170 aic3x_write_reg_cache(codec, reg, *value);
171 return 0;
172}
173
44d0a879
VB		 174#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
175{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
176 .info = snd_soc_info_volsw, \
177 .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \
178 .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) }
179
180/*
181 * All input lines are connected when !0xf and disconnected with 0xf bit field,
182 * so we have to use specific dapm_put call for input mixer
183 */
184static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
185 struct snd_ctl_elem_value *ucontrol)
186{
187 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
4453dba5
EN		 188 struct soc_mixer_control *mc =
189 (struct soc_mixer_control *)kcontrol->private_value;
190 unsigned int reg = mc->reg;
191 unsigned int shift = mc->shift;
192 int max = mc->max;
193 unsigned int mask = (1 << fls(max)) - 1;
194 unsigned int invert = mc->invert;
44d0a879
VB		 195 unsigned short val, val_mask;
196 int ret;
197 struct snd_soc_dapm_path *path;
198 int found = 0;
199
200 val = (ucontrol->value.integer.value[0] & mask);
201
202 mask = 0xf;
203 if (val)
204 val = mask;
205
206 if (invert)
207 val = mask - val;
208 val_mask = mask << shift;
209 val = val << shift;
210
211 mutex_lock(&widget->codec->mutex);
212
213 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
214 /* find dapm widget path assoc with kcontrol */
215 list_for_each_entry(path, &widget->codec->dapm_paths, list) {
216 if (path->kcontrol != kcontrol)
217 continue;
218
219 /* found, now check type */
220 found = 1;
221 if (val)
222 /* new connection */
223 path->connect = invert ? 0 : 1;
224 else
225 /* old connection must be powered down */
226 path->connect = invert ? 1 : 0;
227 break;
228 }
229
230 if (found)
a5302181 231 snd_soc_dapm_sync(widget->codec);
44d0a879
VB		 232 }
233
234 ret = snd_soc_update_bits(widget->codec, reg, val_mask, val);
235
236 mutex_unlock(&widget->codec->mutex);
237 return ret;
238}
239
240static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
241static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
242static const char *aic3x_left_hpcom_mux[] =
243 { "differential of HPLOUT", "constant VCM", "single-ended" };
244static const char *aic3x_right_hpcom_mux[] =
245 { "differential of HPROUT", "constant VCM", "single-ended",
246 "differential of HPLCOM", "external feedback" };
247static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
4d20f70a
JN		 248static const char *aic3x_adc_hpf[] =
249 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
44d0a879
VB		 250
251#define LDAC_ENUM 0
252#define RDAC_ENUM 1
253#define LHPCOM_ENUM 2
254#define RHPCOM_ENUM 3
255#define LINE1L_ENUM 4
256#define LINE1R_ENUM 5
257#define LINE2L_ENUM 6
258#define LINE2R_ENUM 7
4d20f70a 259#define ADC_HPF_ENUM 8
44d0a879
VB		 260
261static const struct soc_enum aic3x_enum[] = {
262 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
263 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
264 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
265 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
266 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
267 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
268 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
269 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
4d20f70a 270 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
44d0a879
VB		 271};
272
7565fc38
JN		 273/*
274 * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
275 */
276static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
277/* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
278static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
279/*
280 * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
281 * Step size is approximately 0.5 dB over most of the scale but increasing
282 * near the very low levels.
283 * Define dB scale so that it is mostly correct for range about -55 to 0 dB
284 * but having increasing dB difference below that (and where it doesn't count
285 * so much). This setting shows -50 dB (actual is -50.3 dB) for register
286 * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
287 */
288static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
289
44d0a879
VB		 290static const struct snd_kcontrol_new aic3x_snd_controls[] = {
291 /* Output */
7565fc38
JN		 292 SOC_DOUBLE_R_TLV("PCM Playback Volume",
293 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
44d0a879 294
098b1718
JN		 295 /*
296 * Output controls that map to output mixer switches. Note these are
297 * only for swapped L-to-R and R-to-L routes. See below stereo controls
298 * for direct L-to-L and R-to-R routes.
299 */
300 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
301 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
302 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
303 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
304 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
305 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
306
307 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
308 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
309 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
310 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
311 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
312 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
313
314 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
315 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
316 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
317 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
318 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
319 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
320
321 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
322 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
323 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
324 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
325 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
326 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
327
328 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
329 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
330 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
331 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
332 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
333 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
334
335 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
336 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
337 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
338 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
339 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
340 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
341
342 /* Stereo output controls for direct L-to-L and R-to-R routes */
343 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
344 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
345 0, 118, 1, output_stage_tlv),
346 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
347 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
348 0, 118, 1, output_stage_tlv),
7565fc38
JN		 349 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
350 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
351 0, 118, 1, output_stage_tlv),
098b1718
JN		 352
353 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
354 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
7565fc38 355 0, 118, 1, output_stage_tlv),
098b1718
JN		 356 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
357 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
7565fc38 358 0, 118, 1, output_stage_tlv),
7565fc38
JN		 359 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
360 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
361 0, 118, 1, output_stage_tlv),
098b1718
JN		 362
363 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
364 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
7565fc38 365 0, 118, 1, output_stage_tlv),
098b1718
JN		 366 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
367 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
7565fc38 368 0, 118, 1, output_stage_tlv),
7565fc38
JN		 369 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
370 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
371 0, 118, 1, output_stage_tlv),
098b1718
JN		 372
373 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
374 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
7565fc38 375 0, 118, 1, output_stage_tlv),
098b1718
JN		 376 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
377 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
7565fc38 378 0, 118, 1, output_stage_tlv),
7565fc38
JN		 379 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
380 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
381 0, 118, 1, output_stage_tlv),
098b1718
JN		 382
383 /* Output pin mute controls */
384 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
385 0x01, 0),
386 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
387 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
388 0x01, 0),
f9bc0297 389 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
44d0a879 390 0x01, 0),
44d0a879
VB		 391
392 /*
393 * Note: enable Automatic input Gain Controller with care. It can
394 * adjust PGA to max value when ADC is on and will never go back.
395 */
396 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
397
398 /* Input */
7565fc38
JN		 399 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
400 0, 119, 0, adc_tlv),
44d0a879 401 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
4d20f70a
JN		 402
403 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
44d0a879
VB		 404};
405
6184f105
RC		 406/*
407 * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
408 */
409static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
410
411static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
412 SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
413
44d0a879
VB		 414/* Left DAC Mux */
415static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
416SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
417
418/* Right DAC Mux */
419static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
420SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
421
422/* Left HPCOM Mux */
423static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
424SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
425
426/* Right HPCOM Mux */
427static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
428SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
429
c3b79e05
JN		 430/* Left Line Mixer */
431static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
432 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
433 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
434 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
435 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
436 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
437 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
44d0a879
VB		 438};
439
c3b79e05
JN		 440/* Right Line Mixer */
441static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
442 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
443 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
444 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
445 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
446 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
447 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
448};
449
450/* Mono Mixer */
451static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
452 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
453 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
454 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
458};
459
460/* Left HP Mixer */
461static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
462 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
463 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
464 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
465 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
466 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
468};
469
470/* Right HP Mixer */
471static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
472 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
473 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
474 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
475 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
476 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
477 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
478};
479
480/* Left HPCOM Mixer */
481static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
482 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
483 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
484 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
485 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
486 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
487 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
488};
489
490/* Right HPCOM Mixer */
491static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
492 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
493 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
494 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
495 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
496 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
497 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
44d0a879
VB		 498};
499
500/* Left PGA Mixer */
501static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
502 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
54f01916 503 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
44d0a879
VB		 504 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
505 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
54f01916 506 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
44d0a879
VB		 507};
508
509/* Right PGA Mixer */
510static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
511 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
54f01916 512 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
44d0a879 513 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
54f01916 514 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
44d0a879
VB		 515 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
516};
517
518/* Left Line1 Mux */
519static const struct snd_kcontrol_new aic3x_left_line1_mux_controls =
520SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_ENUM]);
521
522/* Right Line1 Mux */
523static const struct snd_kcontrol_new aic3x_right_line1_mux_controls =
524SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_ENUM]);
525
526/* Left Line2 Mux */
527static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
528SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
529
530/* Right Line2 Mux */
531static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
532SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
533
44d0a879
VB		 534static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
535 /* Left DAC to Left Outputs */
536 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
537 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
538 &aic3x_left_dac_mux_controls),
44d0a879
VB		 539 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
540 &aic3x_left_hpcom_mux_controls),
541 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
542 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
543 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
544
545 /* Right DAC to Right Outputs */
546 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
547 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
548 &aic3x_right_dac_mux_controls),
44d0a879
VB		 549 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
550 &aic3x_right_hpcom_mux_controls),
551 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
552 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
553 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
554
555 /* Mono Output */
556 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
557
54f01916 558 /* Inputs to Left ADC */
44d0a879
VB		 559 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
560 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
561 &aic3x_left_pga_mixer_controls[0],
562 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
563 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
564 &aic3x_left_line1_mux_controls),
54f01916
DM		 565 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
566 &aic3x_left_line1_mux_controls),
44d0a879
VB		 567 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
568 &aic3x_left_line2_mux_controls),
569
54f01916 570 /* Inputs to Right ADC */
44d0a879
VB		 571 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
572 LINE1R_2_RADC_CTRL, 2, 0),
573 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
574 &aic3x_right_pga_mixer_controls[0],
575 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
54f01916
DM		 576 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
577 &aic3x_right_line1_mux_controls),
44d0a879
VB		 578 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
579 &aic3x_right_line1_mux_controls),
580 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
581 &aic3x_right_line2_mux_controls),
582
ee15ffdb
JN		 583 /*
584 * Not a real mic bias widget but similar function. This is for dynamic
585 * control of GPIO1 digital mic modulator clock output function when
586 * using digital mic.
587 */
588 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
589 AIC3X_GPIO1_REG, 4, 0xf,
590 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
591 AIC3X_GPIO1_FUNC_DISABLED),
592
593 /*
594 * Also similar function like mic bias. Selects digital mic with
595 * configurable oversampling rate instead of ADC converter.
596 */
597 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
598 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
599 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
600 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
601 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
602 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
603
44d0a879 604 /* Mic Bias */
0bd72a3d
JN		 605 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V",
606 MICBIAS_CTRL, 6, 3, 1, 0),
607 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V",
608 MICBIAS_CTRL, 6, 3, 2, 0),
609 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD",
610 MICBIAS_CTRL, 6, 3, 3, 0),
44d0a879 611
c3b79e05
JN		 612 /* Output mixers */
613 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
614 &aic3x_left_line_mixer_controls[0],
615 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
616 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
617 &aic3x_right_line_mixer_controls[0],
618 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
619 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
620 &aic3x_mono_mixer_controls[0],
621 ARRAY_SIZE(aic3x_mono_mixer_controls)),
622 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
623 &aic3x_left_hp_mixer_controls[0],
624 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
625 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
626 &aic3x_right_hp_mixer_controls[0],
627 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
628 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
629 &aic3x_left_hpcom_mixer_controls[0],
630 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
631 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
632 &aic3x_right_hpcom_mixer_controls[0],
633 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
44d0a879
VB		 634
635 SND_SOC_DAPM_OUTPUT("LLOUT"),
636 SND_SOC_DAPM_OUTPUT("RLOUT"),
637 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
638 SND_SOC_DAPM_OUTPUT("HPLOUT"),
639 SND_SOC_DAPM_OUTPUT("HPROUT"),
640 SND_SOC_DAPM_OUTPUT("HPLCOM"),
641 SND_SOC_DAPM_OUTPUT("HPRCOM"),
642
643 SND_SOC_DAPM_INPUT("MIC3L"),
644 SND_SOC_DAPM_INPUT("MIC3R"),
645 SND_SOC_DAPM_INPUT("LINE1L"),
646 SND_SOC_DAPM_INPUT("LINE1R"),
647 SND_SOC_DAPM_INPUT("LINE2L"),
648 SND_SOC_DAPM_INPUT("LINE2R"),
649};
650
6184f105
RC		 651static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
652 /* Class-D outputs */
653 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
654 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
655
656 SND_SOC_DAPM_OUTPUT("SPOP"),
657 SND_SOC_DAPM_OUTPUT("SPOM"),
658};
659
d0cc0d3a 660static const struct snd_soc_dapm_route intercon[] = {
44d0a879
VB		 661 /* Left Input */
662 {"Left Line1L Mux", "single-ended", "LINE1L"},
663 {"Left Line1L Mux", "differential", "LINE1L"},
664
665 {"Left Line2L Mux", "single-ended", "LINE2L"},
666 {"Left Line2L Mux", "differential", "LINE2L"},
667
668 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
54f01916 669 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
44d0a879
VB		 670 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
671 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
54f01916 672 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
44d0a879
VB		 673
674 {"Left ADC", NULL, "Left PGA Mixer"},
ee15ffdb 675 {"Left ADC", NULL, "GPIO1 dmic modclk"},
44d0a879
VB		 676
677 /* Right Input */
678 {"Right Line1R Mux", "single-ended", "LINE1R"},
679 {"Right Line1R Mux", "differential", "LINE1R"},
680
681 {"Right Line2R Mux", "single-ended", "LINE2R"},
682 {"Right Line2R Mux", "differential", "LINE2R"},
683
54f01916 684 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
44d0a879
VB		 685 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
686 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
54f01916 687 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
44d0a879
VB		 688 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
689
690 {"Right ADC", NULL, "Right PGA Mixer"},
ee15ffdb 691 {"Right ADC", NULL, "GPIO1 dmic modclk"},
44d0a879 692
ee15ffdb
JN		 693 /*
694 * Logical path between digital mic enable and GPIO1 modulator clock
695 * output function
696 */
697 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
698 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
699 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
c3b79e05
JN		 700
701 /* Left DAC Output */
702 {"Left DAC Mux", "DAC_L1", "Left DAC"},
703 {"Left DAC Mux", "DAC_L2", "Left DAC"},
704 {"Left DAC Mux", "DAC_L3", "Left DAC"},
705
706 /* Right DAC Output */
707 {"Right DAC Mux", "DAC_R1", "Right DAC"},
708 {"Right DAC Mux", "DAC_R2", "Right DAC"},
709 {"Right DAC Mux", "DAC_R3", "Right DAC"},
710
711 /* Left Line Output */
712 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
713 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
714 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
715 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
716 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
717 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
718
719 {"Left Line Out", NULL, "Left Line Mixer"},
720 {"Left Line Out", NULL, "Left DAC Mux"},
721 {"LLOUT", NULL, "Left Line Out"},
722
723 /* Right Line Output */
724 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
725 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
726 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
727 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
728 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
729 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
730
731 {"Right Line Out", NULL, "Right Line Mixer"},
732 {"Right Line Out", NULL, "Right DAC Mux"},
733 {"RLOUT", NULL, "Right Line Out"},
734
735 /* Mono Output */
736 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
737 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
738 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
739 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
740 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
741 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
742
743 {"Mono Out", NULL, "Mono Mixer"},
744 {"MONO_LOUT", NULL, "Mono Out"},
745
746 /* Left HP Output */
747 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
748 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
749 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
750 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
751 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
752 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
753
754 {"Left HP Out", NULL, "Left HP Mixer"},
755 {"Left HP Out", NULL, "Left DAC Mux"},
756 {"HPLOUT", NULL, "Left HP Out"},
757
758 /* Right HP Output */
759 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
760 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
761 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
762 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
763 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
764 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
765
766 {"Right HP Out", NULL, "Right HP Mixer"},
767 {"Right HP Out", NULL, "Right DAC Mux"},
768 {"HPROUT", NULL, "Right HP Out"},
769
770 /* Left HPCOM Output */
771 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
772 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
773 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
774 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
775 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
776 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
777
778 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
779 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
780 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
781 {"Left HP Com", NULL, "Left HPCOM Mux"},
782 {"HPLCOM", NULL, "Left HP Com"},
783
784 /* Right HPCOM Output */
785 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
786 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
787 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
788 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
789 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
790 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
791
792 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
793 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
794 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
795 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
796 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
797 {"Right HP Com", NULL, "Right HPCOM Mux"},
798 {"HPRCOM", NULL, "Right HP Com"},
44d0a879
VB		 799};
800
6184f105
RC		 801static const struct snd_soc_dapm_route intercon_3007[] = {
802 /* Class-D outputs */
803 {"Left Class-D Out", NULL, "Left Line Out"},
804 {"Right Class-D Out", NULL, "Left Line Out"},
805 {"SPOP", NULL, "Left Class-D Out"},
806 {"SPOM", NULL, "Right Class-D Out"},
807};
808
44d0a879
VB		 809static int aic3x_add_widgets(struct snd_soc_codec *codec)
810{
6184f105
RC		 811 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
812
d0cc0d3a
MB		 813 snd_soc_dapm_new_controls(codec, aic3x_dapm_widgets,
814 ARRAY_SIZE(aic3x_dapm_widgets));
44d0a879
VB		 815
816 /* set up audio path interconnects */
d0cc0d3a 817 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
44d0a879 818
6184f105
RC		 819 if (aic3x->model == AIC3X_MODEL_3007) {
820 snd_soc_dapm_new_controls(codec, aic3007_dapm_widgets,
821 ARRAY_SIZE(aic3007_dapm_widgets));
822 snd_soc_dapm_add_routes(codec, intercon_3007, ARRAY_SIZE(intercon_3007));
823 }
824
44d0a879
VB		 825 return 0;
826}
827
44d0a879 828static int aic3x_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 829 struct snd_pcm_hw_params *params,
830 struct snd_soc_dai *dai)
44d0a879
VB		 831{
832 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 833 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 834 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
4f9c16cc 835 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
255173b4
PM		 836 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
837 u16 d, pll_d = 1;
06c71282 838 u8 reg;
255173b4 839 int clk;
44d0a879 840
4f9c16cc
DM		 841 /* select data word length */
842 data =
843 aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
844 switch (params_format(params)) {
845 case SNDRV_PCM_FORMAT_S16_LE:
44d0a879 846 break;
4f9c16cc
DM		 847 case SNDRV_PCM_FORMAT_S20_3LE:
848 data |= (0x01 << 4);
44d0a879 849 break;
4f9c16cc
DM		 850 case SNDRV_PCM_FORMAT_S24_LE:
851 data |= (0x02 << 4);
44d0a879 852 break;
4f9c16cc
DM		 853 case SNDRV_PCM_FORMAT_S32_LE:
854 data |= (0x03 << 4);
44d0a879
VB		 855 break;
856 }
4f9c16cc
DM		 857 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, data);
858
859 /* Fsref can be 44100 or 48000 */
860 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
861
862 /* Try to find a value for Q which allows us to bypass the PLL and
863 * generate CODEC_CLK directly. */
864 for (pll_q = 2; pll_q < 18; pll_q++)
865 if (aic3x->sysclk / (128 * pll_q) == fsref) {
866 bypass_pll = 1;
867 break;
868 }
869
870 if (bypass_pll) {
871 pll_q &= 0xf;
872 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
873 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
06c71282
C		 874 /* disable PLL if it is bypassed */
875 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
876 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
877
878 } else {
4f9c16cc 879 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
06c71282
C		 880 /* enable PLL when it is used */
881 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
882 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
883 }
4f9c16cc
DM		 884
885 /* Route Left DAC to left channel input and
886 * right DAC to right channel input */
887 data = (LDAC2LCH | RDAC2RCH);
888 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
889 if (params_rate(params) >= 64000)
890 data |= DUAL_RATE_MODE;
44d0a879
VB		 891 aic3x_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
892
893 /* codec sample rate select */
4f9c16cc
DM		 894 data = (fsref * 20) / params_rate(params);
895 if (params_rate(params) < 64000)
896 data /= 2;
897 data /= 5;
898 data -= 2;
44d0a879
VB		 899 data |= (data << 4);
900 aic3x_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
901
4f9c16cc
DM		 902 if (bypass_pll)
903 return 0;
904
255173b4
PM		 905 /* Use PLL, compute apropriate setup for j, d, r and p, the closest
906 * one wins the game. Try with d==0 first, next with d!=0.
907 * Constraints for j are according to the datasheet.
4f9c16cc 908 * The sysclk is divided by 1000 to prevent integer overflows.
44d0a879 909 */
255173b4 910
4f9c16cc
DM		 911 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
912
913 for (r = 1; r <= 16; r++)
914 for (p = 1; p <= 8; p++) {
255173b4
PM		 915 for (j = 4; j <= 55; j++) {
916 /* This is actually 1000*((j+(d/10000))*r)/p
917 * The term had to be converted to get
918 * rid of the division by 10000; d = 0 here
919 */
5baf8315 920 int tmp_clk = (1000 * j * r) / p;
255173b4
PM		 921
922 /* Check whether this values get closer than
923 * the best ones we had before
924 */
5baf8315 925 if (abs(codec_clk - tmp_clk) <
255173b4
PM		 926 abs(codec_clk - last_clk)) {
927 pll_j = j; pll_d = 0;
928 pll_r = r; pll_p = p;
5baf8315 929 last_clk = tmp_clk;
255173b4
PM		 930 }
931
932 /* Early exit for exact matches */
5baf8315 933 if (tmp_clk == codec_clk)
255173b4
PM		 934 goto found;
935 }
936 }
4f9c16cc 937
255173b4
PM		 938 /* try with d != 0 */
939 for (p = 1; p <= 8; p++) {
940 j = codec_clk * p / 1000;
4f9c16cc 941
255173b4
PM		 942 if (j < 4 || j > 11)
943 continue;
4f9c16cc 944
255173b4
PM		 945 /* do not use codec_clk here since we'd loose precision */
946 d = ((2048 * p * fsref) - j * aic3x->sysclk)
947 * 100 / (aic3x->sysclk/100);
4f9c16cc 948
255173b4 949 clk = (10000 * j + d) / (10 * p);
4f9c16cc 950
255173b4
PM		 951 /* check whether this values get closer than the best
952 * ones we had before */
953 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
954 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
955 last_clk = clk;
4f9c16cc
DM		 956 }
957
255173b4
PM		 958 /* Early exit for exact matches */
959 if (clk == codec_clk)
960 goto found;
961 }
962
4f9c16cc
DM		 963 if (last_clk == 0) {
964 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
965 return -EINVAL;
966 }
44d0a879 967
255173b4 968found:
44d0a879
VB		 969 data = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
970 aic3x_write(codec, AIC3X_PLL_PROGA_REG, data | (pll_p << PLLP_SHIFT));
971 aic3x_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, pll_r << PLLR_SHIFT);
972 aic3x_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
973 aic3x_write(codec, AIC3X_PLL_PROGC_REG, (pll_d >> 6) << PLLD_MSB_SHIFT);
974 aic3x_write(codec, AIC3X_PLL_PROGD_REG,
975 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
976
44d0a879
VB		 977 return 0;
978}
979
e550e17f 980static int aic3x_mute(struct snd_soc_dai *dai, int mute)
44d0a879
VB		 981{
982 struct snd_soc_codec *codec = dai->codec;
983 u8 ldac_reg = aic3x_read_reg_cache(codec, LDAC_VOL) & ~MUTE_ON;
984 u8 rdac_reg = aic3x_read_reg_cache(codec, RDAC_VOL) & ~MUTE_ON;
985
986 if (mute) {
987 aic3x_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
988 aic3x_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
989 } else {
990 aic3x_write(codec, LDAC_VOL, ldac_reg);
991 aic3x_write(codec, RDAC_VOL, rdac_reg);
992 }
993
994 return 0;
995}
996
e550e17f 997static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
44d0a879
VB		 998 int clk_id, unsigned int freq, int dir)
999{
1000 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1001 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879 1002
4f9c16cc
DM		 1003 aic3x->sysclk = freq;
1004 return 0;
44d0a879
VB		 1005}
1006
e550e17f 1007static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
44d0a879
VB		 1008 unsigned int fmt)
1009{
1010 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1011 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
81971a14 1012 u8 iface_areg, iface_breg;
a24f4f68 1013 int delay = 0;
81971a14
JN		 1014
1015 iface_areg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1016 iface_breg = aic3x_read_reg_cache(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
44d0a879
VB		 1017
1018 /* set master/slave audio interface */
1019 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1020 case SND_SOC_DAIFMT_CBM_CFM:
1021 aic3x->master = 1;
1022 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1023 break;
1024 case SND_SOC_DAIFMT_CBS_CFS:
1025 aic3x->master = 0;
1026 break;
1027 default:
1028 return -EINVAL;
1029 }
1030
4b7d2831
JN		 1031 /*
1032 * match both interface format and signal polarities since they
1033 * are fixed
1034 */
1035 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1036 SND_SOC_DAIFMT_INV_MASK)) {
1037 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
44d0a879 1038 break;
a24f4f68
TK		 1039 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1040 delay = 1;
4b7d2831 1041 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
44d0a879
VB		 1042 iface_breg |= (0x01 << 6);
1043 break;
4b7d2831 1044 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1045 iface_breg |= (0x02 << 6);
1046 break;
4b7d2831 1047 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
44d0a879
VB		 1048 iface_breg |= (0x03 << 6);
1049 break;
1050 default:
1051 return -EINVAL;
1052 }
1053
1054 /* set iface */
1055 aic3x_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1056 aic3x_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
a24f4f68 1057 aic3x_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
44d0a879
VB		 1058
1059 return 0;
1060}
1061
0be9898a
MB		 1062static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1063 enum snd_soc_bias_level level)
44d0a879 1064{
b2c812e2 1065 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
44d0a879
VB		 1066 u8 reg;
1067
0be9898a
MB		 1068 switch (level) {
1069 case SND_SOC_BIAS_ON:
db13802e
JN		 1070 break;
1071 case SND_SOC_BIAS_PREPARE:
44d0a879
VB		 1072 if (aic3x->master) {
1073 /* enable pll */
1074 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1075 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1076 reg | PLL_ENABLE);
1077 }
1078 break;
0be9898a 1079 case SND_SOC_BIAS_STANDBY:
db13802e 1080 /* fall through and disable pll */
0be9898a 1081 case SND_SOC_BIAS_OFF:
44d0a879
VB		 1082 if (aic3x->master) {
1083 /* disable pll */
1084 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
1085 aic3x_write(codec, AIC3X_PLL_PROGA_REG,
1086 reg & ~PLL_ENABLE);
1087 }
1088 break;
1089 }
0be9898a 1090 codec->bias_level = level;
44d0a879
VB		 1091
1092 return 0;
1093}
1094
54e7e616
DM		 1095void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state)
1096{
1097 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1098 u8 bit = gpio ? 3: 0;
1099 u8 val = aic3x_read_reg_cache(codec, reg) & ~(1 << bit);
1100 aic3x_write(codec, reg, val | (!!state << bit));
1101}
1102EXPORT_SYMBOL_GPL(aic3x_set_gpio);
1103
1104int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio)
1105{
1106 u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG;
1107 u8 val, bit = gpio ? 2: 1;
1108
1109 aic3x_read(codec, reg, &val);
1110 return (val >> bit) & 1;
1111}
1112EXPORT_SYMBOL_GPL(aic3x_get_gpio);
1113
6f2a974b
DM		 1114void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
1115 int headset_debounce, int button_debounce)
1116{
1117 u8 val;
1118
1119 val = ((detect & AIC3X_HEADSET_DETECT_MASK)
1120 << AIC3X_HEADSET_DETECT_SHIFT) |
1121 ((headset_debounce & AIC3X_HEADSET_DEBOUNCE_MASK)
1122 << AIC3X_HEADSET_DEBOUNCE_SHIFT) |
1123 ((button_debounce & AIC3X_BUTTON_DEBOUNCE_MASK)
1124 << AIC3X_BUTTON_DEBOUNCE_SHIFT);
1125
1126 if (detect & AIC3X_HEADSET_DETECT_MASK)
1127 val |= AIC3X_HEADSET_DETECT_ENABLED;
1128
1129 aic3x_write(codec, AIC3X_HEADSET_DETECT_CTRL_A, val);
1130}
1131EXPORT_SYMBOL_GPL(aic3x_set_headset_detection);
1132
54e7e616
DM		 1133int aic3x_headset_detected(struct snd_soc_codec *codec)
1134{
1135 u8 val;
6f2a974b
DM		 1136 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1137 return (val >> 4) & 1;
54e7e616
DM		 1138}
1139EXPORT_SYMBOL_GPL(aic3x_headset_detected);
1140
6f2a974b
DM		 1141int aic3x_button_pressed(struct snd_soc_codec *codec)
1142{
1143 u8 val;
1144 aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val);
1145 return (val >> 5) & 1;
1146}
1147EXPORT_SYMBOL_GPL(aic3x_button_pressed);
1148
44d0a879
VB		 1149#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1150#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1151 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1152
6335d055
EM		 1153static struct snd_soc_dai_ops aic3x_dai_ops = {
1154 .hw_params = aic3x_hw_params,
1155 .digital_mute = aic3x_mute,
1156 .set_sysclk = aic3x_set_dai_sysclk,
1157 .set_fmt = aic3x_set_dai_fmt,
1158};
1159
f0fba2ad
LG		 1160static struct snd_soc_dai_driver aic3x_dai = {
1161 .name = "tlv320aic3x-hifi",
44d0a879
VB		 1162 .playback = {
1163 .stream_name = "Playback",
1164 .channels_min = 1,
1165 .channels_max = 2,
1166 .rates = AIC3X_RATES,
1167 .formats = AIC3X_FORMATS,},
1168 .capture = {
1169 .stream_name = "Capture",
1170 .channels_min = 1,
1171 .channels_max = 2,
1172 .rates = AIC3X_RATES,
1173 .formats = AIC3X_FORMATS,},
6335d055 1174 .ops = &aic3x_dai_ops,
14017615 1175 .symmetric_rates = 1,
44d0a879 1176};
44d0a879 1177
f0fba2ad 1178static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state)
44d0a879 1179{
0be9898a 1180 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
44d0a879
VB		 1181
1182 return 0;
1183}
1184
f0fba2ad 1185static int aic3x_resume(struct snd_soc_codec *codec)
44d0a879 1186{
44d0a879
VB		 1187 int i;
1188 u8 data[2];
1189 u8 *cache = codec->reg_cache;
1190
1191 /* Sync reg_cache with the hardware */
1192 for (i = 0; i < ARRAY_SIZE(aic3x_reg); i++) {
1193 data[0] = i;
1194 data[1] = cache[i];
1195 codec->hw_write(codec->control_data, data, 2);
1196 }
1197
29e189c2 1198 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879
VB		 1199
1200 return 0;
1201}
1202
1203/*
1204 * initialise the AIC3X driver
1205 * register the mixer and dsp interfaces with the kernel
1206 */
cb3826f5 1207static int aic3x_init(struct snd_soc_codec *codec)
44d0a879 1208{
6184f105 1209 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
cb3826f5
BD		 1210 int reg;
1211
44d0a879
VB		 1212 aic3x_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1213 aic3x_write(codec, AIC3X_RESET, SOFT_RESET);
1214
44d0a879
VB		 1215 /* DAC default volume and mute */
1216 aic3x_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1217 aic3x_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1218
1219 /* DAC to HP default volume and route to Output mixer */
1220 aic3x_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1221 aic3x_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1222 aic3x_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1223 aic3x_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1224 /* DAC to Line Out default volume and route to Output mixer */
1225 aic3x_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1226 aic3x_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1227 /* DAC to Mono Line Out default volume and route to Output mixer */
1228 aic3x_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1229 aic3x_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1230
1231 /* unmute all outputs */
1232 reg = aic3x_read_reg_cache(codec, LLOPM_CTRL);
1233 aic3x_write(codec, LLOPM_CTRL, reg | UNMUTE);
1234 reg = aic3x_read_reg_cache(codec, RLOPM_CTRL);
1235 aic3x_write(codec, RLOPM_CTRL, reg | UNMUTE);
1236 reg = aic3x_read_reg_cache(codec, MONOLOPM_CTRL);
1237 aic3x_write(codec, MONOLOPM_CTRL, reg | UNMUTE);
1238 reg = aic3x_read_reg_cache(codec, HPLOUT_CTRL);
1239 aic3x_write(codec, HPLOUT_CTRL, reg | UNMUTE);
1240 reg = aic3x_read_reg_cache(codec, HPROUT_CTRL);
1241 aic3x_write(codec, HPROUT_CTRL, reg | UNMUTE);
1242 reg = aic3x_read_reg_cache(codec, HPLCOM_CTRL);
1243 aic3x_write(codec, HPLCOM_CTRL, reg | UNMUTE);
1244 reg = aic3x_read_reg_cache(codec, HPRCOM_CTRL);
1245 aic3x_write(codec, HPRCOM_CTRL, reg | UNMUTE);
1246
1247 /* ADC default volume and unmute */
1248 aic3x_write(codec, LADC_VOL, DEFAULT_GAIN);
1249 aic3x_write(codec, RADC_VOL, DEFAULT_GAIN);
1250 /* By default route Line1 to ADC PGA mixer */
1251 aic3x_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1252 aic3x_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1253
1254 /* PGA to HP Bypass default volume, disconnect from Output Mixer */
1255 aic3x_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1256 aic3x_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1257 aic3x_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1258 aic3x_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1259 /* PGA to Line Out default volume, disconnect from Output Mixer */
1260 aic3x_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1261 aic3x_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1262 /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
1263 aic3x_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1264 aic3x_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1265
1266 /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
1267 aic3x_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1268 aic3x_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1269 aic3x_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1270 aic3x_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1271 /* Line2 Line Out default volume, disconnect from Output Mixer */
1272 aic3x_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1273 aic3x_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1274 /* Line2 to Mono Out default volume, disconnect from Output Mixer */
1275 aic3x_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1276 aic3x_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1277
6184f105
RC		 1278 if (aic3x->model == AIC3X_MODEL_3007) {
1279 /* Class-D speaker driver init; datasheet p. 46 */
1280 aic3x_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1281 aic3x_write(codec, 0xD, 0x0D);
1282 aic3x_write(codec, 0x8, 0x5C);
1283 aic3x_write(codec, 0x8, 0x5D);
1284 aic3x_write(codec, 0x8, 0x5C);
1285 aic3x_write(codec, AIC3X_PAGE_SELECT, 0x00);
1286 aic3x_write(codec, CLASSD_CTRL, 0);
1287 }
1288
44d0a879 1289 /* off, with power on */
0be9898a 1290 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
44d0a879 1291
cb3826f5
BD		 1292 return 0;
1293}
54e7e616 1294
f0fba2ad 1295static int aic3x_probe(struct snd_soc_codec *codec)
cb3826f5 1296{
f0fba2ad
LG		 1297 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1298
1299 codec->hw_write = (hw_write_t) i2c_master_send;
1300 codec->control_data = aic3x->control_data;
cb3826f5 1301
37b47656
JN		 1302 aic3x_init(codec);
1303
f0fba2ad
LG		 1304 if (aic3x->setup) {
1305 /* setup GPIO functions */
1306 aic3x_write(codec, AIC3X_GPIO1_REG,
1307 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1308 aic3x_write(codec, AIC3X_GPIO2_REG,
1309 (aic3x->setup->gpio_func[1] & 0xf) << 4);
44d0a879
VB		 1310 }
1311
f0fba2ad
LG		 1312 snd_soc_add_controls(codec, aic3x_snd_controls,
1313 ARRAY_SIZE(aic3x_snd_controls));
6184f105
RC		 1314 if (aic3x->model == AIC3X_MODEL_3007)
1315 snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
cb3826f5 1316
f0fba2ad 1317 aic3x_add_widgets(codec);
cb3826f5
BD		 1318
1319 return 0;
44d0a879
VB		 1320}
1321
f0fba2ad 1322static int aic3x_remove(struct snd_soc_codec *codec)
cb3826f5 1323{
f0fba2ad 1324 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
cb3826f5
BD		 1325 return 0;
1326}
44d0a879 1327
f0fba2ad
LG		 1328static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1329 .read = aic3x_read_reg_cache,
1330 .write = aic3x_write,
1331 .set_bias_level = aic3x_set_bias_level,
1332 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1333 .reg_word_size = sizeof(u8),
1334 .reg_cache_default = aic3x_reg,
1335 .probe = aic3x_probe,
1336 .remove = aic3x_remove,
1337 .suspend = aic3x_suspend,
1338 .resume = aic3x_resume,
1339};
1340
44d0a879
VB		 1341#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1342/*
1343 * AIC3X 2 wire address can be up to 4 devices with device addresses
1344 * 0x18, 0x19, 0x1A, 0x1B
1345 */
44d0a879 1346
6184f105
RC		 1347static const struct i2c_device_id aic3x_i2c_id[] = {
1348 [AIC3X_MODEL_3X] = { "tlv320aic3x", 0 },
1349 [AIC3X_MODEL_33] = { "tlv320aic33", 0 },
1350 [AIC3X_MODEL_3007] = { "tlv320aic3007", 0 },
1351 { }
1352};
1353MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1354
44d0a879
VB		 1355/*
1356 * If the i2c layer weren't so broken, we could pass this kind of data
1357 * around
1358 */
ba8ed121
JD		 1359static int aic3x_i2c_probe(struct i2c_client *i2c,
1360 const struct i2c_device_id *id)
44d0a879 1361{
5193d62f 1362 struct aic3x_pdata *pdata = i2c->dev.platform_data;
f0fba2ad 1363 struct aic3x_priv *aic3x;
07779fdd 1364 int ret, i;
6184f105 1365 const struct i2c_device_id *tbl;
44d0a879 1366
cb3826f5
BD		 1367 aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL);
1368 if (aic3x == NULL) {
1369 dev_err(&i2c->dev, "failed to create private data\n");
1370 return -ENOMEM;
1371 }
1372
f0fba2ad 1373 aic3x->control_data = i2c;
cb3826f5 1374 i2c_set_clientdata(i2c, aic3x);
c776357e
JN		 1375 if (pdata) {
1376 aic3x->gpio_reset = pdata->gpio_reset;
1377 aic3x->setup = pdata->setup;
1378 } else {
1379 aic3x->gpio_reset = -1;
1380 }
cb3826f5 1381
c776357e
JN		 1382 if (aic3x->gpio_reset >= 0) {
1383 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
5193d62f
JN		 1384 if (ret != 0)
1385 goto err_gpio;
5193d62f
JN		 1386 gpio_direction_output(aic3x->gpio_reset, 0);
1387 }
1388
6184f105
RC		 1389 for (tbl = aic3x_i2c_id; tbl->name[0]; tbl++) {
1390 if (!strcmp(tbl->name, id->name))
1391 break;
1392 }
1393 aic3x->model = tbl - aic3x_i2c_id;
1394
07779fdd
JN		 1395 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1396 aic3x->supplies[i].supply = aic3x_supply_names[i];
1397
f0fba2ad 1398 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies),
07779fdd
JN		 1399 aic3x->supplies);
1400 if (ret != 0) {
f0fba2ad 1401 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
07779fdd
JN		 1402 goto err_get;
1403 }
1404
1405 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1406 aic3x->supplies);
1407 if (ret != 0) {
f0fba2ad 1408 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
07779fdd
JN		 1409 goto err_enable;
1410 }
1411
5193d62f
JN		 1412 if (aic3x->gpio_reset >= 0) {
1413 udelay(1);
1414 gpio_set_value(aic3x->gpio_reset, 1);
1415 }
1416
f0fba2ad
LG		 1417 ret = snd_soc_register_codec(&i2c->dev,
1418 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1419 if (ret < 0)
1420 goto err_enable;
1421 return ret;
07779fdd
JN		 1422
1423err_enable:
1424 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1425err_get:
5193d62f
JN		 1426 if (aic3x->gpio_reset >= 0)
1427 gpio_free(aic3x->gpio_reset);
1428err_gpio:
07779fdd
JN		 1429 kfree(aic3x);
1430 return ret;
44d0a879
VB		 1431}
1432
ba8ed121 1433static int aic3x_i2c_remove(struct i2c_client *client)
44d0a879 1434{
cb3826f5
BD		 1435 struct aic3x_priv *aic3x = i2c_get_clientdata(client);
1436
f0fba2ad
LG		 1437 if (aic3x->gpio_reset >= 0) {
1438 gpio_set_value(aic3x->gpio_reset, 0);
1439 gpio_free(aic3x->gpio_reset);
1440 }
1441 regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1442 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1443
1444 snd_soc_unregister_codec(&client->dev);
1445 kfree(i2c_get_clientdata(client));
1446 return 0;
44d0a879
VB		 1447}
1448
44d0a879
VB		 1449/* machine i2c codec control layer */
1450static struct i2c_driver aic3x_i2c_driver = {
1451 .driver = {
f0fba2ad 1452 .name = "tlv320aic3x-codec",
44d0a879
VB		 1453 .owner = THIS_MODULE,
1454 },
cb3826f5 1455 .probe = aic3x_i2c_probe,
ba8ed121
JD		 1456 .remove = aic3x_i2c_remove,
1457 .id_table = aic3x_i2c_id,
44d0a879 1458};
54e7e616 1459
cb3826f5 1460static inline void aic3x_i2c_init(void)
ba8ed121 1461{
ba8ed121
JD		 1462 int ret;
1463
1464 ret = i2c_add_driver(&aic3x_i2c_driver);
cb3826f5
BD		 1465 if (ret)
1466 printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
1467 __func__, ret);
1468}
ba8ed121 1469
cb3826f5
BD		 1470static inline void aic3x_i2c_exit(void)
1471{
ba8ed121 1472 i2c_del_driver(&aic3x_i2c_driver);
ba8ed121 1473}
44d0a879
VB		 1474#endif
1475
f0fba2ad 1476static int __init aic3x_modinit(void)
44d0a879 1477{
44d0a879 1478 int ret = 0;
f0fba2ad
LG		 1479#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1480 ret = i2c_add_driver(&aic3x_i2c_driver);
1481 if (ret != 0) {
1482 printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n",
1483 ret);
44d0a879 1484 }
f0fba2ad 1485#endif
44d0a879
VB		 1486 return ret;
1487}
64089b84
MB		 1488module_init(aic3x_modinit);
1489
1490static void __exit aic3x_exit(void)
1491{
f0fba2ad
LG		 1492#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1493 i2c_del_driver(&aic3x_i2c_driver);
1494#endif
64089b84
MB		 1495}
1496module_exit(aic3x_exit);
1497
44d0a879
VB		 1498MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1499MODULE_AUTHOR("Vladimir Barinov");
1500MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)