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44d0a879 VB |
1 | /* |
2 | * ALSA SoC TLV320AIC3X codec driver | |
3 | * | |
d6b52039 | 4 | * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> |
44d0a879 VB |
5 | * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> |
6 | * | |
7 | * Based on sound/soc/codecs/wm8753.c by Liam Girdwood | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * Notes: | |
14 | * The AIC3X is a driver for a low power stereo audio | |
6184f105 | 15 | * codecs aic31, aic32, aic33, aic3007. |
44d0a879 VB |
16 | * |
17 | * It supports full aic33 codec functionality. | |
6184f105 RC |
18 | * The compatibility with aic32, aic31 and aic3007 is as follows: |
19 | * aic32/aic3007 | aic31 | |
44d0a879 VB |
20 | * --------------------------------------- |
21 | * MONO_LOUT -> N/A | MONO_LOUT -> N/A | |
22 | * | IN1L -> LINE1L | |
23 | * | IN1R -> LINE1R | |
24 | * | IN2L -> LINE2L | |
25 | * | IN2R -> LINE2R | |
26 | * | MIC3L/R -> N/A | |
27 | * truncated internal functionality in | |
28 | * accordance with documentation | |
29 | * --------------------------------------- | |
30 | * | |
31 | * Hence the machine layer should disable unsupported inputs/outputs by | |
a5302181 | 32 | * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. |
44d0a879 VB |
33 | */ |
34 | ||
35 | #include <linux/module.h> | |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/pm.h> | |
40 | #include <linux/i2c.h> | |
5193d62f | 41 | #include <linux/gpio.h> |
07779fdd | 42 | #include <linux/regulator/consumer.h> |
b3b70786 | 43 | #include <linux/of.h> |
c24fdc88 | 44 | #include <linux/of_gpio.h> |
5a0e3ad6 | 45 | #include <linux/slab.h> |
44d0a879 VB |
46 | #include <sound/core.h> |
47 | #include <sound/pcm.h> | |
48 | #include <sound/pcm_params.h> | |
49 | #include <sound/soc.h> | |
44d0a879 | 50 | #include <sound/initval.h> |
7565fc38 | 51 | #include <sound/tlv.h> |
5193d62f | 52 | #include <sound/tlv320aic3x.h> |
44d0a879 VB |
53 | |
54 | #include "tlv320aic3x.h" | |
55 | ||
07779fdd JN |
56 | #define AIC3X_NUM_SUPPLIES 4 |
57 | static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { | |
58 | "IOVDD", /* I/O Voltage */ | |
59 | "DVDD", /* Digital Core Voltage */ | |
60 | "AVDD", /* Analog DAC Voltage */ | |
61 | "DRVDD", /* ADC Analog and Output Driver Voltage */ | |
62 | }; | |
44d0a879 | 63 | |
414c73ab JN |
64 | static LIST_HEAD(reset_list); |
65 | ||
5a895f8a JN |
66 | struct aic3x_priv; |
67 | ||
68 | struct aic3x_disable_nb { | |
69 | struct notifier_block nb; | |
70 | struct aic3x_priv *aic3x; | |
71 | }; | |
72 | ||
44d0a879 VB |
73 | /* codec private data */ |
74 | struct aic3x_priv { | |
5a895f8a | 75 | struct snd_soc_codec *codec; |
2a6fedec | 76 | struct regmap *regmap; |
07779fdd | 77 | struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; |
5a895f8a | 78 | struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES]; |
f0fba2ad | 79 | struct aic3x_setup_data *setup; |
44d0a879 | 80 | unsigned int sysclk; |
36849409 PU |
81 | unsigned int dai_fmt; |
82 | unsigned int tdm_delay; | |
414c73ab | 83 | struct list_head list; |
44d0a879 | 84 | int master; |
5193d62f | 85 | int gpio_reset; |
6c1a7d40 | 86 | int power; |
6184f105 RC |
87 | #define AIC3X_MODEL_3X 0 |
88 | #define AIC3X_MODEL_33 1 | |
89 | #define AIC3X_MODEL_3007 2 | |
9503112d | 90 | #define AIC3X_MODEL_3104 3 |
6184f105 | 91 | u16 model; |
e2e8bfdf HG |
92 | |
93 | /* Selects the micbias voltage */ | |
94 | enum aic3x_micbias_voltage micbias_vg; | |
44d0a879 VB |
95 | }; |
96 | ||
2a6fedec MB |
97 | static const struct reg_default aic3x_reg[] = { |
98 | { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x10 }, | |
99 | { 4, 0x04 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 }, | |
100 | { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x01 }, | |
101 | { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x80 }, | |
102 | { 16, 0x80 }, { 17, 0xff }, { 18, 0xff }, { 19, 0x78 }, | |
103 | { 20, 0x78 }, { 21, 0x78 }, { 22, 0x78 }, { 23, 0x78 }, | |
104 | { 24, 0x78 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0xfe }, | |
105 | { 28, 0x00 }, { 29, 0x00 }, { 30, 0xfe }, { 31, 0x00 }, | |
106 | { 32, 0x18 }, { 33, 0x18 }, { 34, 0x00 }, { 35, 0x00 }, | |
107 | { 36, 0x00 }, { 37, 0x00 }, { 38, 0x00 }, { 39, 0x00 }, | |
108 | { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x80 }, | |
109 | { 44, 0x80 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 }, | |
110 | { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x04 }, | |
111 | { 52, 0x00 }, { 53, 0x00 }, { 54, 0x00 }, { 55, 0x00 }, | |
112 | { 56, 0x00 }, { 57, 0x00 }, { 58, 0x04 }, { 59, 0x00 }, | |
113 | { 60, 0x00 }, { 61, 0x00 }, { 62, 0x00 }, { 63, 0x00 }, | |
114 | { 64, 0x00 }, { 65, 0x04 }, { 66, 0x00 }, { 67, 0x00 }, | |
115 | { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 }, | |
116 | { 72, 0x04 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 }, | |
117 | { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 }, | |
118 | { 80, 0x00 }, { 81, 0x00 }, { 82, 0x00 }, { 83, 0x00 }, | |
119 | { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 }, | |
120 | { 88, 0x00 }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 }, | |
121 | { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 }, | |
122 | { 96, 0x00 }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 }, | |
123 | { 100, 0x00 }, { 101, 0x00 }, { 102, 0x02 }, { 103, 0x00 }, | |
124 | { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 }, | |
125 | { 108, 0x00 }, { 109, 0x00 }, | |
126 | }; | |
127 | ||
128 | static const struct regmap_config aic3x_regmap = { | |
129 | .reg_bits = 8, | |
130 | .val_bits = 8, | |
131 | ||
132 | .max_register = DAC_ICC_ADJ, | |
133 | .reg_defaults = aic3x_reg, | |
134 | .num_reg_defaults = ARRAY_SIZE(aic3x_reg), | |
135 | .cache_type = REGCACHE_RBTREE, | |
44d0a879 VB |
136 | }; |
137 | ||
44d0a879 | 138 | #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ |
1476f66f LPC |
139 | SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \ |
140 | snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x) | |
44d0a879 VB |
141 | |
142 | /* | |
143 | * All input lines are connected when !0xf and disconnected with 0xf bit field, | |
144 | * so we have to use specific dapm_put call for input mixer | |
145 | */ | |
146 | static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, | |
147 | struct snd_ctl_elem_value *ucontrol) | |
148 | { | |
eee5d7f9 | 149 | struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol); |
650a18ac | 150 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
4453dba5 EN |
151 | struct soc_mixer_control *mc = |
152 | (struct soc_mixer_control *)kcontrol->private_value; | |
153 | unsigned int reg = mc->reg; | |
154 | unsigned int shift = mc->shift; | |
155 | int max = mc->max; | |
156 | unsigned int mask = (1 << fls(max)) - 1; | |
157 | unsigned int invert = mc->invert; | |
5d99d778 LPC |
158 | unsigned short val; |
159 | struct snd_soc_dapm_update update; | |
160 | int connect, change; | |
44d0a879 VB |
161 | |
162 | val = (ucontrol->value.integer.value[0] & mask); | |
163 | ||
164 | mask = 0xf; | |
165 | if (val) | |
166 | val = mask; | |
167 | ||
5d99d778 LPC |
168 | connect = !!val; |
169 | ||
44d0a879 VB |
170 | if (invert) |
171 | val = mask - val; | |
44d0a879 | 172 | |
5d99d778 LPC |
173 | mask <<= shift; |
174 | val <<= shift; | |
2894770e | 175 | |
e6c111fa | 176 | change = snd_soc_test_bits(codec, reg, mask, val); |
5d99d778 LPC |
177 | if (change) { |
178 | update.kcontrol = kcontrol; | |
179 | update.reg = reg; | |
180 | update.mask = mask; | |
181 | update.val = val; | |
182 | ||
650a18ac | 183 | snd_soc_dapm_mixer_update_power(dapm, kcontrol, connect, |
5d99d778 LPC |
184 | &update); |
185 | } | |
2894770e | 186 | |
5d99d778 | 187 | return change; |
44d0a879 VB |
188 | } |
189 | ||
e2e8bfdf HG |
190 | /* |
191 | * mic bias power on/off share the same register bits with | |
192 | * output voltage of mic bias. when power on mic bias, we | |
193 | * need reclaim it to voltage value. | |
194 | * 0x0 = Powered off | |
195 | * 0x1 = MICBIAS output is powered to 2.0V, | |
196 | * 0x2 = MICBIAS output is powered to 2.5V | |
197 | * 0x3 = MICBIAS output is connected to AVDD | |
198 | */ | |
199 | static int mic_bias_event(struct snd_soc_dapm_widget *w, | |
200 | struct snd_kcontrol *kcontrol, int event) | |
201 | { | |
38d3df61 | 202 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
e2e8bfdf HG |
203 | struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); |
204 | ||
205 | switch (event) { | |
206 | case SND_SOC_DAPM_POST_PMU: | |
207 | /* change mic bias voltage to user defined */ | |
208 | snd_soc_update_bits(codec, MICBIAS_CTRL, | |
209 | MICBIAS_LEVEL_MASK, | |
210 | aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT); | |
211 | break; | |
212 | ||
213 | case SND_SOC_DAPM_PRE_PMD: | |
214 | snd_soc_update_bits(codec, MICBIAS_CTRL, | |
215 | MICBIAS_LEVEL_MASK, 0); | |
216 | break; | |
217 | } | |
218 | return 0; | |
219 | } | |
220 | ||
a60e654b PU |
221 | static const char * const aic3x_left_dac_mux[] = { |
222 | "DAC_L1", "DAC_L3", "DAC_L2" }; | |
223 | static SOC_ENUM_SINGLE_DECL(aic3x_left_dac_enum, DAC_LINE_MUX, 6, | |
224 | aic3x_left_dac_mux); | |
225 | ||
226 | static const char * const aic3x_right_dac_mux[] = { | |
227 | "DAC_R1", "DAC_R3", "DAC_R2" }; | |
228 | static SOC_ENUM_SINGLE_DECL(aic3x_right_dac_enum, DAC_LINE_MUX, 4, | |
229 | aic3x_right_dac_mux); | |
230 | ||
231 | static const char * const aic3x_left_hpcom_mux[] = { | |
232 | "differential of HPLOUT", "constant VCM", "single-ended" }; | |
233 | static SOC_ENUM_SINGLE_DECL(aic3x_left_hpcom_enum, HPLCOM_CFG, 4, | |
234 | aic3x_left_hpcom_mux); | |
235 | ||
236 | static const char * const aic3x_right_hpcom_mux[] = { | |
237 | "differential of HPROUT", "constant VCM", "single-ended", | |
238 | "differential of HPLCOM", "external feedback" }; | |
239 | static SOC_ENUM_SINGLE_DECL(aic3x_right_hpcom_enum, HPRCOM_CFG, 3, | |
240 | aic3x_right_hpcom_mux); | |
241 | ||
242 | static const char * const aic3x_linein_mode_mux[] = { | |
243 | "single-ended", "differential" }; | |
244 | static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_l_enum, LINE1L_2_LADC_CTRL, 7, | |
245 | aic3x_linein_mode_mux); | |
246 | static SOC_ENUM_SINGLE_DECL(aic3x_line1l_2_r_enum, LINE1L_2_RADC_CTRL, 7, | |
247 | aic3x_linein_mode_mux); | |
248 | static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_l_enum, LINE1R_2_LADC_CTRL, 7, | |
249 | aic3x_linein_mode_mux); | |
250 | static SOC_ENUM_SINGLE_DECL(aic3x_line1r_2_r_enum, LINE1R_2_RADC_CTRL, 7, | |
251 | aic3x_linein_mode_mux); | |
252 | static SOC_ENUM_SINGLE_DECL(aic3x_line2l_2_ldac_enum, LINE2L_2_LADC_CTRL, 7, | |
253 | aic3x_linein_mode_mux); | |
254 | static SOC_ENUM_SINGLE_DECL(aic3x_line2r_2_rdac_enum, LINE2R_2_RADC_CTRL, 7, | |
255 | aic3x_linein_mode_mux); | |
256 | ||
257 | static const char * const aic3x_adc_hpf[] = { | |
258 | "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; | |
259 | static SOC_ENUM_DOUBLE_DECL(aic3x_adc_hpf_enum, AIC3X_CODEC_DFILT_CTRL, 6, 4, | |
260 | aic3x_adc_hpf); | |
261 | ||
262 | static const char * const aic3x_agc_level[] = { | |
263 | "-5.5dB", "-8dB", "-10dB", "-12dB", | |
264 | "-14dB", "-17dB", "-20dB", "-24dB" }; | |
265 | static SOC_ENUM_SINGLE_DECL(aic3x_lagc_level_enum, LAGC_CTRL_A, 4, | |
266 | aic3x_agc_level); | |
267 | static SOC_ENUM_SINGLE_DECL(aic3x_ragc_level_enum, RAGC_CTRL_A, 4, | |
268 | aic3x_agc_level); | |
269 | ||
270 | static const char * const aic3x_agc_attack[] = { | |
271 | "8ms", "11ms", "16ms", "20ms" }; | |
272 | static SOC_ENUM_SINGLE_DECL(aic3x_lagc_attack_enum, LAGC_CTRL_A, 2, | |
273 | aic3x_agc_attack); | |
274 | static SOC_ENUM_SINGLE_DECL(aic3x_ragc_attack_enum, RAGC_CTRL_A, 2, | |
275 | aic3x_agc_attack); | |
276 | ||
277 | static const char * const aic3x_agc_decay[] = { | |
278 | "100ms", "200ms", "400ms", "500ms" }; | |
279 | static SOC_ENUM_SINGLE_DECL(aic3x_lagc_decay_enum, LAGC_CTRL_A, 0, | |
280 | aic3x_agc_decay); | |
281 | static SOC_ENUM_SINGLE_DECL(aic3x_ragc_decay_enum, RAGC_CTRL_A, 0, | |
282 | aic3x_agc_decay); | |
bb1daa80 | 283 | |
68d66269 MLC |
284 | static const char * const aic3x_poweron_time[] = { |
285 | "0us", "10us", "100us", "1ms", "10ms", "50ms", | |
286 | "100ms", "200ms", "400ms", "800ms", "2s", "4s" }; | |
287 | static SOC_ENUM_SINGLE_DECL(aic3x_poweron_time_enum, HPOUT_POP_REDUCTION, 4, | |
288 | aic3x_poweron_time); | |
289 | ||
290 | static const char * const aic3x_rampup_step[] = { "0ms", "1ms", "2ms", "4ms" }; | |
291 | static SOC_ENUM_SINGLE_DECL(aic3x_rampup_step_enum, HPOUT_POP_REDUCTION, 2, | |
292 | aic3x_rampup_step); | |
293 | ||
7565fc38 JN |
294 | /* |
295 | * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps | |
296 | */ | |
297 | static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); | |
298 | /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ | |
299 | static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); | |
300 | /* | |
301 | * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. | |
302 | * Step size is approximately 0.5 dB over most of the scale but increasing | |
303 | * near the very low levels. | |
304 | * Define dB scale so that it is mostly correct for range about -55 to 0 dB | |
305 | * but having increasing dB difference below that (and where it doesn't count | |
306 | * so much). This setting shows -50 dB (actual is -50.3 dB) for register | |
307 | * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. | |
308 | */ | |
309 | static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); | |
310 | ||
44d0a879 VB |
311 | static const struct snd_kcontrol_new aic3x_snd_controls[] = { |
312 | /* Output */ | |
7565fc38 JN |
313 | SOC_DOUBLE_R_TLV("PCM Playback Volume", |
314 | LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), | |
44d0a879 | 315 | |
098b1718 JN |
316 | /* |
317 | * Output controls that map to output mixer switches. Note these are | |
318 | * only for swapped L-to-R and R-to-L routes. See below stereo controls | |
319 | * for direct L-to-L and R-to-R routes. | |
320 | */ | |
098b1718 JN |
321 | SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", |
322 | PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), | |
323 | SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", | |
324 | DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), | |
325 | ||
098b1718 JN |
326 | SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", |
327 | PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), | |
328 | SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", | |
329 | DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), | |
330 | ||
098b1718 JN |
331 | SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", |
332 | PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), | |
333 | SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", | |
334 | DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), | |
335 | ||
098b1718 JN |
336 | SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", |
337 | PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), | |
338 | SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", | |
339 | DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), | |
340 | ||
098b1718 JN |
341 | SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", |
342 | PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), | |
343 | SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", | |
344 | DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), | |
345 | ||
098b1718 JN |
346 | SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", |
347 | PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), | |
348 | SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", | |
349 | DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), | |
350 | ||
351 | /* Stereo output controls for direct L-to-L and R-to-R routes */ | |
098b1718 JN |
352 | SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", |
353 | PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, | |
354 | 0, 118, 1, output_stage_tlv), | |
7565fc38 JN |
355 | SOC_DOUBLE_R_TLV("Line DAC Playback Volume", |
356 | DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, | |
357 | 0, 118, 1, output_stage_tlv), | |
098b1718 | 358 | |
098b1718 JN |
359 | SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", |
360 | PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, | |
7565fc38 | 361 | 0, 118, 1, output_stage_tlv), |
7565fc38 JN |
362 | SOC_DOUBLE_R_TLV("HP DAC Playback Volume", |
363 | DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, | |
364 | 0, 118, 1, output_stage_tlv), | |
098b1718 | 365 | |
098b1718 JN |
366 | SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", |
367 | PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, | |
7565fc38 | 368 | 0, 118, 1, output_stage_tlv), |
7565fc38 JN |
369 | SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", |
370 | DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, | |
371 | 0, 118, 1, output_stage_tlv), | |
098b1718 JN |
372 | |
373 | /* Output pin mute controls */ | |
374 | SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, | |
375 | 0x01, 0), | |
098b1718 JN |
376 | SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, |
377 | 0x01, 0), | |
f9bc0297 | 378 | SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, |
44d0a879 | 379 | 0x01, 0), |
44d0a879 VB |
380 | |
381 | /* | |
382 | * Note: enable Automatic input Gain Controller with care. It can | |
383 | * adjust PGA to max value when ADC is on and will never go back. | |
384 | */ | |
385 | SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), | |
a60e654b PU |
386 | SOC_ENUM("Left AGC Target level", aic3x_lagc_level_enum), |
387 | SOC_ENUM("Right AGC Target level", aic3x_ragc_level_enum), | |
388 | SOC_ENUM("Left AGC Attack time", aic3x_lagc_attack_enum), | |
389 | SOC_ENUM("Right AGC Attack time", aic3x_ragc_attack_enum), | |
390 | SOC_ENUM("Left AGC Decay time", aic3x_lagc_decay_enum), | |
391 | SOC_ENUM("Right AGC Decay time", aic3x_ragc_decay_enum), | |
44d0a879 | 392 | |
77444191 JP |
393 | /* De-emphasis */ |
394 | SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0), | |
44d0a879 VB |
395 | |
396 | /* Input */ | |
7565fc38 JN |
397 | SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, |
398 | 0, 119, 0, adc_tlv), | |
44d0a879 | 399 | SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), |
4d20f70a | 400 | |
a60e654b | 401 | SOC_ENUM("ADC HPF Cut-off", aic3x_adc_hpf_enum), |
68d66269 MLC |
402 | |
403 | /* Pop reduction */ | |
404 | SOC_ENUM("Output Driver Power-On time", aic3x_poweron_time_enum), | |
405 | SOC_ENUM("Output Driver Ramp-up step", aic3x_rampup_step_enum), | |
44d0a879 VB |
406 | }; |
407 | ||
9503112d JS |
408 | /* For other than tlv320aic3104 */ |
409 | static const struct snd_kcontrol_new aic3x_extra_snd_controls[] = { | |
410 | /* | |
411 | * Output controls that map to output mixer switches. Note these are | |
412 | * only for swapped L-to-R and R-to-L routes. See below stereo controls | |
413 | * for direct L-to-L and R-to-R routes. | |
414 | */ | |
415 | SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", | |
416 | LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), | |
417 | ||
418 | SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", | |
419 | LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), | |
420 | ||
421 | SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", | |
422 | LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), | |
423 | ||
424 | SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", | |
425 | LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), | |
426 | ||
427 | SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", | |
428 | LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), | |
429 | ||
430 | SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", | |
431 | LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), | |
432 | ||
433 | /* Stereo output controls for direct L-to-L and R-to-R routes */ | |
434 | SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", | |
435 | LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, | |
436 | 0, 118, 1, output_stage_tlv), | |
437 | ||
438 | SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", | |
439 | LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, | |
440 | 0, 118, 1, output_stage_tlv), | |
441 | ||
442 | SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", | |
443 | LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, | |
444 | 0, 118, 1, output_stage_tlv), | |
445 | }; | |
446 | ||
58381da6 JW |
447 | static const struct snd_kcontrol_new aic3x_mono_controls[] = { |
448 | SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", | |
449 | LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, | |
450 | 0, 118, 1, output_stage_tlv), | |
451 | SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", | |
452 | PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, | |
453 | 0, 118, 1, output_stage_tlv), | |
454 | SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", | |
455 | DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, | |
456 | 0, 118, 1, output_stage_tlv), | |
457 | ||
458 | SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), | |
459 | }; | |
460 | ||
6184f105 RC |
461 | /* |
462 | * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps | |
463 | */ | |
464 | static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0); | |
465 | ||
466 | static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl = | |
14a95fe8 | 467 | SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv); |
6184f105 | 468 | |
44d0a879 VB |
469 | /* Left DAC Mux */ |
470 | static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = | |
a60e654b | 471 | SOC_DAPM_ENUM("Route", aic3x_left_dac_enum); |
44d0a879 VB |
472 | |
473 | /* Right DAC Mux */ | |
474 | static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = | |
a60e654b | 475 | SOC_DAPM_ENUM("Route", aic3x_right_dac_enum); |
44d0a879 VB |
476 | |
477 | /* Left HPCOM Mux */ | |
478 | static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = | |
a60e654b | 479 | SOC_DAPM_ENUM("Route", aic3x_left_hpcom_enum); |
44d0a879 VB |
480 | |
481 | /* Right HPCOM Mux */ | |
482 | static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = | |
a60e654b | 483 | SOC_DAPM_ENUM("Route", aic3x_right_hpcom_enum); |
44d0a879 | 484 | |
c3b79e05 JN |
485 | /* Left Line Mixer */ |
486 | static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { | |
c3b79e05 JN |
487 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), |
488 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), | |
c3b79e05 JN |
489 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), |
490 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), | |
9503112d JS |
491 | /* Not on tlv320aic3104 */ |
492 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), | |
493 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), | |
44d0a879 VB |
494 | }; |
495 | ||
c3b79e05 JN |
496 | /* Right Line Mixer */ |
497 | static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { | |
c3b79e05 JN |
498 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), |
499 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), | |
c3b79e05 JN |
500 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), |
501 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), | |
9503112d JS |
502 | /* Not on tlv320aic3104 */ |
503 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), | |
504 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), | |
c3b79e05 JN |
505 | }; |
506 | ||
507 | /* Mono Mixer */ | |
508 | static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { | |
509 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), | |
510 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), | |
511 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), | |
512 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), | |
513 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), | |
514 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), | |
515 | }; | |
516 | ||
517 | /* Left HP Mixer */ | |
518 | static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { | |
c3b79e05 JN |
519 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), |
520 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), | |
c3b79e05 JN |
521 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), |
522 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), | |
9503112d JS |
523 | /* Not on tlv320aic3104 */ |
524 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), | |
525 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), | |
c3b79e05 JN |
526 | }; |
527 | ||
528 | /* Right HP Mixer */ | |
529 | static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { | |
c3b79e05 JN |
530 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), |
531 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), | |
c3b79e05 JN |
532 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), |
533 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), | |
9503112d JS |
534 | /* Not on tlv320aic3104 */ |
535 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), | |
536 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), | |
c3b79e05 JN |
537 | }; |
538 | ||
539 | /* Left HPCOM Mixer */ | |
540 | static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { | |
c3b79e05 JN |
541 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), |
542 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), | |
c3b79e05 JN |
543 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), |
544 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), | |
9503112d JS |
545 | /* Not on tlv320aic3104 */ |
546 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), | |
547 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), | |
c3b79e05 JN |
548 | }; |
549 | ||
550 | /* Right HPCOM Mixer */ | |
551 | static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { | |
c3b79e05 JN |
552 | SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), |
553 | SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), | |
c3b79e05 JN |
554 | SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), |
555 | SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), | |
9503112d JS |
556 | /* Not on tlv320aic3104 */ |
557 | SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), | |
558 | SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), | |
44d0a879 VB |
559 | }; |
560 | ||
561 | /* Left PGA Mixer */ | |
562 | static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { | |
563 | SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), | |
54f01916 | 564 | SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), |
44d0a879 VB |
565 | SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), |
566 | SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), | |
54f01916 | 567 | SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), |
44d0a879 VB |
568 | }; |
569 | ||
570 | /* Right PGA Mixer */ | |
571 | static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { | |
572 | SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), | |
54f01916 | 573 | SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), |
44d0a879 | 574 | SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), |
54f01916 | 575 | SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), |
44d0a879 VB |
576 | SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), |
577 | }; | |
578 | ||
9503112d JS |
579 | /* Left PGA Mixer for tlv320aic3104 */ |
580 | static const struct snd_kcontrol_new aic3104_left_pga_mixer_controls[] = { | |
581 | SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), | |
582 | SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), | |
583 | SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), | |
584 | SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), | |
585 | }; | |
586 | ||
587 | /* Right PGA Mixer for tlv320aic3104 */ | |
588 | static const struct snd_kcontrol_new aic3104_right_pga_mixer_controls[] = { | |
589 | SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), | |
590 | SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), | |
591 | SOC_DAPM_SINGLE_AIC3X("Mic2L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), | |
592 | SOC_DAPM_SINGLE_AIC3X("Mic2R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), | |
593 | }; | |
594 | ||
44d0a879 | 595 | /* Left Line1 Mux */ |
404b5665 | 596 | static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls = |
a60e654b | 597 | SOC_DAPM_ENUM("Route", aic3x_line1l_2_l_enum); |
404b5665 | 598 | static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls = |
a60e654b | 599 | SOC_DAPM_ENUM("Route", aic3x_line1l_2_r_enum); |
44d0a879 VB |
600 | |
601 | /* Right Line1 Mux */ | |
404b5665 | 602 | static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls = |
a60e654b | 603 | SOC_DAPM_ENUM("Route", aic3x_line1r_2_r_enum); |
404b5665 | 604 | static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls = |
a60e654b | 605 | SOC_DAPM_ENUM("Route", aic3x_line1r_2_l_enum); |
44d0a879 VB |
606 | |
607 | /* Left Line2 Mux */ | |
608 | static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = | |
a60e654b | 609 | SOC_DAPM_ENUM("Route", aic3x_line2l_2_ldac_enum); |
44d0a879 VB |
610 | |
611 | /* Right Line2 Mux */ | |
612 | static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = | |
a60e654b | 613 | SOC_DAPM_ENUM("Route", aic3x_line2r_2_rdac_enum); |
44d0a879 | 614 | |
44d0a879 VB |
615 | static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { |
616 | /* Left DAC to Left Outputs */ | |
617 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), | |
618 | SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, | |
619 | &aic3x_left_dac_mux_controls), | |
44d0a879 VB |
620 | SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, |
621 | &aic3x_left_hpcom_mux_controls), | |
622 | SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), | |
623 | SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), | |
624 | SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), | |
625 | ||
626 | /* Right DAC to Right Outputs */ | |
627 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), | |
628 | SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, | |
629 | &aic3x_right_dac_mux_controls), | |
44d0a879 VB |
630 | SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, |
631 | &aic3x_right_hpcom_mux_controls), | |
632 | SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), | |
633 | SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), | |
634 | SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), | |
635 | ||
54f01916 | 636 | /* Inputs to Left ADC */ |
44d0a879 | 637 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), |
44d0a879 | 638 | SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, |
404b5665 | 639 | &aic3x_left_line1l_mux_controls), |
54f01916 | 640 | SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, |
404b5665 | 641 | &aic3x_left_line1r_mux_controls), |
44d0a879 | 642 | |
54f01916 | 643 | /* Inputs to Right ADC */ |
44d0a879 VB |
644 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", |
645 | LINE1R_2_RADC_CTRL, 2, 0), | |
54f01916 | 646 | SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, |
404b5665 | 647 | &aic3x_right_line1l_mux_controls), |
44d0a879 | 648 | SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, |
404b5665 | 649 | &aic3x_right_line1r_mux_controls), |
9503112d JS |
650 | |
651 | /* Mic Bias */ | |
652 | SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0, | |
653 | mic_bias_event, | |
654 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
655 | ||
656 | SND_SOC_DAPM_OUTPUT("LLOUT"), | |
657 | SND_SOC_DAPM_OUTPUT("RLOUT"), | |
658 | SND_SOC_DAPM_OUTPUT("HPLOUT"), | |
659 | SND_SOC_DAPM_OUTPUT("HPROUT"), | |
660 | SND_SOC_DAPM_OUTPUT("HPLCOM"), | |
661 | SND_SOC_DAPM_OUTPUT("HPRCOM"), | |
662 | ||
663 | SND_SOC_DAPM_INPUT("LINE1L"), | |
664 | SND_SOC_DAPM_INPUT("LINE1R"), | |
665 | ||
666 | /* | |
667 | * Virtual output pin to detection block inside codec. This can be | |
668 | * used to keep codec bias on if gpio or detection features are needed. | |
669 | * Force pin on or construct a path with an input jack and mic bias | |
670 | * widgets. | |
671 | */ | |
672 | SND_SOC_DAPM_OUTPUT("Detection"), | |
673 | }; | |
674 | ||
675 | /* For other than tlv320aic3104 */ | |
676 | static const struct snd_soc_dapm_widget aic3x_extra_dapm_widgets[] = { | |
677 | /* Inputs to Left ADC */ | |
678 | SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, | |
679 | &aic3x_left_pga_mixer_controls[0], | |
680 | ARRAY_SIZE(aic3x_left_pga_mixer_controls)), | |
681 | SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, | |
682 | &aic3x_left_line2_mux_controls), | |
683 | ||
684 | /* Inputs to Right ADC */ | |
685 | SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, | |
686 | &aic3x_right_pga_mixer_controls[0], | |
687 | ARRAY_SIZE(aic3x_right_pga_mixer_controls)), | |
44d0a879 VB |
688 | SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, |
689 | &aic3x_right_line2_mux_controls), | |
690 | ||
ee15ffdb JN |
691 | /* |
692 | * Not a real mic bias widget but similar function. This is for dynamic | |
693 | * control of GPIO1 digital mic modulator clock output function when | |
694 | * using digital mic. | |
695 | */ | |
696 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", | |
697 | AIC3X_GPIO1_REG, 4, 0xf, | |
698 | AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, | |
699 | AIC3X_GPIO1_FUNC_DISABLED), | |
700 | ||
701 | /* | |
702 | * Also similar function like mic bias. Selects digital mic with | |
703 | * configurable oversampling rate instead of ADC converter. | |
704 | */ | |
705 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", | |
706 | AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), | |
707 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", | |
708 | AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), | |
709 | SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", | |
710 | AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), | |
711 | ||
c3b79e05 JN |
712 | /* Output mixers */ |
713 | SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, | |
714 | &aic3x_left_line_mixer_controls[0], | |
715 | ARRAY_SIZE(aic3x_left_line_mixer_controls)), | |
716 | SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, | |
717 | &aic3x_right_line_mixer_controls[0], | |
718 | ARRAY_SIZE(aic3x_right_line_mixer_controls)), | |
c3b79e05 JN |
719 | SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, |
720 | &aic3x_left_hp_mixer_controls[0], | |
721 | ARRAY_SIZE(aic3x_left_hp_mixer_controls)), | |
722 | SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, | |
723 | &aic3x_right_hp_mixer_controls[0], | |
724 | ARRAY_SIZE(aic3x_right_hp_mixer_controls)), | |
725 | SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, | |
726 | &aic3x_left_hpcom_mixer_controls[0], | |
727 | ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), | |
728 | SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, | |
729 | &aic3x_right_hpcom_mixer_controls[0], | |
730 | ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), | |
44d0a879 | 731 | |
44d0a879 VB |
732 | SND_SOC_DAPM_INPUT("MIC3L"), |
733 | SND_SOC_DAPM_INPUT("MIC3R"), | |
44d0a879 VB |
734 | SND_SOC_DAPM_INPUT("LINE2L"), |
735 | SND_SOC_DAPM_INPUT("LINE2R"), | |
9503112d | 736 | }; |
19f7ac50 | 737 | |
9503112d JS |
738 | /* For tlv320aic3104 */ |
739 | static const struct snd_soc_dapm_widget aic3104_extra_dapm_widgets[] = { | |
740 | /* Inputs to Left ADC */ | |
741 | SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, | |
742 | &aic3104_left_pga_mixer_controls[0], | |
743 | ARRAY_SIZE(aic3104_left_pga_mixer_controls)), | |
744 | ||
745 | /* Inputs to Right ADC */ | |
746 | SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, | |
747 | &aic3104_right_pga_mixer_controls[0], | |
748 | ARRAY_SIZE(aic3104_right_pga_mixer_controls)), | |
749 | ||
750 | /* Output mixers */ | |
751 | SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, | |
752 | &aic3x_left_line_mixer_controls[0], | |
753 | ARRAY_SIZE(aic3x_left_line_mixer_controls) - 2), | |
754 | SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, | |
755 | &aic3x_right_line_mixer_controls[0], | |
756 | ARRAY_SIZE(aic3x_right_line_mixer_controls) - 2), | |
757 | SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, | |
758 | &aic3x_left_hp_mixer_controls[0], | |
759 | ARRAY_SIZE(aic3x_left_hp_mixer_controls) - 2), | |
760 | SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, | |
761 | &aic3x_right_hp_mixer_controls[0], | |
762 | ARRAY_SIZE(aic3x_right_hp_mixer_controls) - 2), | |
763 | SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, | |
764 | &aic3x_left_hpcom_mixer_controls[0], | |
765 | ARRAY_SIZE(aic3x_left_hpcom_mixer_controls) - 2), | |
766 | SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, | |
767 | &aic3x_right_hpcom_mixer_controls[0], | |
768 | ARRAY_SIZE(aic3x_right_hpcom_mixer_controls) - 2), | |
769 | ||
770 | SND_SOC_DAPM_INPUT("MIC2L"), | |
771 | SND_SOC_DAPM_INPUT("MIC2R"), | |
44d0a879 VB |
772 | }; |
773 | ||
58381da6 JW |
774 | static const struct snd_soc_dapm_widget aic3x_dapm_mono_widgets[] = { |
775 | /* Mono Output */ | |
776 | SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), | |
777 | ||
778 | SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, | |
779 | &aic3x_mono_mixer_controls[0], | |
780 | ARRAY_SIZE(aic3x_mono_mixer_controls)), | |
781 | ||
782 | SND_SOC_DAPM_OUTPUT("MONO_LOUT"), | |
783 | }; | |
784 | ||
6184f105 RC |
785 | static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { |
786 | /* Class-D outputs */ | |
787 | SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0), | |
788 | SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0), | |
789 | ||
790 | SND_SOC_DAPM_OUTPUT("SPOP"), | |
791 | SND_SOC_DAPM_OUTPUT("SPOM"), | |
792 | }; | |
793 | ||
d0cc0d3a | 794 | static const struct snd_soc_dapm_route intercon[] = { |
44d0a879 VB |
795 | /* Left Input */ |
796 | {"Left Line1L Mux", "single-ended", "LINE1L"}, | |
797 | {"Left Line1L Mux", "differential", "LINE1L"}, | |
6b2afee1 PU |
798 | {"Left Line1R Mux", "single-ended", "LINE1R"}, |
799 | {"Left Line1R Mux", "differential", "LINE1R"}, | |
44d0a879 | 800 | |
44d0a879 | 801 | {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, |
54f01916 | 802 | {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, |
44d0a879 VB |
803 | |
804 | {"Left ADC", NULL, "Left PGA Mixer"}, | |
805 | ||
806 | /* Right Input */ | |
807 | {"Right Line1R Mux", "single-ended", "LINE1R"}, | |
808 | {"Right Line1R Mux", "differential", "LINE1R"}, | |
6b2afee1 PU |
809 | {"Right Line1L Mux", "single-ended", "LINE1L"}, |
810 | {"Right Line1L Mux", "differential", "LINE1L"}, | |
44d0a879 | 811 | |
54f01916 | 812 | {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, |
44d0a879 | 813 | {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, |
44d0a879 VB |
814 | |
815 | {"Right ADC", NULL, "Right PGA Mixer"}, | |
c3b79e05 JN |
816 | |
817 | /* Left DAC Output */ | |
818 | {"Left DAC Mux", "DAC_L1", "Left DAC"}, | |
819 | {"Left DAC Mux", "DAC_L2", "Left DAC"}, | |
820 | {"Left DAC Mux", "DAC_L3", "Left DAC"}, | |
821 | ||
822 | /* Right DAC Output */ | |
823 | {"Right DAC Mux", "DAC_R1", "Right DAC"}, | |
824 | {"Right DAC Mux", "DAC_R2", "Right DAC"}, | |
825 | {"Right DAC Mux", "DAC_R3", "Right DAC"}, | |
826 | ||
827 | /* Left Line Output */ | |
c3b79e05 JN |
828 | {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, |
829 | {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, | |
c3b79e05 JN |
830 | {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, |
831 | {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, | |
832 | ||
833 | {"Left Line Out", NULL, "Left Line Mixer"}, | |
834 | {"Left Line Out", NULL, "Left DAC Mux"}, | |
835 | {"LLOUT", NULL, "Left Line Out"}, | |
836 | ||
837 | /* Right Line Output */ | |
c3b79e05 JN |
838 | {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, |
839 | {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, | |
c3b79e05 JN |
840 | {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, |
841 | {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, | |
842 | ||
843 | {"Right Line Out", NULL, "Right Line Mixer"}, | |
844 | {"Right Line Out", NULL, "Right DAC Mux"}, | |
845 | {"RLOUT", NULL, "Right Line Out"}, | |
846 | ||
c3b79e05 | 847 | /* Left HP Output */ |
c3b79e05 JN |
848 | {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, |
849 | {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, | |
c3b79e05 JN |
850 | {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, |
851 | {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, | |
852 | ||
853 | {"Left HP Out", NULL, "Left HP Mixer"}, | |
854 | {"Left HP Out", NULL, "Left DAC Mux"}, | |
855 | {"HPLOUT", NULL, "Left HP Out"}, | |
856 | ||
857 | /* Right HP Output */ | |
c3b79e05 JN |
858 | {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, |
859 | {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, | |
c3b79e05 JN |
860 | {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, |
861 | {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, | |
862 | ||
863 | {"Right HP Out", NULL, "Right HP Mixer"}, | |
864 | {"Right HP Out", NULL, "Right DAC Mux"}, | |
865 | {"HPROUT", NULL, "Right HP Out"}, | |
866 | ||
867 | /* Left HPCOM Output */ | |
c3b79e05 JN |
868 | {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, |
869 | {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, | |
c3b79e05 JN |
870 | {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, |
871 | {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, | |
872 | ||
873 | {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, | |
874 | {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, | |
875 | {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, | |
876 | {"Left HP Com", NULL, "Left HPCOM Mux"}, | |
877 | {"HPLCOM", NULL, "Left HP Com"}, | |
878 | ||
879 | /* Right HPCOM Output */ | |
c3b79e05 JN |
880 | {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, |
881 | {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, | |
c3b79e05 JN |
882 | {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, |
883 | {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, | |
884 | ||
885 | {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, | |
886 | {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, | |
887 | {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, | |
888 | {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, | |
889 | {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, | |
890 | {"Right HP Com", NULL, "Right HPCOM Mux"}, | |
891 | {"HPRCOM", NULL, "Right HP Com"}, | |
44d0a879 VB |
892 | }; |
893 | ||
9503112d JS |
894 | /* For other than tlv320aic3104 */ |
895 | static const struct snd_soc_dapm_route intercon_extra[] = { | |
896 | /* Left Input */ | |
897 | {"Left Line2L Mux", "single-ended", "LINE2L"}, | |
898 | {"Left Line2L Mux", "differential", "LINE2L"}, | |
899 | ||
900 | {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, | |
901 | {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, | |
902 | {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, | |
903 | ||
904 | {"Left ADC", NULL, "GPIO1 dmic modclk"}, | |
905 | ||
906 | /* Right Input */ | |
907 | {"Right Line2R Mux", "single-ended", "LINE2R"}, | |
908 | {"Right Line2R Mux", "differential", "LINE2R"}, | |
909 | ||
910 | {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, | |
911 | {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, | |
912 | {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, | |
913 | ||
914 | {"Right ADC", NULL, "GPIO1 dmic modclk"}, | |
915 | ||
916 | /* | |
917 | * Logical path between digital mic enable and GPIO1 modulator clock | |
918 | * output function | |
919 | */ | |
920 | {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, | |
921 | {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, | |
922 | {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, | |
923 | ||
924 | /* Left Line Output */ | |
925 | {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | |
926 | {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | |
927 | ||
928 | /* Right Line Output */ | |
929 | {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | |
930 | {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | |
931 | ||
932 | /* Left HP Output */ | |
933 | {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | |
934 | {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | |
935 | ||
936 | /* Right HP Output */ | |
937 | {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | |
938 | {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | |
939 | ||
940 | /* Left HPCOM Output */ | |
941 | {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | |
942 | {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | |
943 | ||
944 | /* Right HPCOM Output */ | |
945 | {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | |
946 | {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | |
947 | }; | |
948 | ||
b8255930 | 949 | /* For tlv320aic3104 */ |
9503112d JS |
950 | static const struct snd_soc_dapm_route intercon_extra_3104[] = { |
951 | /* Left Input */ | |
952 | {"Left PGA Mixer", "Mic2L Switch", "MIC2L"}, | |
953 | {"Left PGA Mixer", "Mic2R Switch", "MIC2R"}, | |
954 | ||
955 | /* Right Input */ | |
956 | {"Right PGA Mixer", "Mic2L Switch", "MIC2L"}, | |
957 | {"Right PGA Mixer", "Mic2R Switch", "MIC2R"}, | |
958 | }; | |
959 | ||
58381da6 JW |
960 | static const struct snd_soc_dapm_route intercon_mono[] = { |
961 | /* Mono Output */ | |
962 | {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, | |
963 | {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, | |
964 | {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, | |
965 | {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, | |
966 | {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, | |
967 | {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, | |
968 | {"Mono Out", NULL, "Mono Mixer"}, | |
969 | {"MONO_LOUT", NULL, "Mono Out"}, | |
970 | }; | |
971 | ||
6184f105 RC |
972 | static const struct snd_soc_dapm_route intercon_3007[] = { |
973 | /* Class-D outputs */ | |
974 | {"Left Class-D Out", NULL, "Left Line Out"}, | |
975 | {"Right Class-D Out", NULL, "Left Line Out"}, | |
976 | {"SPOP", NULL, "Left Class-D Out"}, | |
977 | {"SPOM", NULL, "Right Class-D Out"}, | |
978 | }; | |
979 | ||
44d0a879 VB |
980 | static int aic3x_add_widgets(struct snd_soc_codec *codec) |
981 | { | |
6184f105 | 982 | struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); |
650a18ac | 983 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
6184f105 | 984 | |
58381da6 JW |
985 | switch (aic3x->model) { |
986 | case AIC3X_MODEL_3X: | |
987 | case AIC3X_MODEL_33: | |
9503112d JS |
988 | snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets, |
989 | ARRAY_SIZE(aic3x_extra_dapm_widgets)); | |
990 | snd_soc_dapm_add_routes(dapm, intercon_extra, | |
991 | ARRAY_SIZE(intercon_extra)); | |
58381da6 JW |
992 | snd_soc_dapm_new_controls(dapm, aic3x_dapm_mono_widgets, |
993 | ARRAY_SIZE(aic3x_dapm_mono_widgets)); | |
994 | snd_soc_dapm_add_routes(dapm, intercon_mono, | |
995 | ARRAY_SIZE(intercon_mono)); | |
996 | break; | |
997 | case AIC3X_MODEL_3007: | |
9503112d JS |
998 | snd_soc_dapm_new_controls(dapm, aic3x_extra_dapm_widgets, |
999 | ARRAY_SIZE(aic3x_extra_dapm_widgets)); | |
1000 | snd_soc_dapm_add_routes(dapm, intercon_extra, | |
1001 | ARRAY_SIZE(intercon_extra)); | |
ce6120cc | 1002 | snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, |
6184f105 | 1003 | ARRAY_SIZE(aic3007_dapm_widgets)); |
ce6120cc LG |
1004 | snd_soc_dapm_add_routes(dapm, intercon_3007, |
1005 | ARRAY_SIZE(intercon_3007)); | |
58381da6 | 1006 | break; |
9503112d JS |
1007 | case AIC3X_MODEL_3104: |
1008 | snd_soc_dapm_new_controls(dapm, aic3104_extra_dapm_widgets, | |
1009 | ARRAY_SIZE(aic3104_extra_dapm_widgets)); | |
1010 | snd_soc_dapm_add_routes(dapm, intercon_extra_3104, | |
1011 | ARRAY_SIZE(intercon_extra_3104)); | |
1012 | break; | |
6184f105 RC |
1013 | } |
1014 | ||
44d0a879 VB |
1015 | return 0; |
1016 | } | |
1017 | ||
44d0a879 | 1018 | static int aic3x_hw_params(struct snd_pcm_substream *substream, |
dee89c4d MB |
1019 | struct snd_pcm_hw_params *params, |
1020 | struct snd_soc_dai *dai) | |
44d0a879 | 1021 | { |
e6968a17 | 1022 | struct snd_soc_codec *codec = dai->codec; |
b2c812e2 | 1023 | struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); |
4f9c16cc | 1024 | int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; |
255173b4 PM |
1025 | u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; |
1026 | u16 d, pll_d = 1; | |
255173b4 | 1027 | int clk; |
44d0a879 | 1028 | |
4f9c16cc | 1029 | /* select data word length */ |
e18eca43 | 1030 | data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4)); |
3e3e2922 MB |
1031 | switch (params_width(params)) { |
1032 | case 16: | |
44d0a879 | 1033 | break; |
3e3e2922 | 1034 | case 20: |
4f9c16cc | 1035 | data |= (0x01 << 4); |
44d0a879 | 1036 | break; |
3e3e2922 | 1037 | case 24: |
4f9c16cc | 1038 | data |= (0x02 << 4); |
44d0a879 | 1039 | break; |
3e3e2922 | 1040 | case 32: |
4f9c16cc | 1041 | data |= (0x03 << 4); |
44d0a879 VB |
1042 | break; |
1043 | } | |
e18eca43 | 1044 | snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data); |
4f9c16cc DM |
1045 | |
1046 | /* Fsref can be 44100 or 48000 */ | |
1047 | fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000; | |
1048 | ||
1049 | /* Try to find a value for Q which allows us to bypass the PLL and | |
1050 | * generate CODEC_CLK directly. */ | |
1051 | for (pll_q = 2; pll_q < 18; pll_q++) | |
1052 | if (aic3x->sysclk / (128 * pll_q) == fsref) { | |
1053 | bypass_pll = 1; | |
1054 | break; | |
1055 | } | |
1056 | ||
1057 | if (bypass_pll) { | |
1058 | pll_q &= 0xf; | |
e18eca43 JN |
1059 | snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); |
1060 | snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); | |
06c71282 | 1061 | /* disable PLL if it is bypassed */ |
9c173d15 | 1062 | snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); |
06c71282 C |
1063 | |
1064 | } else { | |
e18eca43 | 1065 | snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); |
06c71282 | 1066 | /* enable PLL when it is used */ |
9c173d15 AL |
1067 | snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, |
1068 | PLL_ENABLE, PLL_ENABLE); | |
06c71282 | 1069 | } |
4f9c16cc DM |
1070 | |
1071 | /* Route Left DAC to left channel input and | |
1072 | * right DAC to right channel input */ | |
1073 | data = (LDAC2LCH | RDAC2RCH); | |
1074 | data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000; | |
1075 | if (params_rate(params) >= 64000) | |
1076 | data |= DUAL_RATE_MODE; | |
e18eca43 | 1077 | snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data); |
44d0a879 VB |
1078 | |
1079 | /* codec sample rate select */ | |
4f9c16cc DM |
1080 | data = (fsref * 20) / params_rate(params); |
1081 | if (params_rate(params) < 64000) | |
1082 | data /= 2; | |
1083 | data /= 5; | |
1084 | data -= 2; | |
44d0a879 | 1085 | data |= (data << 4); |
e18eca43 | 1086 | snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data); |
44d0a879 | 1087 | |
4f9c16cc DM |
1088 | if (bypass_pll) |
1089 | return 0; | |
1090 | ||
25985edc | 1091 | /* Use PLL, compute appropriate setup for j, d, r and p, the closest |
255173b4 PM |
1092 | * one wins the game. Try with d==0 first, next with d!=0. |
1093 | * Constraints for j are according to the datasheet. | |
4f9c16cc | 1094 | * The sysclk is divided by 1000 to prevent integer overflows. |
44d0a879 | 1095 | */ |
255173b4 | 1096 | |
4f9c16cc DM |
1097 | codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000); |
1098 | ||
1099 | for (r = 1; r <= 16; r++) | |
1100 | for (p = 1; p <= 8; p++) { | |
255173b4 PM |
1101 | for (j = 4; j <= 55; j++) { |
1102 | /* This is actually 1000*((j+(d/10000))*r)/p | |
1103 | * The term had to be converted to get | |
1104 | * rid of the division by 10000; d = 0 here | |
1105 | */ | |
5baf8315 | 1106 | int tmp_clk = (1000 * j * r) / p; |
255173b4 PM |
1107 | |
1108 | /* Check whether this values get closer than | |
1109 | * the best ones we had before | |
1110 | */ | |
5baf8315 | 1111 | if (abs(codec_clk - tmp_clk) < |
255173b4 PM |
1112 | abs(codec_clk - last_clk)) { |
1113 | pll_j = j; pll_d = 0; | |
1114 | pll_r = r; pll_p = p; | |
5baf8315 | 1115 | last_clk = tmp_clk; |
255173b4 PM |
1116 | } |
1117 | ||
1118 | /* Early exit for exact matches */ | |
5baf8315 | 1119 | if (tmp_clk == codec_clk) |
255173b4 PM |
1120 | goto found; |
1121 | } | |
1122 | } | |
4f9c16cc | 1123 | |
255173b4 PM |
1124 | /* try with d != 0 */ |
1125 | for (p = 1; p <= 8; p++) { | |
1126 | j = codec_clk * p / 1000; | |
4f9c16cc | 1127 | |
255173b4 PM |
1128 | if (j < 4 || j > 11) |
1129 | continue; | |
4f9c16cc | 1130 | |
255173b4 PM |
1131 | /* do not use codec_clk here since we'd loose precision */ |
1132 | d = ((2048 * p * fsref) - j * aic3x->sysclk) | |
1133 | * 100 / (aic3x->sysclk/100); | |
4f9c16cc | 1134 | |
255173b4 | 1135 | clk = (10000 * j + d) / (10 * p); |
4f9c16cc | 1136 | |
255173b4 PM |
1137 | /* check whether this values get closer than the best |
1138 | * ones we had before */ | |
1139 | if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) { | |
1140 | pll_j = j; pll_d = d; pll_r = 1; pll_p = p; | |
1141 | last_clk = clk; | |
4f9c16cc DM |
1142 | } |
1143 | ||
255173b4 PM |
1144 | /* Early exit for exact matches */ |
1145 | if (clk == codec_clk) | |
1146 | goto found; | |
1147 | } | |
1148 | ||
4f9c16cc DM |
1149 | if (last_clk == 0) { |
1150 | printk(KERN_ERR "%s(): unable to setup PLL\n", __func__); | |
1151 | return -EINVAL; | |
1152 | } | |
44d0a879 | 1153 | |
255173b4 | 1154 | found: |
c9fe573a | 1155 | snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p); |
e18eca43 JN |
1156 | snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG, |
1157 | pll_r << PLLR_SHIFT); | |
1158 | snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT); | |
1159 | snd_soc_write(codec, AIC3X_PLL_PROGC_REG, | |
1160 | (pll_d >> 6) << PLLD_MSB_SHIFT); | |
1161 | snd_soc_write(codec, AIC3X_PLL_PROGD_REG, | |
1162 | (pll_d & 0x3F) << PLLD_LSB_SHIFT); | |
44d0a879 | 1163 | |
44d0a879 VB |
1164 | return 0; |
1165 | } | |
1166 | ||
36849409 PU |
1167 | static int aic3x_prepare(struct snd_pcm_substream *substream, |
1168 | struct snd_soc_dai *dai) | |
1169 | { | |
1170 | struct snd_soc_codec *codec = dai->codec; | |
1171 | struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); | |
1172 | int delay = 0; | |
1173 | ||
1174 | /* TDM slot selection only valid in DSP_A/_B mode */ | |
1175 | if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_A) | |
1176 | delay += (aic3x->tdm_delay + 1); | |
1177 | else if (aic3x->dai_fmt == SND_SOC_DAIFMT_DSP_B) | |
1178 | delay += aic3x->tdm_delay; | |
1179 | ||
1180 | /* Configure data delay */ | |
0b65ba99 | 1181 | snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay); |
36849409 PU |
1182 | |
1183 | return 0; | |
1184 | } | |
1185 | ||
e550e17f | 1186 | static int aic3x_mute(struct snd_soc_dai *dai, int mute) |
44d0a879 VB |
1187 | { |
1188 | struct snd_soc_codec *codec = dai->codec; | |
e18eca43 JN |
1189 | u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON; |
1190 | u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON; | |
44d0a879 VB |
1191 | |
1192 | if (mute) { | |
e18eca43 JN |
1193 | snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); |
1194 | snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); | |
44d0a879 | 1195 | } else { |
e18eca43 JN |
1196 | snd_soc_write(codec, LDAC_VOL, ldac_reg); |
1197 | snd_soc_write(codec, RDAC_VOL, rdac_reg); | |
44d0a879 VB |
1198 | } |
1199 | ||
1200 | return 0; | |
1201 | } | |
1202 | ||
e550e17f | 1203 | static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, |
44d0a879 VB |
1204 | int clk_id, unsigned int freq, int dir) |
1205 | { | |
1206 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1207 | struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); |
44d0a879 | 1208 | |
a1f34af0 JP |
1209 | /* set clock on MCLK or GPIO2 or BCLK */ |
1210 | snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK, | |
1211 | clk_id << PLLCLK_IN_SHIFT); | |
1212 | snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK, | |
1213 | clk_id << CLKDIV_IN_SHIFT); | |
1214 | ||
4f9c16cc DM |
1215 | aic3x->sysclk = freq; |
1216 | return 0; | |
44d0a879 VB |
1217 | } |
1218 | ||
e550e17f | 1219 | static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, |
44d0a879 VB |
1220 | unsigned int fmt) |
1221 | { | |
1222 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 1223 | struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); |
81971a14 JN |
1224 | u8 iface_areg, iface_breg; |
1225 | ||
e18eca43 JN |
1226 | iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; |
1227 | iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; | |
44d0a879 VB |
1228 | |
1229 | /* set master/slave audio interface */ | |
1230 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1231 | case SND_SOC_DAIFMT_CBM_CFM: | |
1232 | aic3x->master = 1; | |
1233 | iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; | |
1234 | break; | |
1235 | case SND_SOC_DAIFMT_CBS_CFS: | |
1236 | aic3x->master = 0; | |
68e47981 | 1237 | iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER); |
44d0a879 VB |
1238 | break; |
1239 | default: | |
1240 | return -EINVAL; | |
1241 | } | |
1242 | ||
4b7d2831 JN |
1243 | /* |
1244 | * match both interface format and signal polarities since they | |
1245 | * are fixed | |
1246 | */ | |
1247 | switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | | |
1248 | SND_SOC_DAIFMT_INV_MASK)) { | |
1249 | case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): | |
44d0a879 | 1250 | break; |
a24f4f68 | 1251 | case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): |
4b7d2831 | 1252 | case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): |
44d0a879 VB |
1253 | iface_breg |= (0x01 << 6); |
1254 | break; | |
4b7d2831 | 1255 | case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF): |
44d0a879 VB |
1256 | iface_breg |= (0x02 << 6); |
1257 | break; | |
4b7d2831 | 1258 | case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF): |
44d0a879 VB |
1259 | iface_breg |= (0x03 << 6); |
1260 | break; | |
1261 | default: | |
1262 | return -EINVAL; | |
1263 | } | |
1264 | ||
36849409 PU |
1265 | aic3x->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; |
1266 | ||
44d0a879 | 1267 | /* set iface */ |
e18eca43 JN |
1268 | snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg); |
1269 | snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg); | |
36849409 PU |
1270 | |
1271 | return 0; | |
1272 | } | |
1273 | ||
1274 | static int aic3x_set_dai_tdm_slot(struct snd_soc_dai *codec_dai, | |
1275 | unsigned int tx_mask, unsigned int rx_mask, | |
1276 | int slots, int slot_width) | |
1277 | { | |
1278 | struct snd_soc_codec *codec = codec_dai->codec; | |
1279 | struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); | |
1280 | unsigned int lsb; | |
1281 | ||
1282 | if (tx_mask != rx_mask) { | |
1283 | dev_err(codec->dev, "tx and rx masks must be symmetric\n"); | |
1284 | return -EINVAL; | |
1285 | } | |
1286 | ||
1287 | if (unlikely(!tx_mask)) { | |
1288 | dev_err(codec->dev, "tx and rx masks need to be non 0\n"); | |
1289 | return -EINVAL; | |
1290 | } | |
1291 | ||
1292 | /* TDM based on DSP mode requires slots to be adjacent */ | |
1293 | lsb = __ffs(tx_mask); | |
1294 | if ((lsb + 1) != __fls(tx_mask)) { | |
1295 | dev_err(codec->dev, "Invalid mask, slots must be adjacent\n"); | |
1296 | return -EINVAL; | |
1297 | } | |
1298 | ||
1299 | aic3x->tdm_delay = lsb * slot_width; | |
1300 | ||
1301 | /* DOUT in high-impedance on inactive bit clocks */ | |
1302 | snd_soc_update_bits(codec, AIC3X_ASD_INTF_CTRLA, | |
1303 | DOUT_TRISTATE, DOUT_TRISTATE); | |
44d0a879 VB |
1304 | |
1305 | return 0; | |
1306 | } | |
1307 | ||
5a895f8a JN |
1308 | static int aic3x_regulator_event(struct notifier_block *nb, |
1309 | unsigned long event, void *data) | |
1310 | { | |
1311 | struct aic3x_disable_nb *disable_nb = | |
1312 | container_of(nb, struct aic3x_disable_nb, nb); | |
1313 | struct aic3x_priv *aic3x = disable_nb->aic3x; | |
1314 | ||
1315 | if (event & REGULATOR_EVENT_DISABLE) { | |
1316 | /* | |
1317 | * Put codec to reset and require cache sync as at least one | |
1318 | * of the supplies was disabled | |
1319 | */ | |
79ee820d | 1320 | if (gpio_is_valid(aic3x->gpio_reset)) |
5a895f8a | 1321 | gpio_set_value(aic3x->gpio_reset, 0); |
2a6fedec | 1322 | regcache_mark_dirty(aic3x->regmap); |
5a895f8a JN |
1323 | } |
1324 | ||
1325 | return 0; | |
1326 | } | |
1327 | ||
6c1a7d40 JN |
1328 | static int aic3x_set_power(struct snd_soc_codec *codec, int power) |
1329 | { | |
1330 | struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); | |
31d9f8fa | 1331 | unsigned int pll_c, pll_d; |
2a6fedec | 1332 | int ret; |
6c1a7d40 JN |
1333 | |
1334 | if (power) { | |
1335 | ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), | |
1336 | aic3x->supplies); | |
1337 | if (ret) | |
1338 | goto out; | |
1339 | aic3x->power = 1; | |
5a895f8a | 1340 | |
79ee820d | 1341 | if (gpio_is_valid(aic3x->gpio_reset)) { |
6c1a7d40 JN |
1342 | udelay(1); |
1343 | gpio_set_value(aic3x->gpio_reset, 1); | |
1344 | } | |
1345 | ||
1346 | /* Sync reg_cache with the hardware */ | |
2a6fedec MB |
1347 | regcache_cache_only(aic3x->regmap, false); |
1348 | regcache_sync(aic3x->regmap); | |
31d9f8fa DL |
1349 | |
1350 | /* Rewrite paired PLL D registers in case cached sync skipped | |
1351 | * writing one of them and thus caused other one also not | |
1352 | * being written | |
1353 | */ | |
1354 | pll_c = snd_soc_read(codec, AIC3X_PLL_PROGC_REG); | |
1355 | pll_d = snd_soc_read(codec, AIC3X_PLL_PROGD_REG); | |
1356 | if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def || | |
1357 | pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) { | |
1358 | snd_soc_write(codec, AIC3X_PLL_PROGC_REG, pll_c); | |
1359 | snd_soc_write(codec, AIC3X_PLL_PROGD_REG, pll_d); | |
1360 | } | |
6c1a7d40 | 1361 | } else { |
9fb352b1 JN |
1362 | /* |
1363 | * Do soft reset to this codec instance in order to clear | |
1364 | * possible VDD leakage currents in case the supply regulators | |
1365 | * remain on | |
1366 | */ | |
1367 | snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); | |
2a6fedec | 1368 | regcache_mark_dirty(aic3x->regmap); |
6c1a7d40 | 1369 | aic3x->power = 0; |
5a895f8a | 1370 | /* HW writes are needless when bias is off */ |
2a6fedec | 1371 | regcache_cache_only(aic3x->regmap, true); |
6c1a7d40 JN |
1372 | ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), |
1373 | aic3x->supplies); | |
1374 | } | |
1375 | out: | |
1376 | return ret; | |
1377 | } | |
1378 | ||
0be9898a MB |
1379 | static int aic3x_set_bias_level(struct snd_soc_codec *codec, |
1380 | enum snd_soc_bias_level level) | |
44d0a879 | 1381 | { |
b2c812e2 | 1382 | struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); |
44d0a879 | 1383 | |
0be9898a MB |
1384 | switch (level) { |
1385 | case SND_SOC_BIAS_ON: | |
db13802e JN |
1386 | break; |
1387 | case SND_SOC_BIAS_PREPARE: | |
650a18ac | 1388 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY && |
c23fd751 | 1389 | aic3x->master) { |
44d0a879 | 1390 | /* enable pll */ |
9c173d15 AL |
1391 | snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, |
1392 | PLL_ENABLE, PLL_ENABLE); | |
44d0a879 VB |
1393 | } |
1394 | break; | |
0be9898a | 1395 | case SND_SOC_BIAS_STANDBY: |
6c1a7d40 JN |
1396 | if (!aic3x->power) |
1397 | aic3x_set_power(codec, 1); | |
650a18ac | 1398 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_PREPARE && |
c23fd751 | 1399 | aic3x->master) { |
44d0a879 | 1400 | /* disable pll */ |
9c173d15 AL |
1401 | snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, |
1402 | PLL_ENABLE, 0); | |
44d0a879 VB |
1403 | } |
1404 | break; | |
c23fd751 | 1405 | case SND_SOC_BIAS_OFF: |
6c1a7d40 JN |
1406 | if (aic3x->power) |
1407 | aic3x_set_power(codec, 0); | |
c23fd751 | 1408 | break; |
44d0a879 | 1409 | } |
44d0a879 VB |
1410 | |
1411 | return 0; | |
1412 | } | |
1413 | ||
1414 | #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 | |
1415 | #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
2a11a10a PU |
1416 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE | \ |
1417 | SNDRV_PCM_FMTBIT_S32_LE) | |
44d0a879 | 1418 | |
85e7652d | 1419 | static const struct snd_soc_dai_ops aic3x_dai_ops = { |
6335d055 | 1420 | .hw_params = aic3x_hw_params, |
36849409 | 1421 | .prepare = aic3x_prepare, |
6335d055 EM |
1422 | .digital_mute = aic3x_mute, |
1423 | .set_sysclk = aic3x_set_dai_sysclk, | |
1424 | .set_fmt = aic3x_set_dai_fmt, | |
36849409 | 1425 | .set_tdm_slot = aic3x_set_dai_tdm_slot, |
6335d055 EM |
1426 | }; |
1427 | ||
f0fba2ad LG |
1428 | static struct snd_soc_dai_driver aic3x_dai = { |
1429 | .name = "tlv320aic3x-hifi", | |
44d0a879 VB |
1430 | .playback = { |
1431 | .stream_name = "Playback", | |
06378da4 | 1432 | .channels_min = 2, |
44d0a879 VB |
1433 | .channels_max = 2, |
1434 | .rates = AIC3X_RATES, | |
1435 | .formats = AIC3X_FORMATS,}, | |
1436 | .capture = { | |
1437 | .stream_name = "Capture", | |
06378da4 | 1438 | .channels_min = 2, |
44d0a879 VB |
1439 | .channels_max = 2, |
1440 | .rates = AIC3X_RATES, | |
1441 | .formats = AIC3X_FORMATS,}, | |
6335d055 | 1442 | .ops = &aic3x_dai_ops, |
14017615 | 1443 | .symmetric_rates = 1, |
44d0a879 | 1444 | }; |
44d0a879 | 1445 | |
58381da6 JW |
1446 | static void aic3x_mono_init(struct snd_soc_codec *codec) |
1447 | { | |
1448 | /* DAC to Mono Line Out default volume and route to Output mixer */ | |
1449 | snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1450 | snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1451 | ||
1452 | /* unmute all outputs */ | |
1453 | snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE); | |
1454 | ||
1455 | /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ | |
1456 | snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1457 | snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1458 | ||
1459 | /* Line2 to Mono Out default volume, disconnect from Output Mixer */ | |
1460 | snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1461 | snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); | |
1462 | } | |
1463 | ||
44d0a879 VB |
1464 | /* |
1465 | * initialise the AIC3X driver | |
1466 | * register the mixer and dsp interfaces with the kernel | |
1467 | */ | |
cb3826f5 | 1468 | static int aic3x_init(struct snd_soc_codec *codec) |
44d0a879 | 1469 | { |
6184f105 | 1470 | struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); |
cb3826f5 | 1471 | |
e18eca43 JN |
1472 | snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); |
1473 | snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); | |
44d0a879 | 1474 | |
44d0a879 | 1475 | /* DAC default volume and mute */ |
e18eca43 JN |
1476 | snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); |
1477 | snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); | |
44d0a879 VB |
1478 | |
1479 | /* DAC to HP default volume and route to Output mixer */ | |
e18eca43 JN |
1480 | snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); |
1481 | snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); | |
1482 | snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); | |
1483 | snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); | |
44d0a879 | 1484 | /* DAC to Line Out default volume and route to Output mixer */ |
e18eca43 JN |
1485 | snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); |
1486 | snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); | |
44d0a879 VB |
1487 | |
1488 | /* unmute all outputs */ | |
9c173d15 AL |
1489 | snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE); |
1490 | snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE); | |
9c173d15 AL |
1491 | snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE); |
1492 | snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE); | |
1493 | snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE); | |
1494 | snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE); | |
44d0a879 VB |
1495 | |
1496 | /* ADC default volume and unmute */ | |
e18eca43 JN |
1497 | snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN); |
1498 | snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN); | |
44d0a879 | 1499 | /* By default route Line1 to ADC PGA mixer */ |
e18eca43 JN |
1500 | snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0); |
1501 | snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0); | |
44d0a879 VB |
1502 | |
1503 | /* PGA to HP Bypass default volume, disconnect from Output Mixer */ | |
e18eca43 JN |
1504 | snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); |
1505 | snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); | |
1506 | snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); | |
1507 | snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); | |
44d0a879 | 1508 | /* PGA to Line Out default volume, disconnect from Output Mixer */ |
e18eca43 JN |
1509 | snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); |
1510 | snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); | |
44d0a879 VB |
1511 | |
1512 | /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ | |
e18eca43 JN |
1513 | snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); |
1514 | snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); | |
1515 | snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); | |
1516 | snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); | |
44d0a879 | 1517 | /* Line2 Line Out default volume, disconnect from Output Mixer */ |
e18eca43 JN |
1518 | snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); |
1519 | snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); | |
44d0a879 | 1520 | |
58381da6 JW |
1521 | switch (aic3x->model) { |
1522 | case AIC3X_MODEL_3X: | |
1523 | case AIC3X_MODEL_33: | |
1524 | aic3x_mono_init(codec); | |
1525 | break; | |
1526 | case AIC3X_MODEL_3007: | |
e18eca43 | 1527 | snd_soc_write(codec, CLASSD_CTRL, 0); |
58381da6 | 1528 | break; |
6184f105 RC |
1529 | } |
1530 | ||
cb3826f5 BD |
1531 | return 0; |
1532 | } | |
54e7e616 | 1533 | |
414c73ab JN |
1534 | static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x) |
1535 | { | |
1536 | struct aic3x_priv *a; | |
1537 | ||
1538 | list_for_each_entry(a, &reset_list, list) { | |
1539 | if (gpio_is_valid(aic3x->gpio_reset) && | |
1540 | aic3x->gpio_reset == a->gpio_reset) | |
1541 | return true; | |
1542 | } | |
1543 | ||
1544 | return false; | |
1545 | } | |
1546 | ||
f0fba2ad | 1547 | static int aic3x_probe(struct snd_soc_codec *codec) |
cb3826f5 | 1548 | { |
f0fba2ad | 1549 | struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); |
2f24111a | 1550 | int ret, i; |
f0fba2ad | 1551 | |
414c73ab | 1552 | INIT_LIST_HEAD(&aic3x->list); |
5a895f8a | 1553 | aic3x->codec = codec; |
cb3826f5 | 1554 | |
5a895f8a JN |
1555 | for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) { |
1556 | aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; | |
1557 | aic3x->disable_nb[i].aic3x = aic3x; | |
1558 | ret = regulator_register_notifier(aic3x->supplies[i].consumer, | |
1559 | &aic3x->disable_nb[i].nb); | |
1560 | if (ret) { | |
1561 | dev_err(codec->dev, | |
1562 | "Failed to request regulator notifier: %d\n", | |
1563 | ret); | |
1564 | goto err_notif; | |
1565 | } | |
1566 | } | |
2f24111a | 1567 | |
2a6fedec | 1568 | regcache_mark_dirty(aic3x->regmap); |
37b47656 JN |
1569 | aic3x_init(codec); |
1570 | ||
f0fba2ad | 1571 | if (aic3x->setup) { |
9503112d JS |
1572 | if (aic3x->model != AIC3X_MODEL_3104) { |
1573 | /* setup GPIO functions */ | |
1574 | snd_soc_write(codec, AIC3X_GPIO1_REG, | |
1575 | (aic3x->setup->gpio_func[0] & 0xf) << 4); | |
1576 | snd_soc_write(codec, AIC3X_GPIO2_REG, | |
1577 | (aic3x->setup->gpio_func[1] & 0xf) << 4); | |
1578 | } else { | |
1579 | dev_warn(codec->dev, "GPIO functionality is not supported on tlv320aic3104\n"); | |
1580 | } | |
44d0a879 VB |
1581 | } |
1582 | ||
58381da6 JW |
1583 | switch (aic3x->model) { |
1584 | case AIC3X_MODEL_3X: | |
1585 | case AIC3X_MODEL_33: | |
9503112d JS |
1586 | snd_soc_add_codec_controls(codec, aic3x_extra_snd_controls, |
1587 | ARRAY_SIZE(aic3x_extra_snd_controls)); | |
58381da6 JW |
1588 | snd_soc_add_codec_controls(codec, aic3x_mono_controls, |
1589 | ARRAY_SIZE(aic3x_mono_controls)); | |
1590 | break; | |
1591 | case AIC3X_MODEL_3007: | |
9503112d JS |
1592 | snd_soc_add_codec_controls(codec, aic3x_extra_snd_controls, |
1593 | ARRAY_SIZE(aic3x_extra_snd_controls)); | |
58381da6 JW |
1594 | snd_soc_add_codec_controls(codec, |
1595 | &aic3x_classd_amp_gain_ctrl, 1); | |
1596 | break; | |
9503112d JS |
1597 | case AIC3X_MODEL_3104: |
1598 | break; | |
58381da6 | 1599 | } |
cb3826f5 | 1600 | |
e2e8bfdf HG |
1601 | /* set mic bias voltage */ |
1602 | switch (aic3x->micbias_vg) { | |
1603 | case AIC3X_MICBIAS_2_0V: | |
1604 | case AIC3X_MICBIAS_2_5V: | |
1605 | case AIC3X_MICBIAS_AVDDV: | |
1606 | snd_soc_update_bits(codec, MICBIAS_CTRL, | |
1607 | MICBIAS_LEVEL_MASK, | |
1608 | (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT); | |
1609 | break; | |
1610 | case AIC3X_MICBIAS_OFF: | |
1611 | /* | |
1612 | * noting to do. target won't enter here. This is just to avoid | |
1613 | * compile time warning "warning: enumeration value | |
1614 | * 'AIC3X_MICBIAS_OFF' not handled in switch" | |
1615 | */ | |
1616 | break; | |
1617 | } | |
1618 | ||
f0fba2ad | 1619 | aic3x_add_widgets(codec); |
cb3826f5 BD |
1620 | |
1621 | return 0; | |
2f24111a | 1622 | |
5a895f8a JN |
1623 | err_notif: |
1624 | while (i--) | |
1625 | regulator_unregister_notifier(aic3x->supplies[i].consumer, | |
1626 | &aic3x->disable_nb[i].nb); | |
2f24111a | 1627 | return ret; |
44d0a879 VB |
1628 | } |
1629 | ||
f0fba2ad | 1630 | static int aic3x_remove(struct snd_soc_codec *codec) |
cb3826f5 | 1631 | { |
2f24111a | 1632 | struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); |
5a895f8a | 1633 | int i; |
2f24111a | 1634 | |
414c73ab | 1635 | list_del(&aic3x->list); |
5a895f8a JN |
1636 | for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) |
1637 | regulator_unregister_notifier(aic3x->supplies[i].consumer, | |
1638 | &aic3x->disable_nb[i].nb); | |
2f24111a | 1639 | |
cb3826f5 BD |
1640 | return 0; |
1641 | } | |
44d0a879 | 1642 | |
f0fba2ad | 1643 | static struct snd_soc_codec_driver soc_codec_dev_aic3x = { |
f0fba2ad | 1644 | .set_bias_level = aic3x_set_bias_level, |
eb3032f8 | 1645 | .idle_bias_off = true, |
f0fba2ad LG |
1646 | .probe = aic3x_probe, |
1647 | .remove = aic3x_remove, | |
f9df1ae6 MB |
1648 | .controls = aic3x_snd_controls, |
1649 | .num_controls = ARRAY_SIZE(aic3x_snd_controls), | |
58a63fbd MB |
1650 | .dapm_widgets = aic3x_dapm_widgets, |
1651 | .num_dapm_widgets = ARRAY_SIZE(aic3x_dapm_widgets), | |
1652 | .dapm_routes = intercon, | |
1653 | .num_dapm_routes = ARRAY_SIZE(intercon), | |
f0fba2ad LG |
1654 | }; |
1655 | ||
44d0a879 VB |
1656 | /* |
1657 | * AIC3X 2 wire address can be up to 4 devices with device addresses | |
1658 | * 0x18, 0x19, 0x1A, 0x1B | |
1659 | */ | |
44d0a879 | 1660 | |
6184f105 | 1661 | static const struct i2c_device_id aic3x_i2c_id[] = { |
177fdd89 AL |
1662 | { "tlv320aic3x", AIC3X_MODEL_3X }, |
1663 | { "tlv320aic33", AIC3X_MODEL_33 }, | |
1664 | { "tlv320aic3007", AIC3X_MODEL_3007 }, | |
cbaa5689 | 1665 | { "tlv320aic3106", AIC3X_MODEL_3X }, |
9503112d | 1666 | { "tlv320aic3104", AIC3X_MODEL_3104 }, |
6184f105 RC |
1667 | { } |
1668 | }; | |
1669 | MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); | |
1670 | ||
2a6fedec MB |
1671 | static const struct reg_default aic3007_class_d[] = { |
1672 | /* Class-D speaker driver init; datasheet p. 46 */ | |
1673 | { AIC3X_PAGE_SELECT, 0x0D }, | |
1674 | { 0xD, 0x0D }, | |
1675 | { 0x8, 0x5C }, | |
1676 | { 0x8, 0x5D }, | |
1677 | { 0x8, 0x5C }, | |
1678 | { AIC3X_PAGE_SELECT, 0x00 }, | |
1679 | }; | |
1680 | ||
44d0a879 VB |
1681 | /* |
1682 | * If the i2c layer weren't so broken, we could pass this kind of data | |
1683 | * around | |
1684 | */ | |
ba8ed121 JD |
1685 | static int aic3x_i2c_probe(struct i2c_client *i2c, |
1686 | const struct i2c_device_id *id) | |
44d0a879 | 1687 | { |
5193d62f | 1688 | struct aic3x_pdata *pdata = i2c->dev.platform_data; |
f0fba2ad | 1689 | struct aic3x_priv *aic3x; |
c24fdc88 HG |
1690 | struct aic3x_setup_data *ai3x_setup; |
1691 | struct device_node *np = i2c->dev.of_node; | |
6f818e04 | 1692 | int ret, i; |
e2e8bfdf | 1693 | u32 value; |
44d0a879 | 1694 | |
e2257db3 | 1695 | aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL); |
b1117f52 | 1696 | if (!aic3x) |
cb3826f5 | 1697 | return -ENOMEM; |
cb3826f5 | 1698 | |
2a6fedec MB |
1699 | aic3x->regmap = devm_regmap_init_i2c(i2c, &aic3x_regmap); |
1700 | if (IS_ERR(aic3x->regmap)) { | |
1701 | ret = PTR_ERR(aic3x->regmap); | |
1702 | return ret; | |
1703 | } | |
1704 | ||
1705 | regcache_cache_only(aic3x->regmap, true); | |
a84a441b | 1706 | |
cb3826f5 | 1707 | i2c_set_clientdata(i2c, aic3x); |
c776357e JN |
1708 | if (pdata) { |
1709 | aic3x->gpio_reset = pdata->gpio_reset; | |
1710 | aic3x->setup = pdata->setup; | |
e2e8bfdf | 1711 | aic3x->micbias_vg = pdata->micbias_vg; |
c24fdc88 HG |
1712 | } else if (np) { |
1713 | ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup), | |
1714 | GFP_KERNEL); | |
b1117f52 | 1715 | if (!ai3x_setup) |
c24fdc88 | 1716 | return -ENOMEM; |
c24fdc88 HG |
1717 | |
1718 | ret = of_get_named_gpio(np, "gpio-reset", 0); | |
1719 | if (ret >= 0) | |
1720 | aic3x->gpio_reset = ret; | |
1721 | else | |
1722 | aic3x->gpio_reset = -1; | |
1723 | ||
1724 | if (of_property_read_u32_array(np, "ai3x-gpio-func", | |
1725 | ai3x_setup->gpio_func, 2) >= 0) { | |
1726 | aic3x->setup = ai3x_setup; | |
1727 | } | |
1728 | ||
e2e8bfdf HG |
1729 | if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) { |
1730 | switch (value) { | |
1731 | case 1 : | |
1732 | aic3x->micbias_vg = AIC3X_MICBIAS_2_0V; | |
1733 | break; | |
1734 | case 2 : | |
1735 | aic3x->micbias_vg = AIC3X_MICBIAS_2_5V; | |
1736 | break; | |
1737 | case 3 : | |
1738 | aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV; | |
1739 | break; | |
1740 | default : | |
1741 | aic3x->micbias_vg = AIC3X_MICBIAS_OFF; | |
1742 | dev_err(&i2c->dev, "Unsuitable MicBias voltage " | |
1743 | "found in DT\n"); | |
1744 | } | |
1745 | } else { | |
1746 | aic3x->micbias_vg = AIC3X_MICBIAS_OFF; | |
1747 | } | |
1748 | ||
c776357e JN |
1749 | } else { |
1750 | aic3x->gpio_reset = -1; | |
1751 | } | |
cb3826f5 | 1752 | |
177fdd89 | 1753 | aic3x->model = id->driver_data; |
6184f105 | 1754 | |
6f818e04 MB |
1755 | if (gpio_is_valid(aic3x->gpio_reset) && |
1756 | !aic3x_is_shared_reset(aic3x)) { | |
1757 | ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); | |
1758 | if (ret != 0) | |
1759 | goto err; | |
1760 | gpio_direction_output(aic3x->gpio_reset, 0); | |
1761 | } | |
1762 | ||
1763 | for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) | |
1764 | aic3x->supplies[i].supply = aic3x_supply_names[i]; | |
1765 | ||
1766 | ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(aic3x->supplies), | |
1767 | aic3x->supplies); | |
1768 | if (ret != 0) { | |
1769 | dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); | |
1770 | goto err_gpio; | |
1771 | } | |
1772 | ||
2a6fedec MB |
1773 | if (aic3x->model == AIC3X_MODEL_3007) { |
1774 | ret = regmap_register_patch(aic3x->regmap, aic3007_class_d, | |
1775 | ARRAY_SIZE(aic3007_class_d)); | |
1776 | if (ret != 0) | |
1777 | dev_err(&i2c->dev, "Failed to init class D: %d\n", | |
1778 | ret); | |
1779 | } | |
1780 | ||
f0fba2ad LG |
1781 | ret = snd_soc_register_codec(&i2c->dev, |
1782 | &soc_codec_dev_aic3x, &aic3x_dai, 1); | |
3b5b2431 SR |
1783 | |
1784 | if (ret != 0) | |
1785 | goto err_gpio; | |
1786 | ||
1787 | list_add(&aic3x->list, &reset_list); | |
1788 | ||
1789 | return 0; | |
6f818e04 MB |
1790 | |
1791 | err_gpio: | |
1792 | if (gpio_is_valid(aic3x->gpio_reset) && | |
1793 | !aic3x_is_shared_reset(aic3x)) | |
1794 | gpio_free(aic3x->gpio_reset); | |
1795 | err: | |
1796 | return ret; | |
44d0a879 VB |
1797 | } |
1798 | ||
ba8ed121 | 1799 | static int aic3x_i2c_remove(struct i2c_client *client) |
44d0a879 | 1800 | { |
6f818e04 MB |
1801 | struct aic3x_priv *aic3x = i2c_get_clientdata(client); |
1802 | ||
f0fba2ad | 1803 | snd_soc_unregister_codec(&client->dev); |
6f818e04 MB |
1804 | if (gpio_is_valid(aic3x->gpio_reset) && |
1805 | !aic3x_is_shared_reset(aic3x)) { | |
1806 | gpio_set_value(aic3x->gpio_reset, 0); | |
1807 | gpio_free(aic3x->gpio_reset); | |
1808 | } | |
f0fba2ad | 1809 | return 0; |
44d0a879 VB |
1810 | } |
1811 | ||
c24fdc88 HG |
1812 | #if defined(CONFIG_OF) |
1813 | static const struct of_device_id tlv320aic3x_of_match[] = { | |
1814 | { .compatible = "ti,tlv320aic3x", }, | |
f2c4fa65 MB |
1815 | { .compatible = "ti,tlv320aic33" }, |
1816 | { .compatible = "ti,tlv320aic3007" }, | |
cbaa5689 | 1817 | { .compatible = "ti,tlv320aic3106" }, |
9503112d | 1818 | { .compatible = "ti,tlv320aic3104" }, |
c24fdc88 HG |
1819 | {}, |
1820 | }; | |
1821 | MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match); | |
1822 | #endif | |
1823 | ||
44d0a879 VB |
1824 | /* machine i2c codec control layer */ |
1825 | static struct i2c_driver aic3x_i2c_driver = { | |
1826 | .driver = { | |
f0fba2ad | 1827 | .name = "tlv320aic3x-codec", |
44d0a879 | 1828 | .owner = THIS_MODULE, |
c24fdc88 | 1829 | .of_match_table = of_match_ptr(tlv320aic3x_of_match), |
44d0a879 | 1830 | }, |
cb3826f5 | 1831 | .probe = aic3x_i2c_probe, |
ba8ed121 JD |
1832 | .remove = aic3x_i2c_remove, |
1833 | .id_table = aic3x_i2c_id, | |
44d0a879 | 1834 | }; |
44d0a879 | 1835 | |
fd39d14b | 1836 | module_i2c_driver(aic3x_i2c_driver); |
64089b84 | 1837 | |
44d0a879 VB |
1838 | MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); |
1839 | MODULE_AUTHOR("Vladimir Barinov"); | |
1840 | MODULE_LICENSE("GPL"); |