Merge branch 'fix/tlv320aic31xx' of https://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / sound / soc / codecs / tlv320aic31xx.h
CommitLineData
b1c52b7e 1// SPDX-License-Identifier: GPL-2.0
e00447fa 2/*
b1c52b7e 3 * ALSA SoC TLV320AIC31xx CODEC Driver Definitions
e00447fa 4 *
b1c52b7e 5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
e00447fa 6 */
b1c52b7e 7
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8#ifndef _TLV320AIC31XX_H
9#define _TLV320AIC31XX_H
10
11#define AIC31XX_RATES SNDRV_PCM_RATE_8000_192000
12
13#define AIC31XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
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14 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \
15 | SNDRV_PCM_FMTBIT_S32_LE)
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16
17
18#define AIC31XX_STEREO_CLASS_D_BIT 0x1
19#define AIC31XX_MINIDSP_BIT 0x2
ef9656b6 20#define DAC31XX_BIT 0x4
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21
22enum aic31xx_type {
23 AIC3100 = 0,
24 AIC3110 = AIC31XX_STEREO_CLASS_D_BIT,
25 AIC3120 = AIC31XX_MINIDSP_BIT,
26 AIC3111 = (AIC31XX_STEREO_CLASS_D_BIT | AIC31XX_MINIDSP_BIT),
ef9656b6 27 DAC3100 = DAC31XX_BIT,
4e2cc814 28 DAC3101 = DAC31XX_BIT | AIC31XX_STEREO_CLASS_D_BIT,
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29};
30
31struct aic31xx_pdata {
32 enum aic31xx_type codec_type;
33 unsigned int gpio_reset;
34 int micbias_vg;
35};
36
bafcbfe4
PU
37#define AIC31XX_REG(page, reg) ((page * 128) + reg)
38
e00447fa 39/* Page Control Register */
bafcbfe4 40#define AIC31XX_PAGECTL AIC31XX_REG(0, 0)
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41
42/* Page 0 Registers */
43/* Software reset register */
bafcbfe4 44#define AIC31XX_RESET AIC31XX_REG(0, 1)
e00447fa 45/* OT FLAG register */
bafcbfe4 46#define AIC31XX_OT_FLAG AIC31XX_REG(0, 3)
e00447fa 47/* Clock clock Gen muxing, Multiplexers*/
bafcbfe4 48#define AIC31XX_CLKMUX AIC31XX_REG(0, 4)
e00447fa 49/* PLL P and R-VAL register */
bafcbfe4 50#define AIC31XX_PLLPR AIC31XX_REG(0, 5)
e00447fa 51/* PLL J-VAL register */
bafcbfe4 52#define AIC31XX_PLLJ AIC31XX_REG(0, 6)
e00447fa 53/* PLL D-VAL MSB register */
bafcbfe4 54#define AIC31XX_PLLDMSB AIC31XX_REG(0, 7)
e00447fa 55/* PLL D-VAL LSB register */
bafcbfe4 56#define AIC31XX_PLLDLSB AIC31XX_REG(0, 8)
e00447fa 57/* DAC NDAC_VAL register*/
bafcbfe4 58#define AIC31XX_NDAC AIC31XX_REG(0, 11)
e00447fa 59/* DAC MDAC_VAL register */
bafcbfe4 60#define AIC31XX_MDAC AIC31XX_REG(0, 12)
e00447fa 61/* DAC OSR setting register 1, MSB value */
bafcbfe4 62#define AIC31XX_DOSRMSB AIC31XX_REG(0, 13)
e00447fa 63/* DAC OSR setting register 2, LSB value */
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64#define AIC31XX_DOSRLSB AIC31XX_REG(0, 14)
65#define AIC31XX_MINI_DSP_INPOL AIC31XX_REG(0, 16)
e00447fa 66/* Clock setting register 8, PLL */
bafcbfe4 67#define AIC31XX_NADC AIC31XX_REG(0, 18)
e00447fa 68/* Clock setting register 9, PLL */
bafcbfe4 69#define AIC31XX_MADC AIC31XX_REG(0, 19)
e00447fa 70/* ADC Oversampling (AOSR) Register */
bafcbfe4 71#define AIC31XX_AOSR AIC31XX_REG(0, 20)
e00447fa 72/* Clock setting register 9, Multiplexers */
bafcbfe4 73#define AIC31XX_CLKOUTMUX AIC31XX_REG(0, 25)
e00447fa 74/* Clock setting register 10, CLOCKOUT M divider value */
bafcbfe4 75#define AIC31XX_CLKOUTMVAL AIC31XX_REG(0, 26)
e00447fa 76/* Audio Interface Setting Register 1 */
bafcbfe4 77#define AIC31XX_IFACE1 AIC31XX_REG(0, 27)
e00447fa 78/* Audio Data Slot Offset Programming */
bafcbfe4 79#define AIC31XX_DATA_OFFSET AIC31XX_REG(0, 28)
e00447fa 80/* Audio Interface Setting Register 2 */
bafcbfe4 81#define AIC31XX_IFACE2 AIC31XX_REG(0, 29)
e00447fa 82/* Clock setting register 11, BCLK N Divider */
bafcbfe4 83#define AIC31XX_BCLKN AIC31XX_REG(0, 30)
e00447fa 84/* Audio Interface Setting Register 3, Secondary Audio Interface */
bafcbfe4 85#define AIC31XX_IFACESEC1 AIC31XX_REG(0, 31)
e00447fa 86/* Audio Interface Setting Register 4 */
bafcbfe4 87#define AIC31XX_IFACESEC2 AIC31XX_REG(0, 32)
e00447fa 88/* Audio Interface Setting Register 5 */
bafcbfe4 89#define AIC31XX_IFACESEC3 AIC31XX_REG(0, 33)
e00447fa 90/* I2C Bus Condition */
bafcbfe4 91#define AIC31XX_I2C AIC31XX_REG(0, 34)
e00447fa 92/* ADC FLAG */
bafcbfe4 93#define AIC31XX_ADCFLAG AIC31XX_REG(0, 36)
e00447fa 94/* DAC Flag Registers */
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95#define AIC31XX_DACFLAG1 AIC31XX_REG(0, 37)
96#define AIC31XX_DACFLAG2 AIC31XX_REG(0, 38)
e00447fa 97/* Sticky Interrupt flag (overflow) */
bafcbfe4 98#define AIC31XX_OFFLAG AIC31XX_REG(0, 39)
e00447fa 99/* Sticy DAC Interrupt flags */
bafcbfe4 100#define AIC31XX_INTRDACFLAG AIC31XX_REG(0, 44)
e00447fa 101/* Sticy ADC Interrupt flags */
bafcbfe4 102#define AIC31XX_INTRADCFLAG AIC31XX_REG(0, 45)
e00447fa 103/* DAC Interrupt flags 2 */
bafcbfe4 104#define AIC31XX_INTRDACFLAG2 AIC31XX_REG(0, 46)
e00447fa 105/* ADC Interrupt flags 2 */
bafcbfe4 106#define AIC31XX_INTRADCFLAG2 AIC31XX_REG(0, 47)
e00447fa 107/* INT1 interrupt control */
bafcbfe4 108#define AIC31XX_INT1CTRL AIC31XX_REG(0, 48)
e00447fa 109/* INT2 interrupt control */
bafcbfe4 110#define AIC31XX_INT2CTRL AIC31XX_REG(0, 49)
e00447fa 111/* GPIO1 control */
737e0b7b 112#define AIC31XX_GPIO1 AIC31XX_REG(0, 51)
e00447fa 113
bafcbfe4 114#define AIC31XX_DACPRB AIC31XX_REG(0, 60)
e00447fa 115/* ADC Instruction Set Register */
bafcbfe4 116#define AIC31XX_ADCPRB AIC31XX_REG(0, 61)
e00447fa 117/* DAC channel setup register */
bafcbfe4 118#define AIC31XX_DACSETUP AIC31XX_REG(0, 63)
e00447fa 119/* DAC Mute and volume control register */
bafcbfe4 120#define AIC31XX_DACMUTE AIC31XX_REG(0, 64)
e00447fa 121/* Left DAC channel digital volume control */
bafcbfe4 122#define AIC31XX_LDACVOL AIC31XX_REG(0, 65)
e00447fa 123/* Right DAC channel digital volume control */
bafcbfe4 124#define AIC31XX_RDACVOL AIC31XX_REG(0, 66)
e00447fa 125/* Headset detection */
bafcbfe4 126#define AIC31XX_HSDETECT AIC31XX_REG(0, 67)
e00447fa 127/* ADC Digital Mic */
bafcbfe4 128#define AIC31XX_ADCSETUP AIC31XX_REG(0, 81)
e00447fa 129/* ADC Digital Volume Control Fine Adjust */
bafcbfe4 130#define AIC31XX_ADCFGA AIC31XX_REG(0, 82)
e00447fa 131/* ADC Digital Volume Control Coarse Adjust */
bafcbfe4 132#define AIC31XX_ADCVOL AIC31XX_REG(0, 83)
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133
134
135/* Page 1 Registers */
136/* Headphone drivers */
bafcbfe4 137#define AIC31XX_HPDRIVER AIC31XX_REG(1, 31)
e00447fa 138/* Class-D Speakear Amplifier */
bafcbfe4 139#define AIC31XX_SPKAMP AIC31XX_REG(1, 32)
e00447fa 140/* HP Output Drivers POP Removal Settings */
bafcbfe4 141#define AIC31XX_HPPOP AIC31XX_REG(1, 33)
e00447fa 142/* Output Driver PGA Ramp-Down Period Control */
bafcbfe4 143#define AIC31XX_SPPGARAMP AIC31XX_REG(1, 34)
e00447fa 144/* DAC_L and DAC_R Output Mixer Routing */
bafcbfe4 145#define AIC31XX_DACMIXERROUTE AIC31XX_REG(1, 35)
e00447fa 146/* Left Analog Vol to HPL */
bafcbfe4 147#define AIC31XX_LANALOGHPL AIC31XX_REG(1, 36)
e00447fa 148/* Right Analog Vol to HPR */
bafcbfe4 149#define AIC31XX_RANALOGHPR AIC31XX_REG(1, 37)
e00447fa 150/* Left Analog Vol to SPL */
bafcbfe4 151#define AIC31XX_LANALOGSPL AIC31XX_REG(1, 38)
e00447fa 152/* Right Analog Vol to SPR */
bafcbfe4 153#define AIC31XX_RANALOGSPR AIC31XX_REG(1, 39)
e00447fa 154/* HPL Driver */
bafcbfe4 155#define AIC31XX_HPLGAIN AIC31XX_REG(1, 40)
e00447fa 156/* HPR Driver */
bafcbfe4 157#define AIC31XX_HPRGAIN AIC31XX_REG(1, 41)
e00447fa 158/* SPL Driver */
bafcbfe4 159#define AIC31XX_SPLGAIN AIC31XX_REG(1, 42)
e00447fa 160/* SPR Driver */
bafcbfe4 161#define AIC31XX_SPRGAIN AIC31XX_REG(1, 43)
e00447fa 162/* HP Driver Control */
bafcbfe4 163#define AIC31XX_HPCONTROL AIC31XX_REG(1, 44)
e00447fa 164/* MIC Bias Control */
bafcbfe4 165#define AIC31XX_MICBIAS AIC31XX_REG(1, 46)
e00447fa 166/* MIC PGA*/
bafcbfe4 167#define AIC31XX_MICPGA AIC31XX_REG(1, 47)
e00447fa 168/* Delta-Sigma Mono ADC Channel Fine-Gain Input Selection for P-Terminal */
bafcbfe4 169#define AIC31XX_MICPGAPI AIC31XX_REG(1, 48)
e00447fa 170/* ADC Input Selection for M-Terminal */
bafcbfe4 171#define AIC31XX_MICPGAMI AIC31XX_REG(1, 49)
e00447fa 172/* Input CM Settings */
bafcbfe4 173#define AIC31XX_MICPGACM AIC31XX_REG(1, 50)
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174
175/* Bits, masks and shifts */
176
177/* AIC31XX_CLKMUX */
178#define AIC31XX_PLL_CLKIN_MASK 0x0c
179#define AIC31XX_PLL_CLKIN_SHIFT 2
180#define AIC31XX_PLL_CLKIN_MCLK 0
181#define AIC31XX_CODEC_CLKIN_MASK 0x03
182#define AIC31XX_CODEC_CLKIN_SHIFT 0
183#define AIC31XX_CODEC_CLKIN_PLL 3
184#define AIC31XX_CODEC_CLKIN_BCLK 1
185
186/* AIC31XX_PLLPR, AIC31XX_NDAC, AIC31XX_MDAC, AIC31XX_NADC, AIC31XX_MADC,
187 AIC31XX_BCLKN */
188#define AIC31XX_PLL_MASK 0x7f
189#define AIC31XX_PM_MASK 0x80
190
191/* AIC31XX_IFACE1 */
192#define AIC31XX_WORD_LEN_16BITS 0x00
193#define AIC31XX_WORD_LEN_20BITS 0x01
194#define AIC31XX_WORD_LEN_24BITS 0x02
195#define AIC31XX_WORD_LEN_32BITS 0x03
196#define AIC31XX_IFACE1_DATALEN_MASK 0x30
197#define AIC31XX_IFACE1_DATALEN_SHIFT (4)
198#define AIC31XX_IFACE1_DATATYPE_MASK 0xC0
199#define AIC31XX_IFACE1_DATATYPE_SHIFT (6)
200#define AIC31XX_I2S_MODE 0x00
201#define AIC31XX_DSP_MODE 0x01
202#define AIC31XX_RIGHT_JUSTIFIED_MODE 0x02
203#define AIC31XX_LEFT_JUSTIFIED_MODE 0x03
204#define AIC31XX_IFACE1_MASTER_MASK 0x0C
205#define AIC31XX_BCLK_MASTER 0x08
206#define AIC31XX_WCLK_MASTER 0x04
207
208/* AIC31XX_DATA_OFFSET */
209#define AIC31XX_DATA_OFFSET_MASK 0xFF
210
211/* AIC31XX_IFACE2 */
212#define AIC31XX_BCLKINV_MASK 0x08
213#define AIC31XX_BDIVCLK_MASK 0x03
214#define AIC31XX_DAC2BCLK 0x00
215#define AIC31XX_DACMOD2BCLK 0x01
216#define AIC31XX_ADC2BCLK 0x02
217#define AIC31XX_ADCMOD2BCLK 0x03
218
219/* AIC31XX_ADCFLAG */
220#define AIC31XX_ADCPWRSTATUS_MASK 0x40
221
222/* AIC31XX_DACFLAG1 */
223#define AIC31XX_LDACPWRSTATUS_MASK 0x80
224#define AIC31XX_RDACPWRSTATUS_MASK 0x08
225#define AIC31XX_HPLDRVPWRSTATUS_MASK 0x20
226#define AIC31XX_HPRDRVPWRSTATUS_MASK 0x02
227#define AIC31XX_SPLDRVPWRSTATUS_MASK 0x10
228#define AIC31XX_SPRDRVPWRSTATUS_MASK 0x01
229
230/* AIC31XX_INTRDACFLAG */
231#define AIC31XX_HPSCDETECT_MASK 0x80
232#define AIC31XX_BUTTONPRESS_MASK 0x20
233#define AIC31XX_HSPLUG_MASK 0x10
234#define AIC31XX_LDRCTHRES_MASK 0x08
235#define AIC31XX_RDRCTHRES_MASK 0x04
236#define AIC31XX_DACSINT_MASK 0x02
237#define AIC31XX_DACAINT_MASK 0x01
238
239/* AIC31XX_INT1CTRL */
240#define AIC31XX_HSPLUGDET_MASK 0x80
241#define AIC31XX_BUTTONPRESSDET_MASK 0x40
242#define AIC31XX_DRCTHRES_MASK 0x20
243#define AIC31XX_AGCNOISE_MASK 0x10
244#define AIC31XX_OC_MASK 0x08
245#define AIC31XX_ENGINE_MASK 0x04
246
247/* AIC31XX_DACSETUP */
248#define AIC31XX_SOFTSTEP_MASK 0x03
249
250/* AIC31XX_DACMUTE */
251#define AIC31XX_DACMUTE_MASK 0x0C
252
253/* AIC31XX_MICBIAS */
254#define AIC31XX_MICBIAS_MASK 0x03
255#define AIC31XX_MICBIAS_SHIFT 0
256
257#endif /* _TLV320AIC31XX_H */