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ASoC: tlv320aic31xx: Change aic31xx_power_off return type to void
[linux-2.6-block.git] / sound / soc / codecs / tlv320aic31xx.c
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b1c52b7e 1// SPDX-License-Identifier: GPL-2.0
e00447fa 2/*
b1c52b7e 3 * ALSA SoC TLV320AIC31xx CODEC Driver
e00447fa 4 *
b1c52b7e
AD		 5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
6 * Jyri Sarha <jsarha@ti.com>
e00447fa
JS		 7 *
8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
9 *
b1c52b7e
AD		 10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated
11 * high performance codecs which provides a stereo DAC, a mono ADC,
e00447fa
JS		 12 * and mono/stereo Class-D speaker driver.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/gpio.h>
22#include <linux/regulator/consumer.h>
f5cc1772 23#include <linux/acpi.h>
0faabc4f 24#include <linux/of.h>
e00447fa
JS		 25#include <linux/of_gpio.h>
26#include <linux/slab.h>
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
34
35#include "tlv320aic31xx.h"
36
37static const struct reg_default aic31xx_reg_defaults[] = {
38 { AIC31XX_CLKMUX, 0x00 },
39 { AIC31XX_PLLPR, 0x11 },
40 { AIC31XX_PLLJ, 0x04 },
41 { AIC31XX_PLLDMSB, 0x00 },
42 { AIC31XX_PLLDLSB, 0x00 },
43 { AIC31XX_NDAC, 0x01 },
44 { AIC31XX_MDAC, 0x01 },
45 { AIC31XX_DOSRMSB, 0x00 },
46 { AIC31XX_DOSRLSB, 0x80 },
47 { AIC31XX_NADC, 0x01 },
48 { AIC31XX_MADC, 0x01 },
49 { AIC31XX_AOSR, 0x80 },
50 { AIC31XX_IFACE1, 0x00 },
51 { AIC31XX_DATA_OFFSET, 0x00 },
52 { AIC31XX_IFACE2, 0x00 },
53 { AIC31XX_BCLKN, 0x01 },
54 { AIC31XX_DACSETUP, 0x14 },
55 { AIC31XX_DACMUTE, 0x0c },
56 { AIC31XX_LDACVOL, 0x00 },
57 { AIC31XX_RDACVOL, 0x00 },
58 { AIC31XX_ADCSETUP, 0x00 },
59 { AIC31XX_ADCFGA, 0x80 },
60 { AIC31XX_ADCVOL, 0x00 },
61 { AIC31XX_HPDRIVER, 0x04 },
62 { AIC31XX_SPKAMP, 0x06 },
63 { AIC31XX_DACMIXERROUTE, 0x00 },
64 { AIC31XX_LANALOGHPL, 0x7f },
65 { AIC31XX_RANALOGHPR, 0x7f },
66 { AIC31XX_LANALOGSPL, 0x7f },
67 { AIC31XX_RANALOGSPR, 0x7f },
68 { AIC31XX_HPLGAIN, 0x02 },
69 { AIC31XX_HPRGAIN, 0x02 },
70 { AIC31XX_SPLGAIN, 0x00 },
71 { AIC31XX_SPRGAIN, 0x00 },
72 { AIC31XX_MICBIAS, 0x00 },
73 { AIC31XX_MICPGA, 0x80 },
74 { AIC31XX_MICPGAPI, 0x00 },
75 { AIC31XX_MICPGAMI, 0x00 },
76};
77
78static bool aic31xx_volatile(struct device *dev, unsigned int reg)
79{
80 switch (reg) {
81 case AIC31XX_PAGECTL: /* regmap implementation requires this */
82 case AIC31XX_RESET: /* always clears after write */
83 case AIC31XX_OT_FLAG:
84 case AIC31XX_ADCFLAG:
85 case AIC31XX_DACFLAG1:
86 case AIC31XX_DACFLAG2:
87 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
88 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
89 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
90 case AIC31XX_INTRDACFLAG2:
91 case AIC31XX_INTRADCFLAG2:
92 return true;
93 }
94 return false;
95}
96
97static bool aic31xx_writeable(struct device *dev, unsigned int reg)
98{
99 switch (reg) {
100 case AIC31XX_OT_FLAG:
101 case AIC31XX_ADCFLAG:
102 case AIC31XX_DACFLAG1:
103 case AIC31XX_DACFLAG2:
104 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
105 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
106 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
107 case AIC31XX_INTRDACFLAG2:
108 case AIC31XX_INTRADCFLAG2:
109 return false;
110 }
111 return true;
112}
113
114static const struct regmap_range_cfg aic31xx_ranges[] = {
115 {
116 .range_min = 0,
117 .range_max = 12 * 128,
118 .selector_reg = AIC31XX_PAGECTL,
119 .selector_mask = 0xff,
120 .selector_shift = 0,
121 .window_start = 0,
122 .window_len = 128,
123 },
124};
125
9296f4da 126static const struct regmap_config aic31xx_i2c_regmap = {
e00447fa
JS		 127 .reg_bits = 8,
128 .val_bits = 8,
129 .writeable_reg = aic31xx_writeable,
130 .volatile_reg = aic31xx_volatile,
131 .reg_defaults = aic31xx_reg_defaults,
132 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),
133 .cache_type = REGCACHE_RBTREE,
134 .ranges = aic31xx_ranges,
135 .num_ranges = ARRAY_SIZE(aic31xx_ranges),
136 .max_register = 12 * 128,
137};
138
139#define AIC31XX_NUM_SUPPLIES 6
140static const char * const aic31xx_supply_names[AIC31XX_NUM_SUPPLIES] = {
141 "HPVDD",
142 "SPRVDD",
143 "SPLVDD",
144 "AVDD",
145 "IOVDD",
146 "DVDD",
147};
148
149struct aic31xx_disable_nb {
150 struct notifier_block nb;
151 struct aic31xx_priv *aic31xx;
152};
153
154struct aic31xx_priv {
155 struct snd_soc_codec *codec;
156 u8 i2c_regs_status;
157 struct device *dev;
158 struct regmap *regmap;
159 struct aic31xx_pdata pdata;
160 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
161 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
162 unsigned int sysclk;
7ed36e96 163 u8 p_div;
e00447fa
JS		 164 int rate_div_line;
165};
166
167struct aic31xx_rate_divs {
7ed36e96 168 u32 mclk_p;
e00447fa 169 u32 rate;
e00447fa
JS		 170 u8 pll_j;
171 u16 pll_d;
172 u16 dosr;
173 u8 ndac;
174 u8 mdac;
175 u8 aosr;
176 u8 nadc;
177 u8 madc;
178};
179
180/* ADC dividers can be disabled by cofiguring them to 0 */
181static const struct aic31xx_rate_divs aic31xx_divs[] = {
7ed36e96 182 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */
e00447fa 183 /* 8k rate */
7ed36e96
JS		 184 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2},
185 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3},
186 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2},
e00447fa 187 /* 11.025k rate */
7ed36e96
JS		 188 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2},
189 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3},
190 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2},
e00447fa 191 /* 16k rate */
7ed36e96
JS		 192 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2},
193 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3},
194 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2},
e00447fa 195 /* 22.05k rate */
7ed36e96
JS		 196 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2},
197 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3},
198 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2},
e00447fa 199 /* 32k rate */
7ed36e96
JS		 200 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2},
201 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3},
202 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2},
e00447fa 203 /* 44.1k rate */
7ed36e96
JS		 204 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2},
205 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3},
206 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2},
e00447fa 207 /* 48k rate */
7ed36e96
JS		 208 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2},
209 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4},
210 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2},
e00447fa 211 /* 88.2k rate */
7ed36e96
JS		 212 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2},
213 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3},
214 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2},
e00447fa 215 /* 96k rate */
7ed36e96
JS		 216 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2},
217 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4},
218 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2},
e00447fa 219 /* 176.4k rate */
7ed36e96
JS		 220 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2},
221 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3},
222 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2},
e00447fa 223 /* 192k rate */
7ed36e96
JS		 224 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2},
225 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4},
226 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2},
e00447fa
JS		 227};
228
229static const char * const ldac_in_text[] = {
230 "Off", "Left Data", "Right Data", "Mono"
231};
232
233static const char * const rdac_in_text[] = {
234 "Off", "Right Data", "Left Data", "Mono"
235};
236
237static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);
238
239static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);
240
241static const char * const mic_select_text[] = {
242 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
243};
244
914bc160
LPC		 245static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,
246 mic_select_text);
247static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,
248 mic_select_text);
249static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
250 mic_select_text);
e00447fa 251
914bc160
LPC		 252static SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text);
253static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
254 mic_select_text);
e00447fa
JS		 255
256static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
257static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
258static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
259static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
260static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
261static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
262static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
263static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
264
265/*
266 * controls to be exported to the user space
267 */
ef9656b6 268static const struct snd_kcontrol_new common31xx_snd_controls[] = {
e00447fa
JS		 269 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,
270 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
271
ef9656b6
NY		 272 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,
273 AIC31XX_HPRGAIN, 2, 1, 0),
274 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,
275 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
276
277 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
278 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
279};
280
281static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
e00447fa
JS		 282 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,
283 adc_fgain_tlv),
284
285 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),
286 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,
287 0, -24, 40, 6, 0, adc_cgain_tlv),
288
289 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
290 119, 0, mic_pga_tlv),
e00447fa
JS		 291};
292
293static const struct snd_kcontrol_new aic311x_snd_controls[] = {
294 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
295 AIC31XX_SPRGAIN, 2, 1, 0),
296 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
297 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
298
299 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
300 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
301};
302
303static const struct snd_kcontrol_new aic310x_snd_controls[] = {
304 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
305 2, 1, 0),
306 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
307 3, 3, 0, class_D_drv_tlv),
308
309 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
310 0, 0x7F, 1, sp_vol_tlv),
311};
312
313static const struct snd_kcontrol_new ldac_in_control =
314 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);
315
316static const struct snd_kcontrol_new rdac_in_control =
317 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);
318
9296f4da
MB		 319static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,
320 unsigned int mask, unsigned int wbits, int sleep,
321 int count)
e00447fa
JS		 322{
323 unsigned int bits;
324 int counter = count;
325 int ret = regmap_read(aic31xx->regmap, reg, &bits);
423ca88e 326
e00447fa
JS		 327 while ((bits & mask) != wbits && counter && !ret) {
328 usleep_range(sleep, sleep * 2);
329 ret = regmap_read(aic31xx->regmap, reg, &bits);
330 counter--;
331 }
332 if ((bits & mask) != wbits) {
333 dev_err(aic31xx->dev,
334 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
335 __func__, reg, bits, wbits, ret, mask,
336 (count - counter) * sleep);
337 ret = -1;
338 }
339 return ret;
340}
341
342#define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
343
344static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
345 struct snd_kcontrol *kcontrol, int event)
346{
dd943d36
LPC		 347 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
348 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
e00447fa
JS		 349 unsigned int reg = AIC31XX_DACFLAG1;
350 unsigned int mask;
351
352 switch (WIDGET_BIT(w->reg, w->shift)) {
353 case WIDGET_BIT(AIC31XX_DACSETUP, 7):
354 mask = AIC31XX_LDACPWRSTATUS_MASK;
355 break;
356 case WIDGET_BIT(AIC31XX_DACSETUP, 6):
357 mask = AIC31XX_RDACPWRSTATUS_MASK;
358 break;
359 case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
360 mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
361 break;
362 case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
363 mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
364 break;
365 case WIDGET_BIT(AIC31XX_SPKAMP, 7):
366 mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
367 break;
368 case WIDGET_BIT(AIC31XX_SPKAMP, 6):
369 mask = AIC31XX_SPRDRVPWRSTATUS_MASK;
370 break;
371 case WIDGET_BIT(AIC31XX_ADCSETUP, 7):
372 mask = AIC31XX_ADCPWRSTATUS_MASK;
373 reg = AIC31XX_ADCFLAG;
374 break;
375 default:
dd943d36 376 dev_err(codec->dev, "Unknown widget '%s' calling %s\n",
e00447fa
JS		 377 w->name, __func__);
378 return -EINVAL;
379 }
380
381 switch (event) {
382 case SND_SOC_DAPM_POST_PMU:
383 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100);
384 case SND_SOC_DAPM_POST_PMD:
385 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100);
386 default:
dd943d36 387 dev_dbg(codec->dev,
e00447fa
JS		 388 "Unhandled dapm widget event %d from %s\n",
389 event, w->name);
390 }
391 return 0;
392}
393
ef9656b6 394static const struct snd_kcontrol_new aic31xx_left_output_switches[] = {
e00447fa
JS		 395 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
396 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
397 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
398};
399
ef9656b6 400static const struct snd_kcontrol_new aic31xx_right_output_switches[] = {
e00447fa
JS		 401 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
402 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
403};
404
ef9656b6
NY		 405static const struct snd_kcontrol_new dac31xx_left_output_switches[] = {
406 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
407 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0),
408 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0),
409};
410
411static const struct snd_kcontrol_new dac31xx_right_output_switches[] = {
412 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
413 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0),
414};
415
e00447fa
JS		 416static const struct snd_kcontrol_new p_term_mic1lp =
417 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
418
419static const struct snd_kcontrol_new p_term_mic1rp =
420 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
421
422static const struct snd_kcontrol_new p_term_mic1lm =
423 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
424
425static const struct snd_kcontrol_new m_term_mic1lm =
426 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
427
428static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =
429 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
430
431static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =
432 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
433
434static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =
435 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
436
437static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =
438 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
439
440static int mic_bias_event(struct snd_soc_dapm_widget *w,
441 struct snd_kcontrol *kcontrol, int event)
442{
dd943d36 443 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
e00447fa 444 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
423ca88e 445
e00447fa
JS		 446 switch (event) {
447 case SND_SOC_DAPM_POST_PMU:
448 /* change mic bias voltage to user defined */
449 snd_soc_update_bits(codec, AIC31XX_MICBIAS,
450 AIC31XX_MICBIAS_MASK,
451 aic31xx->pdata.micbias_vg <<
452 AIC31XX_MICBIAS_SHIFT);
453 dev_dbg(codec->dev, "%s: turned on\n", __func__);
454 break;
455 case SND_SOC_DAPM_PRE_PMD:
456 /* turn mic bias off */
457 snd_soc_update_bits(codec, AIC31XX_MICBIAS,
458 AIC31XX_MICBIAS_MASK, 0);
459 dev_dbg(codec->dev, "%s: turned off\n", __func__);
460 break;
461 }
462 return 0;
463}
464
ef9656b6 465static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = {
e00447fa
JS		 466 SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0),
467
468 SND_SOC_DAPM_MUX("DAC Left Input",
469 SND_SOC_NOPM, 0, 0, &ldac_in_control),
470 SND_SOC_DAPM_MUX("DAC Right Input",
471 SND_SOC_NOPM, 0, 0, &rdac_in_control),
472 /* DACs */
473 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
474 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
475 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
476
477 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
478 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
479 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
480
ef9656b6 481 /* HP */
e00447fa
JS		 482 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
483 &aic31xx_dapm_hpl_switch),
484 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
485 &aic31xx_dapm_hpr_switch),
486
487 /* Output drivers */
488 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
489 NULL, 0, aic31xx_dapm_power_event,
490 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
491 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
492 NULL, 0, aic31xx_dapm_power_event,
493 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
494
ef9656b6
NY		 495 /* Mic Bias */
496 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
497 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
498
499 /* Outputs */
500 SND_SOC_DAPM_OUTPUT("HPL"),
501 SND_SOC_DAPM_OUTPUT("HPR"),
502};
503
504static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = {
505 /* Inputs */
506 SND_SOC_DAPM_INPUT("AIN1"),
507 SND_SOC_DAPM_INPUT("AIN2"),
508
509 /* Output Mixers */
510 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
511 dac31xx_left_output_switches,
512 ARRAY_SIZE(dac31xx_left_output_switches)),
513 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
514 dac31xx_right_output_switches,
515 ARRAY_SIZE(dac31xx_right_output_switches)),
516};
517
518static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
519 /* Inputs */
520 SND_SOC_DAPM_INPUT("MIC1LP"),
521 SND_SOC_DAPM_INPUT("MIC1RP"),
522 SND_SOC_DAPM_INPUT("MIC1LM"),
e00447fa
JS		 523
524 /* Input Selection to MIC_PGA */
525 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
526 &p_term_mic1lp),
527 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
528 &p_term_mic1rp),
529 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
530 &p_term_mic1lm),
531
ef9656b6
NY		 532 /* ADC */
533 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
534 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
535 SND_SOC_DAPM_POST_PMD),
536
e00447fa
JS		 537 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
538 &m_term_mic1lm),
ef9656b6 539
e00447fa
JS		 540 /* Enabling & Disabling MIC Gain Ctl */
541 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,
542 7, 1, NULL, 0),
543
ef9656b6
NY		 544 /* Output Mixers */
545 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
546 aic31xx_left_output_switches,
547 ARRAY_SIZE(aic31xx_left_output_switches)),
548 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
549 aic31xx_right_output_switches,
550 ARRAY_SIZE(aic31xx_right_output_switches)),
e00447fa
JS		 551};
552
553static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {
554 /* AIC3111 and AIC3110 have stereo class-D amplifier */
555 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
556 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
557 SND_SOC_DAPM_POST_PMD),
558 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
559 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
560 SND_SOC_DAPM_POST_PMD),
561 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
562 &aic31xx_dapm_spl_switch),
563 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
564 &aic31xx_dapm_spr_switch),
565 SND_SOC_DAPM_OUTPUT("SPL"),
566 SND_SOC_DAPM_OUTPUT("SPR"),
567};
568
569/* AIC3100 and AIC3120 have only mono class-D amplifier */
570static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {
571 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
572 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
573 SND_SOC_DAPM_POST_PMD),
574 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
575 &aic31xx_dapm_spl_switch),
576 SND_SOC_DAPM_OUTPUT("SPK"),
577};
578
579static const struct snd_soc_dapm_route
ef9656b6 580common31xx_audio_map[] = {
e00447fa
JS		 581 /* DAC Input Routing */
582 {"DAC Left Input", "Left Data", "DAC IN"},
583 {"DAC Left Input", "Right Data", "DAC IN"},
584 {"DAC Left Input", "Mono", "DAC IN"},
585 {"DAC Right Input", "Left Data", "DAC IN"},
586 {"DAC Right Input", "Right Data", "DAC IN"},
587 {"DAC Right Input", "Mono", "DAC IN"},
588 {"DAC Left", NULL, "DAC Left Input"},
589 {"DAC Right", NULL, "DAC Right Input"},
590
ef9656b6
NY		 591 /* HPL path */
592 {"HP Left", "Switch", "Output Left"},
593 {"HPL Driver", NULL, "HP Left"},
594 {"HPL", NULL, "HPL Driver"},
595
596 /* HPR path */
597 {"HP Right", "Switch", "Output Right"},
598 {"HPR Driver", NULL, "HP Right"},
599 {"HPR", NULL, "HPR Driver"},
600};
601
602static const struct snd_soc_dapm_route
603dac31xx_audio_map[] = {
604 /* Left Output */
605 {"Output Left", "From Left DAC", "DAC Left"},
606 {"Output Left", "From AIN1", "AIN1"},
607 {"Output Left", "From AIN2", "AIN2"},
608
609 /* Right Output */
610 {"Output Right", "From Right DAC", "DAC Right"},
611 {"Output Right", "From AIN2", "AIN2"},
612};
613
614static const struct snd_soc_dapm_route
615aic31xx_audio_map[] = {
e00447fa
JS		 616 /* Mic input */
617 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
618 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
619 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
620 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
621 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
622 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
623 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
624 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
625 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
626
627 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
628 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
629 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
630
631 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
632 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
633 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
634 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
635
636 {"ADC", NULL, "MIC_GAIN_CTL"},
637
638 /* Left Output */
639 {"Output Left", "From Left DAC", "DAC Left"},
640 {"Output Left", "From MIC1LP", "MIC1LP"},
641 {"Output Left", "From MIC1RP", "MIC1RP"},
642
643 /* Right Output */
644 {"Output Right", "From Right DAC", "DAC Right"},
645 {"Output Right", "From MIC1RP", "MIC1RP"},
e00447fa
JS		 646};
647
648static const struct snd_soc_dapm_route
649aic311x_audio_map[] = {
650 /* SP L path */
651 {"Speaker Left", "Switch", "Output Left"},
652 {"SPL ClassD", NULL, "Speaker Left"},
653 {"SPL", NULL, "SPL ClassD"},
654
655 /* SP R path */
656 {"Speaker Right", "Switch", "Output Right"},
657 {"SPR ClassD", NULL, "Speaker Right"},
658 {"SPR", NULL, "SPR ClassD"},
659};
660
661static const struct snd_soc_dapm_route
662aic310x_audio_map[] = {
663 /* SP L path */
664 {"Speaker", "Switch", "Output Left"},
665 {"SPK ClassD", NULL, "Speaker"},
666 {"SPK", NULL, "SPK ClassD"},
667};
668
669static int aic31xx_add_controls(struct snd_soc_codec *codec)
670{
671 int ret = 0;
672 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
673
ef9656b6
NY		 674 if (!(aic31xx->pdata.codec_type & DAC31XX_BIT))
675 ret = snd_soc_add_codec_controls(
676 codec, aic31xx_snd_controls,
677 ARRAY_SIZE(aic31xx_snd_controls));
678 if (ret)
679 return ret;
680
e00447fa
JS		 681 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT)
682 ret = snd_soc_add_codec_controls(
683 codec, aic311x_snd_controls,
684 ARRAY_SIZE(aic311x_snd_controls));
685 else
686 ret = snd_soc_add_codec_controls(
687 codec, aic310x_snd_controls,
688 ARRAY_SIZE(aic310x_snd_controls));
689
690 return ret;
691}
692
693static int aic31xx_add_widgets(struct snd_soc_codec *codec)
694{
378d1e43 695 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
e00447fa
JS		 696 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
697 int ret = 0;
698
ef9656b6
NY		 699 if (aic31xx->pdata.codec_type & DAC31XX_BIT) {
700 ret = snd_soc_dapm_new_controls(
701 dapm, dac31xx_dapm_widgets,
702 ARRAY_SIZE(dac31xx_dapm_widgets));
703 if (ret)
704 return ret;
705
706 ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map,
707 ARRAY_SIZE(dac31xx_audio_map));
708 if (ret)
709 return ret;
710 } else {
711 ret = snd_soc_dapm_new_controls(
712 dapm, aic31xx_dapm_widgets,
713 ARRAY_SIZE(aic31xx_dapm_widgets));
714 if (ret)
715 return ret;
716
717 ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map,
718 ARRAY_SIZE(aic31xx_audio_map));
719 if (ret)
720 return ret;
721 }
722
e00447fa
JS		 723 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
724 ret = snd_soc_dapm_new_controls(
725 dapm, aic311x_dapm_widgets,
726 ARRAY_SIZE(aic311x_dapm_widgets));
727 if (ret)
728 return ret;
729
730 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
731 ARRAY_SIZE(aic311x_audio_map));
732 if (ret)
733 return ret;
734 } else {
735 ret = snd_soc_dapm_new_controls(
736 dapm, aic310x_dapm_widgets,
737 ARRAY_SIZE(aic310x_dapm_widgets));
738 if (ret)
739 return ret;
740
741 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
742 ARRAY_SIZE(aic310x_audio_map));
743 if (ret)
744 return ret;
745 }
746
747 return 0;
748}
749
750static int aic31xx_setup_pll(struct snd_soc_codec *codec,
751 struct snd_pcm_hw_params *params)
752{
753 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
03be88ee 754 int bclk_score = snd_soc_params_to_frame_size(params);
7ed36e96 755 int mclk_p = aic31xx->sysclk / aic31xx->p_div;
e00447fa 756 int bclk_n = 0;
03be88ee 757 int match = -1;
e00447fa
JS		 758 int i;
759
760 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
761 snd_soc_update_bits(codec, AIC31XX_CLKMUX,
762 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
763 snd_soc_update_bits(codec, AIC31XX_IFACE2,
764 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
765
766 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
767 if (aic31xx_divs[i].rate == params_rate(params) &&
7ed36e96 768 aic31xx_divs[i].mclk_p == mclk_p) {
03be88ee
JS		 769 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
770 snd_soc_params_to_frame_size(params);
771 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
772 snd_soc_params_to_frame_size(params);
773 if (s < bclk_score && bn > 0) {
774 match = i;
775 bclk_n = bn;
776 bclk_score = s;
777 }
778 }
e00447fa
JS		 779 }
780
03be88ee
JS		 781 if (match == -1) {
782 dev_err(codec->dev,
783 "%s: Sample rate (%u) and format not supported\n",
e00447fa 784 __func__, params_rate(params));
03be88ee 785 /* See bellow for details how fix this. */
e00447fa
JS		 786 return -EINVAL;
787 }
03be88ee
JS		 788 if (bclk_score != 0) {
789 dev_warn(codec->dev, "Can not produce exact bitclock");
790 /* This is fine if using dsp format, but if using i2s
791 there may be trouble. To fix the issue edit the
792 aic31xx_divs table for your mclk and sample
793 rate. Details can be found from:
794 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
795 Section: 5.6 CLOCK Generation and PLL
796 */
797 }
798 i = match;
e00447fa
JS		 799
800 /* PLL configuration */
801 snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
7ed36e96 802 (aic31xx->p_div << 4) | 0x01);
e00447fa
JS		 803 snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
804
805 snd_soc_write(codec, AIC31XX_PLLDMSB,
806 aic31xx_divs[i].pll_d >> 8);
807 snd_soc_write(codec, AIC31XX_PLLDLSB,
808 aic31xx_divs[i].pll_d & 0xff);
809
810 /* DAC dividers configuration */
811 snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK,
812 aic31xx_divs[i].ndac);
813 snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK,
814 aic31xx_divs[i].mdac);
815
816 snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
817 snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
818
819 /* ADC dividers configuration. Write reset value 1 if not used. */
820 snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK,
821 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
822 snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK,
823 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
824
825 snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr);
826
827 /* Bit clock divider configuration. */
e00447fa
JS		 828 snd_soc_update_bits(codec, AIC31XX_BCLKN,
829 AIC31XX_PLL_MASK, bclk_n);
830
831 aic31xx->rate_div_line = i;
832
833 dev_dbg(codec->dev,
834 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
835 aic31xx_divs[i].pll_j, aic31xx_divs[i].pll_d,
7ed36e96 836 aic31xx->p_div, aic31xx_divs[i].dosr,
e00447fa
JS		 837 aic31xx_divs[i].ndac, aic31xx_divs[i].mdac,
838 aic31xx_divs[i].aosr, aic31xx_divs[i].nadc,
839 aic31xx_divs[i].madc, bclk_n);
840
841 return 0;
842}
843
844static int aic31xx_hw_params(struct snd_pcm_substream *substream,
845 struct snd_pcm_hw_params *params,
ab64246c 846 struct snd_soc_dai *dai)
e00447fa 847{
ab64246c 848 struct snd_soc_codec *codec = dai->codec;
e00447fa
JS		 849 u8 data = 0;
850
88be681b
MB		 851 dev_dbg(codec->dev, "## %s: width %d rate %d\n",
852 __func__, params_width(params),
e00447fa
JS		 853 params_rate(params));
854
855 switch (params_width(params)) {
856 case 16:
857 break;
858 case 20:
859 data = (AIC31XX_WORD_LEN_20BITS <<
860 AIC31XX_IFACE1_DATALEN_SHIFT);
861 break;
862 case 24:
863 data = (AIC31XX_WORD_LEN_24BITS <<
864 AIC31XX_IFACE1_DATALEN_SHIFT);
865 break;
866 case 32:
867 data = (AIC31XX_WORD_LEN_32BITS <<
868 AIC31XX_IFACE1_DATALEN_SHIFT);
869 break;
870 default:
88be681b
MB		 871 dev_err(codec->dev, "%s: Unsupported width %d\n",
872 __func__, params_width(params));
e00447fa
JS		 873 return -EINVAL;
874 }
875
876 snd_soc_update_bits(codec, AIC31XX_IFACE1,
877 AIC31XX_IFACE1_DATALEN_MASK,
878 data);
879
880 return aic31xx_setup_pll(codec, params);
881}
882
883static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute)
884{
885 struct snd_soc_codec *codec = codec_dai->codec;
886
887 if (mute) {
888 snd_soc_update_bits(codec, AIC31XX_DACMUTE,
889 AIC31XX_DACMUTE_MASK,
890 AIC31XX_DACMUTE_MASK);
891 } else {
892 snd_soc_update_bits(codec, AIC31XX_DACMUTE,
893 AIC31XX_DACMUTE_MASK, 0x0);
894 }
895
896 return 0;
897}
898
899static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
900 unsigned int fmt)
901{
902 struct snd_soc_codec *codec = codec_dai->codec;
903 u8 iface_reg1 = 0;
085f3ec6 904 u8 iface_reg2 = 0;
e00447fa
JS		 905 u8 dsp_a_val = 0;
906
907 dev_dbg(codec->dev, "## %s: fmt = 0x%x\n", __func__, fmt);
908
909 /* set master/slave audio interface */
910 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
911 case SND_SOC_DAIFMT_CBM_CFM:
912 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;
913 break;
914 default:
915 dev_alert(codec->dev, "Invalid DAI master/slave interface\n");
916 return -EINVAL;
917 }
918
919 /* interface format */
920 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
921 case SND_SOC_DAIFMT_I2S:
922 break;
923 case SND_SOC_DAIFMT_DSP_A:
09fc38c1 924 dsp_a_val = 0x1; /* fall through */
e00447fa
JS		 925 case SND_SOC_DAIFMT_DSP_B:
926 /* NOTE: BCLKINV bit value 1 equas NB and 0 equals IB */
927 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
928 case SND_SOC_DAIFMT_NB_NF:
085f3ec6 929 iface_reg2 |= AIC31XX_BCLKINV_MASK;
e00447fa
JS		 930 break;
931 case SND_SOC_DAIFMT_IB_NF:
932 break;
933 default:
934 return -EINVAL;
935 }
936 iface_reg1 |= (AIC31XX_DSP_MODE <<
937 AIC31XX_IFACE1_DATATYPE_SHIFT);
938 break;
939 case SND_SOC_DAIFMT_RIGHT_J:
940 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<
941 AIC31XX_IFACE1_DATATYPE_SHIFT);
942 break;
943 case SND_SOC_DAIFMT_LEFT_J:
944 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<
945 AIC31XX_IFACE1_DATATYPE_SHIFT);
946 break;
947 default:
948 dev_err(codec->dev, "Invalid DAI interface format\n");
949 return -EINVAL;
950 }
951
952 snd_soc_update_bits(codec, AIC31XX_IFACE1,
953 AIC31XX_IFACE1_DATATYPE_MASK |
954 AIC31XX_IFACE1_MASTER_MASK,
955 iface_reg1);
956 snd_soc_update_bits(codec, AIC31XX_DATA_OFFSET,
957 AIC31XX_DATA_OFFSET_MASK,
958 dsp_a_val);
959 snd_soc_update_bits(codec, AIC31XX_IFACE2,
960 AIC31XX_BCLKINV_MASK,
085f3ec6 961 iface_reg2);
e00447fa
JS		 962
963 return 0;
964}
965
966static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
967 int clk_id, unsigned int freq, int dir)
968{
969 struct snd_soc_codec *codec = codec_dai->codec;
970 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
971 int i;
972
973 dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
974 __func__, clk_id, freq, dir);
975
7ed36e96
JS		 976 for (i = 1; freq/i > 20000000 && i < 8; i++)
977 ;
978 if (freq/i > 20000000) {
979 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
980 __func__, freq);
981 return -EINVAL;
982 }
983 aic31xx->p_div = i;
984
bbc686b3
JS		 985 for (i = 0; i < ARRAY_SIZE(aic31xx_divs) &&
986 aic31xx_divs[i].mclk_p != freq/aic31xx->p_div; i++)
987 ;
988 if (i == ARRAY_SIZE(aic31xx_divs)) {
989 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
990 __func__, freq);
991 return -EINVAL;
e00447fa
JS		 992 }
993
994 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */
995 snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
996 clk_id << AIC31XX_PLL_CLKIN_SHIFT);
997
998 aic31xx->sysclk = freq;
999 return 0;
1000}
1001
1002static int aic31xx_regulator_event(struct notifier_block *nb,
1003 unsigned long event, void *data)
1004{
1005 struct aic31xx_disable_nb *disable_nb =
1006 container_of(nb, struct aic31xx_disable_nb, nb);
1007 struct aic31xx_priv *aic31xx = disable_nb->aic31xx;
1008
1009 if (event & REGULATOR_EVENT_DISABLE) {
1010 /*
1011 * Put codec to reset and as at least one of the
1012 * supplies was disabled.
1013 */
1014 if (gpio_is_valid(aic31xx->pdata.gpio_reset))
1015 gpio_set_value(aic31xx->pdata.gpio_reset, 0);
1016
1017 regcache_mark_dirty(aic31xx->regmap);
1018 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);
1019 }
1020
1021 return 0;
1022}
1023
1024static void aic31xx_clk_on(struct snd_soc_codec *codec)
1025{
1026 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1027 u8 mask = AIC31XX_PM_MASK;
1028 u8 on = AIC31XX_PM_MASK;
1029
1030 dev_dbg(codec->dev, "codec clock -> on (rate %d)\n",
1031 aic31xx_divs[aic31xx->rate_div_line].rate);
1032 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, on);
1033 mdelay(10);
1034 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, on);
1035 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, on);
1036 if (aic31xx_divs[aic31xx->rate_div_line].nadc)
1037 snd_soc_update_bits(codec, AIC31XX_NADC, mask, on);
1038 if (aic31xx_divs[aic31xx->rate_div_line].madc)
1039 snd_soc_update_bits(codec, AIC31XX_MADC, mask, on);
1040 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, on);
1041}
1042
1043static void aic31xx_clk_off(struct snd_soc_codec *codec)
1044{
e00447fa
JS		 1045 u8 mask = AIC31XX_PM_MASK;
1046 u8 off = 0;
1047
1048 dev_dbg(codec->dev, "codec clock -> off\n");
1049 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, off);
1050 snd_soc_update_bits(codec, AIC31XX_MADC, mask, off);
1051 snd_soc_update_bits(codec, AIC31XX_NADC, mask, off);
1052 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, off);
1053 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, off);
1054 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, off);
1055}
1056
1057static int aic31xx_power_on(struct snd_soc_codec *codec)
1058{
1059 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1060 int ret = 0;
1061
1062 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
1063 aic31xx->supplies);
1064 if (ret)
1065 return ret;
1066
1067 if (gpio_is_valid(aic31xx->pdata.gpio_reset)) {
1068 gpio_set_value(aic31xx->pdata.gpio_reset, 1);
1069 udelay(100);
1070 }
1071 regcache_cache_only(aic31xx->regmap, false);
1072 ret = regcache_sync(aic31xx->regmap);
1073 if (ret != 0) {
1074 dev_err(codec->dev,
1075 "Failed to restore cache: %d\n", ret);
1076 regcache_cache_only(aic31xx->regmap, true);
1077 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1078 aic31xx->supplies);
1079 return ret;
1080 }
1081 return 0;
1082}
1083
c7734e8e 1084static void aic31xx_power_off(struct snd_soc_codec *codec)
e00447fa
JS		 1085{
1086 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
e00447fa
JS		 1087
1088 regcache_cache_only(aic31xx->regmap, true);
c7734e8e
AD		 1089 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1090 aic31xx->supplies);
e00447fa
JS		 1091}
1092
1093static int aic31xx_set_bias_level(struct snd_soc_codec *codec,
1094 enum snd_soc_bias_level level)
1095{
1096 dev_dbg(codec->dev, "## %s: %d -> %d\n", __func__,
378d1e43 1097 snd_soc_codec_get_bias_level(codec), level);
e00447fa
JS		 1098
1099 switch (level) {
1100 case SND_SOC_BIAS_ON:
1101 break;
1102 case SND_SOC_BIAS_PREPARE:
378d1e43 1103 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY)
e00447fa
JS		 1104 aic31xx_clk_on(codec);
1105 break;
1106 case SND_SOC_BIAS_STANDBY:
378d1e43 1107 switch (snd_soc_codec_get_bias_level(codec)) {
e00447fa
JS		 1108 case SND_SOC_BIAS_OFF:
1109 aic31xx_power_on(codec);
1110 break;
1111 case SND_SOC_BIAS_PREPARE:
1112 aic31xx_clk_off(codec);
1113 break;
1114 default:
1115 BUG();
1116 }
1117 break;
1118 case SND_SOC_BIAS_OFF:
378d1e43 1119 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY)
fd218aa3 1120 aic31xx_power_off(codec);
e00447fa
JS		 1121 break;
1122 }
e00447fa
JS		 1123
1124 return 0;
1125}
1126
e00447fa
JS		 1127static int aic31xx_codec_probe(struct snd_soc_codec *codec)
1128{
1129 int ret = 0;
1130 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1131 int i;
1132
1133 dev_dbg(aic31xx->dev, "## %s\n", __func__);
1134
1135 aic31xx = snd_soc_codec_get_drvdata(codec);
e00447fa
JS		 1136
1137 aic31xx->codec = codec;
1138
e00447fa
JS		 1139 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {
1140 aic31xx->disable_nb[i].nb.notifier_call =
1141 aic31xx_regulator_event;
1142 aic31xx->disable_nb[i].aic31xx = aic31xx;
1143 ret = regulator_register_notifier(aic31xx->supplies[i].consumer,
1144 &aic31xx->disable_nb[i].nb);
1145 if (ret) {
1146 dev_err(codec->dev,
1147 "Failed to request regulator notifier: %d\n",
1148 ret);
1149 return ret;
1150 }
1151 }
1152
1153 regcache_cache_only(aic31xx->regmap, true);
1154 regcache_mark_dirty(aic31xx->regmap);
1155
1156 ret = aic31xx_add_controls(codec);
1157 if (ret)
1158 return ret;
1159
1160 ret = aic31xx_add_widgets(codec);
1161
1162 return ret;
1163}
1164
1165static int aic31xx_codec_remove(struct snd_soc_codec *codec)
1166{
1167 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1168 int i;
e00447fa
JS		 1169
1170 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1171 regulator_unregister_notifier(aic31xx->supplies[i].consumer,
1172 &aic31xx->disable_nb[i].nb);
1173
1174 return 0;
1175}
1176
a180ba45 1177static const struct snd_soc_codec_driver soc_codec_driver_aic31xx = {
e00447fa
JS		 1178 .probe = aic31xx_codec_probe,
1179 .remove = aic31xx_codec_remove,
e00447fa 1180 .set_bias_level = aic31xx_set_bias_level,
a43a2629
LPC		 1181 .suspend_bias_off = true,
1182
1bb99f2a 1183 .component_driver = {
ef9656b6
NY		 1184 .controls = common31xx_snd_controls,
1185 .num_controls = ARRAY_SIZE(common31xx_snd_controls),
1186 .dapm_widgets = common31xx_dapm_widgets,
1187 .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets),
1188 .dapm_routes = common31xx_audio_map,
1189 .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map),
1bb99f2a 1190 },
e00447fa
JS		 1191};
1192
64793047 1193static const struct snd_soc_dai_ops aic31xx_dai_ops = {
e00447fa
JS		 1194 .hw_params = aic31xx_hw_params,
1195 .set_sysclk = aic31xx_set_dai_sysclk,
1196 .set_fmt = aic31xx_set_dai_fmt,
1197 .digital_mute = aic31xx_dac_mute,
1198};
1199
ef9656b6
NY		 1200static struct snd_soc_dai_driver dac31xx_dai_driver[] = {
1201 {
51827c41 1202 .name = "tlv320dac31xx-hifi",
ef9656b6
NY		 1203 .playback = {
1204 .stream_name = "Playback",
3520646d 1205 .channels_min = 2,
ef9656b6
NY		 1206 .channels_max = 2,
1207 .rates = AIC31XX_RATES,
1208 .formats = AIC31XX_FORMATS,
1209 },
1210 .ops = &aic31xx_dai_ops,
1211 .symmetric_rates = 1,
1212 }
1213};
1214
e00447fa
JS		 1215static struct snd_soc_dai_driver aic31xx_dai_driver[] = {
1216 {
1217 .name = "tlv320aic31xx-hifi",
1218 .playback = {
1219 .stream_name = "Playback",
3520646d 1220 .channels_min = 2,
e00447fa
JS		 1221 .channels_max = 2,
1222 .rates = AIC31XX_RATES,
1223 .formats = AIC31XX_FORMATS,
1224 },
1225 .capture = {
1226 .stream_name = "Capture",
3520646d 1227 .channels_min = 2,
e00447fa
JS		 1228 .channels_max = 2,
1229 .rates = AIC31XX_RATES,
1230 .formats = AIC31XX_FORMATS,
1231 },
1232 .ops = &aic31xx_dai_ops,
1233 .symmetric_rates = 1,
1234 }
1235};
1236
1237#if defined(CONFIG_OF)
1238static const struct of_device_id tlv320aic31xx_of_match[] = {
1239 { .compatible = "ti,tlv320aic310x" },
1240 { .compatible = "ti,tlv320aic311x" },
1241 { .compatible = "ti,tlv320aic3100" },
1242 { .compatible = "ti,tlv320aic3110" },
1243 { .compatible = "ti,tlv320aic3120" },
1244 { .compatible = "ti,tlv320aic3111" },
a4a1d79e 1245 { .compatible = "ti,tlv320dac3100" },
4e2cc814 1246 { .compatible = "ti,tlv320dac3101" },
e00447fa
JS		 1247 {},
1248};
1249MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
1250
1251static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
1252{
1253 struct device_node *np = aic31xx->dev->of_node;
1254 unsigned int value = MICBIAS_2_0V;
1255 int ret;
1256
1257 of_property_read_u32(np, "ai31xx-micbias-vg", &value);
1258 switch (value) {
1259 case MICBIAS_2_0V:
1260 case MICBIAS_2_5V:
1261 case MICBIAS_AVDDV:
1262 aic31xx->pdata.micbias_vg = value;
1263 break;
1264 default:
1265 dev_err(aic31xx->dev,
1266 "Bad ai31xx-micbias-vg value %d DT\n",
1267 value);
1268 aic31xx->pdata.micbias_vg = MICBIAS_2_0V;
1269 }
1270
a825f31f
AD		 1271 ret = of_get_named_gpio(np, "reset-gpios", 0);
1272 if (ret > 0) {
e00447fa 1273 aic31xx->pdata.gpio_reset = ret;
a825f31f
AD		 1274 } else {
1275 ret = of_get_named_gpio(np, "gpio-reset", 0);
1276 if (ret > 0) {
1277 dev_warn(aic31xx->dev, "Using deprecated property \"gpio-reset\", please update your DT");
1278 aic31xx->pdata.gpio_reset = ret;
1279 }
1280 }
e00447fa
JS		 1281}
1282#else /* CONFIG_OF */
1283static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
1284{
1285}
1286#endif /* CONFIG_OF */
1287
a72d2abb 1288static int aic31xx_device_init(struct aic31xx_priv *aic31xx)
e00447fa
JS		 1289{
1290 int ret, i;
1291
1292 dev_set_drvdata(aic31xx->dev, aic31xx);
1293
1294 if (dev_get_platdata(aic31xx->dev))
1295 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev),
1296 sizeof(aic31xx->pdata));
1297 else if (aic31xx->dev->of_node)
1298 aic31xx_pdata_from_of(aic31xx);
1299
1300 if (aic31xx->pdata.gpio_reset) {
1301 ret = devm_gpio_request_one(aic31xx->dev,
1302 aic31xx->pdata.gpio_reset,
1303 GPIOF_OUT_INIT_HIGH,
1304 "aic31xx-reset-pin");
1305 if (ret < 0) {
1306 dev_err(aic31xx->dev, "not able to acquire gpio\n");
a72d2abb 1307 return ret;
e00447fa
JS		 1308 }
1309 }
1310
1311 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1312 aic31xx->supplies[i].supply = aic31xx_supply_names[i];
1313
1314 ret = devm_regulator_bulk_get(aic31xx->dev,
1315 ARRAY_SIZE(aic31xx->supplies),
1316 aic31xx->supplies);
1317 if (ret != 0)
1318 dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret);
1319
a72d2abb 1320 return ret;
e00447fa
JS		 1321}
1322
1323static int aic31xx_i2c_probe(struct i2c_client *i2c,
1324 const struct i2c_device_id *id)
1325{
1326 struct aic31xx_priv *aic31xx;
1327 int ret;
1328 const struct regmap_config *regmap_config;
1329
1330 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,
1331 id->name, (int) id->driver_data);
1332
1333 regmap_config = &aic31xx_i2c_regmap;
1334
1335 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);
1336 if (aic31xx == NULL)
1337 return -ENOMEM;
1338
1339 aic31xx->regmap = devm_regmap_init_i2c(i2c, regmap_config);
e00447fa
JS		 1340 if (IS_ERR(aic31xx->regmap)) {
1341 ret = PTR_ERR(aic31xx->regmap);
1342 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1343 ret);
1344 return ret;
1345 }
1346 aic31xx->dev = &i2c->dev;
1347
1348 aic31xx->pdata.codec_type = id->driver_data;
1349
a72d2abb
PU		 1350 ret = aic31xx_device_init(aic31xx);
1351 if (ret)
1352 return ret;
e00447fa 1353
ef9656b6
NY		 1354 if (aic31xx->pdata.codec_type & DAC31XX_BIT)
1355 return snd_soc_register_codec(&i2c->dev,
1356 &soc_codec_driver_aic31xx,
1357 dac31xx_dai_driver,
1358 ARRAY_SIZE(dac31xx_dai_driver));
1359 else
1360 return snd_soc_register_codec(&i2c->dev,
1361 &soc_codec_driver_aic31xx,
1362 aic31xx_dai_driver,
1363 ARRAY_SIZE(aic31xx_dai_driver));
e00447fa
JS		 1364}
1365
1366static int aic31xx_i2c_remove(struct i2c_client *i2c)
1367{
dac7e404 1368 snd_soc_unregister_codec(&i2c->dev);
e00447fa
JS		 1369 return 0;
1370}
1371
1372static const struct i2c_device_id aic31xx_i2c_id[] = {
1373 { "tlv320aic310x", AIC3100 },
1374 { "tlv320aic311x", AIC3110 },
1375 { "tlv320aic3100", AIC3100 },
1376 { "tlv320aic3110", AIC3110 },
1377 { "tlv320aic3120", AIC3120 },
1378 { "tlv320aic3111", AIC3111 },
ef9656b6 1379 { "tlv320dac3100", DAC3100 },
4e2cc814 1380 { "tlv320dac3101", DAC3101 },
e00447fa
JS		 1381 { }
1382};
1383MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
1384
f5cc1772
BN		 1385#ifdef CONFIG_ACPI
1386static const struct acpi_device_id aic31xx_acpi_match[] = {
1387 { "10TI3100", 0 },
1388 { }
1389};
1390MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match);
1391#endif
1392
e00447fa
JS		 1393static struct i2c_driver aic31xx_i2c_driver = {
1394 .driver = {
1395 .name = "tlv320aic31xx-codec",
e00447fa 1396 .of_match_table = of_match_ptr(tlv320aic31xx_of_match),
f5cc1772 1397 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match),
e00447fa
JS		 1398 },
1399 .probe = aic31xx_i2c_probe,
dac7e404 1400 .remove = aic31xx_i2c_remove,
e00447fa
JS		 1401 .id_table = aic31xx_i2c_id,
1402};
1403
1404module_i2c_driver(aic31xx_i2c_driver);
1405
b1c52b7e
AD		 1406MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>");
1407MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver");
1408MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)