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ASoC: tlv320aic31xx: Reformat header file using GENMASK and BIT macros
[linux-2.6-block.git] / sound / soc / codecs / tlv320aic31xx.c
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b1c52b7e 1// SPDX-License-Identifier: GPL-2.0
e00447fa 2/*
b1c52b7e 3 * ALSA SoC TLV320AIC31xx CODEC Driver
e00447fa 4 *
b1c52b7e
AD		 5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
6 * Jyri Sarha <jsarha@ti.com>
e00447fa
JS		 7 *
8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
9 *
b1c52b7e
AD		 10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated
11 * high performance codecs which provides a stereo DAC, a mono ADC,
e00447fa
JS		 12 * and mono/stereo Class-D speaker driver.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/gpio.h>
22#include <linux/regulator/consumer.h>
f5cc1772 23#include <linux/acpi.h>
0faabc4f 24#include <linux/of.h>
e00447fa
JS		 25#include <linux/of_gpio.h>
26#include <linux/slab.h>
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
34
35#include "tlv320aic31xx.h"
36
37static const struct reg_default aic31xx_reg_defaults[] = {
38 { AIC31XX_CLKMUX, 0x00 },
39 { AIC31XX_PLLPR, 0x11 },
40 { AIC31XX_PLLJ, 0x04 },
41 { AIC31XX_PLLDMSB, 0x00 },
42 { AIC31XX_PLLDLSB, 0x00 },
43 { AIC31XX_NDAC, 0x01 },
44 { AIC31XX_MDAC, 0x01 },
45 { AIC31XX_DOSRMSB, 0x00 },
46 { AIC31XX_DOSRLSB, 0x80 },
47 { AIC31XX_NADC, 0x01 },
48 { AIC31XX_MADC, 0x01 },
49 { AIC31XX_AOSR, 0x80 },
50 { AIC31XX_IFACE1, 0x00 },
51 { AIC31XX_DATA_OFFSET, 0x00 },
52 { AIC31XX_IFACE2, 0x00 },
53 { AIC31XX_BCLKN, 0x01 },
54 { AIC31XX_DACSETUP, 0x14 },
55 { AIC31XX_DACMUTE, 0x0c },
56 { AIC31XX_LDACVOL, 0x00 },
57 { AIC31XX_RDACVOL, 0x00 },
58 { AIC31XX_ADCSETUP, 0x00 },
59 { AIC31XX_ADCFGA, 0x80 },
60 { AIC31XX_ADCVOL, 0x00 },
61 { AIC31XX_HPDRIVER, 0x04 },
62 { AIC31XX_SPKAMP, 0x06 },
63 { AIC31XX_DACMIXERROUTE, 0x00 },
64 { AIC31XX_LANALOGHPL, 0x7f },
65 { AIC31XX_RANALOGHPR, 0x7f },
66 { AIC31XX_LANALOGSPL, 0x7f },
67 { AIC31XX_RANALOGSPR, 0x7f },
68 { AIC31XX_HPLGAIN, 0x02 },
69 { AIC31XX_HPRGAIN, 0x02 },
70 { AIC31XX_SPLGAIN, 0x00 },
71 { AIC31XX_SPRGAIN, 0x00 },
72 { AIC31XX_MICBIAS, 0x00 },
73 { AIC31XX_MICPGA, 0x80 },
74 { AIC31XX_MICPGAPI, 0x00 },
75 { AIC31XX_MICPGAMI, 0x00 },
76};
77
78static bool aic31xx_volatile(struct device *dev, unsigned int reg)
79{
80 switch (reg) {
81 case AIC31XX_PAGECTL: /* regmap implementation requires this */
82 case AIC31XX_RESET: /* always clears after write */
83 case AIC31XX_OT_FLAG:
84 case AIC31XX_ADCFLAG:
85 case AIC31XX_DACFLAG1:
86 case AIC31XX_DACFLAG2:
87 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
88 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
89 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
90 case AIC31XX_INTRDACFLAG2:
91 case AIC31XX_INTRADCFLAG2:
92 return true;
93 }
94 return false;
95}
96
97static bool aic31xx_writeable(struct device *dev, unsigned int reg)
98{
99 switch (reg) {
100 case AIC31XX_OT_FLAG:
101 case AIC31XX_ADCFLAG:
102 case AIC31XX_DACFLAG1:
103 case AIC31XX_DACFLAG2:
104 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
105 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
106 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
107 case AIC31XX_INTRDACFLAG2:
108 case AIC31XX_INTRADCFLAG2:
109 return false;
110 }
111 return true;
112}
113
114static const struct regmap_range_cfg aic31xx_ranges[] = {
115 {
116 .range_min = 0,
117 .range_max = 12 * 128,
118 .selector_reg = AIC31XX_PAGECTL,
119 .selector_mask = 0xff,
120 .selector_shift = 0,
121 .window_start = 0,
122 .window_len = 128,
123 },
124};
125
9296f4da 126static const struct regmap_config aic31xx_i2c_regmap = {
e00447fa
JS		 127 .reg_bits = 8,
128 .val_bits = 8,
129 .writeable_reg = aic31xx_writeable,
130 .volatile_reg = aic31xx_volatile,
131 .reg_defaults = aic31xx_reg_defaults,
132 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),
133 .cache_type = REGCACHE_RBTREE,
134 .ranges = aic31xx_ranges,
135 .num_ranges = ARRAY_SIZE(aic31xx_ranges),
136 .max_register = 12 * 128,
137};
138
ca7840fb 139static const char * const aic31xx_supply_names[] = {
e00447fa
JS		 140 "HPVDD",
141 "SPRVDD",
142 "SPLVDD",
143 "AVDD",
144 "IOVDD",
145 "DVDD",
146};
147
ca7840fb
AD		 148#define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names)
149
e00447fa
JS		 150struct aic31xx_disable_nb {
151 struct notifier_block nb;
152 struct aic31xx_priv *aic31xx;
153};
154
155struct aic31xx_priv {
156 struct snd_soc_codec *codec;
157 u8 i2c_regs_status;
158 struct device *dev;
159 struct regmap *regmap;
160 struct aic31xx_pdata pdata;
161 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
162 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
163 unsigned int sysclk;
7ed36e96 164 u8 p_div;
e00447fa
JS		 165 int rate_div_line;
166};
167
168struct aic31xx_rate_divs {
7ed36e96 169 u32 mclk_p;
e00447fa 170 u32 rate;
e00447fa
JS		 171 u8 pll_j;
172 u16 pll_d;
173 u16 dosr;
174 u8 ndac;
175 u8 mdac;
176 u8 aosr;
177 u8 nadc;
178 u8 madc;
179};
180
ca7840fb 181/* ADC dividers can be disabled by configuring them to 0 */
e00447fa 182static const struct aic31xx_rate_divs aic31xx_divs[] = {
7ed36e96 183 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */
e00447fa 184 /* 8k rate */
7ed36e96
JS		 185 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2},
186 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3},
187 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2},
e00447fa 188 /* 11.025k rate */
7ed36e96
JS		 189 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2},
190 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3},
191 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2},
e00447fa 192 /* 16k rate */
7ed36e96
JS		 193 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2},
194 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3},
195 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2},
e00447fa 196 /* 22.05k rate */
7ed36e96
JS		 197 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2},
198 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3},
199 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2},
e00447fa 200 /* 32k rate */
7ed36e96
JS		 201 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2},
202 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3},
203 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2},
e00447fa 204 /* 44.1k rate */
7ed36e96
JS		 205 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2},
206 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3},
207 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2},
e00447fa 208 /* 48k rate */
7ed36e96
JS		 209 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2},
210 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4},
211 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2},
e00447fa 212 /* 88.2k rate */
7ed36e96
JS		 213 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2},
214 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3},
215 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2},
e00447fa 216 /* 96k rate */
7ed36e96
JS		 217 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2},
218 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4},
219 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2},
e00447fa 220 /* 176.4k rate */
7ed36e96
JS		 221 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2},
222 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3},
223 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2},
e00447fa 224 /* 192k rate */
7ed36e96
JS		 225 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2},
226 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4},
227 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2},
e00447fa
JS		 228};
229
230static const char * const ldac_in_text[] = {
231 "Off", "Left Data", "Right Data", "Mono"
232};
233
234static const char * const rdac_in_text[] = {
235 "Off", "Right Data", "Left Data", "Mono"
236};
237
238static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);
239
240static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);
241
242static const char * const mic_select_text[] = {
243 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
244};
245
914bc160
LPC		 246static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,
247 mic_select_text);
248static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,
249 mic_select_text);
250static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
251 mic_select_text);
e00447fa 252
914bc160
LPC		 253static SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text);
254static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
255 mic_select_text);
e00447fa
JS		 256
257static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
258static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
259static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
260static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
261static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
262static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
263static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
264static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
265
266/*
267 * controls to be exported to the user space
268 */
ef9656b6 269static const struct snd_kcontrol_new common31xx_snd_controls[] = {
e00447fa
JS		 270 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,
271 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
272
ef9656b6
NY		 273 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,
274 AIC31XX_HPRGAIN, 2, 1, 0),
275 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,
276 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
277
278 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
279 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
280};
281
282static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
e00447fa
JS		 283 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,
284 adc_fgain_tlv),
285
286 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),
287 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,
288 0, -24, 40, 6, 0, adc_cgain_tlv),
289
290 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
291 119, 0, mic_pga_tlv),
e00447fa
JS		 292};
293
294static const struct snd_kcontrol_new aic311x_snd_controls[] = {
295 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
296 AIC31XX_SPRGAIN, 2, 1, 0),
297 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
298 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
299
300 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
301 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
302};
303
304static const struct snd_kcontrol_new aic310x_snd_controls[] = {
305 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
306 2, 1, 0),
307 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
308 3, 3, 0, class_D_drv_tlv),
309
310 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
311 0, 0x7F, 1, sp_vol_tlv),
312};
313
314static const struct snd_kcontrol_new ldac_in_control =
315 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);
316
317static const struct snd_kcontrol_new rdac_in_control =
318 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);
319
9296f4da
MB		 320static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,
321 unsigned int mask, unsigned int wbits, int sleep,
322 int count)
e00447fa
JS		 323{
324 unsigned int bits;
325 int counter = count;
326 int ret = regmap_read(aic31xx->regmap, reg, &bits);
423ca88e 327
e00447fa
JS		 328 while ((bits & mask) != wbits && counter && !ret) {
329 usleep_range(sleep, sleep * 2);
330 ret = regmap_read(aic31xx->regmap, reg, &bits);
331 counter--;
332 }
333 if ((bits & mask) != wbits) {
334 dev_err(aic31xx->dev,
335 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
336 __func__, reg, bits, wbits, ret, mask,
337 (count - counter) * sleep);
338 ret = -1;
339 }
340 return ret;
341}
342
343#define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
344
345static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
346 struct snd_kcontrol *kcontrol, int event)
347{
dd943d36
LPC		 348 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
349 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
e00447fa
JS		 350 unsigned int reg = AIC31XX_DACFLAG1;
351 unsigned int mask;
352
353 switch (WIDGET_BIT(w->reg, w->shift)) {
354 case WIDGET_BIT(AIC31XX_DACSETUP, 7):
355 mask = AIC31XX_LDACPWRSTATUS_MASK;
356 break;
357 case WIDGET_BIT(AIC31XX_DACSETUP, 6):
358 mask = AIC31XX_RDACPWRSTATUS_MASK;
359 break;
360 case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
361 mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
362 break;
363 case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
364 mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
365 break;
366 case WIDGET_BIT(AIC31XX_SPKAMP, 7):
367 mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
368 break;
369 case WIDGET_BIT(AIC31XX_SPKAMP, 6):
370 mask = AIC31XX_SPRDRVPWRSTATUS_MASK;
371 break;
372 case WIDGET_BIT(AIC31XX_ADCSETUP, 7):
373 mask = AIC31XX_ADCPWRSTATUS_MASK;
374 reg = AIC31XX_ADCFLAG;
375 break;
376 default:
dd943d36 377 dev_err(codec->dev, "Unknown widget '%s' calling %s\n",
e00447fa
JS		 378 w->name, __func__);
379 return -EINVAL;
380 }
381
382 switch (event) {
383 case SND_SOC_DAPM_POST_PMU:
384 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100);
385 case SND_SOC_DAPM_POST_PMD:
386 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100);
387 default:
dd943d36 388 dev_dbg(codec->dev,
e00447fa
JS		 389 "Unhandled dapm widget event %d from %s\n",
390 event, w->name);
391 }
392 return 0;
393}
394
ef9656b6 395static const struct snd_kcontrol_new aic31xx_left_output_switches[] = {
e00447fa
JS		 396 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
397 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
398 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
399};
400
ef9656b6 401static const struct snd_kcontrol_new aic31xx_right_output_switches[] = {
e00447fa
JS		 402 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
403 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
404};
405
ef9656b6
NY		 406static const struct snd_kcontrol_new dac31xx_left_output_switches[] = {
407 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
408 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0),
409 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0),
410};
411
412static const struct snd_kcontrol_new dac31xx_right_output_switches[] = {
413 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
414 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0),
415};
416
e00447fa
JS		 417static const struct snd_kcontrol_new p_term_mic1lp =
418 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
419
420static const struct snd_kcontrol_new p_term_mic1rp =
421 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
422
423static const struct snd_kcontrol_new p_term_mic1lm =
424 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
425
426static const struct snd_kcontrol_new m_term_mic1lm =
427 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
428
429static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =
430 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
431
432static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =
433 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
434
435static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =
436 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
437
438static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =
439 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
440
441static int mic_bias_event(struct snd_soc_dapm_widget *w,
442 struct snd_kcontrol *kcontrol, int event)
443{
dd943d36 444 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
e00447fa 445 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
423ca88e 446
e00447fa
JS		 447 switch (event) {
448 case SND_SOC_DAPM_POST_PMU:
449 /* change mic bias voltage to user defined */
450 snd_soc_update_bits(codec, AIC31XX_MICBIAS,
451 AIC31XX_MICBIAS_MASK,
452 aic31xx->pdata.micbias_vg <<
453 AIC31XX_MICBIAS_SHIFT);
454 dev_dbg(codec->dev, "%s: turned on\n", __func__);
455 break;
456 case SND_SOC_DAPM_PRE_PMD:
457 /* turn mic bias off */
458 snd_soc_update_bits(codec, AIC31XX_MICBIAS,
459 AIC31XX_MICBIAS_MASK, 0);
460 dev_dbg(codec->dev, "%s: turned off\n", __func__);
461 break;
462 }
463 return 0;
464}
465
ef9656b6 466static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = {
e00447fa
JS		 467 SND_SOC_DAPM_AIF_IN("DAC IN", "DAC Playback", 0, SND_SOC_NOPM, 0, 0),
468
469 SND_SOC_DAPM_MUX("DAC Left Input",
470 SND_SOC_NOPM, 0, 0, &ldac_in_control),
471 SND_SOC_DAPM_MUX("DAC Right Input",
472 SND_SOC_NOPM, 0, 0, &rdac_in_control),
473 /* DACs */
474 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
475 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
476 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
477
478 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
479 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
480 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
481
ef9656b6 482 /* HP */
e00447fa
JS		 483 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
484 &aic31xx_dapm_hpl_switch),
485 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
486 &aic31xx_dapm_hpr_switch),
487
488 /* Output drivers */
489 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
490 NULL, 0, aic31xx_dapm_power_event,
491 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
492 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
493 NULL, 0, aic31xx_dapm_power_event,
494 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
495
ef9656b6
NY		 496 /* Mic Bias */
497 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
498 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
499
500 /* Outputs */
501 SND_SOC_DAPM_OUTPUT("HPL"),
502 SND_SOC_DAPM_OUTPUT("HPR"),
503};
504
505static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = {
506 /* Inputs */
507 SND_SOC_DAPM_INPUT("AIN1"),
508 SND_SOC_DAPM_INPUT("AIN2"),
509
510 /* Output Mixers */
511 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
512 dac31xx_left_output_switches,
513 ARRAY_SIZE(dac31xx_left_output_switches)),
514 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
515 dac31xx_right_output_switches,
516 ARRAY_SIZE(dac31xx_right_output_switches)),
517};
518
519static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
520 /* Inputs */
521 SND_SOC_DAPM_INPUT("MIC1LP"),
522 SND_SOC_DAPM_INPUT("MIC1RP"),
523 SND_SOC_DAPM_INPUT("MIC1LM"),
e00447fa
JS		 524
525 /* Input Selection to MIC_PGA */
526 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
527 &p_term_mic1lp),
528 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
529 &p_term_mic1rp),
530 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
531 &p_term_mic1lm),
532
ef9656b6
NY		 533 /* ADC */
534 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
535 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
536 SND_SOC_DAPM_POST_PMD),
537
e00447fa
JS		 538 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
539 &m_term_mic1lm),
ef9656b6 540
e00447fa
JS		 541 /* Enabling & Disabling MIC Gain Ctl */
542 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,
543 7, 1, NULL, 0),
544
ef9656b6
NY		 545 /* Output Mixers */
546 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
547 aic31xx_left_output_switches,
548 ARRAY_SIZE(aic31xx_left_output_switches)),
549 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
550 aic31xx_right_output_switches,
551 ARRAY_SIZE(aic31xx_right_output_switches)),
e00447fa
JS		 552};
553
554static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {
555 /* AIC3111 and AIC3110 have stereo class-D amplifier */
556 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
557 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
558 SND_SOC_DAPM_POST_PMD),
559 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
560 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
561 SND_SOC_DAPM_POST_PMD),
562 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
563 &aic31xx_dapm_spl_switch),
564 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
565 &aic31xx_dapm_spr_switch),
566 SND_SOC_DAPM_OUTPUT("SPL"),
567 SND_SOC_DAPM_OUTPUT("SPR"),
568};
569
570/* AIC3100 and AIC3120 have only mono class-D amplifier */
571static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {
572 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
573 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
574 SND_SOC_DAPM_POST_PMD),
575 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
576 &aic31xx_dapm_spl_switch),
577 SND_SOC_DAPM_OUTPUT("SPK"),
578};
579
580static const struct snd_soc_dapm_route
ef9656b6 581common31xx_audio_map[] = {
e00447fa
JS		 582 /* DAC Input Routing */
583 {"DAC Left Input", "Left Data", "DAC IN"},
584 {"DAC Left Input", "Right Data", "DAC IN"},
585 {"DAC Left Input", "Mono", "DAC IN"},
586 {"DAC Right Input", "Left Data", "DAC IN"},
587 {"DAC Right Input", "Right Data", "DAC IN"},
588 {"DAC Right Input", "Mono", "DAC IN"},
589 {"DAC Left", NULL, "DAC Left Input"},
590 {"DAC Right", NULL, "DAC Right Input"},
591
ef9656b6
NY		 592 /* HPL path */
593 {"HP Left", "Switch", "Output Left"},
594 {"HPL Driver", NULL, "HP Left"},
595 {"HPL", NULL, "HPL Driver"},
596
597 /* HPR path */
598 {"HP Right", "Switch", "Output Right"},
599 {"HPR Driver", NULL, "HP Right"},
600 {"HPR", NULL, "HPR Driver"},
601};
602
603static const struct snd_soc_dapm_route
604dac31xx_audio_map[] = {
605 /* Left Output */
606 {"Output Left", "From Left DAC", "DAC Left"},
607 {"Output Left", "From AIN1", "AIN1"},
608 {"Output Left", "From AIN2", "AIN2"},
609
610 /* Right Output */
611 {"Output Right", "From Right DAC", "DAC Right"},
612 {"Output Right", "From AIN2", "AIN2"},
613};
614
615static const struct snd_soc_dapm_route
616aic31xx_audio_map[] = {
e00447fa
JS		 617 /* Mic input */
618 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
619 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
620 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
621 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
622 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
623 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
624 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
625 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
626 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
627
628 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
629 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
630 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
631
632 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
633 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
634 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
635 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
636
637 {"ADC", NULL, "MIC_GAIN_CTL"},
638
639 /* Left Output */
640 {"Output Left", "From Left DAC", "DAC Left"},
641 {"Output Left", "From MIC1LP", "MIC1LP"},
642 {"Output Left", "From MIC1RP", "MIC1RP"},
643
644 /* Right Output */
645 {"Output Right", "From Right DAC", "DAC Right"},
646 {"Output Right", "From MIC1RP", "MIC1RP"},
e00447fa
JS		 647};
648
649static const struct snd_soc_dapm_route
650aic311x_audio_map[] = {
651 /* SP L path */
652 {"Speaker Left", "Switch", "Output Left"},
653 {"SPL ClassD", NULL, "Speaker Left"},
654 {"SPL", NULL, "SPL ClassD"},
655
656 /* SP R path */
657 {"Speaker Right", "Switch", "Output Right"},
658 {"SPR ClassD", NULL, "Speaker Right"},
659 {"SPR", NULL, "SPR ClassD"},
660};
661
662static const struct snd_soc_dapm_route
663aic310x_audio_map[] = {
664 /* SP L path */
665 {"Speaker", "Switch", "Output Left"},
666 {"SPK ClassD", NULL, "Speaker"},
667 {"SPK", NULL, "SPK ClassD"},
668};
669
670static int aic31xx_add_controls(struct snd_soc_codec *codec)
671{
672 int ret = 0;
673 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
674
ef9656b6
NY		 675 if (!(aic31xx->pdata.codec_type & DAC31XX_BIT))
676 ret = snd_soc_add_codec_controls(
677 codec, aic31xx_snd_controls,
678 ARRAY_SIZE(aic31xx_snd_controls));
679 if (ret)
680 return ret;
681
e00447fa
JS		 682 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT)
683 ret = snd_soc_add_codec_controls(
684 codec, aic311x_snd_controls,
685 ARRAY_SIZE(aic311x_snd_controls));
686 else
687 ret = snd_soc_add_codec_controls(
688 codec, aic310x_snd_controls,
689 ARRAY_SIZE(aic310x_snd_controls));
690
691 return ret;
692}
693
694static int aic31xx_add_widgets(struct snd_soc_codec *codec)
695{
378d1e43 696 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
e00447fa
JS		 697 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
698 int ret = 0;
699
ef9656b6
NY		 700 if (aic31xx->pdata.codec_type & DAC31XX_BIT) {
701 ret = snd_soc_dapm_new_controls(
702 dapm, dac31xx_dapm_widgets,
703 ARRAY_SIZE(dac31xx_dapm_widgets));
704 if (ret)
705 return ret;
706
707 ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map,
708 ARRAY_SIZE(dac31xx_audio_map));
709 if (ret)
710 return ret;
711 } else {
712 ret = snd_soc_dapm_new_controls(
713 dapm, aic31xx_dapm_widgets,
714 ARRAY_SIZE(aic31xx_dapm_widgets));
715 if (ret)
716 return ret;
717
718 ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map,
719 ARRAY_SIZE(aic31xx_audio_map));
720 if (ret)
721 return ret;
722 }
723
e00447fa
JS		 724 if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
725 ret = snd_soc_dapm_new_controls(
726 dapm, aic311x_dapm_widgets,
727 ARRAY_SIZE(aic311x_dapm_widgets));
728 if (ret)
729 return ret;
730
731 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
732 ARRAY_SIZE(aic311x_audio_map));
733 if (ret)
734 return ret;
735 } else {
736 ret = snd_soc_dapm_new_controls(
737 dapm, aic310x_dapm_widgets,
738 ARRAY_SIZE(aic310x_dapm_widgets));
739 if (ret)
740 return ret;
741
742 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
743 ARRAY_SIZE(aic310x_audio_map));
744 if (ret)
745 return ret;
746 }
747
748 return 0;
749}
750
751static int aic31xx_setup_pll(struct snd_soc_codec *codec,
752 struct snd_pcm_hw_params *params)
753{
754 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
03be88ee 755 int bclk_score = snd_soc_params_to_frame_size(params);
7ed36e96 756 int mclk_p = aic31xx->sysclk / aic31xx->p_div;
e00447fa 757 int bclk_n = 0;
03be88ee 758 int match = -1;
e00447fa
JS		 759 int i;
760
761 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
762 snd_soc_update_bits(codec, AIC31XX_CLKMUX,
763 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
764 snd_soc_update_bits(codec, AIC31XX_IFACE2,
765 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
766
767 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
768 if (aic31xx_divs[i].rate == params_rate(params) &&
7ed36e96 769 aic31xx_divs[i].mclk_p == mclk_p) {
03be88ee
JS		 770 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
771 snd_soc_params_to_frame_size(params);
772 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
773 snd_soc_params_to_frame_size(params);
774 if (s < bclk_score && bn > 0) {
775 match = i;
776 bclk_n = bn;
777 bclk_score = s;
778 }
779 }
e00447fa
JS		 780 }
781
03be88ee
JS		 782 if (match == -1) {
783 dev_err(codec->dev,
784 "%s: Sample rate (%u) and format not supported\n",
e00447fa 785 __func__, params_rate(params));
03be88ee 786 /* See bellow for details how fix this. */
e00447fa
JS		 787 return -EINVAL;
788 }
03be88ee
JS		 789 if (bclk_score != 0) {
790 dev_warn(codec->dev, "Can not produce exact bitclock");
791 /* This is fine if using dsp format, but if using i2s
792 there may be trouble. To fix the issue edit the
793 aic31xx_divs table for your mclk and sample
794 rate. Details can be found from:
795 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
796 Section: 5.6 CLOCK Generation and PLL
797 */
798 }
799 i = match;
e00447fa
JS		 800
801 /* PLL configuration */
802 snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
7ed36e96 803 (aic31xx->p_div << 4) | 0x01);
e00447fa
JS		 804 snd_soc_write(codec, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
805
806 snd_soc_write(codec, AIC31XX_PLLDMSB,
807 aic31xx_divs[i].pll_d >> 8);
808 snd_soc_write(codec, AIC31XX_PLLDLSB,
809 aic31xx_divs[i].pll_d & 0xff);
810
811 /* DAC dividers configuration */
812 snd_soc_update_bits(codec, AIC31XX_NDAC, AIC31XX_PLL_MASK,
813 aic31xx_divs[i].ndac);
814 snd_soc_update_bits(codec, AIC31XX_MDAC, AIC31XX_PLL_MASK,
815 aic31xx_divs[i].mdac);
816
817 snd_soc_write(codec, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
818 snd_soc_write(codec, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
819
820 /* ADC dividers configuration. Write reset value 1 if not used. */
821 snd_soc_update_bits(codec, AIC31XX_NADC, AIC31XX_PLL_MASK,
822 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
823 snd_soc_update_bits(codec, AIC31XX_MADC, AIC31XX_PLL_MASK,
824 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
825
826 snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr);
827
828 /* Bit clock divider configuration. */
e00447fa
JS		 829 snd_soc_update_bits(codec, AIC31XX_BCLKN,
830 AIC31XX_PLL_MASK, bclk_n);
831
832 aic31xx->rate_div_line = i;
833
834 dev_dbg(codec->dev,
835 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
ca7840fb
AD		 836 aic31xx_divs[i].pll_j,
837 aic31xx_divs[i].pll_d,
838 aic31xx->p_div,
839 aic31xx_divs[i].dosr,
840 aic31xx_divs[i].ndac,
841 aic31xx_divs[i].mdac,
842 aic31xx_divs[i].aosr,
843 aic31xx_divs[i].nadc,
844 aic31xx_divs[i].madc,
845 bclk_n
846 );
e00447fa
JS		 847
848 return 0;
849}
850
851static int aic31xx_hw_params(struct snd_pcm_substream *substream,
852 struct snd_pcm_hw_params *params,
ab64246c 853 struct snd_soc_dai *dai)
e00447fa 854{
ab64246c 855 struct snd_soc_codec *codec = dai->codec;
e00447fa
JS		 856 u8 data = 0;
857
88be681b
MB		 858 dev_dbg(codec->dev, "## %s: width %d rate %d\n",
859 __func__, params_width(params),
e00447fa
JS		 860 params_rate(params));
861
862 switch (params_width(params)) {
863 case 16:
864 break;
865 case 20:
866 data = (AIC31XX_WORD_LEN_20BITS <<
867 AIC31XX_IFACE1_DATALEN_SHIFT);
868 break;
869 case 24:
870 data = (AIC31XX_WORD_LEN_24BITS <<
871 AIC31XX_IFACE1_DATALEN_SHIFT);
872 break;
873 case 32:
874 data = (AIC31XX_WORD_LEN_32BITS <<
875 AIC31XX_IFACE1_DATALEN_SHIFT);
876 break;
877 default:
88be681b
MB		 878 dev_err(codec->dev, "%s: Unsupported width %d\n",
879 __func__, params_width(params));
e00447fa
JS		 880 return -EINVAL;
881 }
882
883 snd_soc_update_bits(codec, AIC31XX_IFACE1,
884 AIC31XX_IFACE1_DATALEN_MASK,
885 data);
886
887 return aic31xx_setup_pll(codec, params);
888}
889
890static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute)
891{
892 struct snd_soc_codec *codec = codec_dai->codec;
893
894 if (mute) {
895 snd_soc_update_bits(codec, AIC31XX_DACMUTE,
896 AIC31XX_DACMUTE_MASK,
897 AIC31XX_DACMUTE_MASK);
898 } else {
899 snd_soc_update_bits(codec, AIC31XX_DACMUTE,
900 AIC31XX_DACMUTE_MASK, 0x0);
901 }
902
903 return 0;
904}
905
906static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
907 unsigned int fmt)
908{
909 struct snd_soc_codec *codec = codec_dai->codec;
910 u8 iface_reg1 = 0;
085f3ec6 911 u8 iface_reg2 = 0;
e00447fa
JS		 912 u8 dsp_a_val = 0;
913
914 dev_dbg(codec->dev, "## %s: fmt = 0x%x\n", __func__, fmt);
915
916 /* set master/slave audio interface */
917 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
918 case SND_SOC_DAIFMT_CBM_CFM:
919 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;
920 break;
921 default:
922 dev_alert(codec->dev, "Invalid DAI master/slave interface\n");
923 return -EINVAL;
924 }
925
926 /* interface format */
927 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
928 case SND_SOC_DAIFMT_I2S:
929 break;
930 case SND_SOC_DAIFMT_DSP_A:
09fc38c1 931 dsp_a_val = 0x1; /* fall through */
e00447fa
JS		 932 case SND_SOC_DAIFMT_DSP_B:
933 /* NOTE: BCLKINV bit value 1 equas NB and 0 equals IB */
934 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
935 case SND_SOC_DAIFMT_NB_NF:
085f3ec6 936 iface_reg2 |= AIC31XX_BCLKINV_MASK;
e00447fa
JS		 937 break;
938 case SND_SOC_DAIFMT_IB_NF:
939 break;
940 default:
941 return -EINVAL;
942 }
943 iface_reg1 |= (AIC31XX_DSP_MODE <<
944 AIC31XX_IFACE1_DATATYPE_SHIFT);
945 break;
946 case SND_SOC_DAIFMT_RIGHT_J:
947 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<
948 AIC31XX_IFACE1_DATATYPE_SHIFT);
949 break;
950 case SND_SOC_DAIFMT_LEFT_J:
951 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<
952 AIC31XX_IFACE1_DATATYPE_SHIFT);
953 break;
954 default:
955 dev_err(codec->dev, "Invalid DAI interface format\n");
956 return -EINVAL;
957 }
958
959 snd_soc_update_bits(codec, AIC31XX_IFACE1,
960 AIC31XX_IFACE1_DATATYPE_MASK |
961 AIC31XX_IFACE1_MASTER_MASK,
962 iface_reg1);
963 snd_soc_update_bits(codec, AIC31XX_DATA_OFFSET,
964 AIC31XX_DATA_OFFSET_MASK,
965 dsp_a_val);
966 snd_soc_update_bits(codec, AIC31XX_IFACE2,
967 AIC31XX_BCLKINV_MASK,
085f3ec6 968 iface_reg2);
e00447fa
JS		 969
970 return 0;
971}
972
973static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
974 int clk_id, unsigned int freq, int dir)
975{
976 struct snd_soc_codec *codec = codec_dai->codec;
977 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
978 int i;
979
980 dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
981 __func__, clk_id, freq, dir);
982
ca7840fb
AD		 983 for (i = 1; i < 8; i++)
984 if (freq / i <= 20000000)
985 break;
7ed36e96
JS		 986 if (freq/i > 20000000) {
987 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
988 __func__, freq);
989 return -EINVAL;
990 }
991 aic31xx->p_div = i;
992
ca7840fb
AD		 993 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++)
994 if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div)
995 break;
bbc686b3
JS		 996 if (i == ARRAY_SIZE(aic31xx_divs)) {
997 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
998 __func__, freq);
999 return -EINVAL;
e00447fa
JS		 1000 }
1001
1002 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */
1003 snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
1004 clk_id << AIC31XX_PLL_CLKIN_SHIFT);
1005
1006 aic31xx->sysclk = freq;
ca7840fb 1007
e00447fa
JS		 1008 return 0;
1009}
1010
1011static int aic31xx_regulator_event(struct notifier_block *nb,
1012 unsigned long event, void *data)
1013{
1014 struct aic31xx_disable_nb *disable_nb =
1015 container_of(nb, struct aic31xx_disable_nb, nb);
1016 struct aic31xx_priv *aic31xx = disable_nb->aic31xx;
1017
1018 if (event & REGULATOR_EVENT_DISABLE) {
1019 /*
1020 * Put codec to reset and as at least one of the
1021 * supplies was disabled.
1022 */
1023 if (gpio_is_valid(aic31xx->pdata.gpio_reset))
1024 gpio_set_value(aic31xx->pdata.gpio_reset, 0);
1025
1026 regcache_mark_dirty(aic31xx->regmap);
1027 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);
1028 }
1029
1030 return 0;
1031}
1032
1033static void aic31xx_clk_on(struct snd_soc_codec *codec)
1034{
1035 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1036 u8 mask = AIC31XX_PM_MASK;
1037 u8 on = AIC31XX_PM_MASK;
1038
1039 dev_dbg(codec->dev, "codec clock -> on (rate %d)\n",
1040 aic31xx_divs[aic31xx->rate_div_line].rate);
1041 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, on);
1042 mdelay(10);
1043 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, on);
1044 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, on);
1045 if (aic31xx_divs[aic31xx->rate_div_line].nadc)
1046 snd_soc_update_bits(codec, AIC31XX_NADC, mask, on);
1047 if (aic31xx_divs[aic31xx->rate_div_line].madc)
1048 snd_soc_update_bits(codec, AIC31XX_MADC, mask, on);
1049 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, on);
1050}
1051
1052static void aic31xx_clk_off(struct snd_soc_codec *codec)
1053{
e00447fa
JS		 1054 u8 mask = AIC31XX_PM_MASK;
1055 u8 off = 0;
1056
1057 dev_dbg(codec->dev, "codec clock -> off\n");
1058 snd_soc_update_bits(codec, AIC31XX_BCLKN, mask, off);
1059 snd_soc_update_bits(codec, AIC31XX_MADC, mask, off);
1060 snd_soc_update_bits(codec, AIC31XX_NADC, mask, off);
1061 snd_soc_update_bits(codec, AIC31XX_MDAC, mask, off);
1062 snd_soc_update_bits(codec, AIC31XX_NDAC, mask, off);
1063 snd_soc_update_bits(codec, AIC31XX_PLLPR, mask, off);
1064}
1065
1066static int aic31xx_power_on(struct snd_soc_codec *codec)
1067{
1068 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
ca7840fb 1069 int ret;
e00447fa
JS		 1070
1071 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
1072 aic31xx->supplies);
1073 if (ret)
1074 return ret;
1075
1076 if (gpio_is_valid(aic31xx->pdata.gpio_reset)) {
1077 gpio_set_value(aic31xx->pdata.gpio_reset, 1);
1078 udelay(100);
1079 }
1080 regcache_cache_only(aic31xx->regmap, false);
1081 ret = regcache_sync(aic31xx->regmap);
ca7840fb 1082 if (ret) {
e00447fa
JS		 1083 dev_err(codec->dev,
1084 "Failed to restore cache: %d\n", ret);
1085 regcache_cache_only(aic31xx->regmap, true);
1086 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1087 aic31xx->supplies);
1088 return ret;
1089 }
ca7840fb 1090
e00447fa
JS		 1091 return 0;
1092}
1093
c7734e8e 1094static void aic31xx_power_off(struct snd_soc_codec *codec)
e00447fa
JS		 1095{
1096 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
e00447fa
JS		 1097
1098 regcache_cache_only(aic31xx->regmap, true);
c7734e8e
AD		 1099 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1100 aic31xx->supplies);
e00447fa
JS		 1101}
1102
1103static int aic31xx_set_bias_level(struct snd_soc_codec *codec,
1104 enum snd_soc_bias_level level)
1105{
1106 dev_dbg(codec->dev, "## %s: %d -> %d\n", __func__,
378d1e43 1107 snd_soc_codec_get_bias_level(codec), level);
e00447fa
JS		 1108
1109 switch (level) {
1110 case SND_SOC_BIAS_ON:
1111 break;
1112 case SND_SOC_BIAS_PREPARE:
378d1e43 1113 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY)
e00447fa
JS		 1114 aic31xx_clk_on(codec);
1115 break;
1116 case SND_SOC_BIAS_STANDBY:
378d1e43 1117 switch (snd_soc_codec_get_bias_level(codec)) {
e00447fa
JS		 1118 case SND_SOC_BIAS_OFF:
1119 aic31xx_power_on(codec);
1120 break;
1121 case SND_SOC_BIAS_PREPARE:
1122 aic31xx_clk_off(codec);
1123 break;
1124 default:
1125 BUG();
1126 }
1127 break;
1128 case SND_SOC_BIAS_OFF:
378d1e43 1129 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_STANDBY)
fd218aa3 1130 aic31xx_power_off(codec);
e00447fa
JS		 1131 break;
1132 }
e00447fa
JS		 1133
1134 return 0;
1135}
1136
e00447fa
JS		 1137static int aic31xx_codec_probe(struct snd_soc_codec *codec)
1138{
e00447fa 1139 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
ca7840fb 1140 int i, ret;
e00447fa
JS		 1141
1142 dev_dbg(aic31xx->dev, "## %s\n", __func__);
1143
e00447fa
JS		 1144 aic31xx->codec = codec;
1145
e00447fa
JS		 1146 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {
1147 aic31xx->disable_nb[i].nb.notifier_call =
1148 aic31xx_regulator_event;
1149 aic31xx->disable_nb[i].aic31xx = aic31xx;
1150 ret = regulator_register_notifier(aic31xx->supplies[i].consumer,
1151 &aic31xx->disable_nb[i].nb);
1152 if (ret) {
1153 dev_err(codec->dev,
1154 "Failed to request regulator notifier: %d\n",
1155 ret);
1156 return ret;
1157 }
1158 }
1159
1160 regcache_cache_only(aic31xx->regmap, true);
1161 regcache_mark_dirty(aic31xx->regmap);
1162
1163 ret = aic31xx_add_controls(codec);
1164 if (ret)
1165 return ret;
1166
1167 ret = aic31xx_add_widgets(codec);
ca7840fb
AD		 1168 if (ret)
1169 return ret;
e00447fa 1170
ca7840fb 1171 return 0;
e00447fa
JS		 1172}
1173
1174static int aic31xx_codec_remove(struct snd_soc_codec *codec)
1175{
1176 struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
1177 int i;
e00447fa
JS		 1178
1179 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1180 regulator_unregister_notifier(aic31xx->supplies[i].consumer,
1181 &aic31xx->disable_nb[i].nb);
1182
1183 return 0;
1184}
1185
a180ba45 1186static const struct snd_soc_codec_driver soc_codec_driver_aic31xx = {
e00447fa
JS		 1187 .probe = aic31xx_codec_probe,
1188 .remove = aic31xx_codec_remove,
e00447fa 1189 .set_bias_level = aic31xx_set_bias_level,
a43a2629
LPC		 1190 .suspend_bias_off = true,
1191
1bb99f2a 1192 .component_driver = {
ef9656b6
NY		 1193 .controls = common31xx_snd_controls,
1194 .num_controls = ARRAY_SIZE(common31xx_snd_controls),
1195 .dapm_widgets = common31xx_dapm_widgets,
1196 .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets),
1197 .dapm_routes = common31xx_audio_map,
1198 .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map),
1bb99f2a 1199 },
e00447fa
JS		 1200};
1201
64793047 1202static const struct snd_soc_dai_ops aic31xx_dai_ops = {
e00447fa
JS		 1203 .hw_params = aic31xx_hw_params,
1204 .set_sysclk = aic31xx_set_dai_sysclk,
1205 .set_fmt = aic31xx_set_dai_fmt,
1206 .digital_mute = aic31xx_dac_mute,
1207};
1208
ef9656b6
NY		 1209static struct snd_soc_dai_driver dac31xx_dai_driver[] = {
1210 {
51827c41 1211 .name = "tlv320dac31xx-hifi",
ef9656b6
NY		 1212 .playback = {
1213 .stream_name = "Playback",
3520646d 1214 .channels_min = 2,
ef9656b6
NY		 1215 .channels_max = 2,
1216 .rates = AIC31XX_RATES,
1217 .formats = AIC31XX_FORMATS,
1218 },
1219 .ops = &aic31xx_dai_ops,
1220 .symmetric_rates = 1,
1221 }
1222};
1223
e00447fa
JS		 1224static struct snd_soc_dai_driver aic31xx_dai_driver[] = {
1225 {
1226 .name = "tlv320aic31xx-hifi",
1227 .playback = {
1228 .stream_name = "Playback",
3520646d 1229 .channels_min = 2,
e00447fa
JS		 1230 .channels_max = 2,
1231 .rates = AIC31XX_RATES,
1232 .formats = AIC31XX_FORMATS,
1233 },
1234 .capture = {
1235 .stream_name = "Capture",
3520646d 1236 .channels_min = 2,
e00447fa
JS		 1237 .channels_max = 2,
1238 .rates = AIC31XX_RATES,
1239 .formats = AIC31XX_FORMATS,
1240 },
1241 .ops = &aic31xx_dai_ops,
1242 .symmetric_rates = 1,
1243 }
1244};
1245
1246#if defined(CONFIG_OF)
1247static const struct of_device_id tlv320aic31xx_of_match[] = {
1248 { .compatible = "ti,tlv320aic310x" },
1249 { .compatible = "ti,tlv320aic311x" },
1250 { .compatible = "ti,tlv320aic3100" },
1251 { .compatible = "ti,tlv320aic3110" },
1252 { .compatible = "ti,tlv320aic3120" },
1253 { .compatible = "ti,tlv320aic3111" },
a4a1d79e 1254 { .compatible = "ti,tlv320dac3100" },
4e2cc814 1255 { .compatible = "ti,tlv320dac3101" },
e00447fa
JS		 1256 {},
1257};
1258MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
1259
1260static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
1261{
1262 struct device_node *np = aic31xx->dev->of_node;
1263 unsigned int value = MICBIAS_2_0V;
1264 int ret;
1265
1266 of_property_read_u32(np, "ai31xx-micbias-vg", &value);
1267 switch (value) {
1268 case MICBIAS_2_0V:
1269 case MICBIAS_2_5V:
1270 case MICBIAS_AVDDV:
1271 aic31xx->pdata.micbias_vg = value;
1272 break;
1273 default:
1274 dev_err(aic31xx->dev,
1275 "Bad ai31xx-micbias-vg value %d DT\n",
1276 value);
1277 aic31xx->pdata.micbias_vg = MICBIAS_2_0V;
1278 }
1279
a825f31f
AD		 1280 ret = of_get_named_gpio(np, "reset-gpios", 0);
1281 if (ret > 0) {
e00447fa 1282 aic31xx->pdata.gpio_reset = ret;
a825f31f
AD		 1283 } else {
1284 ret = of_get_named_gpio(np, "gpio-reset", 0);
1285 if (ret > 0) {
1286 dev_warn(aic31xx->dev, "Using deprecated property \"gpio-reset\", please update your DT");
1287 aic31xx->pdata.gpio_reset = ret;
1288 }
1289 }
e00447fa
JS		 1290}
1291#else /* CONFIG_OF */
1292static void aic31xx_pdata_from_of(struct aic31xx_priv *aic31xx)
1293{
1294}
1295#endif /* CONFIG_OF */
1296
09303601
AD		 1297#ifdef CONFIG_ACPI
1298static const struct acpi_device_id aic31xx_acpi_match[] = {
1299 { "10TI3100", 0 },
1300 { }
1301};
1302MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match);
1303#endif
1304
a72d2abb 1305static int aic31xx_device_init(struct aic31xx_priv *aic31xx)
e00447fa
JS		 1306{
1307 int ret, i;
1308
1309 dev_set_drvdata(aic31xx->dev, aic31xx);
1310
1311 if (dev_get_platdata(aic31xx->dev))
1312 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev),
1313 sizeof(aic31xx->pdata));
1314 else if (aic31xx->dev->of_node)
1315 aic31xx_pdata_from_of(aic31xx);
1316
1317 if (aic31xx->pdata.gpio_reset) {
1318 ret = devm_gpio_request_one(aic31xx->dev,
1319 aic31xx->pdata.gpio_reset,
1320 GPIOF_OUT_INIT_HIGH,
1321 "aic31xx-reset-pin");
1322 if (ret < 0) {
1323 dev_err(aic31xx->dev, "not able to acquire gpio\n");
a72d2abb 1324 return ret;
e00447fa
JS		 1325 }
1326 }
1327
1328 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1329 aic31xx->supplies[i].supply = aic31xx_supply_names[i];
1330
1331 ret = devm_regulator_bulk_get(aic31xx->dev,
1332 ARRAY_SIZE(aic31xx->supplies),
1333 aic31xx->supplies);
ca7840fb 1334 if (ret) {
e00447fa 1335 dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret);
ca7840fb
AD		 1336 return ret;
1337 }
e00447fa 1338
ca7840fb 1339 return 0;
e00447fa
JS		 1340}
1341
1342static int aic31xx_i2c_probe(struct i2c_client *i2c,
1343 const struct i2c_device_id *id)
1344{
1345 struct aic31xx_priv *aic31xx;
1346 int ret;
e00447fa
JS		 1347
1348 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,
1349 id->name, (int) id->driver_data);
1350
e00447fa 1351 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);
ca7840fb 1352 if (!aic31xx)
e00447fa
JS		 1353 return -ENOMEM;
1354
ca7840fb 1355 aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap);
e00447fa
JS		 1356 if (IS_ERR(aic31xx->regmap)) {
1357 ret = PTR_ERR(aic31xx->regmap);
1358 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1359 ret);
1360 return ret;
1361 }
1362 aic31xx->dev = &i2c->dev;
1363
1364 aic31xx->pdata.codec_type = id->driver_data;
1365
a72d2abb
PU		 1366 ret = aic31xx_device_init(aic31xx);
1367 if (ret)
1368 return ret;
e00447fa 1369
ef9656b6
NY		 1370 if (aic31xx->pdata.codec_type & DAC31XX_BIT)
1371 return snd_soc_register_codec(&i2c->dev,
1372 &soc_codec_driver_aic31xx,
1373 dac31xx_dai_driver,
1374 ARRAY_SIZE(dac31xx_dai_driver));
1375 else
1376 return snd_soc_register_codec(&i2c->dev,
1377 &soc_codec_driver_aic31xx,
1378 aic31xx_dai_driver,
1379 ARRAY_SIZE(aic31xx_dai_driver));
e00447fa
JS		 1380}
1381
1382static int aic31xx_i2c_remove(struct i2c_client *i2c)
1383{
dac7e404 1384 snd_soc_unregister_codec(&i2c->dev);
e00447fa
JS		 1385 return 0;
1386}
1387
1388static const struct i2c_device_id aic31xx_i2c_id[] = {
1389 { "tlv320aic310x", AIC3100 },
1390 { "tlv320aic311x", AIC3110 },
1391 { "tlv320aic3100", AIC3100 },
1392 { "tlv320aic3110", AIC3110 },
1393 { "tlv320aic3120", AIC3120 },
1394 { "tlv320aic3111", AIC3111 },
ef9656b6 1395 { "tlv320dac3100", DAC3100 },
4e2cc814 1396 { "tlv320dac3101", DAC3101 },
e00447fa
JS		 1397 { }
1398};
1399MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
1400
1401static struct i2c_driver aic31xx_i2c_driver = {
1402 .driver = {
1403 .name = "tlv320aic31xx-codec",
e00447fa 1404 .of_match_table = of_match_ptr(tlv320aic31xx_of_match),
f5cc1772 1405 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match),
e00447fa
JS		 1406 },
1407 .probe = aic31xx_i2c_probe,
dac7e404 1408 .remove = aic31xx_i2c_remove,
e00447fa
JS		 1409 .id_table = aic31xx_i2c_id,
1410};
e00447fa
JS		 1411module_i2c_driver(aic31xx_i2c_driver);
1412
b1c52b7e
AD		 1413MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>");
1414MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver");
1415MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)