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ASoC: sta32x: Add support for XTI clock
[linux-2.6-block.git] / sound / soc / codecs / sta32x.c
CommitLineData
c034abf6
JS		 1/*
2 * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system
3 *
4 * Copyright: 2011 Raumfeld GmbH
5 * Author: Johannes Stezenbach <js@sig21.net>
6 *
7 * based on code from:
8 * Wolfson Microelectronics PLC.
9 * Mark Brown <broonie@opensource.wolfsonmicro.com>
10 * Freescale Semiconductor, Inc.
11 * Timur Tabi <timur@freescale.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
20
21#include <linux/module.h>
22#include <linux/moduleparam.h>
23#include <linux/init.h>
fce9ec95 24#include <linux/clk.h>
c034abf6
JS		 25#include <linux/delay.h>
26#include <linux/pm.h>
27#include <linux/i2c.h>
f04b1e76
TN		 28#include <linux/of_device.h>
29#include <linux/of_gpio.h>
29fdf4fb 30#include <linux/regmap.h>
c034abf6 31#include <linux/regulator/consumer.h>
b66a2980 32#include <linux/gpio/consumer.h>
c034abf6 33#include <linux/slab.h>
3fb5eac5 34#include <linux/workqueue.h>
c034abf6
JS		 35#include <sound/core.h>
36#include <sound/pcm.h>
37#include <sound/pcm_params.h>
38#include <sound/soc.h>
39#include <sound/soc-dapm.h>
40#include <sound/initval.h>
41#include <sound/tlv.h>
42
e012ba24 43#include <sound/sta32x.h>
c034abf6
JS		 44#include "sta32x.h"
45
46#define STA32X_RATES (SNDRV_PCM_RATE_32000 | \
47 SNDRV_PCM_RATE_44100 | \
48 SNDRV_PCM_RATE_48000 | \
49 SNDRV_PCM_RATE_88200 | \
50 SNDRV_PCM_RATE_96000 | \
51 SNDRV_PCM_RATE_176400 | \
52 SNDRV_PCM_RATE_192000)
53
54#define STA32X_FORMATS \
55 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
56 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
57 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \
58 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \
59 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
60 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE)
61
62/* Power-up register defaults */
29fdf4fb
MB		 63static const struct reg_default sta32x_regs[] = {
64 { 0x0, 0x63 },
65 { 0x1, 0x80 },
66 { 0x2, 0xc2 },
67 { 0x3, 0x40 },
68 { 0x4, 0xc2 },
69 { 0x5, 0x5c },
70 { 0x6, 0x10 },
71 { 0x7, 0xff },
72 { 0x8, 0x60 },
73 { 0x9, 0x60 },
74 { 0xa, 0x60 },
75 { 0xb, 0x80 },
76 { 0xc, 0x00 },
77 { 0xd, 0x00 },
78 { 0xe, 0x00 },
79 { 0xf, 0x40 },
80 { 0x10, 0x80 },
81 { 0x11, 0x77 },
82 { 0x12, 0x6a },
83 { 0x13, 0x69 },
84 { 0x14, 0x6a },
85 { 0x15, 0x69 },
86 { 0x16, 0x00 },
87 { 0x17, 0x00 },
88 { 0x18, 0x00 },
89 { 0x19, 0x00 },
90 { 0x1a, 0x00 },
91 { 0x1b, 0x00 },
92 { 0x1c, 0x00 },
93 { 0x1d, 0x00 },
94 { 0x1e, 0x00 },
95 { 0x1f, 0x00 },
96 { 0x20, 0x00 },
97 { 0x21, 0x00 },
98 { 0x22, 0x00 },
99 { 0x23, 0x00 },
100 { 0x24, 0x00 },
101 { 0x25, 0x00 },
102 { 0x26, 0x00 },
103 { 0x27, 0x2d },
104 { 0x28, 0xc0 },
105 { 0x2b, 0x00 },
106 { 0x2c, 0x0c },
c034abf6
JS		 107};
108
a1be4cea 109static const struct regmap_range sta32x_write_regs_range[] = {
148388f3 110 regmap_reg_range(STA32X_CONFA, STA32X_FDRC2),
a1be4cea
TN		 111};
112
113static const struct regmap_range sta32x_read_regs_range[] = {
148388f3 114 regmap_reg_range(STA32X_CONFA, STA32X_FDRC2),
a1be4cea
TN		 115};
116
117static const struct regmap_range sta32x_volatile_regs_range[] = {
118 regmap_reg_range(STA32X_CFADDR2, STA32X_CFUD),
119};
120
121static const struct regmap_access_table sta32x_write_regs = {
122 .yes_ranges = sta32x_write_regs_range,
123 .n_yes_ranges = ARRAY_SIZE(sta32x_write_regs_range),
124};
125
126static const struct regmap_access_table sta32x_read_regs = {
127 .yes_ranges = sta32x_read_regs_range,
128 .n_yes_ranges = ARRAY_SIZE(sta32x_read_regs_range),
129};
130
131static const struct regmap_access_table sta32x_volatile_regs = {
132 .yes_ranges = sta32x_volatile_regs_range,
133 .n_yes_ranges = ARRAY_SIZE(sta32x_volatile_regs_range),
134};
135
c034abf6
JS		 136/* regulator power supply names */
137static const char *sta32x_supply_names[] = {
138 "Vdda", /* analog supply, 3.3VV */
139 "Vdd3", /* digital supply, 3.3V */
140 "Vcc" /* power amp spply, 10V - 36V */
141};
142
143/* codec private data */
144struct sta32x_priv {
29fdf4fb 145 struct regmap *regmap;
fce9ec95 146 struct clk *xti_clk;
c034abf6 147 struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)];
ee183590 148 struct snd_soc_component *component;
e012ba24 149 struct sta32x_platform_data *pdata;
c034abf6
JS		 150
151 unsigned int mclk;
152 unsigned int format;
54dc6cab
JS		 153
154 u32 coef_shadow[STA32X_COEF_COUNT];
3fb5eac5
JS		 155 struct delayed_work watchdog_work;
156 int shutdown;
b66a2980 157 struct gpio_desc *gpiod_nreset;
a1be4cea 158 struct mutex coeff_lock;
c034abf6
JS		 159};
160
161static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1);
162static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
163static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0);
164
165static const char *sta32x_drc_ac[] = {
166 "Anti-Clipping", "Dynamic Range Compression" };
167static const char *sta32x_auto_eq_mode[] = {
168 "User", "Preset", "Loudness" };
169static const char *sta32x_auto_gc_mode[] = {
170 "User", "AC no clipping", "AC limited clipping (10%)",
171 "DRC nighttime listening mode" };
172static const char *sta32x_auto_xo_mode[] = {
173 "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz",
174 "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" };
175static const char *sta32x_preset_eq_mode[] = {
176 "Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft",
177 "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1",
178 "Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2",
179 "Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7",
180 "Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12",
181 "Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" };
182static const char *sta32x_limiter_select[] = {
183 "Limiter Disabled", "Limiter #1", "Limiter #2" };
184static const char *sta32x_limiter_attack_rate[] = {
185 "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
186 "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
187 "0.0645", "0.0564", "0.0501", "0.0451" };
188static const char *sta32x_limiter_release_rate[] = {
189 "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
190 "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
191 "0.0134", "0.0117", "0.0110", "0.0104" };
88483f59 192static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_attack_tlv,
c034abf6
JS		 193 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
194 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
88483f59 195);
c034abf6 196
88483f59 197static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_release_tlv,
c034abf6
JS		 198 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
199 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
200 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
201 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
202 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
88483f59 203);
c034abf6 204
88483f59 205static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_attack_tlv,
c034abf6
JS		 206 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
207 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
208 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
88483f59 209);
c034abf6 210
88483f59 211static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_release_tlv,
c034abf6
JS		 212 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
213 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
214 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
215 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
216 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
88483f59 217);
c034abf6 218
025c3fa9
TI		 219static SOC_ENUM_SINGLE_DECL(sta32x_drc_ac_enum,
220 STA32X_CONFD, STA32X_CONFD_DRC_SHIFT,
221 sta32x_drc_ac);
222static SOC_ENUM_SINGLE_DECL(sta32x_auto_eq_enum,
223 STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT,
224 sta32x_auto_eq_mode);
225static SOC_ENUM_SINGLE_DECL(sta32x_auto_gc_enum,
226 STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT,
227 sta32x_auto_gc_mode);
228static SOC_ENUM_SINGLE_DECL(sta32x_auto_xo_enum,
229 STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT,
230 sta32x_auto_xo_mode);
231static SOC_ENUM_SINGLE_DECL(sta32x_preset_eq_enum,
232 STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT,
233 sta32x_preset_eq_mode);
234static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch1_enum,
235 STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT,
236 sta32x_limiter_select);
237static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch2_enum,
238 STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT,
239 sta32x_limiter_select);
240static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch3_enum,
241 STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT,
242 sta32x_limiter_select);
243static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_attack_rate_enum,
244 STA32X_L1AR, STA32X_LxA_SHIFT,
245 sta32x_limiter_attack_rate);
246static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_attack_rate_enum,
247 STA32X_L2AR, STA32X_LxA_SHIFT,
248 sta32x_limiter_attack_rate);
249static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_release_rate_enum,
250 STA32X_L1AR, STA32X_LxR_SHIFT,
251 sta32x_limiter_release_rate);
252static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_release_rate_enum,
253 STA32X_L2AR, STA32X_LxR_SHIFT,
254 sta32x_limiter_release_rate);
79688439
JS		 255
256/* byte array controls for setting biquad, mixer, scaling coefficients;
257 * for biquads all five coefficients need to be set in one go,
258 * mixer and pre/postscale coefs can be set individually;
259 * each coef is 24bit, the bytes are ordered in the same way
260 * as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0)
261 */
262
263static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol,
264 struct snd_ctl_elem_info *uinfo)
265{
266 int numcoef = kcontrol->private_value >> 16;
267 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
268 uinfo->count = 3 * numcoef;
269 return 0;
270}
271
272static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
273 struct snd_ctl_elem_value *ucontrol)
274{
ee183590
KM		 275 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
276 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
79688439
JS		 277 int numcoef = kcontrol->private_value >> 16;
278 int index = kcontrol->private_value & 0xffff;
a1be4cea
TN		 279 unsigned int cfud, val;
280 int i, ret = 0;
281
282 mutex_lock(&sta32x->coeff_lock);
79688439
JS		 283
284 /* preserve reserved bits in STA32X_CFUD */
a1be4cea
TN		 285 regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
286 cfud &= 0xf0;
287 /*
288 * chip documentation does not say if the bits are self clearing,
289 * so do it explicitly
290 */
291 regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
79688439 292
a1be4cea
TN		 293 regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
294 if (numcoef == 1) {
295 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x04);
296 } else if (numcoef == 5) {
297 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x08);
298 } else {
299 ret = -EINVAL;
300 goto exit_unlock;
301 }
79688439 302
a1be4cea
TN		 303 for (i = 0; i < 3 * numcoef; i++) {
304 regmap_read(sta32x->regmap, STA32X_B1CF1 + i, &val);
305 ucontrol->value.bytes.data[i] = val;
306 }
307
308exit_unlock:
309 mutex_unlock(&sta32x->coeff_lock);
310
311 return ret;
79688439
JS		 312}
313
314static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
315 struct snd_ctl_elem_value *ucontrol)
316{
ee183590
KM		 317 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
318 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
79688439
JS		 319 int numcoef = kcontrol->private_value >> 16;
320 int index = kcontrol->private_value & 0xffff;
321 unsigned int cfud;
322 int i;
323
324 /* preserve reserved bits in STA32X_CFUD */
a1be4cea
TN		 325 regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
326 cfud &= 0xf0;
327 /*
328 * chip documentation does not say if the bits are self clearing,
329 * so do it explicitly
330 */
331 regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
79688439 332
a1be4cea 333 regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
54dc6cab
JS		 334 for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++)
335 sta32x->coef_shadow[index + i] =
336 (ucontrol->value.bytes.data[3 * i] << 16)
337 | (ucontrol->value.bytes.data[3 * i + 1] << 8)
338 | (ucontrol->value.bytes.data[3 * i + 2]);
79688439 339 for (i = 0; i < 3 * numcoef; i++)
a1be4cea
TN		 340 regmap_write(sta32x->regmap, STA32X_B1CF1 + i,
341 ucontrol->value.bytes.data[i]);
79688439 342 if (numcoef == 1)
a1be4cea 343 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
79688439 344 else if (numcoef == 5)
a1be4cea 345 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x02);
79688439
JS		 346 else
347 return -EINVAL;
348
349 return 0;
350}
351
ee183590 352static int sta32x_sync_coef_shadow(struct snd_soc_component *component)
54dc6cab 353{
ee183590 354 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
54dc6cab
JS		 355 unsigned int cfud;
356 int i;
357
358 /* preserve reserved bits in STA32X_CFUD */
a1be4cea
TN		 359 regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
360 cfud &= 0xf0;
54dc6cab
JS		 361
362 for (i = 0; i < STA32X_COEF_COUNT; i++) {
a1be4cea
TN		 363 regmap_write(sta32x->regmap, STA32X_CFADDR2, i);
364 regmap_write(sta32x->regmap, STA32X_B1CF1,
365 (sta32x->coef_shadow[i] >> 16) & 0xff);
366 regmap_write(sta32x->regmap, STA32X_B1CF2,
367 (sta32x->coef_shadow[i] >> 8) & 0xff);
368 regmap_write(sta32x->regmap, STA32X_B1CF3,
369 (sta32x->coef_shadow[i]) & 0xff);
370 /*
371 * chip documentation does not say if the bits are
372 * self-clearing, so do it explicitly
373 */
374 regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
375 regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
54dc6cab
JS		 376 }
377 return 0;
378}
379
ee183590 380static int sta32x_cache_sync(struct snd_soc_component *component)
54dc6cab 381{
ee183590 382 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
54dc6cab
JS		 383 unsigned int mute;
384 int rc;
385
54dc6cab 386 /* mute during register sync */
a1be4cea
TN		 387 regmap_read(sta32x->regmap, STA32X_MMUTE, &mute);
388 regmap_write(sta32x->regmap, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE);
ee183590 389 sta32x_sync_coef_shadow(component);
29fdf4fb 390 rc = regcache_sync(sta32x->regmap);
a1be4cea 391 regmap_write(sta32x->regmap, STA32X_MMUTE, mute);
54dc6cab
JS		 392 return rc;
393}
394
3fb5eac5
JS		 395/* work around ESD issue where sta32x resets and loses all configuration */
396static void sta32x_watchdog(struct work_struct *work)
397{
398 struct sta32x_priv *sta32x = container_of(work, struct sta32x_priv,
399 watchdog_work.work);
ee183590 400 struct snd_soc_component *component = sta32x->component;
3fb5eac5
JS		 401 unsigned int confa, confa_cached;
402
403 /* check if sta32x has reset itself */
ee183590 404 confa_cached = snd_soc_component_read32(component, STA32X_CONFA);
29fdf4fb 405 regcache_cache_bypass(sta32x->regmap, true);
ee183590 406 confa = snd_soc_component_read32(component, STA32X_CONFA);
29fdf4fb 407 regcache_cache_bypass(sta32x->regmap, false);
3fb5eac5 408 if (confa != confa_cached) {
29fdf4fb 409 regcache_mark_dirty(sta32x->regmap);
ee183590 410 sta32x_cache_sync(component);
3fb5eac5
JS		 411 }
412
413 if (!sta32x->shutdown)
a14d9829
MB		 414 queue_delayed_work(system_power_efficient_wq,
415 &sta32x->watchdog_work,
416 round_jiffies_relative(HZ));
3fb5eac5
JS		 417}
418
419static void sta32x_watchdog_start(struct sta32x_priv *sta32x)
420{
421 if (sta32x->pdata->needs_esd_watchdog) {
422 sta32x->shutdown = 0;
a14d9829
MB		 423 queue_delayed_work(system_power_efficient_wq,
424 &sta32x->watchdog_work,
425 round_jiffies_relative(HZ));
3fb5eac5
JS		 426 }
427}
428
429static void sta32x_watchdog_stop(struct sta32x_priv *sta32x)
430{
431 if (sta32x->pdata->needs_esd_watchdog) {
432 sta32x->shutdown = 1;
433 cancel_delayed_work_sync(&sta32x->watchdog_work);
434 }
435}
436
79688439
JS		 437#define SINGLE_COEF(xname, index) \
438{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
439 .info = sta32x_coefficient_info, \
440 .get = sta32x_coefficient_get,\
441 .put = sta32x_coefficient_put, \
442 .private_value = index | (1 << 16) }
443
444#define BIQUAD_COEFS(xname, index) \
445{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
446 .info = sta32x_coefficient_info, \
447 .get = sta32x_coefficient_get,\
448 .put = sta32x_coefficient_put, \
449 .private_value = index | (5 << 16) }
450
c034abf6
JS		 451static const struct snd_kcontrol_new sta32x_snd_controls[] = {
452SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv),
453SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1),
454SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1),
455SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1),
456SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1),
457SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv),
458SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv),
459SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv),
460SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0),
461SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum),
462SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0),
463SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0),
464SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0),
465SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0),
466SOC_ENUM("Automode EQ", sta32x_auto_eq_enum),
467SOC_ENUM("Automode GC", sta32x_auto_gc_enum),
468SOC_ENUM("Automode XO", sta32x_auto_xo_enum),
469SOC_ENUM("Preset EQ", sta32x_preset_eq_enum),
470SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
471SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
472SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
473SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
474SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
475SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
476SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
477SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum),
478SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum),
479SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum),
480SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv),
481SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv),
482SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum),
483SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum),
484SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum),
b3619b28 485SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter2_release_rate_enum),
c034abf6
JS		 486
487/* depending on mode, the attack/release thresholds have
488 * two different enum definitions; provide both
489 */
490SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
491 16, 0, sta32x_limiter_ac_attack_tlv),
492SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
493 16, 0, sta32x_limiter_ac_attack_tlv),
494SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
495 16, 0, sta32x_limiter_ac_release_tlv),
496SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
497 16, 0, sta32x_limiter_ac_release_tlv),
498SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
499 16, 0, sta32x_limiter_drc_attack_tlv),
500SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
501 16, 0, sta32x_limiter_drc_attack_tlv),
502SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
503 16, 0, sta32x_limiter_drc_release_tlv),
504SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
505 16, 0, sta32x_limiter_drc_release_tlv),
79688439
JS		 506
507BIQUAD_COEFS("Ch1 - Biquad 1", 0),
508BIQUAD_COEFS("Ch1 - Biquad 2", 5),
509BIQUAD_COEFS("Ch1 - Biquad 3", 10),
510BIQUAD_COEFS("Ch1 - Biquad 4", 15),
511BIQUAD_COEFS("Ch2 - Biquad 1", 20),
512BIQUAD_COEFS("Ch2 - Biquad 2", 25),
513BIQUAD_COEFS("Ch2 - Biquad 3", 30),
514BIQUAD_COEFS("Ch2 - Biquad 4", 35),
515BIQUAD_COEFS("High-pass", 40),
516BIQUAD_COEFS("Low-pass", 45),
517SINGLE_COEF("Ch1 - Prescale", 50),
518SINGLE_COEF("Ch2 - Prescale", 51),
519SINGLE_COEF("Ch1 - Postscale", 52),
520SINGLE_COEF("Ch2 - Postscale", 53),
521SINGLE_COEF("Ch3 - Postscale", 54),
522SINGLE_COEF("Thermal warning - Postscale", 55),
523SINGLE_COEF("Ch1 - Mix 1", 56),
524SINGLE_COEF("Ch1 - Mix 2", 57),
525SINGLE_COEF("Ch2 - Mix 1", 58),
526SINGLE_COEF("Ch2 - Mix 2", 59),
527SINGLE_COEF("Ch3 - Mix 1", 60),
528SINGLE_COEF("Ch3 - Mix 2", 61),
c034abf6
JS		 529};
530
531static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = {
532SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
533SND_SOC_DAPM_OUTPUT("LEFT"),
534SND_SOC_DAPM_OUTPUT("RIGHT"),
535SND_SOC_DAPM_OUTPUT("SUB"),
536};
537
538static const struct snd_soc_dapm_route sta32x_dapm_routes[] = {
539 { "LEFT", NULL, "DAC" },
540 { "RIGHT", NULL, "DAC" },
541 { "SUB", NULL, "DAC" },
542};
543
544/* MCLK interpolation ratio per fs */
545static struct {
546 int fs;
547 int ir;
548} interpolation_ratios[] = {
549 { 32000, 0 },
550 { 44100, 0 },
551 { 48000, 0 },
552 { 88200, 1 },
553 { 96000, 1 },
554 { 176400, 2 },
555 { 192000, 2 },
556};
557
558/* MCLK to fs clock ratios */
1c34c876
TN		 559static int mcs_ratio_table[3][7] = {
560 { 768, 512, 384, 256, 128, 576, 0 },
561 { 384, 256, 192, 128, 64, 0 },
562 { 384, 256, 192, 128, 64, 0 },
c034abf6
JS		 563};
564
c034abf6
JS		 565/**
566 * sta32x_set_dai_sysclk - configure MCLK
567 * @codec_dai: the codec DAI
568 * @clk_id: the clock ID (ignored)
569 * @freq: the MCLK input frequency
570 * @dir: the clock direction (ignored)
571 *
572 * The value of MCLK is used to determine which sample rates are supported
573 * by the STA32X, based on the mclk_ratios table.
574 *
575 * This function must be called by the machine driver's 'startup' function,
576 * otherwise the list of supported sample rates will not be available in
577 * time for ALSA.
578 *
579 * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause
580 * theoretically possible sample rates to be enabled. Call it again with a
581 * proper value set one the external clock is set (most probably you would do
582 * that from a machine's driver 'hw_param' hook.
583 */
584static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
585 int clk_id, unsigned int freq, int dir)
586{
ee183590
KM		 587 struct snd_soc_component *component = codec_dai->component;
588 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
c034abf6 589
ee183590 590 dev_dbg(component->dev, "mclk=%u\n", freq);
c034abf6
JS		 591 sta32x->mclk = freq;
592
c034abf6
JS		 593 return 0;
594}
595
596/**
597 * sta32x_set_dai_fmt - configure the codec for the selected audio format
598 * @codec_dai: the codec DAI
599 * @fmt: a SND_SOC_DAIFMT_x value indicating the data format
600 *
601 * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
602 * codec accordingly.
603 */
604static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai,
605 unsigned int fmt)
606{
ee183590
KM		 607 struct snd_soc_component *component = codec_dai->component;
608 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
a1be4cea 609 u8 confb = 0;
c034abf6
JS		 610
611 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
612 case SND_SOC_DAIFMT_CBS_CFS:
613 break;
614 default:
615 return -EINVAL;
616 }
617
618 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
619 case SND_SOC_DAIFMT_I2S:
620 case SND_SOC_DAIFMT_RIGHT_J:
621 case SND_SOC_DAIFMT_LEFT_J:
622 sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
623 break;
624 default:
625 return -EINVAL;
626 }
627
628 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
629 case SND_SOC_DAIFMT_NB_NF:
630 confb |= STA32X_CONFB_C2IM;
631 break;
632 case SND_SOC_DAIFMT_NB_IF:
633 confb |= STA32X_CONFB_C1IM;
634 break;
635 default:
636 return -EINVAL;
637 }
638
a1be4cea
TN		 639 return regmap_update_bits(sta32x->regmap, STA32X_CONFB,
640 STA32X_CONFB_C1IM | STA32X_CONFB_C2IM, confb);
c034abf6
JS		 641}
642
643/**
644 * sta32x_hw_params - program the STA32X with the given hardware parameters.
645 * @substream: the audio stream
646 * @params: the hardware parameters to set
647 * @dai: the SOC DAI (ignored)
648 *
649 * This function programs the hardware with the values provided.
650 * Specifically, the sample rate and the data format.
651 */
652static int sta32x_hw_params(struct snd_pcm_substream *substream,
653 struct snd_pcm_hw_params *params,
654 struct snd_soc_dai *dai)
655{
ee183590
KM		 656 struct snd_soc_component *component = dai->component;
657 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
1c34c876 658 int i, mcs = -EINVAL, ir = -EINVAL;
a1be4cea 659 unsigned int confa, confb;
1c34c876
TN		 660 unsigned int rate, ratio;
661 int ret;
662
663 if (!sta32x->mclk) {
ee183590 664 dev_err(component->dev,
1c34c876
TN		 665 "sta32x->mclk is unset. Unable to determine ratio\n");
666 return -EIO;
667 }
c034abf6
JS		 668
669 rate = params_rate(params);
1c34c876 670 ratio = sta32x->mclk / rate;
ee183590 671 dev_dbg(component->dev, "rate: %u, ratio: %u\n", rate, ratio);
1c34c876
TN		 672
673 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
a595238b 674 if (interpolation_ratios[i].fs == rate) {
c034abf6 675 ir = interpolation_ratios[i].ir;
a595238b
AL		 676 break;
677 }
1c34c876
TN		 678 }
679
680 if (ir < 0) {
ee183590 681 dev_err(component->dev, "Unsupported samplerate: %u\n", rate);
c034abf6 682 return -EINVAL;
1c34c876
TN		 683 }
684
685 for (i = 0; i < 6; i++) {
686 if (mcs_ratio_table[ir][i] == ratio) {
687 mcs = i;
a595238b
AL		 688 break;
689 }
1c34c876
TN		 690 }
691
692 if (mcs < 0) {
ee183590 693 dev_err(component->dev, "Unresolvable ratio: %u\n", ratio);
c034abf6 694 return -EINVAL;
1c34c876 695 }
c034abf6 696
a1be4cea
TN		 697 confa = (ir << STA32X_CONFA_IR_SHIFT) |
698 (mcs << STA32X_CONFA_MCS_SHIFT);
699 confb = 0;
c034abf6 700
737e0f89
MB		 701 switch (params_width(params)) {
702 case 24:
ee183590 703 dev_dbg(component->dev, "24bit\n");
c034abf6 704 /* fall through */
737e0f89 705 case 32:
ee183590 706 dev_dbg(component->dev, "24bit or 32bit\n");
c034abf6
JS		 707 switch (sta32x->format) {
708 case SND_SOC_DAIFMT_I2S:
709 confb |= 0x0;
710 break;
711 case SND_SOC_DAIFMT_LEFT_J:
712 confb |= 0x1;
713 break;
714 case SND_SOC_DAIFMT_RIGHT_J:
715 confb |= 0x2;
716 break;
717 }
718
719 break;
737e0f89 720 case 20:
ee183590 721 dev_dbg(component->dev, "20bit\n");
c034abf6
JS		 722 switch (sta32x->format) {
723 case SND_SOC_DAIFMT_I2S:
724 confb |= 0x4;
725 break;
726 case SND_SOC_DAIFMT_LEFT_J:
727 confb |= 0x5;
728 break;
729 case SND_SOC_DAIFMT_RIGHT_J:
730 confb |= 0x6;
731 break;
732 }
733
734 break;
737e0f89 735 case 18:
ee183590 736 dev_dbg(component->dev, "18bit\n");
c034abf6
JS		 737 switch (sta32x->format) {
738 case SND_SOC_DAIFMT_I2S:
739 confb |= 0x8;
740 break;
741 case SND_SOC_DAIFMT_LEFT_J:
742 confb |= 0x9;
743 break;
744 case SND_SOC_DAIFMT_RIGHT_J:
745 confb |= 0xa;
746 break;
747 }
748
749 break;
737e0f89 750 case 16:
ee183590 751 dev_dbg(component->dev, "16bit\n");
c034abf6
JS		 752 switch (sta32x->format) {
753 case SND_SOC_DAIFMT_I2S:
754 confb |= 0x0;
755 break;
756 case SND_SOC_DAIFMT_LEFT_J:
757 confb |= 0xd;
758 break;
759 case SND_SOC_DAIFMT_RIGHT_J:
760 confb |= 0xe;
761 break;
762 }
763
764 break;
765 default:
766 return -EINVAL;
767 }
768
a1be4cea
TN		 769 ret = regmap_update_bits(sta32x->regmap, STA32X_CONFA,
770 STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK,
771 confa);
772 if (ret < 0)
773 return ret;
774
775 ret = regmap_update_bits(sta32x->regmap, STA32X_CONFB,
776 STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB,
777 confb);
778 if (ret < 0)
779 return ret;
780
781 return 0;
782}
b66a2980
TN		 783
784static int sta32x_startup_sequence(struct sta32x_priv *sta32x)
785{
786 if (sta32x->gpiod_nreset) {
787 gpiod_set_value(sta32x->gpiod_nreset, 0);
788 mdelay(1);
789 gpiod_set_value(sta32x->gpiod_nreset, 1);
790 mdelay(1);
791 }
792
c034abf6
JS		 793 return 0;
794}
795
796/**
797 * sta32x_set_bias_level - DAPM callback
ee183590 798 * @component: the component device
c034abf6
JS		 799 * @level: DAPM power level
800 *
ee183590
KM		 801 * This is called by ALSA to put the component into low power mode
802 * or to wake it up. If the component is powered off completely
c034abf6
JS		 803 * all registers must be restored after power on.
804 */
ee183590 805static int sta32x_set_bias_level(struct snd_soc_component *component,
c034abf6
JS		 806 enum snd_soc_bias_level level)
807{
808 int ret;
ee183590 809 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
c034abf6 810
ee183590 811 dev_dbg(component->dev, "level = %d\n", level);
c034abf6
JS		 812 switch (level) {
813 case SND_SOC_BIAS_ON:
814 break;
815
816 case SND_SOC_BIAS_PREPARE:
817 /* Full power on */
a1be4cea 818 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
c034abf6
JS		 819 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
820 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
821 break;
822
823 case SND_SOC_BIAS_STANDBY:
ee183590 824 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
c034abf6
JS		 825 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
826 sta32x->supplies);
827 if (ret != 0) {
ee183590 828 dev_err(component->dev,
c034abf6
JS		 829 "Failed to enable supplies: %d\n", ret);
830 return ret;
831 }
832
b66a2980 833 sta32x_startup_sequence(sta32x);
ee183590 834 sta32x_cache_sync(component);
3fb5eac5 835 sta32x_watchdog_start(sta32x);
c034abf6
JS		 836 }
837
a1be4cea
TN		 838 /* Power down */
839 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
840 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
841 0);
c034abf6
JS		 842
843 break;
844
845 case SND_SOC_BIAS_OFF:
846 /* The chip runs through the power down sequence for us. */
a1be4cea
TN		 847 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
848 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 0);
c034abf6 849 msleep(300);
3fb5eac5 850 sta32x_watchdog_stop(sta32x);
b66a2980 851
c5efe232 852 gpiod_set_value(sta32x->gpiod_nreset, 0);
b66a2980 853
c034abf6
JS		 854 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies),
855 sta32x->supplies);
856 break;
857 }
c034abf6
JS		 858 return 0;
859}
860
85e7652d 861static const struct snd_soc_dai_ops sta32x_dai_ops = {
c034abf6
JS		 862 .hw_params = sta32x_hw_params,
863 .set_sysclk = sta32x_set_dai_sysclk,
864 .set_fmt = sta32x_set_dai_fmt,
865};
866
867static struct snd_soc_dai_driver sta32x_dai = {
3c9390ad 868 .name = "sta32x-hifi",
c034abf6
JS		 869 .playback = {
870 .stream_name = "Playback",
871 .channels_min = 2,
872 .channels_max = 2,
873 .rates = STA32X_RATES,
874 .formats = STA32X_FORMATS,
875 },
876 .ops = &sta32x_dai_ops,
877};
878
ee183590 879static int sta32x_probe(struct snd_soc_component *component)
c034abf6 880{
ee183590 881 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
a1be4cea 882 struct sta32x_platform_data *pdata = sta32x->pdata;
e012ba24 883 int i, ret = 0, thermal = 0;
fce9ec95
DM		 884
885 sta32x->component = component;
886
887 if (sta32x->xti_clk) {
888 ret = clk_prepare_enable(sta32x->xti_clk);
889 if (ret != 0) {
890 dev_err(component->dev,
891 "Failed to enable clock: %d\n", ret);
892 return ret;
893 }
894 }
895
c034abf6
JS		 896 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
897 sta32x->supplies);
898 if (ret != 0) {
ee183590 899 dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
aff041af 900 return ret;
c034abf6
JS		 901 }
902
b66a2980
TN		 903 ret = sta32x_startup_sequence(sta32x);
904 if (ret < 0) {
ee183590 905 dev_err(component->dev, "Failed to startup device\n");
b66a2980
TN		 906 return ret;
907 }
f04b1e76
TN		 908
909 /* CONFA */
a1be4cea 910 if (!pdata->thermal_warning_recovery)
e012ba24 911 thermal |= STA32X_CONFA_TWAB;
a1be4cea 912 if (!pdata->thermal_warning_adjustment)
e012ba24 913 thermal |= STA32X_CONFA_TWRB;
f04b1e76
TN		 914 if (!pdata->fault_detect_recovery)
915 thermal |= STA32X_CONFA_FDRB;
a1be4cea 916 regmap_update_bits(sta32x->regmap, STA32X_CONFA,
f04b1e76
TN		 917 STA32X_CONFA_TWAB | STA32X_CONFA_TWRB |
918 STA32X_CONFA_FDRB,
a1be4cea 919 thermal);
c034abf6 920
f04b1e76
TN		 921 /* CONFC */
922 regmap_update_bits(sta32x->regmap, STA32X_CONFC,
923 STA32X_CONFC_CSZ_MASK,
924 pdata->drop_compensation_ns
925 << STA32X_CONFC_CSZ_SHIFT);
926
927 /* CONFE */
928 regmap_update_bits(sta32x->regmap, STA32X_CONFE,
929 STA32X_CONFE_MPCV,
930 pdata->max_power_use_mpcc ?
931 STA32X_CONFE_MPCV : 0);
932 regmap_update_bits(sta32x->regmap, STA32X_CONFE,
933 STA32X_CONFE_MPC,
934 pdata->max_power_correction ?
935 STA32X_CONFE_MPC : 0);
936 regmap_update_bits(sta32x->regmap, STA32X_CONFE,
937 STA32X_CONFE_AME,
938 pdata->am_reduction_mode ?
939 STA32X_CONFE_AME : 0);
940 regmap_update_bits(sta32x->regmap, STA32X_CONFE,
941 STA32X_CONFE_PWMS,
942 pdata->odd_pwm_speed_mode ?
943 STA32X_CONFE_PWMS : 0);
944
945 /* CONFF */
946 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
947 STA32X_CONFF_IDE,
948 pdata->invalid_input_detect_mute ?
949 STA32X_CONFF_IDE : 0);
950
e012ba24 951 /* select output configuration */
a1be4cea
TN		 952 regmap_update_bits(sta32x->regmap, STA32X_CONFF,
953 STA32X_CONFF_OCFG_MASK,
954 pdata->output_conf
955 << STA32X_CONFF_OCFG_SHIFT);
c034abf6 956
e012ba24 957 /* channel to output mapping */
a1be4cea
TN		 958 regmap_update_bits(sta32x->regmap, STA32X_C1CFG,
959 STA32X_CxCFG_OM_MASK,
960 pdata->ch1_output_mapping
961 << STA32X_CxCFG_OM_SHIFT);
962 regmap_update_bits(sta32x->regmap, STA32X_C2CFG,
963 STA32X_CxCFG_OM_MASK,
964 pdata->ch2_output_mapping
965 << STA32X_CxCFG_OM_SHIFT);
966 regmap_update_bits(sta32x->regmap, STA32X_C3CFG,
967 STA32X_CxCFG_OM_MASK,
968 pdata->ch3_output_mapping
969 << STA32X_CxCFG_OM_SHIFT);
c034abf6 970
54dc6cab
JS		 971 /* initialize coefficient shadow RAM with reset values */
972 for (i = 4; i <= 49; i += 5)
973 sta32x->coef_shadow[i] = 0x400000;
974 for (i = 50; i <= 54; i++)
975 sta32x->coef_shadow[i] = 0x7fffff;
976 sta32x->coef_shadow[55] = 0x5a9df7;
977 sta32x->coef_shadow[56] = 0x7fffff;
978 sta32x->coef_shadow[59] = 0x7fffff;
979 sta32x->coef_shadow[60] = 0x400000;
980 sta32x->coef_shadow[61] = 0x400000;
981
3fb5eac5
JS		 982 if (sta32x->pdata->needs_esd_watchdog)
983 INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog);
984
ee183590 985 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
c034abf6
JS		 986 /* Bias level configuration will have done an extra enable */
987 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
988
989 return 0;
c034abf6
JS		 990}
991
ee183590 992static void sta32x_remove(struct snd_soc_component *component)
c034abf6 993{
ee183590 994 struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
c034abf6 995
3fb5eac5 996 sta32x_watchdog_stop(sta32x);
c034abf6 997 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
fce9ec95
DM		 998
999 if (sta32x->xti_clk)
1000 clk_disable_unprepare(sta32x->xti_clk);
c034abf6
JS		 1001}
1002
ee183590
KM		 1003static const struct snd_soc_component_driver sta32x_component = {
1004 .probe = sta32x_probe,
1005 .remove = sta32x_remove,
1006 .set_bias_level = sta32x_set_bias_level,
1007 .controls = sta32x_snd_controls,
1008 .num_controls = ARRAY_SIZE(sta32x_snd_controls),
1009 .dapm_widgets = sta32x_dapm_widgets,
1010 .num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets),
1011 .dapm_routes = sta32x_dapm_routes,
1012 .num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes),
1013 .suspend_bias_off = 1,
1014 .idle_bias_on = 1,
1015 .use_pmdown_time = 1,
1016 .endianness = 1,
1017 .non_legacy_dai_naming = 1,
c034abf6
JS		 1018};
1019
29fdf4fb
MB		 1020static const struct regmap_config sta32x_regmap = {
1021 .reg_bits = 8,
1022 .val_bits = 8,
1023 .max_register = STA32X_FDRC2,
1024 .reg_defaults = sta32x_regs,
1025 .num_reg_defaults = ARRAY_SIZE(sta32x_regs),
1026 .cache_type = REGCACHE_RBTREE,
a1be4cea
TN		 1027 .wr_table = &sta32x_write_regs,
1028 .rd_table = &sta32x_read_regs,
1029 .volatile_table = &sta32x_volatile_regs,
1030};
f04b1e76
TN		 1031
1032#ifdef CONFIG_OF
1033static const struct of_device_id st32x_dt_ids[] = {
1034 { .compatible = "st,sta32x", },
1035 { }
29fdf4fb 1036};
f04b1e76
TN		 1037MODULE_DEVICE_TABLE(of, st32x_dt_ids);
1038
1039static int sta32x_probe_dt(struct device *dev, struct sta32x_priv *sta32x)
1040{
1041 struct device_node *np = dev->of_node;
1042 struct sta32x_platform_data *pdata;
1043 u16 tmp;
1044
1045 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1046 if (!pdata)
1047 return -ENOMEM;
1048
1049 of_property_read_u8(np, "st,output-conf",
1050 &pdata->output_conf);
1051 of_property_read_u8(np, "st,ch1-output-mapping",
1052 &pdata->ch1_output_mapping);
1053 of_property_read_u8(np, "st,ch2-output-mapping",
1054 &pdata->ch2_output_mapping);
1055 of_property_read_u8(np, "st,ch3-output-mapping",
1056 &pdata->ch3_output_mapping);
1057
466dee75
DM		 1058 if (of_get_property(np, "st,fault-detect-recovery", NULL))
1059 pdata->fault_detect_recovery = 1;
f04b1e76
TN		 1060 if (of_get_property(np, "st,thermal-warning-recovery", NULL))
1061 pdata->thermal_warning_recovery = 1;
1062 if (of_get_property(np, "st,thermal-warning-adjustment", NULL))
1063 pdata->thermal_warning_adjustment = 1;
1064 if (of_get_property(np, "st,needs_esd_watchdog", NULL))
1065 pdata->needs_esd_watchdog = 1;
1066
1067 tmp = 140;
1068 of_property_read_u16(np, "st,drop-compensation-ns", &tmp);
1069 pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20;
1070
1071 /* CONFE */
1072 if (of_get_property(np, "st,max-power-use-mpcc", NULL))
1073 pdata->max_power_use_mpcc = 1;
1074
1075 if (of_get_property(np, "st,max-power-correction", NULL))
1076 pdata->max_power_correction = 1;
1077
1078 if (of_get_property(np, "st,am-reduction-mode", NULL))
1079 pdata->am_reduction_mode = 1;
1080
1081 if (of_get_property(np, "st,odd-pwm-speed-mode", NULL))
1082 pdata->odd_pwm_speed_mode = 1;
1083
1084 /* CONFF */
1085 if (of_get_property(np, "st,invalid-input-detect-mute", NULL))
1086 pdata->invalid_input_detect_mute = 1;
1087
1088 sta32x->pdata = pdata;
1089
1090 return 0;
1091}
1092#endif
29fdf4fb 1093
7a79e94e
BP		 1094static int sta32x_i2c_probe(struct i2c_client *i2c,
1095 const struct i2c_device_id *id)
c034abf6 1096{
a1be4cea 1097 struct device *dev = &i2c->dev;
c034abf6 1098 struct sta32x_priv *sta32x;
aff041af 1099 int ret, i;
c034abf6 1100
d999c021
AL		 1101 sta32x = devm_kzalloc(&i2c->dev, sizeof(struct sta32x_priv),
1102 GFP_KERNEL);
c034abf6
JS		 1103 if (!sta32x)
1104 return -ENOMEM;
1105
a1be4cea
TN		 1106 mutex_init(&sta32x->coeff_lock);
1107 sta32x->pdata = dev_get_platdata(dev);
b66a2980 1108
f04b1e76
TN		 1109#ifdef CONFIG_OF
1110 if (dev->of_node) {
1111 ret = sta32x_probe_dt(dev, sta32x);
1112 if (ret < 0)
1113 return ret;
1114 }
1115#endif
1116
fce9ec95
DM		 1117 /* Clock */
1118 sta32x->xti_clk = devm_clk_get(dev, "xti");
1119 if (IS_ERR(sta32x->xti_clk)) {
1120 ret = PTR_ERR(sta32x->xti_clk);
1121
1122 if (ret == -EPROBE_DEFER)
1123 return ret;
1124
1125 sta32x->xti_clk = NULL;
1126 }
1127
b66a2980 1128 /* GPIOs */
1137e580
UKK		 1129 sta32x->gpiod_nreset = devm_gpiod_get_optional(dev, "reset",
1130 GPIOD_OUT_LOW);
1131 if (IS_ERR(sta32x->gpiod_nreset))
1132 return PTR_ERR(sta32x->gpiod_nreset);
b66a2980 1133
aff041af
MB		 1134 /* regulators */
1135 for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++)
1136 sta32x->supplies[i].supply = sta32x_supply_names[i];
1137
1138 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(sta32x->supplies),
1139 sta32x->supplies);
1140 if (ret != 0) {
1141 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1142 return ret;
1143 }
1144
29fdf4fb
MB		 1145 sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap);
1146 if (IS_ERR(sta32x->regmap)) {
1147 ret = PTR_ERR(sta32x->regmap);
a1be4cea 1148 dev_err(dev, "Failed to init regmap: %d\n", ret);
29fdf4fb
MB		 1149 return ret;
1150 }
1151
c034abf6
JS		 1152 i2c_set_clientdata(i2c, sta32x);
1153
ee183590
KM		 1154 ret = devm_snd_soc_register_component(dev, &sta32x_component,
1155 &sta32x_dai, 1);
a1be4cea 1156 if (ret < 0)
ee183590 1157 dev_err(dev, "Failed to register component (%d)\n", ret);
c034abf6 1158
d999c021 1159 return ret;
c034abf6
JS		 1160}
1161
c034abf6
JS		 1162static const struct i2c_device_id sta32x_i2c_id[] = {
1163 { "sta326", 0 },
1164 { "sta328", 0 },
1165 { "sta329", 0 },
1166 { }
1167};
1168MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id);
1169
1170static struct i2c_driver sta32x_i2c_driver = {
1171 .driver = {
1172 .name = "sta32x",
f04b1e76 1173 .of_match_table = of_match_ptr(st32x_dt_ids),
c034abf6
JS		 1174 },
1175 .probe = sta32x_i2c_probe,
c034abf6
JS		 1176 .id_table = sta32x_i2c_id,
1177};
1178
0ead1136 1179module_i2c_driver(sta32x_i2c_driver);
c034abf6
JS		 1180
1181MODULE_DESCRIPTION("ASoC STA32X driver");
1182MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>");
1183MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)