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3c1d663b FE |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // | |
3 | // sgtl5000.c -- SGTL5000 ALSA SoC Audio driver | |
4 | // | |
5 | // Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. | |
9b34e6cc ZZ |
6 | |
7 | #include <linux/module.h> | |
8 | #include <linux/moduleparam.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/pm.h> | |
13 | #include <linux/i2c.h> | |
14 | #include <linux/clk.h> | |
bd0593f5 | 15 | #include <linux/log2.h> |
e5d80e82 | 16 | #include <linux/regmap.h> |
9b34e6cc ZZ |
17 | #include <linux/regulator/driver.h> |
18 | #include <linux/regulator/machine.h> | |
19 | #include <linux/regulator/consumer.h> | |
58e49424 | 20 | #include <linux/of_device.h> |
9b34e6cc ZZ |
21 | #include <sound/core.h> |
22 | #include <sound/tlv.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/soc-dapm.h> | |
27 | #include <sound/initval.h> | |
9b34e6cc ZZ |
28 | |
29 | #include "sgtl5000.h" | |
30 | ||
31 | #define SGTL5000_DAP_REG_OFFSET 0x0100 | |
32 | #define SGTL5000_MAX_REG_OFFSET 0x013A | |
33 | ||
b1f373a1 OS |
34 | /* Delay for the VAG ramp up */ |
35 | #define SGTL5000_VAG_POWERUP_DELAY 500 /* ms */ | |
36 | /* Delay for the VAG ramp down */ | |
37 | #define SGTL5000_VAG_POWERDOWN_DELAY 500 /* ms */ | |
38 | ||
39 | #define SGTL5000_OUTPUTS_MUTE (SGTL5000_HP_MUTE | SGTL5000_LINE_OUT_MUTE) | |
40 | ||
151798f8 | 41 | /* default value of sgtl5000 registers */ |
e5d80e82 | 42 | static const struct reg_default sgtl5000_reg_defaults[] = { |
29aa37cd | 43 | { SGTL5000_CHIP_DIG_POWER, 0x0000 }, |
e5d80e82 | 44 | { SGTL5000_CHIP_I2S_CTRL, 0x0010 }, |
016fcab8 | 45 | { SGTL5000_CHIP_SSS_CTRL, 0x0010 }, |
29aa37cd | 46 | { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c }, |
e5d80e82 FE |
47 | { SGTL5000_CHIP_DAC_VOL, 0x3c3c }, |
48 | { SGTL5000_CHIP_PAD_STRENGTH, 0x015f }, | |
29aa37cd | 49 | { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 }, |
e5d80e82 FE |
50 | { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 }, |
51 | { SGTL5000_CHIP_ANA_CTRL, 0x0111 }, | |
29aa37cd FE |
52 | { SGTL5000_CHIP_REF_CTRL, 0x0000 }, |
53 | { SGTL5000_CHIP_MIC_CTRL, 0x0000 }, | |
54 | { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 }, | |
e5d80e82 | 55 | { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 }, |
e5d80e82 | 56 | { SGTL5000_CHIP_PLL_CTRL, 0x5000 }, |
29aa37cd FE |
57 | { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 }, |
58 | { SGTL5000_CHIP_ANA_STATUS, 0x0000 }, | |
59 | { SGTL5000_CHIP_SHORT_CTRL, 0x0000 }, | |
60 | { SGTL5000_CHIP_ANA_TEST2, 0x0000 }, | |
61 | { SGTL5000_DAP_CTRL, 0x0000 }, | |
62 | { SGTL5000_DAP_PEQ, 0x0000 }, | |
e5d80e82 FE |
63 | { SGTL5000_DAP_BASS_ENHANCE, 0x0040 }, |
64 | { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f }, | |
29aa37cd | 65 | { SGTL5000_DAP_AUDIO_EQ, 0x0000 }, |
e5d80e82 FE |
66 | { SGTL5000_DAP_SURROUND, 0x0040 }, |
67 | { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f }, | |
68 | { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f }, | |
69 | { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f }, | |
70 | { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f }, | |
71 | { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f }, | |
72 | { SGTL5000_DAP_MAIN_CHAN, 0x8000 }, | |
29aa37cd | 73 | { SGTL5000_DAP_MIX_CHAN, 0x0000 }, |
f86f58e3 | 74 | { SGTL5000_DAP_AVC_CTRL, 0x5100 }, |
e5d80e82 FE |
75 | { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 }, |
76 | { SGTL5000_DAP_AVC_ATTACK, 0x0028 }, | |
77 | { SGTL5000_DAP_AVC_DECAY, 0x0050 }, | |
9b34e6cc ZZ |
78 | }; |
79 | ||
a7295267 RL |
80 | /* AVC: Threshold dB -> register: pre-calculated values */ |
81 | static const u16 avc_thr_db2reg[97] = { | |
82 | 0x5168, 0x488E, 0x40AA, 0x39A1, 0x335D, 0x2DC7, 0x28CC, 0x245D, 0x2068, | |
83 | 0x1CE2, 0x19BE, 0x16F1, 0x1472, 0x1239, 0x103E, 0x0E7A, 0x0CE6, 0x0B7F, | |
84 | 0x0A3F, 0x0922, 0x0824, 0x0741, 0x0677, 0x05C3, 0x0522, 0x0493, 0x0414, | |
85 | 0x03A2, 0x033D, 0x02E3, 0x0293, 0x024B, 0x020B, 0x01D2, 0x019F, 0x0172, | |
86 | 0x014A, 0x0126, 0x0106, 0x00E9, 0x00D0, 0x00B9, 0x00A5, 0x0093, 0x0083, | |
87 | 0x0075, 0x0068, 0x005D, 0x0052, 0x0049, 0x0041, 0x003A, 0x0034, 0x002E, | |
88 | 0x0029, 0x0025, 0x0021, 0x001D, 0x001A, 0x0017, 0x0014, 0x0012, 0x0010, | |
89 | 0x000E, 0x000D, 0x000B, 0x000A, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005, | |
90 | 0x0005, 0x0004, 0x0004, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002, 0x0002, | |
91 | 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000, | |
92 | 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000}; | |
93 | ||
9b34e6cc ZZ |
94 | /* regulator supplies for sgtl5000, VDDD is an optional external supply */ |
95 | enum sgtl5000_regulator_supplies { | |
96 | VDDA, | |
97 | VDDIO, | |
98 | VDDD, | |
99 | SGTL5000_SUPPLY_NUM | |
100 | }; | |
101 | ||
102 | /* vddd is optional supply */ | |
103 | static const char *supply_names[SGTL5000_SUPPLY_NUM] = { | |
104 | "VDDA", | |
105 | "VDDIO", | |
106 | "VDDD" | |
107 | }; | |
108 | ||
9b34e6cc | 109 | #define LDO_VOLTAGE 1200000 |
3d632cc8 | 110 | #define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50) |
9b34e6cc | 111 | |
bd0593f5 JMH |
112 | enum sgtl5000_micbias_resistor { |
113 | SGTL5000_MICBIAS_OFF = 0, | |
114 | SGTL5000_MICBIAS_2K = 2, | |
115 | SGTL5000_MICBIAS_4K = 4, | |
116 | SGTL5000_MICBIAS_8K = 8, | |
117 | }; | |
118 | ||
570c70a6 FE |
119 | enum { |
120 | I2S_LRCLK_STRENGTH_DISABLE, | |
121 | I2S_LRCLK_STRENGTH_LOW, | |
122 | I2S_LRCLK_STRENGTH_MEDIUM, | |
123 | I2S_LRCLK_STRENGTH_HIGH, | |
124 | }; | |
125 | ||
5dc4ca29 AW |
126 | enum { |
127 | I2S_SCLK_STRENGTH_DISABLE, | |
128 | I2S_SCLK_STRENGTH_LOW, | |
129 | I2S_SCLK_STRENGTH_MEDIUM, | |
130 | I2S_SCLK_STRENGTH_HIGH, | |
131 | }; | |
132 | ||
b1f373a1 OS |
133 | enum { |
134 | HP_POWER_EVENT, | |
135 | DAC_POWER_EVENT, | |
136 | ADC_POWER_EVENT, | |
137 | LAST_POWER_EVENT = ADC_POWER_EVENT | |
138 | }; | |
139 | ||
9b34e6cc ZZ |
140 | /* sgtl5000 private structure in codec */ |
141 | struct sgtl5000_priv { | |
142 | int sysclk; /* sysclk rate */ | |
143 | int master; /* i2s master or not */ | |
144 | int fmt; /* i2s data format */ | |
145 | struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM]; | |
940adb28 | 146 | int num_supplies; |
e5d80e82 | 147 | struct regmap *regmap; |
9e13f345 | 148 | struct clk *mclk; |
252e91ff | 149 | int revision; |
bd0593f5 | 150 | u8 micbias_resistor; |
87357797 | 151 | u8 micbias_voltage; |
570c70a6 | 152 | u8 lrclk_strength; |
5dc4ca29 | 153 | u8 sclk_strength; |
b1f373a1 | 154 | u16 mute_state[LAST_POWER_EVENT + 1]; |
9b34e6cc ZZ |
155 | }; |
156 | ||
b1f373a1 OS |
157 | static inline int hp_sel_input(struct snd_soc_component *component) |
158 | { | |
981abdfe | 159 | return (snd_soc_component_read(component, SGTL5000_CHIP_ANA_CTRL) & |
b1f373a1 OS |
160 | SGTL5000_HP_SEL_MASK) >> SGTL5000_HP_SEL_SHIFT; |
161 | } | |
162 | ||
163 | static inline u16 mute_output(struct snd_soc_component *component, | |
164 | u16 mute_mask) | |
165 | { | |
981abdfe | 166 | u16 mute_reg = snd_soc_component_read(component, |
b1f373a1 OS |
167 | SGTL5000_CHIP_ANA_CTRL); |
168 | ||
169 | snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL, | |
170 | mute_mask, mute_mask); | |
171 | return mute_reg; | |
172 | } | |
173 | ||
174 | static inline void restore_output(struct snd_soc_component *component, | |
175 | u16 mute_mask, u16 mute_reg) | |
176 | { | |
177 | snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL, | |
178 | mute_mask, mute_reg); | |
179 | } | |
180 | ||
181 | static void vag_power_on(struct snd_soc_component *component, u32 source) | |
182 | { | |
981abdfe | 183 | if (snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER) & |
b1f373a1 OS |
184 | SGTL5000_VAG_POWERUP) |
185 | return; | |
186 | ||
187 | snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, | |
188 | SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP); | |
189 | ||
190 | /* When VAG powering on to get local loop from Line-In, the sleep | |
191 | * is required to avoid loud pop. | |
192 | */ | |
193 | if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN && | |
194 | source == HP_POWER_EVENT) | |
195 | msleep(SGTL5000_VAG_POWERUP_DELAY); | |
196 | } | |
197 | ||
198 | static int vag_power_consumers(struct snd_soc_component *component, | |
199 | u16 ana_pwr_reg, u32 source) | |
200 | { | |
201 | int consumers = 0; | |
202 | ||
203 | /* count dac/adc consumers unconditional */ | |
204 | if (ana_pwr_reg & SGTL5000_DAC_POWERUP) | |
205 | consumers++; | |
206 | if (ana_pwr_reg & SGTL5000_ADC_POWERUP) | |
207 | consumers++; | |
208 | ||
209 | /* | |
210 | * If the event comes from HP and Line-In is selected, | |
211 | * current action is 'DAC to be powered down'. | |
212 | * As HP_POWERUP is not set when HP muxed to line-in, | |
213 | * we need to keep VAG power ON. | |
214 | */ | |
215 | if (source == HP_POWER_EVENT) { | |
216 | if (hp_sel_input(component) == SGTL5000_HP_SEL_LINE_IN) | |
217 | consumers++; | |
218 | } else { | |
219 | if (ana_pwr_reg & SGTL5000_HP_POWERUP) | |
220 | consumers++; | |
221 | } | |
222 | ||
223 | return consumers; | |
224 | } | |
225 | ||
226 | static void vag_power_off(struct snd_soc_component *component, u32 source) | |
227 | { | |
981abdfe | 228 | u16 ana_pwr = snd_soc_component_read(component, |
b1f373a1 OS |
229 | SGTL5000_CHIP_ANA_POWER); |
230 | ||
231 | if (!(ana_pwr & SGTL5000_VAG_POWERUP)) | |
232 | return; | |
233 | ||
234 | /* | |
235 | * This function calls when any of VAG power consumers is disappearing. | |
236 | * Thus, if there is more than one consumer at the moment, as minimum | |
237 | * one consumer will definitely stay after the end of the current | |
238 | * event. | |
239 | * Don't clear VAG_POWERUP if 2 or more consumers of VAG present: | |
240 | * - LINE_IN (for HP events) / HP (for DAC/ADC events) | |
241 | * - DAC | |
242 | * - ADC | |
243 | * (the current consumer is disappearing right now) | |
244 | */ | |
245 | if (vag_power_consumers(component, ana_pwr, source) >= 2) | |
246 | return; | |
247 | ||
248 | snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, | |
249 | SGTL5000_VAG_POWERUP, 0); | |
250 | /* In power down case, we need wait 400-1000 ms | |
251 | * when VAG fully ramped down. | |
252 | * As longer we wait, as smaller pop we've got. | |
253 | */ | |
254 | msleep(SGTL5000_VAG_POWERDOWN_DELAY); | |
255 | } | |
256 | ||
9b34e6cc ZZ |
257 | /* |
258 | * mic_bias power on/off share the same register bits with | |
259 | * output impedance of mic bias, when power on mic bias, we | |
260 | * need reclaim it to impedance value. | |
261 | * 0x0 = Powered off | |
262 | * 0x1 = 2Kohm | |
263 | * 0x2 = 4Kohm | |
264 | * 0x3 = 8Kohm | |
265 | */ | |
266 | static int mic_bias_event(struct snd_soc_dapm_widget *w, | |
267 | struct snd_kcontrol *kcontrol, int event) | |
268 | { | |
2f8b3188 KM |
269 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
270 | struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); | |
bd0593f5 | 271 | |
9b34e6cc ZZ |
272 | switch (event) { |
273 | case SND_SOC_DAPM_POST_PMU: | |
bd0593f5 | 274 | /* change mic bias resistor */ |
2f8b3188 | 275 | snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL, |
bd0593f5 JMH |
276 | SGTL5000_BIAS_R_MASK, |
277 | sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); | |
9b34e6cc ZZ |
278 | break; |
279 | ||
280 | case SND_SOC_DAPM_PRE_PMD: | |
2f8b3188 | 281 | snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL, |
dc56c5a8 | 282 | SGTL5000_BIAS_R_MASK, 0); |
9b34e6cc ZZ |
283 | break; |
284 | } | |
285 | return 0; | |
286 | } | |
287 | ||
b1f373a1 OS |
288 | static int vag_and_mute_control(struct snd_soc_component *component, |
289 | int event, int event_source) | |
9b34e6cc | 290 | { |
b1f373a1 OS |
291 | static const u16 mute_mask[] = { |
292 | /* | |
293 | * Mask for HP_POWER_EVENT. | |
294 | * Muxing Headphones have to be wrapped with mute/unmute | |
295 | * headphones only. | |
296 | */ | |
297 | SGTL5000_HP_MUTE, | |
298 | /* | |
299 | * Masks for DAC_POWER_EVENT/ADC_POWER_EVENT. | |
300 | * Muxing DAC or ADC block have to wrapped with mute/unmute | |
301 | * both headphones and line-out. | |
302 | */ | |
303 | SGTL5000_OUTPUTS_MUTE, | |
304 | SGTL5000_OUTPUTS_MUTE | |
305 | }; | |
306 | ||
307 | struct sgtl5000_priv *sgtl5000 = | |
308 | snd_soc_component_get_drvdata(component); | |
f091f3f0 | 309 | |
9b34e6cc | 310 | switch (event) { |
b1f373a1 OS |
311 | case SND_SOC_DAPM_PRE_PMU: |
312 | sgtl5000->mute_state[event_source] = | |
313 | mute_output(component, mute_mask[event_source]); | |
314 | break; | |
dd4d2d6d | 315 | case SND_SOC_DAPM_POST_PMU: |
b1f373a1 OS |
316 | vag_power_on(component, event_source); |
317 | restore_output(component, mute_mask[event_source], | |
318 | sgtl5000->mute_state[event_source]); | |
9b34e6cc | 319 | break; |
dd4d2d6d | 320 | case SND_SOC_DAPM_PRE_PMD: |
b1f373a1 OS |
321 | sgtl5000->mute_state[event_source] = |
322 | mute_output(component, mute_mask[event_source]); | |
323 | vag_power_off(component, event_source); | |
324 | break; | |
325 | case SND_SOC_DAPM_POST_PMD: | |
326 | restore_output(component, mute_mask[event_source], | |
327 | sgtl5000->mute_state[event_source]); | |
9b34e6cc ZZ |
328 | break; |
329 | default: | |
330 | break; | |
331 | } | |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
b1f373a1 OS |
336 | /* |
337 | * Mute Headphone when power it up/down. | |
338 | * Control VAG power on HP power path. | |
339 | */ | |
340 | static int headphone_pga_event(struct snd_soc_dapm_widget *w, | |
341 | struct snd_kcontrol *kcontrol, int event) | |
342 | { | |
343 | struct snd_soc_component *component = | |
344 | snd_soc_dapm_to_component(w->dapm); | |
345 | ||
346 | return vag_and_mute_control(component, event, HP_POWER_EVENT); | |
347 | } | |
348 | ||
349 | /* As manual describes, ADC/DAC powering up/down requires | |
350 | * to mute outputs to avoid pops. | |
351 | * Control VAG power on ADC/DAC power path. | |
352 | */ | |
353 | static int adc_updown_depop(struct snd_soc_dapm_widget *w, | |
354 | struct snd_kcontrol *kcontrol, int event) | |
355 | { | |
356 | struct snd_soc_component *component = | |
357 | snd_soc_dapm_to_component(w->dapm); | |
358 | ||
359 | return vag_and_mute_control(component, event, ADC_POWER_EVENT); | |
360 | } | |
361 | ||
362 | static int dac_updown_depop(struct snd_soc_dapm_widget *w, | |
363 | struct snd_kcontrol *kcontrol, int event) | |
364 | { | |
365 | struct snd_soc_component *component = | |
366 | snd_soc_dapm_to_component(w->dapm); | |
367 | ||
368 | return vag_and_mute_control(component, event, DAC_POWER_EVENT); | |
369 | } | |
370 | ||
9b34e6cc ZZ |
371 | /* input sources for ADC */ |
372 | static const char *adc_mux_text[] = { | |
373 | "MIC_IN", "LINE_IN" | |
374 | }; | |
375 | ||
c8ed6504 TI |
376 | static SOC_ENUM_SINGLE_DECL(adc_enum, |
377 | SGTL5000_CHIP_ANA_CTRL, 2, | |
378 | adc_mux_text); | |
9b34e6cc ZZ |
379 | |
380 | static const struct snd_kcontrol_new adc_mux = | |
381 | SOC_DAPM_ENUM("Capture Mux", adc_enum); | |
382 | ||
7f7d5239 MO |
383 | /* input sources for headphone */ |
384 | static const char *hp_mux_text[] = { | |
385 | "DAC", "LINE_IN" | |
386 | }; | |
387 | ||
388 | static SOC_ENUM_SINGLE_DECL(hp_enum, | |
389 | SGTL5000_CHIP_ANA_CTRL, 6, | |
390 | hp_mux_text); | |
391 | ||
392 | static const struct snd_kcontrol_new hp_mux = | |
393 | SOC_DAPM_ENUM("Headphone Mux", hp_enum); | |
394 | ||
9b34e6cc ZZ |
395 | /* input sources for DAC */ |
396 | static const char *dac_mux_text[] = { | |
7f7d5239 | 397 | "ADC", "I2S", "Rsvrd", "DAP" |
9b34e6cc ZZ |
398 | }; |
399 | ||
c8ed6504 | 400 | static SOC_ENUM_SINGLE_DECL(dac_enum, |
7f7d5239 | 401 | SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAC_SEL_SHIFT, |
c8ed6504 | 402 | dac_mux_text); |
9b34e6cc ZZ |
403 | |
404 | static const struct snd_kcontrol_new dac_mux = | |
7f7d5239 MO |
405 | SOC_DAPM_ENUM("Digital Input Mux", dac_enum); |
406 | ||
407 | /* input sources for DAP */ | |
408 | static const char *dap_mux_text[] = { | |
409 | "ADC", "I2S" | |
410 | }; | |
411 | ||
412 | static SOC_ENUM_SINGLE_DECL(dap_enum, | |
413 | SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_SEL_SHIFT, | |
414 | dap_mux_text); | |
415 | ||
416 | static const struct snd_kcontrol_new dap_mux = | |
417 | SOC_DAPM_ENUM("DAP Mux", dap_enum); | |
418 | ||
419 | /* input sources for DAP mix */ | |
420 | static const char *dapmix_mux_text[] = { | |
421 | "ADC", "I2S" | |
422 | }; | |
423 | ||
424 | static SOC_ENUM_SINGLE_DECL(dapmix_enum, | |
425 | SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_MIX_SEL_SHIFT, | |
426 | dapmix_mux_text); | |
427 | ||
428 | static const struct snd_kcontrol_new dapmix_mux = | |
429 | SOC_DAPM_ENUM("DAP MIX Mux", dapmix_enum); | |
430 | ||
9b34e6cc ZZ |
431 | |
432 | static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = { | |
433 | SND_SOC_DAPM_INPUT("LINE_IN"), | |
434 | SND_SOC_DAPM_INPUT("MIC_IN"), | |
435 | ||
436 | SND_SOC_DAPM_OUTPUT("HP_OUT"), | |
437 | SND_SOC_DAPM_OUTPUT("LINE_OUT"), | |
438 | ||
8fc8ec92 MB |
439 | SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0, |
440 | mic_bias_event, | |
441 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
9b34e6cc | 442 | |
b1f373a1 OS |
443 | SND_SOC_DAPM_PGA_E("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0, |
444 | headphone_pga_event, | |
445 | SND_SOC_DAPM_PRE_POST_PMU | | |
446 | SND_SOC_DAPM_PRE_POST_PMD), | |
f0cdcf3a | 447 | SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0), |
9b34e6cc ZZ |
448 | |
449 | SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux), | |
7f7d5239 MO |
450 | SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &hp_mux), |
451 | SND_SOC_DAPM_MUX("Digital Input Mux", SND_SOC_NOPM, 0, 0, &dac_mux), | |
452 | SND_SOC_DAPM_MUX("DAP Mux", SGTL5000_DAP_CTRL, 0, 0, &dap_mux), | |
453 | SND_SOC_DAPM_MUX("DAP MIX Mux", SGTL5000_DAP_CTRL, 4, 0, &dapmix_mux), | |
454 | SND_SOC_DAPM_MIXER("DAP", SGTL5000_CHIP_DIG_POWER, 4, 0, NULL, 0), | |
455 | ||
9b34e6cc ZZ |
456 | |
457 | /* aif for i2s input */ | |
458 | SND_SOC_DAPM_AIF_IN("AIFIN", "Playback", | |
459 | 0, SGTL5000_CHIP_DIG_POWER, | |
460 | 0, 0), | |
461 | ||
462 | /* aif for i2s output */ | |
463 | SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture", | |
464 | 0, SGTL5000_CHIP_DIG_POWER, | |
465 | 1, 0), | |
466 | ||
b1f373a1 OS |
467 | SND_SOC_DAPM_ADC_E("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0, |
468 | adc_updown_depop, SND_SOC_DAPM_PRE_POST_PMU | | |
469 | SND_SOC_DAPM_PRE_POST_PMD), | |
470 | SND_SOC_DAPM_DAC_E("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0, | |
471 | dac_updown_depop, SND_SOC_DAPM_PRE_POST_PMU | | |
472 | SND_SOC_DAPM_PRE_POST_PMD), | |
9b34e6cc ZZ |
473 | }; |
474 | ||
475 | /* routes for sgtl5000 */ | |
89989637 | 476 | static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = { |
9b34e6cc ZZ |
477 | {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */ |
478 | {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */ | |
479 | ||
480 | {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */ | |
481 | {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */ | |
482 | ||
7f7d5239 MO |
483 | {"DAP Mux", "ADC", "ADC"}, /* adc --> DAP mux */ |
484 | {"DAP Mux", NULL, "AIFIN"}, /* i2s --> DAP mux */ | |
485 | {"DAP", NULL, "DAP Mux"}, /* DAP mux --> dap */ | |
486 | ||
487 | {"DAP MIX Mux", "ADC", "ADC"}, /* adc --> DAP MIX mux */ | |
488 | {"DAP MIX Mux", NULL, "AIFIN"}, /* i2s --> DAP MIX mux */ | |
489 | {"DAP", NULL, "DAP MIX Mux"}, /* DAP MIX mux --> dap */ | |
490 | ||
491 | {"Digital Input Mux", "ADC", "ADC"}, /* adc --> audio mux */ | |
492 | {"Digital Input Mux", NULL, "AIFIN"}, /* i2s --> audio mux */ | |
493 | {"Digital Input Mux", NULL, "DAP"}, /* dap --> audio mux */ | |
494 | {"DAC", NULL, "Digital Input Mux"}, /* audio mux --> dac */ | |
495 | ||
9b34e6cc ZZ |
496 | {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */ |
497 | {"LO", NULL, "DAC"}, /* dac --> line_out */ | |
498 | ||
499 | {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */ | |
500 | {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */ | |
501 | ||
502 | {"LINE_OUT", NULL, "LO"}, | |
503 | {"HP_OUT", NULL, "HP"}, | |
504 | }; | |
505 | ||
506 | /* custom function to fetch info of PCM playback volume */ | |
507 | static int dac_info_volsw(struct snd_kcontrol *kcontrol, | |
508 | struct snd_ctl_elem_info *uinfo) | |
509 | { | |
510 | uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; | |
511 | uinfo->count = 2; | |
512 | uinfo->value.integer.min = 0; | |
513 | uinfo->value.integer.max = 0xfc - 0x3c; | |
514 | return 0; | |
515 | } | |
516 | ||
517 | /* | |
518 | * custom function to get of PCM playback volume | |
519 | * | |
520 | * dac volume register | |
521 | * 15-------------8-7--------------0 | |
522 | * | R channel vol | L channel vol | | |
523 | * ------------------------------- | |
524 | * | |
525 | * PCM volume with 0.5017 dB steps from 0 to -90 dB | |
526 | * | |
527 | * register values map to dB | |
528 | * 0x3B and less = Reserved | |
529 | * 0x3C = 0 dB | |
530 | * 0x3D = -0.5 dB | |
531 | * 0xF0 = -90 dB | |
532 | * 0xFC and greater = Muted | |
533 | * | |
534 | * register value map to userspace value | |
535 | * | |
536 | * register value 0x3c(0dB) 0xf0(-90dB)0xfc | |
537 | * ------------------------------ | |
538 | * userspace value 0xc0 0 | |
539 | */ | |
540 | static int dac_get_volsw(struct snd_kcontrol *kcontrol, | |
541 | struct snd_ctl_elem_value *ucontrol) | |
542 | { | |
2f8b3188 | 543 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
9b34e6cc ZZ |
544 | int reg; |
545 | int l; | |
546 | int r; | |
547 | ||
981abdfe | 548 | reg = snd_soc_component_read(component, SGTL5000_CHIP_DAC_VOL); |
9b34e6cc ZZ |
549 | |
550 | /* get left channel volume */ | |
551 | l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; | |
552 | ||
553 | /* get right channel volume */ | |
554 | r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT; | |
555 | ||
556 | /* make sure value fall in (0x3c,0xfc) */ | |
557 | l = clamp(l, 0x3c, 0xfc); | |
558 | r = clamp(r, 0x3c, 0xfc); | |
559 | ||
560 | /* invert it and map to userspace value */ | |
561 | l = 0xfc - l; | |
562 | r = 0xfc - r; | |
563 | ||
564 | ucontrol->value.integer.value[0] = l; | |
565 | ucontrol->value.integer.value[1] = r; | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | /* | |
571 | * custom function to put of PCM playback volume | |
572 | * | |
573 | * dac volume register | |
574 | * 15-------------8-7--------------0 | |
575 | * | R channel vol | L channel vol | | |
576 | * ------------------------------- | |
577 | * | |
578 | * PCM volume with 0.5017 dB steps from 0 to -90 dB | |
579 | * | |
580 | * register values map to dB | |
581 | * 0x3B and less = Reserved | |
582 | * 0x3C = 0 dB | |
583 | * 0x3D = -0.5 dB | |
584 | * 0xF0 = -90 dB | |
585 | * 0xFC and greater = Muted | |
586 | * | |
587 | * userspace value map to register value | |
588 | * | |
589 | * userspace value 0xc0 0 | |
590 | * ------------------------------ | |
591 | * register value 0x3c(0dB) 0xf0(-90dB)0xfc | |
592 | */ | |
593 | static int dac_put_volsw(struct snd_kcontrol *kcontrol, | |
594 | struct snd_ctl_elem_value *ucontrol) | |
595 | { | |
2f8b3188 | 596 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
9b34e6cc ZZ |
597 | int reg; |
598 | int l; | |
599 | int r; | |
600 | ||
601 | l = ucontrol->value.integer.value[0]; | |
602 | r = ucontrol->value.integer.value[1]; | |
603 | ||
604 | /* make sure userspace volume fall in (0, 0xfc-0x3c) */ | |
605 | l = clamp(l, 0, 0xfc - 0x3c); | |
606 | r = clamp(r, 0, 0xfc - 0x3c); | |
607 | ||
608 | /* invert it, get the value can be set to register */ | |
609 | l = 0xfc - l; | |
610 | r = 0xfc - r; | |
611 | ||
612 | /* shift to get the register value */ | |
613 | reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT | | |
614 | r << SGTL5000_DAC_VOL_RIGHT_SHIFT; | |
615 | ||
2f8b3188 | 616 | snd_soc_component_write(component, SGTL5000_CHIP_DAC_VOL, reg); |
9b34e6cc ZZ |
617 | |
618 | return 0; | |
619 | } | |
620 | ||
a7295267 RL |
621 | /* |
622 | * custom function to get AVC threshold | |
623 | * | |
624 | * The threshold dB is calculated by rearranging the calculation from the | |
625 | * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==> | |
626 | * dB = ( fls(register_value) - 14.347 ) * 6.02 | |
627 | * | |
51e78694 | 628 | * As this calculation is expensive and the threshold dB values may not exceed |
a7295267 RL |
629 | * 0 to 96 we use pre-calculated values. |
630 | */ | |
631 | static int avc_get_threshold(struct snd_kcontrol *kcontrol, | |
632 | struct snd_ctl_elem_value *ucontrol) | |
633 | { | |
2f8b3188 | 634 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
a7295267 | 635 | int db, i; |
981abdfe | 636 | u16 reg = snd_soc_component_read(component, SGTL5000_DAP_AVC_THRESHOLD); |
a7295267 RL |
637 | |
638 | /* register value 0 => -96dB */ | |
639 | if (!reg) { | |
640 | ucontrol->value.integer.value[0] = 96; | |
641 | ucontrol->value.integer.value[1] = 96; | |
642 | return 0; | |
643 | } | |
644 | ||
645 | /* get dB from register value (rounded down) */ | |
646 | for (i = 0; avc_thr_db2reg[i] > reg; i++) | |
647 | ; | |
648 | db = i; | |
649 | ||
650 | ucontrol->value.integer.value[0] = db; | |
651 | ucontrol->value.integer.value[1] = db; | |
652 | ||
653 | return 0; | |
654 | } | |
655 | ||
656 | /* | |
657 | * custom function to put AVC threshold | |
658 | * | |
659 | * The register value is calculated by following formula: | |
660 | * register_value = 10^(dB/20) * 0.636 * 2^15 | |
51e78694 | 661 | * As this calculation is expensive and the threshold dB values may not exceed |
a7295267 RL |
662 | * 0 to 96 we use pre-calculated values. |
663 | */ | |
664 | static int avc_put_threshold(struct snd_kcontrol *kcontrol, | |
665 | struct snd_ctl_elem_value *ucontrol) | |
666 | { | |
2f8b3188 | 667 | struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); |
a7295267 RL |
668 | int db; |
669 | u16 reg; | |
670 | ||
671 | db = (int)ucontrol->value.integer.value[0]; | |
672 | if (db < 0 || db > 96) | |
673 | return -EINVAL; | |
674 | reg = avc_thr_db2reg[db]; | |
2f8b3188 | 675 | snd_soc_component_write(component, SGTL5000_DAP_AVC_THRESHOLD, reg); |
a7295267 RL |
676 | |
677 | return 0; | |
678 | } | |
679 | ||
9b34e6cc ZZ |
680 | static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0); |
681 | ||
682 | /* tlv for mic gain, 0db 20db 30db 40db */ | |
53eb1ca3 | 683 | static const DECLARE_TLV_DB_RANGE(mic_gain_tlv, |
9b34e6cc | 684 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), |
53eb1ca3 LPC |
685 | 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0) |
686 | ); | |
9b34e6cc | 687 | |
7f7d5239 MO |
688 | /* tlv for DAP channels, 0% - 100% - 200% */ |
689 | static const DECLARE_TLV_DB_SCALE(dap_volume, 0, 1, 0); | |
690 | ||
92a2742f MO |
691 | /* tlv for bass bands, -11.75db to 12.0db, step .25db */ |
692 | static const DECLARE_TLV_DB_SCALE(bass_band, -1175, 25, 0); | |
693 | ||
9b34e6cc ZZ |
694 | /* tlv for hp volume, -51.5db to 12.0db, step .5db */ |
695 | static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0); | |
696 | ||
0593d461 KK |
697 | /* tlv for lineout volume, 31 steps of .5db each */ |
698 | static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0); | |
699 | ||
a7295267 RL |
700 | /* tlv for dap avc max gain, 0db, 6db, 12db */ |
701 | static const DECLARE_TLV_DB_SCALE(avc_max_gain, 0, 600, 0); | |
702 | ||
703 | /* tlv for dap avc threshold, */ | |
704 | static const DECLARE_TLV_DB_MINMAX(avc_threshold, 0, 9600); | |
705 | ||
9b34e6cc ZZ |
706 | static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { |
707 | /* SOC_DOUBLE_S8_TLV with invert */ | |
708 | { | |
709 | .iface = SNDRV_CTL_ELEM_IFACE_MIXER, | |
710 | .name = "PCM Playback Volume", | |
711 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | | |
712 | SNDRV_CTL_ELEM_ACCESS_READWRITE, | |
713 | .info = dac_info_volsw, | |
714 | .get = dac_get_volsw, | |
715 | .put = dac_put_volsw, | |
716 | }, | |
717 | ||
718 | SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0), | |
719 | SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)", | |
720 | SGTL5000_CHIP_ANA_ADC_CTRL, | |
65f2b226 | 721 | 8, 1, 0, capture_6db_attenuate), |
9b34e6cc | 722 | SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), |
694b1455 | 723 | SOC_SINGLE("Capture Switch", SGTL5000_CHIP_ANA_CTRL, 0, 1, 1), |
9b34e6cc ZZ |
724 | |
725 | SOC_DOUBLE_TLV("Headphone Playback Volume", | |
726 | SGTL5000_CHIP_ANA_HP_CTRL, | |
727 | 0, 8, | |
728 | 0x7f, 1, | |
729 | headphone_volume), | |
904a9873 RL |
730 | SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL, |
731 | 4, 1, 1), | |
9b34e6cc ZZ |
732 | SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL, |
733 | 5, 1, 0), | |
734 | ||
735 | SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL, | |
b50684da | 736 | 0, 3, 0, mic_gain_tlv), |
0593d461 KK |
737 | |
738 | SOC_DOUBLE_TLV("Lineout Playback Volume", | |
739 | SGTL5000_CHIP_LINE_OUT_VOL, | |
740 | SGTL5000_LINE_OUT_VOL_LEFT_SHIFT, | |
741 | SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT, | |
742 | 0x1f, 1, | |
743 | lineout_volume), | |
904a9873 | 744 | SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1), |
a7295267 | 745 | |
7f7d5239 MO |
746 | SOC_SINGLE_TLV("DAP Main channel", SGTL5000_DAP_MAIN_CHAN, |
747 | 0, 0xffff, 0, dap_volume), | |
748 | ||
749 | SOC_SINGLE_TLV("DAP Mix channel", SGTL5000_DAP_MIX_CHAN, | |
750 | 0, 0xffff, 0, dap_volume), | |
a7295267 RL |
751 | /* Automatic Volume Control (DAP AVC) */ |
752 | SOC_SINGLE("AVC Switch", SGTL5000_DAP_AVC_CTRL, 0, 1, 0), | |
753 | SOC_SINGLE("AVC Hard Limiter Switch", SGTL5000_DAP_AVC_CTRL, 5, 1, 0), | |
754 | SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0, | |
755 | avc_max_gain), | |
756 | SOC_SINGLE("AVC Integrator Response", SGTL5000_DAP_AVC_CTRL, 8, 3, 0), | |
757 | SOC_SINGLE_EXT_TLV("AVC Threshold Volume", SGTL5000_DAP_AVC_THRESHOLD, | |
758 | 0, 96, 0, avc_get_threshold, avc_put_threshold, | |
759 | avc_threshold), | |
92a2742f MO |
760 | |
761 | SOC_SINGLE_TLV("BASS 0", SGTL5000_DAP_EQ_BASS_BAND0, | |
762 | 0, 0x5F, 0, bass_band), | |
763 | ||
764 | SOC_SINGLE_TLV("BASS 1", SGTL5000_DAP_EQ_BASS_BAND1, | |
765 | 0, 0x5F, 0, bass_band), | |
766 | ||
767 | SOC_SINGLE_TLV("BASS 2", SGTL5000_DAP_EQ_BASS_BAND2, | |
768 | 0, 0x5F, 0, bass_band), | |
769 | ||
770 | SOC_SINGLE_TLV("BASS 3", SGTL5000_DAP_EQ_BASS_BAND3, | |
771 | 0, 0x5F, 0, bass_band), | |
772 | ||
773 | SOC_SINGLE_TLV("BASS 4", SGTL5000_DAP_EQ_BASS_BAND4, | |
774 | 0, 0x5F, 0, bass_band), | |
9b34e6cc ZZ |
775 | }; |
776 | ||
777 | /* mute the codec used by alsa core */ | |
54b59270 | 778 | static int sgtl5000_mute_stream(struct snd_soc_dai *codec_dai, int mute, int direction) |
9b34e6cc | 779 | { |
2f8b3188 | 780 | struct snd_soc_component *component = codec_dai->component; |
c5489f9f | 781 | u16 i2s_pwr = SGTL5000_I2S_IN_POWERUP; |
9b34e6cc | 782 | |
c5489f9f MO |
783 | /* |
784 | * During 'digital mute' do not mute DAC | |
785 | * because LINE_IN would be muted aswell. We want to mute | |
786 | * only I2S block - this can be done by powering it off | |
787 | */ | |
58fadc19 | 788 | snd_soc_component_update_bits(component, SGTL5000_CHIP_DIG_POWER, |
c5489f9f | 789 | i2s_pwr, mute ? 0 : i2s_pwr); |
9b34e6cc ZZ |
790 | |
791 | return 0; | |
792 | } | |
793 | ||
794 | /* set codec format */ | |
795 | static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) | |
796 | { | |
2f8b3188 KM |
797 | struct snd_soc_component *component = codec_dai->component; |
798 | struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); | |
9b34e6cc ZZ |
799 | u16 i2sctl = 0; |
800 | ||
801 | sgtl5000->master = 0; | |
802 | /* | |
803 | * i2s clock and frame master setting. | |
804 | * ONLY support: | |
805 | * - clock and frame slave, | |
806 | * - clock and frame master | |
807 | */ | |
808 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
809 | case SND_SOC_DAIFMT_CBS_CFS: | |
810 | break; | |
811 | case SND_SOC_DAIFMT_CBM_CFM: | |
812 | i2sctl |= SGTL5000_I2S_MASTER; | |
813 | sgtl5000->master = 1; | |
814 | break; | |
815 | default: | |
816 | return -EINVAL; | |
817 | } | |
818 | ||
819 | /* setting i2s data format */ | |
820 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
821 | case SND_SOC_DAIFMT_DSP_A: | |
9ee802ec | 822 | i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT; |
9b34e6cc ZZ |
823 | break; |
824 | case SND_SOC_DAIFMT_DSP_B: | |
9ee802ec | 825 | i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT; |
9b34e6cc ZZ |
826 | i2sctl |= SGTL5000_I2S_LRALIGN; |
827 | break; | |
828 | case SND_SOC_DAIFMT_I2S: | |
9ee802ec | 829 | i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT; |
9b34e6cc ZZ |
830 | break; |
831 | case SND_SOC_DAIFMT_RIGHT_J: | |
9ee802ec | 832 | i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT; |
9b34e6cc ZZ |
833 | i2sctl |= SGTL5000_I2S_LRPOL; |
834 | break; | |
835 | case SND_SOC_DAIFMT_LEFT_J: | |
9ee802ec | 836 | i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT; |
9b34e6cc ZZ |
837 | i2sctl |= SGTL5000_I2S_LRALIGN; |
838 | break; | |
839 | default: | |
840 | return -EINVAL; | |
841 | } | |
842 | ||
843 | sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK; | |
844 | ||
845 | /* Clock inversion */ | |
846 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
847 | case SND_SOC_DAIFMT_NB_NF: | |
848 | break; | |
849 | case SND_SOC_DAIFMT_IB_NF: | |
850 | i2sctl |= SGTL5000_I2S_SCLK_INV; | |
851 | break; | |
852 | default: | |
853 | return -EINVAL; | |
854 | } | |
855 | ||
2f8b3188 | 856 | snd_soc_component_write(component, SGTL5000_CHIP_I2S_CTRL, i2sctl); |
9b34e6cc ZZ |
857 | |
858 | return 0; | |
859 | } | |
860 | ||
861 | /* set codec sysclk */ | |
862 | static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
863 | int clk_id, unsigned int freq, int dir) | |
864 | { | |
2f8b3188 KM |
865 | struct snd_soc_component *component = codec_dai->component; |
866 | struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); | |
9b34e6cc ZZ |
867 | |
868 | switch (clk_id) { | |
869 | case SGTL5000_SYSCLK: | |
870 | sgtl5000->sysclk = freq; | |
871 | break; | |
872 | default: | |
873 | return -EINVAL; | |
874 | } | |
875 | ||
876 | return 0; | |
877 | } | |
878 | ||
879 | /* | |
880 | * set clock according to i2s frame clock, | |
7f6d75d7 FE |
881 | * sgtl5000 provides 2 clock sources: |
882 | * 1. sys_mclk: sample freq can only be configured to | |
9b34e6cc | 883 | * 1/256, 1/384, 1/512 of sys_mclk. |
7f6d75d7 | 884 | * 2. pll: can derive any audio clocks. |
9b34e6cc ZZ |
885 | * |
886 | * clock setting rules: | |
7f6d75d7 FE |
887 | * 1. in slave mode, only sys_mclk can be used |
888 | * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz | |
889 | * and above. | |
890 | * 3. usage of sys_mclk is preferred over pll to save power. | |
9b34e6cc | 891 | */ |
2f8b3188 | 892 | static int sgtl5000_set_clock(struct snd_soc_component *component, int frame_rate) |
9b34e6cc | 893 | { |
2f8b3188 | 894 | struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); |
9b34e6cc ZZ |
895 | int clk_ctl = 0; |
896 | int sys_fs; /* sample freq */ | |
897 | ||
898 | /* | |
899 | * sample freq should be divided by frame clock, | |
7f6d75d7 FE |
900 | * if frame clock is lower than 44.1 kHz, sample freq should be set to |
901 | * 32 kHz or 44.1 kHz. | |
9b34e6cc ZZ |
902 | */ |
903 | switch (frame_rate) { | |
904 | case 8000: | |
905 | case 16000: | |
906 | sys_fs = 32000; | |
907 | break; | |
908 | case 11025: | |
909 | case 22050: | |
910 | sys_fs = 44100; | |
911 | break; | |
912 | default: | |
913 | sys_fs = frame_rate; | |
914 | break; | |
915 | } | |
916 | ||
917 | /* set divided factor of frame clock */ | |
918 | switch (sys_fs / frame_rate) { | |
919 | case 4: | |
920 | clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT; | |
921 | break; | |
922 | case 2: | |
923 | clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT; | |
924 | break; | |
925 | case 1: | |
926 | clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT; | |
927 | break; | |
928 | default: | |
929 | return -EINVAL; | |
930 | } | |
931 | ||
932 | /* set the sys_fs according to frame rate */ | |
933 | switch (sys_fs) { | |
934 | case 32000: | |
935 | clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT; | |
936 | break; | |
937 | case 44100: | |
938 | clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT; | |
939 | break; | |
940 | case 48000: | |
941 | clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT; | |
942 | break; | |
943 | case 96000: | |
944 | clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT; | |
945 | break; | |
946 | default: | |
2f8b3188 | 947 | dev_err(component->dev, "frame rate %d not supported\n", |
9b34e6cc ZZ |
948 | frame_rate); |
949 | return -EINVAL; | |
950 | } | |
951 | ||
952 | /* | |
953 | * calculate the divider of mclk/sample_freq, | |
7f6d75d7 FE |
954 | * factor of freq = 96 kHz can only be 256, since mclk is in the range |
955 | * of 8 MHz - 27 MHz | |
9b34e6cc | 956 | */ |
2a4cfd10 | 957 | switch (sgtl5000->sysclk / frame_rate) { |
9b34e6cc ZZ |
958 | case 256: |
959 | clk_ctl |= SGTL5000_MCLK_FREQ_256FS << | |
960 | SGTL5000_MCLK_FREQ_SHIFT; | |
961 | break; | |
962 | case 384: | |
963 | clk_ctl |= SGTL5000_MCLK_FREQ_384FS << | |
964 | SGTL5000_MCLK_FREQ_SHIFT; | |
965 | break; | |
966 | case 512: | |
967 | clk_ctl |= SGTL5000_MCLK_FREQ_512FS << | |
968 | SGTL5000_MCLK_FREQ_SHIFT; | |
969 | break; | |
970 | default: | |
7f6d75d7 | 971 | /* if mclk does not satisfy the divider, use pll */ |
9b34e6cc ZZ |
972 | if (sgtl5000->master) { |
973 | clk_ctl |= SGTL5000_MCLK_FREQ_PLL << | |
974 | SGTL5000_MCLK_FREQ_SHIFT; | |
975 | } else { | |
2f8b3188 | 976 | dev_err(component->dev, |
9b34e6cc | 977 | "PLL not supported in slave mode\n"); |
2f8b3188 | 978 | dev_err(component->dev, "%d ratio is not supported. " |
fa558d01 | 979 | "SYS_MCLK needs to be 256, 384 or 512 * fs\n", |
2a4cfd10 | 980 | sgtl5000->sysclk / frame_rate); |
9b34e6cc ZZ |
981 | return -EINVAL; |
982 | } | |
983 | } | |
984 | ||
985 | /* if using pll, please check manual 6.4.2 for detail */ | |
986 | if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) { | |
987 | u64 out, t; | |
988 | int div2; | |
989 | int pll_ctl; | |
990 | unsigned int in, int_div, frac_div; | |
991 | ||
992 | if (sgtl5000->sysclk > 17000000) { | |
993 | div2 = 1; | |
994 | in = sgtl5000->sysclk / 2; | |
995 | } else { | |
996 | div2 = 0; | |
997 | in = sgtl5000->sysclk; | |
998 | } | |
999 | if (sys_fs == 44100) | |
1000 | out = 180633600; | |
1001 | else | |
1002 | out = 196608000; | |
1003 | t = do_div(out, in); | |
1004 | int_div = out; | |
1005 | t *= 2048; | |
1006 | do_div(t, in); | |
1007 | frac_div = t; | |
1008 | pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT | | |
1009 | frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT; | |
1010 | ||
2f8b3188 | 1011 | snd_soc_component_write(component, SGTL5000_CHIP_PLL_CTRL, pll_ctl); |
9b34e6cc | 1012 | if (div2) |
2f8b3188 | 1013 | snd_soc_component_update_bits(component, |
9b34e6cc ZZ |
1014 | SGTL5000_CHIP_CLK_TOP_CTRL, |
1015 | SGTL5000_INPUT_FREQ_DIV2, | |
1016 | SGTL5000_INPUT_FREQ_DIV2); | |
1017 | else | |
2f8b3188 | 1018 | snd_soc_component_update_bits(component, |
9b34e6cc ZZ |
1019 | SGTL5000_CHIP_CLK_TOP_CTRL, |
1020 | SGTL5000_INPUT_FREQ_DIV2, | |
1021 | 0); | |
1022 | ||
1023 | /* power up pll */ | |
2f8b3188 | 1024 | snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, |
9b34e6cc ZZ |
1025 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, |
1026 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP); | |
e06e4c2d OS |
1027 | |
1028 | /* if using pll, clk_ctrl must be set after pll power up */ | |
2f8b3188 | 1029 | snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl); |
9b34e6cc | 1030 | } else { |
e06e4c2d | 1031 | /* otherwise, clk_ctrl must be set before pll power down */ |
2f8b3188 | 1032 | snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl); |
e06e4c2d | 1033 | |
9b34e6cc | 1034 | /* power down pll */ |
2f8b3188 | 1035 | snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, |
9b34e6cc ZZ |
1036 | SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP, |
1037 | 0); | |
1038 | } | |
1039 | ||
9b34e6cc ZZ |
1040 | return 0; |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * Set PCM DAI bit size and sample rate. | |
1045 | * input: params_rate, params_fmt | |
1046 | */ | |
1047 | static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream, | |
1048 | struct snd_pcm_hw_params *params, | |
1049 | struct snd_soc_dai *dai) | |
1050 | { | |
2f8b3188 KM |
1051 | struct snd_soc_component *component = dai->component; |
1052 | struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); | |
9b34e6cc ZZ |
1053 | int channels = params_channels(params); |
1054 | int i2s_ctl = 0; | |
1055 | int stereo; | |
1056 | int ret; | |
1057 | ||
1058 | /* sysclk should already set */ | |
1059 | if (!sgtl5000->sysclk) { | |
2f8b3188 | 1060 | dev_err(component->dev, "%s: set sysclk first!\n", __func__); |
9b34e6cc ZZ |
1061 | return -EFAULT; |
1062 | } | |
1063 | ||
1064 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
1065 | stereo = SGTL5000_DAC_STEREO; | |
1066 | else | |
1067 | stereo = SGTL5000_ADC_STEREO; | |
1068 | ||
1069 | /* set mono to save power */ | |
2f8b3188 | 1070 | snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, stereo, |
9b34e6cc ZZ |
1071 | channels == 1 ? 0 : stereo); |
1072 | ||
1073 | /* set codec clock base on lrclk */ | |
2f8b3188 | 1074 | ret = sgtl5000_set_clock(component, params_rate(params)); |
9b34e6cc ZZ |
1075 | if (ret) |
1076 | return ret; | |
1077 | ||
1078 | /* set i2s data format */ | |
dacc2aef MB |
1079 | switch (params_width(params)) { |
1080 | case 16: | |
9b34e6cc ZZ |
1081 | if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) |
1082 | return -EINVAL; | |
1083 | i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT; | |
1084 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS << | |
1085 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
1086 | break; | |
dacc2aef | 1087 | case 20: |
9b34e6cc ZZ |
1088 | i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT; |
1089 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
1090 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
1091 | break; | |
dacc2aef | 1092 | case 24: |
9b34e6cc ZZ |
1093 | i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT; |
1094 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
1095 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
1096 | break; | |
dacc2aef | 1097 | case 32: |
9b34e6cc ZZ |
1098 | if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J) |
1099 | return -EINVAL; | |
1100 | i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT; | |
1101 | i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS << | |
1102 | SGTL5000_I2S_SCLKFREQ_SHIFT; | |
1103 | break; | |
1104 | default: | |
1105 | return -EINVAL; | |
1106 | } | |
1107 | ||
2f8b3188 | 1108 | snd_soc_component_update_bits(component, SGTL5000_CHIP_I2S_CTRL, |
33cb92cf AL |
1109 | SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK, |
1110 | i2s_ctl); | |
9b34e6cc ZZ |
1111 | |
1112 | return 0; | |
1113 | } | |
1114 | ||
9b34e6cc ZZ |
1115 | /* |
1116 | * set dac bias | |
1117 | * common state changes: | |
1118 | * startup: | |
1119 | * off --> standby --> prepare --> on | |
1120 | * standby --> prepare --> on | |
1121 | * | |
1122 | * stop: | |
1123 | * on --> prepare --> standby | |
1124 | */ | |
2f8b3188 | 1125 | static int sgtl5000_set_bias_level(struct snd_soc_component *component, |
9b34e6cc ZZ |
1126 | enum snd_soc_bias_level level) |
1127 | { | |
27a4b3f9 | 1128 | struct sgtl5000_priv *sgtl = snd_soc_component_get_drvdata(component); |
a8992973 FE |
1129 | int ret; |
1130 | ||
9b34e6cc ZZ |
1131 | switch (level) { |
1132 | case SND_SOC_BIAS_ON: | |
1133 | case SND_SOC_BIAS_PREPARE: | |
9b34e6cc | 1134 | case SND_SOC_BIAS_STANDBY: |
a8992973 FE |
1135 | regcache_cache_only(sgtl->regmap, false); |
1136 | ret = regcache_sync(sgtl->regmap); | |
1137 | if (ret) { | |
1138 | regcache_cache_only(sgtl->regmap, true); | |
1139 | return ret; | |
1140 | } | |
1141 | ||
2f8b3188 | 1142 | snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, |
8419caa7 EN |
1143 | SGTL5000_REFTOP_POWERUP, |
1144 | SGTL5000_REFTOP_POWERUP); | |
9b34e6cc ZZ |
1145 | break; |
1146 | case SND_SOC_BIAS_OFF: | |
a8992973 | 1147 | regcache_cache_only(sgtl->regmap, true); |
2f8b3188 | 1148 | snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, |
8419caa7 | 1149 | SGTL5000_REFTOP_POWERUP, 0); |
9b34e6cc ZZ |
1150 | break; |
1151 | } | |
1152 | ||
9b34e6cc ZZ |
1153 | return 0; |
1154 | } | |
1155 | ||
1156 | #define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
1157 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
1158 | SNDRV_PCM_FMTBIT_S24_LE |\ | |
1159 | SNDRV_PCM_FMTBIT_S32_LE) | |
1160 | ||
85e7652d | 1161 | static const struct snd_soc_dai_ops sgtl5000_ops = { |
9b34e6cc | 1162 | .hw_params = sgtl5000_pcm_hw_params, |
54b59270 | 1163 | .mute_stream = sgtl5000_mute_stream, |
9b34e6cc ZZ |
1164 | .set_fmt = sgtl5000_set_dai_fmt, |
1165 | .set_sysclk = sgtl5000_set_dai_sysclk, | |
54b59270 | 1166 | .no_capture_mute = 1, |
9b34e6cc ZZ |
1167 | }; |
1168 | ||
1169 | static struct snd_soc_dai_driver sgtl5000_dai = { | |
1170 | .name = "sgtl5000", | |
1171 | .playback = { | |
1172 | .stream_name = "Playback", | |
1173 | .channels_min = 1, | |
1174 | .channels_max = 2, | |
1175 | /* | |
1176 | * only support 8~48K + 96K, | |
1177 | * TODO modify hw_param to support more | |
1178 | */ | |
1179 | .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, | |
1180 | .formats = SGTL5000_FORMATS, | |
1181 | }, | |
1182 | .capture = { | |
1183 | .stream_name = "Capture", | |
1184 | .channels_min = 1, | |
1185 | .channels_max = 2, | |
1186 | .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000, | |
1187 | .formats = SGTL5000_FORMATS, | |
1188 | }, | |
1189 | .ops = &sgtl5000_ops, | |
bea17630 | 1190 | .symmetric_rate = 1, |
9b34e6cc ZZ |
1191 | }; |
1192 | ||
e5d80e82 | 1193 | static bool sgtl5000_volatile(struct device *dev, unsigned int reg) |
9b34e6cc ZZ |
1194 | { |
1195 | switch (reg) { | |
1196 | case SGTL5000_CHIP_ID: | |
1197 | case SGTL5000_CHIP_ADCDAC_CTRL: | |
1198 | case SGTL5000_CHIP_ANA_STATUS: | |
e5d80e82 | 1199 | return true; |
9b34e6cc ZZ |
1200 | } |
1201 | ||
e5d80e82 FE |
1202 | return false; |
1203 | } | |
1204 | ||
1205 | static bool sgtl5000_readable(struct device *dev, unsigned int reg) | |
1206 | { | |
1207 | switch (reg) { | |
1208 | case SGTL5000_CHIP_ID: | |
1209 | case SGTL5000_CHIP_DIG_POWER: | |
1210 | case SGTL5000_CHIP_CLK_CTRL: | |
1211 | case SGTL5000_CHIP_I2S_CTRL: | |
1212 | case SGTL5000_CHIP_SSS_CTRL: | |
1213 | case SGTL5000_CHIP_ADCDAC_CTRL: | |
1214 | case SGTL5000_CHIP_DAC_VOL: | |
1215 | case SGTL5000_CHIP_PAD_STRENGTH: | |
1216 | case SGTL5000_CHIP_ANA_ADC_CTRL: | |
1217 | case SGTL5000_CHIP_ANA_HP_CTRL: | |
1218 | case SGTL5000_CHIP_ANA_CTRL: | |
1219 | case SGTL5000_CHIP_LINREG_CTRL: | |
1220 | case SGTL5000_CHIP_REF_CTRL: | |
1221 | case SGTL5000_CHIP_MIC_CTRL: | |
1222 | case SGTL5000_CHIP_LINE_OUT_CTRL: | |
1223 | case SGTL5000_CHIP_LINE_OUT_VOL: | |
1224 | case SGTL5000_CHIP_ANA_POWER: | |
1225 | case SGTL5000_CHIP_PLL_CTRL: | |
1226 | case SGTL5000_CHIP_CLK_TOP_CTRL: | |
1227 | case SGTL5000_CHIP_ANA_STATUS: | |
1228 | case SGTL5000_CHIP_SHORT_CTRL: | |
1229 | case SGTL5000_CHIP_ANA_TEST2: | |
1230 | case SGTL5000_DAP_CTRL: | |
1231 | case SGTL5000_DAP_PEQ: | |
1232 | case SGTL5000_DAP_BASS_ENHANCE: | |
1233 | case SGTL5000_DAP_BASS_ENHANCE_CTRL: | |
1234 | case SGTL5000_DAP_AUDIO_EQ: | |
1235 | case SGTL5000_DAP_SURROUND: | |
1236 | case SGTL5000_DAP_FLT_COEF_ACCESS: | |
1237 | case SGTL5000_DAP_COEF_WR_B0_MSB: | |
1238 | case SGTL5000_DAP_COEF_WR_B0_LSB: | |
1239 | case SGTL5000_DAP_EQ_BASS_BAND0: | |
1240 | case SGTL5000_DAP_EQ_BASS_BAND1: | |
1241 | case SGTL5000_DAP_EQ_BASS_BAND2: | |
1242 | case SGTL5000_DAP_EQ_BASS_BAND3: | |
1243 | case SGTL5000_DAP_EQ_BASS_BAND4: | |
1244 | case SGTL5000_DAP_MAIN_CHAN: | |
1245 | case SGTL5000_DAP_MIX_CHAN: | |
1246 | case SGTL5000_DAP_AVC_CTRL: | |
1247 | case SGTL5000_DAP_AVC_THRESHOLD: | |
1248 | case SGTL5000_DAP_AVC_ATTACK: | |
1249 | case SGTL5000_DAP_AVC_DECAY: | |
1250 | case SGTL5000_DAP_COEF_WR_B1_MSB: | |
1251 | case SGTL5000_DAP_COEF_WR_B1_LSB: | |
1252 | case SGTL5000_DAP_COEF_WR_B2_MSB: | |
1253 | case SGTL5000_DAP_COEF_WR_B2_LSB: | |
1254 | case SGTL5000_DAP_COEF_WR_A1_MSB: | |
1255 | case SGTL5000_DAP_COEF_WR_A1_LSB: | |
1256 | case SGTL5000_DAP_COEF_WR_A2_MSB: | |
1257 | case SGTL5000_DAP_COEF_WR_A2_LSB: | |
1258 | return true; | |
1259 | ||
1260 | default: | |
1261 | return false; | |
1262 | } | |
9b34e6cc ZZ |
1263 | } |
1264 | ||
1f39d939 AS |
1265 | /* |
1266 | * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results | |
1267 | * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL | |
1268 | * The calculatation was done for all possible register values which | |
1269 | * is the array index and the following formula: 10^((idx−15)/40) * 100 | |
1270 | */ | |
1271 | static const u8 vol_quot_table[] = { | |
1272 | 42, 45, 47, 50, 53, 56, 60, 63, | |
1273 | 67, 71, 75, 79, 84, 89, 94, 100, | |
1274 | 106, 112, 119, 126, 133, 141, 150, 158, | |
1275 | 168, 178, 188, 200, 211, 224, 237, 251 | |
1276 | }; | |
1277 | ||
9b34e6cc ZZ |
1278 | /* |
1279 | * sgtl5000 has 3 internal power supplies: | |
1280 | * 1. VAG, normally set to vdda/2 | |
7f6d75d7 | 1281 | * 2. charge pump, set to different value |
9b34e6cc ZZ |
1282 | * according to voltage of vdda and vddio |
1283 | * 3. line out VAG, normally set to vddio/2 | |
1284 | * | |
1285 | * and should be set according to: | |
1286 | * 1. vddd provided by external or not | |
1287 | * 2. vdda and vddio voltage value. > 3.1v or not | |
9b34e6cc | 1288 | */ |
2f8b3188 | 1289 | static int sgtl5000_set_power_regs(struct snd_soc_component *component) |
9b34e6cc ZZ |
1290 | { |
1291 | int vddd; | |
1292 | int vdda; | |
1293 | int vddio; | |
1294 | u16 ana_pwr; | |
1295 | u16 lreg_ctrl; | |
1296 | int vag; | |
d2b7c2aa | 1297 | int lo_vag; |
1f39d939 AS |
1298 | int vol_quot; |
1299 | int lo_vol; | |
1300 | size_t i; | |
2f8b3188 | 1301 | struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); |
9b34e6cc ZZ |
1302 | |
1303 | vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer); | |
1304 | vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer); | |
940adb28 EN |
1305 | vddd = (sgtl5000->num_supplies > VDDD) |
1306 | ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer) | |
1307 | : LDO_VOLTAGE; | |
9b34e6cc ZZ |
1308 | |
1309 | vdda = vdda / 1000; | |
1310 | vddio = vddio / 1000; | |
1311 | vddd = vddd / 1000; | |
1312 | ||
1313 | if (vdda <= 0 || vddio <= 0 || vddd < 0) { | |
2f8b3188 | 1314 | dev_err(component->dev, "regulator voltage not set correctly\n"); |
9b34e6cc ZZ |
1315 | |
1316 | return -EINVAL; | |
1317 | } | |
1318 | ||
1319 | /* according to datasheet, maximum voltage of supplies */ | |
1320 | if (vdda > 3600 || vddio > 3600 || vddd > 1980) { | |
2f8b3188 | 1321 | dev_err(component->dev, |
cf1ee98d | 1322 | "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n", |
9b34e6cc ZZ |
1323 | vdda, vddio, vddd); |
1324 | ||
1325 | return -EINVAL; | |
1326 | } | |
1327 | ||
1328 | /* reset value */ | |
981abdfe | 1329 | ana_pwr = snd_soc_component_read(component, SGTL5000_CHIP_ANA_POWER); |
9b34e6cc ZZ |
1330 | ana_pwr |= SGTL5000_DAC_STEREO | |
1331 | SGTL5000_ADC_STEREO | | |
1332 | SGTL5000_REFTOP_POWERUP; | |
981abdfe | 1333 | lreg_ctrl = snd_soc_component_read(component, SGTL5000_CHIP_LINREG_CTRL); |
9b34e6cc ZZ |
1334 | |
1335 | if (vddio < 3100 && vdda < 3100) { | |
1336 | /* enable internal oscillator used for charge pump */ | |
2f8b3188 | 1337 | snd_soc_component_update_bits(component, SGTL5000_CHIP_CLK_TOP_CTRL, |
9b34e6cc ZZ |
1338 | SGTL5000_INT_OSC_EN, |
1339 | SGTL5000_INT_OSC_EN); | |
1340 | /* Enable VDDC charge pump */ | |
1341 | ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP; | |
b6319b06 | 1342 | } else { |
c7d910b8 | 1343 | ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP; |
b6319b06 OS |
1344 | /* |
1345 | * if vddio == vdda the source of charge pump should be | |
1346 | * assigned manually to VDDIO | |
1347 | */ | |
e19ecbf1 MV |
1348 | if (regulator_is_equal(sgtl5000->supplies[VDDA].consumer, |
1349 | sgtl5000->supplies[VDDIO].consumer)) { | |
b6319b06 OS |
1350 | lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD; |
1351 | lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO << | |
1352 | SGTL5000_VDDC_MAN_ASSN_SHIFT; | |
1353 | } | |
9b34e6cc ZZ |
1354 | } |
1355 | ||
2f8b3188 | 1356 | snd_soc_component_write(component, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl); |
9b34e6cc | 1357 | |
2f8b3188 | 1358 | snd_soc_component_write(component, SGTL5000_CHIP_ANA_POWER, ana_pwr); |
9b34e6cc | 1359 | |
9b34e6cc ZZ |
1360 | /* |
1361 | * set ADC/DAC VAG to vdda / 2, | |
1362 | * should stay in range (0.8v, 1.575v) | |
1363 | */ | |
1364 | vag = vdda / 2; | |
1365 | if (vag <= SGTL5000_ANA_GND_BASE) | |
1366 | vag = 0; | |
1367 | else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP * | |
1368 | (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT)) | |
1369 | vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT; | |
1370 | else | |
1371 | vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP; | |
1372 | ||
2f8b3188 | 1373 | snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL, |
33cb92cf | 1374 | SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT); |
9b34e6cc ZZ |
1375 | |
1376 | /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */ | |
d2b7c2aa AS |
1377 | lo_vag = vddio / 2; |
1378 | if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE) | |
1379 | lo_vag = 0; | |
1380 | else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE + | |
9b34e6cc | 1381 | SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX) |
d2b7c2aa | 1382 | lo_vag = SGTL5000_LINE_OUT_GND_MAX; |
9b34e6cc | 1383 | else |
d2b7c2aa | 1384 | lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) / |
9b34e6cc ZZ |
1385 | SGTL5000_LINE_OUT_GND_STP; |
1386 | ||
2f8b3188 | 1387 | snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_CTRL, |
33cb92cf AL |
1388 | SGTL5000_LINE_OUT_CURRENT_MASK | |
1389 | SGTL5000_LINE_OUT_GND_MASK, | |
d2b7c2aa | 1390 | lo_vag << SGTL5000_LINE_OUT_GND_SHIFT | |
9b34e6cc ZZ |
1391 | SGTL5000_LINE_OUT_CURRENT_360u << |
1392 | SGTL5000_LINE_OUT_CURRENT_SHIFT); | |
1393 | ||
1f39d939 AS |
1394 | /* |
1395 | * Set lineout output level in range (0..31) | |
1396 | * the same value is used for right and left channel | |
1397 | * | |
1398 | * Searching for a suitable index solving this formula: | |
1399 | * idx = 40 * log10(vag_val / lo_cagcntrl) + 15 | |
1400 | */ | |
9ab708ae | 1401 | vol_quot = lo_vag ? (vag * 100) / lo_vag : 0; |
1f39d939 AS |
1402 | lo_vol = 0; |
1403 | for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) { | |
1404 | if (vol_quot >= vol_quot_table[i]) | |
1405 | lo_vol = i; | |
1406 | else | |
1407 | break; | |
1408 | } | |
1409 | ||
2f8b3188 | 1410 | snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_VOL, |
1f39d939 AS |
1411 | SGTL5000_LINE_OUT_VOL_RIGHT_MASK | |
1412 | SGTL5000_LINE_OUT_VOL_LEFT_MASK, | |
1413 | lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT | | |
1414 | lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT); | |
1415 | ||
9b34e6cc ZZ |
1416 | return 0; |
1417 | } | |
1418 | ||
940adb28 | 1419 | static int sgtl5000_enable_regulators(struct i2c_client *client) |
9b34e6cc | 1420 | { |
9b34e6cc | 1421 | int ret; |
9b34e6cc ZZ |
1422 | int i; |
1423 | int external_vddd = 0; | |
11db0da8 | 1424 | struct regulator *vddd; |
940adb28 | 1425 | struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); |
9b34e6cc ZZ |
1426 | |
1427 | for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++) | |
1428 | sgtl5000->supplies[i].supply = supply_names[i]; | |
1429 | ||
940adb28 EN |
1430 | vddd = regulator_get_optional(&client->dev, "VDDD"); |
1431 | if (IS_ERR(vddd)) { | |
1432 | /* See if it's just not registered yet */ | |
1433 | if (PTR_ERR(vddd) == -EPROBE_DEFER) | |
1434 | return -EPROBE_DEFER; | |
1435 | } else { | |
1436 | external_vddd = 1; | |
1437 | regulator_put(vddd); | |
9b34e6cc ZZ |
1438 | } |
1439 | ||
940adb28 EN |
1440 | sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies) |
1441 | - 1 + external_vddd; | |
1442 | ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies, | |
11db0da8 SG |
1443 | sgtl5000->supplies); |
1444 | if (ret) | |
940adb28 | 1445 | return ret; |
9b34e6cc | 1446 | |
940adb28 EN |
1447 | ret = regulator_bulk_enable(sgtl5000->num_supplies, |
1448 | sgtl5000->supplies); | |
1449 | if (!ret) | |
1450 | usleep_range(10, 20); | |
1451 | else | |
1452 | regulator_bulk_free(sgtl5000->num_supplies, | |
1453 | sgtl5000->supplies); | |
9b34e6cc | 1454 | |
9b34e6cc | 1455 | return ret; |
9b34e6cc ZZ |
1456 | } |
1457 | ||
2f8b3188 | 1458 | static int sgtl5000_probe(struct snd_soc_component *component) |
9b34e6cc ZZ |
1459 | { |
1460 | int ret; | |
570c70a6 | 1461 | u16 reg; |
2f8b3188 | 1462 | struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component); |
631bc8f0 | 1463 | unsigned int zcd_mask = SGTL5000_HP_ZCD_EN | SGTL5000_ADC_ZCD_EN; |
9b34e6cc | 1464 | |
9b34e6cc | 1465 | /* power up sgtl5000 */ |
2f8b3188 | 1466 | ret = sgtl5000_set_power_regs(component); |
9b34e6cc ZZ |
1467 | if (ret) |
1468 | goto err; | |
1469 | ||
1470 | /* enable small pop, introduce 400ms delay in turning off */ | |
2f8b3188 | 1471 | snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL, |
cadee10c | 1472 | SGTL5000_SMALL_POP, SGTL5000_SMALL_POP); |
9b34e6cc ZZ |
1473 | |
1474 | /* disable short cut detector */ | |
2f8b3188 | 1475 | snd_soc_component_write(component, SGTL5000_CHIP_SHORT_CTRL, 0); |
9b34e6cc | 1476 | |
2f8b3188 | 1477 | snd_soc_component_write(component, SGTL5000_CHIP_DIG_POWER, |
9b34e6cc ZZ |
1478 | SGTL5000_ADC_EN | SGTL5000_DAC_EN); |
1479 | ||
1480 | /* enable dac volume ramp by default */ | |
2f8b3188 | 1481 | snd_soc_component_write(component, SGTL5000_CHIP_ADCDAC_CTRL, |
9b34e6cc ZZ |
1482 | SGTL5000_DAC_VOL_RAMP_EN | |
1483 | SGTL5000_DAC_MUTE_RIGHT | | |
1484 | SGTL5000_DAC_MUTE_LEFT); | |
1485 | ||
5dc4ca29 AW |
1486 | reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT | |
1487 | (sgtl5000->sclk_strength) << SGTL5000_PAD_I2S_SCLK_SHIFT | | |
1488 | 0x1f); | |
2f8b3188 | 1489 | snd_soc_component_write(component, SGTL5000_CHIP_PAD_STRENGTH, reg); |
9b34e6cc | 1490 | |
631bc8f0 OS |
1491 | snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_CTRL, |
1492 | zcd_mask, zcd_mask); | |
9b34e6cc | 1493 | |
2f8b3188 | 1494 | snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL, |
bd0593f5 JMH |
1495 | SGTL5000_BIAS_R_MASK, |
1496 | sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT); | |
9b34e6cc | 1497 | |
2f8b3188 | 1498 | snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL, |
e256da84 GR |
1499 | SGTL5000_BIAS_VOLT_MASK, |
1500 | sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT); | |
9b34e6cc | 1501 | /* |
92a2742f | 1502 | * enable DAP Graphic EQ |
9b34e6cc | 1503 | * TODO: |
92a2742f | 1504 | * Add control for changing between PEQ/Tone Control/GEQ |
9b34e6cc | 1505 | */ |
92a2742f | 1506 | snd_soc_component_write(component, SGTL5000_DAP_AUDIO_EQ, SGTL5000_DAP_SEL_GEQ); |
9b34e6cc | 1507 | |
c5489f9f | 1508 | /* Unmute DAC after start */ |
58fadc19 | 1509 | snd_soc_component_update_bits(component, SGTL5000_CHIP_ADCDAC_CTRL, |
c5489f9f MO |
1510 | SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT, 0); |
1511 | ||
9b34e6cc ZZ |
1512 | return 0; |
1513 | ||
1514 | err: | |
9b34e6cc ZZ |
1515 | return ret; |
1516 | } | |
1517 | ||
06bf8ea4 MV |
1518 | static int sgtl5000_of_xlate_dai_id(struct snd_soc_component *component, |
1519 | struct device_node *endpoint) | |
1520 | { | |
1521 | /* return dai id 0, whatever the endpoint index */ | |
1522 | return 0; | |
1523 | } | |
1524 | ||
2f8b3188 KM |
1525 | static const struct snd_soc_component_driver sgtl5000_driver = { |
1526 | .probe = sgtl5000_probe, | |
1527 | .set_bias_level = sgtl5000_set_bias_level, | |
1528 | .controls = sgtl5000_snd_controls, | |
1529 | .num_controls = ARRAY_SIZE(sgtl5000_snd_controls), | |
1530 | .dapm_widgets = sgtl5000_dapm_widgets, | |
1531 | .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets), | |
1532 | .dapm_routes = sgtl5000_dapm_routes, | |
1533 | .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes), | |
06bf8ea4 | 1534 | .of_xlate_dai_id = sgtl5000_of_xlate_dai_id, |
2f8b3188 KM |
1535 | .suspend_bias_off = 1, |
1536 | .idle_bias_on = 1, | |
1537 | .use_pmdown_time = 1, | |
1538 | .endianness = 1, | |
1539 | .non_legacy_dai_naming = 1, | |
9b34e6cc ZZ |
1540 | }; |
1541 | ||
e5d80e82 FE |
1542 | static const struct regmap_config sgtl5000_regmap = { |
1543 | .reg_bits = 16, | |
1544 | .val_bits = 16, | |
cb23e852 | 1545 | .reg_stride = 2, |
e5d80e82 FE |
1546 | |
1547 | .max_register = SGTL5000_MAX_REG_OFFSET, | |
1548 | .volatile_reg = sgtl5000_volatile, | |
1549 | .readable_reg = sgtl5000_readable, | |
1550 | ||
1551 | .cache_type = REGCACHE_RBTREE, | |
1552 | .reg_defaults = sgtl5000_reg_defaults, | |
1553 | .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults), | |
1554 | }; | |
1555 | ||
af8ee112 FE |
1556 | /* |
1557 | * Write all the default values from sgtl5000_reg_defaults[] array into the | |
1558 | * sgtl5000 registers, to make sure we always start with the sane registers | |
1559 | * values as stated in the datasheet. | |
1560 | * | |
1561 | * Since sgtl5000 does not have a reset line, nor a reset command in software, | |
1562 | * we follow this approach to guarantee we always start from the default values | |
1563 | * and avoid problems like, not being able to probe after an audio playback | |
1564 | * followed by a system reset or a 'reboot' command in Linux | |
1565 | */ | |
f219b169 | 1566 | static void sgtl5000_fill_defaults(struct i2c_client *client) |
af8ee112 | 1567 | { |
f219b169 | 1568 | struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); |
af8ee112 FE |
1569 | int i, ret, val, index; |
1570 | ||
1571 | for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) { | |
1572 | val = sgtl5000_reg_defaults[i].def; | |
1573 | index = sgtl5000_reg_defaults[i].reg; | |
1574 | ret = regmap_write(sgtl5000->regmap, index, val); | |
1575 | if (ret) | |
f219b169 EN |
1576 | dev_err(&client->dev, |
1577 | "%s: error %d setting reg 0x%02x to 0x%04x\n", | |
1578 | __func__, ret, index, val); | |
af8ee112 | 1579 | } |
af8ee112 FE |
1580 | } |
1581 | ||
7a79e94e BP |
1582 | static int sgtl5000_i2c_probe(struct i2c_client *client, |
1583 | const struct i2c_device_id *id) | |
9b34e6cc ZZ |
1584 | { |
1585 | struct sgtl5000_priv *sgtl5000; | |
b871f1ad | 1586 | int ret, reg, rev; |
bd0593f5 JMH |
1587 | struct device_node *np = client->dev.of_node; |
1588 | u32 value; | |
3d632cc8 | 1589 | u16 ana_pwr; |
9b34e6cc | 1590 | |
3f7256fe | 1591 | sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL); |
9b34e6cc ZZ |
1592 | if (!sgtl5000) |
1593 | return -ENOMEM; | |
1594 | ||
940adb28 EN |
1595 | i2c_set_clientdata(client, sgtl5000); |
1596 | ||
1597 | ret = sgtl5000_enable_regulators(client); | |
1598 | if (ret) | |
1599 | return ret; | |
1600 | ||
e5d80e82 FE |
1601 | sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap); |
1602 | if (IS_ERR(sgtl5000->regmap)) { | |
1603 | ret = PTR_ERR(sgtl5000->regmap); | |
1604 | dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret); | |
940adb28 | 1605 | goto disable_regs; |
e5d80e82 FE |
1606 | } |
1607 | ||
9e13f345 FE |
1608 | sgtl5000->mclk = devm_clk_get(&client->dev, NULL); |
1609 | if (IS_ERR(sgtl5000->mclk)) { | |
1610 | ret = PTR_ERR(sgtl5000->mclk); | |
46a5905e SG |
1611 | /* Defer the probe to see if the clk will be provided later */ |
1612 | if (ret == -ENOENT) | |
940adb28 | 1613 | ret = -EPROBE_DEFER; |
8af5748f | 1614 | |
ec1e0e72 KM |
1615 | dev_err_probe(&client->dev, ret, "Failed to get mclock\n"); |
1616 | ||
940adb28 | 1617 | goto disable_regs; |
9e13f345 FE |
1618 | } |
1619 | ||
1620 | ret = clk_prepare_enable(sgtl5000->mclk); | |
940adb28 EN |
1621 | if (ret) { |
1622 | dev_err(&client->dev, "Error enabling clock %d\n", ret); | |
1623 | goto disable_regs; | |
1624 | } | |
9e13f345 | 1625 | |
58cc9c9a EN |
1626 | /* Need 8 clocks before I2C accesses */ |
1627 | udelay(1); | |
1628 | ||
b871f1ad FE |
1629 | /* read chip information */ |
1630 | ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, ®); | |
940adb28 EN |
1631 | if (ret) { |
1632 | dev_err(&client->dev, "Error reading chip id %d\n", ret); | |
9e13f345 | 1633 | goto disable_clk; |
940adb28 | 1634 | } |
b871f1ad FE |
1635 | |
1636 | if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) != | |
1637 | SGTL5000_PARTID_PART_ID) { | |
1638 | dev_err(&client->dev, | |
1639 | "Device with ID register %x is not a sgtl5000\n", reg); | |
9e13f345 FE |
1640 | ret = -ENODEV; |
1641 | goto disable_clk; | |
b871f1ad FE |
1642 | } |
1643 | ||
1644 | rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT; | |
1645 | dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev); | |
252e91ff | 1646 | sgtl5000->revision = rev; |
b871f1ad | 1647 | |
08dea16e EN |
1648 | /* reconfigure the clocks in case we're using the PLL */ |
1649 | ret = regmap_write(sgtl5000->regmap, | |
1650 | SGTL5000_CHIP_CLK_CTRL, | |
1651 | SGTL5000_CHIP_CLK_CTRL_DEFAULT); | |
1652 | if (ret) | |
1653 | dev_err(&client->dev, | |
1654 | "Error %d initializing CHIP_CLK_CTRL\n", ret); | |
1655 | ||
aa781273 SR |
1656 | /* Mute everything to avoid pop from the following power-up */ |
1657 | ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_CTRL, | |
1658 | SGTL5000_CHIP_ANA_CTRL_DEFAULT); | |
1659 | if (ret) { | |
1660 | dev_err(&client->dev, | |
1661 | "Error %d muting outputs via CHIP_ANA_CTRL\n", ret); | |
1662 | goto disable_clk; | |
1663 | } | |
1664 | ||
1665 | /* | |
1666 | * If VAG is powered-on (e.g. from previous boot), it would be disabled | |
1667 | * by the write to ANA_POWER in later steps of the probe code. This | |
1668 | * may create a loud pop even with all outputs muted. The proper way | |
1669 | * to circumvent this is disabling the bit first and waiting the proper | |
1670 | * cool-down time. | |
1671 | */ | |
1672 | ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, &value); | |
1673 | if (ret) { | |
1674 | dev_err(&client->dev, "Failed to read ANA_POWER: %d\n", ret); | |
1675 | goto disable_clk; | |
1676 | } | |
1677 | if (value & SGTL5000_VAG_POWERUP) { | |
1678 | ret = regmap_update_bits(sgtl5000->regmap, | |
1679 | SGTL5000_CHIP_ANA_POWER, | |
1680 | SGTL5000_VAG_POWERUP, | |
1681 | 0); | |
1682 | if (ret) { | |
1683 | dev_err(&client->dev, "Error %d disabling VAG\n", ret); | |
1684 | goto disable_clk; | |
1685 | } | |
1686 | ||
1687 | msleep(SGTL5000_VAG_POWERDOWN_DELAY); | |
1688 | } | |
1689 | ||
940adb28 | 1690 | /* Follow section 2.2.1.1 of AN3663 */ |
3d632cc8 | 1691 | ana_pwr = SGTL5000_ANA_POWER_DEFAULT; |
940adb28 EN |
1692 | if (sgtl5000->num_supplies <= VDDD) { |
1693 | /* internal VDDD at 1.2V */ | |
3d632cc8 EN |
1694 | ret = regmap_update_bits(sgtl5000->regmap, |
1695 | SGTL5000_CHIP_LINREG_CTRL, | |
1696 | SGTL5000_LINREG_VDDD_MASK, | |
1697 | LINREG_VDDD); | |
1698 | if (ret) | |
1699 | dev_err(&client->dev, | |
1700 | "Error %d setting LINREG_VDDD\n", ret); | |
1701 | ||
1702 | ana_pwr |= SGTL5000_LINEREG_D_POWERUP; | |
1703 | dev_info(&client->dev, | |
da689e0d | 1704 | "Using internal LDO instead of VDDD: check ER1 erratum\n"); |
940adb28 EN |
1705 | } else { |
1706 | /* using external LDO for VDDD | |
1707 | * Clear startup powerup and simple powerup | |
1708 | * bits to save power | |
1709 | */ | |
3d632cc8 EN |
1710 | ana_pwr &= ~(SGTL5000_STARTUP_POWERUP |
1711 | | SGTL5000_LINREG_SIMPLE_POWERUP); | |
940adb28 EN |
1712 | dev_dbg(&client->dev, "Using external VDDD\n"); |
1713 | } | |
3d632cc8 EN |
1714 | ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr); |
1715 | if (ret) | |
1716 | dev_err(&client->dev, | |
1717 | "Error %d setting CHIP_ANA_POWER to %04x\n", | |
1718 | ret, ana_pwr); | |
940adb28 | 1719 | |
bd0593f5 JMH |
1720 | if (np) { |
1721 | if (!of_property_read_u32(np, | |
1722 | "micbias-resistor-k-ohms", &value)) { | |
1723 | switch (value) { | |
1724 | case SGTL5000_MICBIAS_OFF: | |
1725 | sgtl5000->micbias_resistor = 0; | |
1726 | break; | |
1727 | case SGTL5000_MICBIAS_2K: | |
1728 | sgtl5000->micbias_resistor = 1; | |
1729 | break; | |
1730 | case SGTL5000_MICBIAS_4K: | |
1731 | sgtl5000->micbias_resistor = 2; | |
1732 | break; | |
1733 | case SGTL5000_MICBIAS_8K: | |
1734 | sgtl5000->micbias_resistor = 3; | |
1735 | break; | |
1736 | default: | |
1737 | sgtl5000->micbias_resistor = 2; | |
1738 | dev_err(&client->dev, | |
1739 | "Unsuitable MicBias resistor\n"); | |
1740 | } | |
1741 | } else { | |
1742 | /* default is 4Kohms */ | |
1743 | sgtl5000->micbias_resistor = 2; | |
1744 | } | |
87357797 JMH |
1745 | if (!of_property_read_u32(np, |
1746 | "micbias-voltage-m-volts", &value)) { | |
1747 | /* 1250mV => 0 */ | |
1748 | /* steps of 250mV */ | |
1749 | if ((value >= 1250) && (value <= 3000)) | |
1750 | sgtl5000->micbias_voltage = (value / 250) - 5; | |
1751 | else { | |
1752 | sgtl5000->micbias_voltage = 0; | |
bd0593f5 | 1753 | dev_err(&client->dev, |
fb97d75b | 1754 | "Unsuitable MicBias voltage\n"); |
bd0593f5 JMH |
1755 | } |
1756 | } else { | |
87357797 | 1757 | sgtl5000->micbias_voltage = 0; |
bd0593f5 JMH |
1758 | } |
1759 | } | |
1760 | ||
570c70a6 FE |
1761 | sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW; |
1762 | if (!of_property_read_u32(np, "lrclk-strength", &value)) { | |
1763 | if (value > I2S_LRCLK_STRENGTH_HIGH) | |
1764 | value = I2S_LRCLK_STRENGTH_LOW; | |
1765 | sgtl5000->lrclk_strength = value; | |
1766 | } | |
1767 | ||
5dc4ca29 AW |
1768 | sgtl5000->sclk_strength = I2S_SCLK_STRENGTH_LOW; |
1769 | if (!of_property_read_u32(np, "sclk-strength", &value)) { | |
1770 | if (value > I2S_SCLK_STRENGTH_HIGH) | |
1771 | value = I2S_SCLK_STRENGTH_LOW; | |
1772 | sgtl5000->sclk_strength = value; | |
1773 | } | |
1774 | ||
af8ee112 | 1775 | /* Ensure sgtl5000 will start with sane register values */ |
f219b169 | 1776 | sgtl5000_fill_defaults(client); |
af8ee112 | 1777 | |
2f8b3188 | 1778 | ret = devm_snd_soc_register_component(&client->dev, |
9b34e6cc | 1779 | &sgtl5000_driver, &sgtl5000_dai, 1); |
9e13f345 FE |
1780 | if (ret) |
1781 | goto disable_clk; | |
1782 | ||
1783 | return 0; | |
1784 | ||
1785 | disable_clk: | |
1786 | clk_disable_unprepare(sgtl5000->mclk); | |
940adb28 EN |
1787 | |
1788 | disable_regs: | |
1789 | regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies); | |
1790 | regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies); | |
1791 | ||
512fa7c4 | 1792 | return ret; |
9b34e6cc ZZ |
1793 | } |
1794 | ||
7a79e94e | 1795 | static int sgtl5000_i2c_remove(struct i2c_client *client) |
9b34e6cc | 1796 | { |
7c647af4 | 1797 | struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client); |
9b34e6cc | 1798 | |
9e13f345 | 1799 | clk_disable_unprepare(sgtl5000->mclk); |
940adb28 EN |
1800 | regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies); |
1801 | regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies); | |
1802 | ||
9b34e6cc ZZ |
1803 | return 0; |
1804 | } | |
1805 | ||
1806 | static const struct i2c_device_id sgtl5000_id[] = { | |
1807 | {"sgtl5000", 0}, | |
1808 | {}, | |
1809 | }; | |
1810 | ||
1811 | MODULE_DEVICE_TABLE(i2c, sgtl5000_id); | |
1812 | ||
58e49424 SG |
1813 | static const struct of_device_id sgtl5000_dt_ids[] = { |
1814 | { .compatible = "fsl,sgtl5000", }, | |
1815 | { /* sentinel */ } | |
1816 | }; | |
4c54c6de | 1817 | MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids); |
58e49424 | 1818 | |
9b34e6cc ZZ |
1819 | static struct i2c_driver sgtl5000_i2c_driver = { |
1820 | .driver = { | |
5d90fef6 FE |
1821 | .name = "sgtl5000", |
1822 | .of_match_table = sgtl5000_dt_ids, | |
1823 | }, | |
9b34e6cc | 1824 | .probe = sgtl5000_i2c_probe, |
7a79e94e | 1825 | .remove = sgtl5000_i2c_remove, |
9b34e6cc ZZ |
1826 | .id_table = sgtl5000_id, |
1827 | }; | |
1828 | ||
67d45090 | 1829 | module_i2c_driver(sgtl5000_i2c_driver); |
9b34e6cc ZZ |
1830 | |
1831 | MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver"); | |
f7cb8a4b | 1832 | MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>"); |
9b34e6cc | 1833 | MODULE_LICENSE("GPL"); |