[linux-2.6-block.git] / sound / soc / codecs / rt5677-spi.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * rt5677-spi.c  --  RT5677 ALSA SoC audio codec driver
 *
 * Copyright 2013 Realtek Semiconductor Corp.
 * Author: Oder Chiou <oder_chiou@realtek.com>
 */

#include <linux/module.h>
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/uaccess.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_qos.h>
#include <linux/sysfs.h>
#include <linux/clk.h>
#include <linux/firmware.h>
#include <linux/acpi.h>

#include <sound/soc.h>

#include "rt5677-spi.h"

#define DRV_NAME "rt5677spi"

#define RT5677_SPI_BURST_LEN	240
#define RT5677_SPI_HEADER	5
#define RT5677_SPI_FREQ		6000000

/* The AddressPhase and DataPhase of SPI commands are MSB first on the wire.
 * DataPhase word size of 16-bit commands is 2 bytes.
 * DataPhase word size of 32-bit commands is 4 bytes.
 * DataPhase word size of burst commands is 8 bytes.
 * The DSP CPU is little-endian.
 */
#define RT5677_SPI_WRITE_BURST	0x5
#define RT5677_SPI_READ_BURST	0x4
#define RT5677_SPI_WRITE_32	0x3
#define RT5677_SPI_READ_32	0x2
#define RT5677_SPI_WRITE_16	0x1
#define RT5677_SPI_READ_16	0x0

#define RT5677_BUF_BYTES_TOTAL		0x20000
#define RT5677_MIC_BUF_ADDR		0x60030000
#define RT5677_MODEL_ADDR		0x5FFC9800
#define RT5677_MIC_BUF_BYTES		((u32)(RT5677_BUF_BYTES_TOTAL - \
					sizeof(u32)))
#define RT5677_MIC_BUF_FIRST_READ_SIZE	0x10000

static struct spi_device *g_spi;
static DEFINE_MUTEX(spi_mutex);

struct rt5677_dsp {
	struct device *dev;
	struct delayed_work copy_work;
	struct mutex dma_lock;
	struct snd_pcm_substream *substream;
	size_t dma_offset;	/* zero-based offset into runtime->dma_area */
	size_t avail_bytes;	/* number of new bytes since last period */
	u32 mic_read_offset;	/* zero-based offset into DSP's mic buffer */
	bool new_hotword;	/* a new hotword is fired */
};

static const struct snd_pcm_hardware rt5677_spi_pcm_hardware = {
	.info			= SNDRV_PCM_INFO_MMAP |
				  SNDRV_PCM_INFO_MMAP_VALID |
				  SNDRV_PCM_INFO_INTERLEAVED,
	.formats		= SNDRV_PCM_FMTBIT_S16_LE,
	.period_bytes_min	= PAGE_SIZE,
	.period_bytes_max	= RT5677_BUF_BYTES_TOTAL / 8,
	.periods_min		= 8,
	.periods_max		= 8,
	.channels_min		= 1,
	.channels_max		= 1,
	.buffer_bytes_max	= RT5677_BUF_BYTES_TOTAL,
};

static struct snd_soc_dai_driver rt5677_spi_dai = {
	/* The DAI name "rt5677-dsp-cpu-dai" is not used. The actual DAI name
	 * registered with ASoC is the name of the device "spi-RT5677AA:00",
	 * because we only have one DAI. See snd_soc_register_dais().
	 */
	.name = "rt5677-dsp-cpu-dai",
	.id = 0,
	.capture = {
		.stream_name = "DSP Capture",
		.channels_min = 1,
		.channels_max = 1,
		.rates = SNDRV_PCM_RATE_16000,
		.formats = SNDRV_PCM_FMTBIT_S16_LE,
	},
};

/* PCM for streaming audio from the DSP buffer */
static int rt5677_spi_pcm_open(
		struct snd_soc_component *component,
		struct snd_pcm_substream *substream)
{
	snd_soc_set_runtime_hwparams(substream, &rt5677_spi_pcm_hardware);
	return 0;
}

static int rt5677_spi_pcm_close(
		struct snd_soc_component *component,
		struct snd_pcm_substream *substream)
{
	struct rt5677_dsp *rt5677_dsp =
			snd_soc_component_get_drvdata(component);

	cancel_delayed_work_sync(&rt5677_dsp->copy_work);
	return 0;
}

static int rt5677_spi_hw_params(
		struct snd_soc_component *component,
		struct snd_pcm_substream *substream,
		struct snd_pcm_hw_params *hw_params)
{
	struct rt5677_dsp *rt5677_dsp =
			snd_soc_component_get_drvdata(component);
	int ret;

	mutex_lock(&rt5677_dsp->dma_lock);
	ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
	rt5677_dsp->substream = substream;
	mutex_unlock(&rt5677_dsp->dma_lock);

	return ret;
}

static int rt5677_spi_hw_free(
		struct snd_soc_component *component,
		struct snd_pcm_substream *substream)
{
	struct rt5677_dsp *rt5677_dsp =
			snd_soc_component_get_drvdata(component);

	mutex_lock(&rt5677_dsp->dma_lock);
	rt5677_dsp->substream = NULL;
	mutex_unlock(&rt5677_dsp->dma_lock);

	return snd_pcm_lib_free_pages(substream);
}

static int rt5677_spi_prepare(
		struct snd_soc_component *component,
		struct snd_pcm_substream *substream)
{
	struct rt5677_dsp *rt5677_dsp =
			snd_soc_component_get_drvdata(component);

	rt5677_dsp->dma_offset = 0;
	rt5677_dsp->avail_bytes = 0;
	return 0;
}

static snd_pcm_uframes_t rt5677_spi_pcm_pointer(
		struct snd_soc_component *component,
		struct snd_pcm_substream *substream)
{
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct rt5677_dsp *rt5677_dsp =
			snd_soc_component_get_drvdata(component);

	return bytes_to_frames(runtime, rt5677_dsp->dma_offset);
}

static int rt5677_spi_mic_write_offset(u32 *mic_write_offset)
{
	int ret;
	/* Grab the first 4 bytes that hold the write pointer on the
	 * dsp, and check to make sure that it points somewhere inside the
	 * buffer.
	 */
	ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR, mic_write_offset,
			sizeof(u32));
	if (ret)
		return ret;
	/* Adjust the offset so that it's zero-based */
	*mic_write_offset = *mic_write_offset - sizeof(u32);
	return *mic_write_offset < RT5677_MIC_BUF_BYTES ? 0 : -EFAULT;
}

/*
 * Copy one contiguous block of audio samples from the DSP mic buffer to the
 * dma_area of the pcm runtime. The receiving buffer may wrap around.
 * @begin: start offset of the block to copy, in bytes.
 * @end:   offset of the first byte after the block to copy, must be greater
 *         than or equal to begin.
 *
 * Return: Zero if successful, or a negative error code on failure.
 */
static int rt5677_spi_copy_block(struct rt5677_dsp *rt5677_dsp,
		u32 begin, u32 end)
{
	struct snd_pcm_runtime *runtime = rt5677_dsp->substream->runtime;
	size_t bytes_per_frame = frames_to_bytes(runtime, 1);
	size_t first_chunk_len, second_chunk_len;
	int ret;

	if (begin > end || runtime->dma_bytes < 2 * bytes_per_frame) {
		dev_err(rt5677_dsp->dev,
			"Invalid copy from (%u, %u), dma_area size %zu\n",
			begin, end, runtime->dma_bytes);
		return -EINVAL;
	}

	/* The block to copy is empty */
	if (begin == end)
		return 0;

	/* If the incoming chunk is too big for the receiving buffer, only the
	 * last "receiving buffer size - one frame" bytes are copied.
	 */
	if (end - begin > runtime->dma_bytes - bytes_per_frame)
		begin = end - (runtime->dma_bytes - bytes_per_frame);

	/* May need to split to two chunks, calculate the size of each */
	first_chunk_len = end - begin;
	second_chunk_len = 0;
	if (rt5677_dsp->dma_offset + first_chunk_len > runtime->dma_bytes) {
		/* Receiving buffer wrapped around */
		second_chunk_len = first_chunk_len;
		first_chunk_len = runtime->dma_bytes - rt5677_dsp->dma_offset;
		second_chunk_len -= first_chunk_len;
	}

	/* Copy first chunk */
	ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR + sizeof(u32) + begin,
			runtime->dma_area + rt5677_dsp->dma_offset,
			first_chunk_len);
	if (ret)
		return ret;
	rt5677_dsp->dma_offset += first_chunk_len;
	if (rt5677_dsp->dma_offset == runtime->dma_bytes)
		rt5677_dsp->dma_offset = 0;

	/* Copy second chunk */
	if (second_chunk_len) {
		ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR + sizeof(u32) +
				begin + first_chunk_len, runtime->dma_area,
				second_chunk_len);
		if (!ret)
			rt5677_dsp->dma_offset = second_chunk_len;
	}
	return ret;
}

/*
 * Copy a given amount of audio samples from the DSP mic buffer starting at
 * mic_read_offset, to the dma_area of the pcm runtime. The source buffer may
 * wrap around. mic_read_offset is updated after successful copy.
 * @amount: amount of samples to copy, in bytes.
 *
 * Return: Zero if successful, or a negative error code on failure.
 */
static int rt5677_spi_copy(struct rt5677_dsp *rt5677_dsp, u32 amount)
{
	int ret = 0;
	u32 target;

	if (amount == 0)
		return ret;

	target = rt5677_dsp->mic_read_offset + amount;
	/* Copy the first chunk in DSP's mic buffer */
	ret |= rt5677_spi_copy_block(rt5677_dsp, rt5677_dsp->mic_read_offset,
			min(target, RT5677_MIC_BUF_BYTES));

	if (target >= RT5677_MIC_BUF_BYTES) {
		/* Wrap around, copy the second chunk */
		target -= RT5677_MIC_BUF_BYTES;
		ret |= rt5677_spi_copy_block(rt5677_dsp, 0, target);
	}

	if (!ret)
		rt5677_dsp->mic_read_offset = target;
	return ret;
}

/*
 * A delayed work that streams audio samples from the DSP mic buffer to the
 * dma_area of the pcm runtime via SPI.
 */
static void rt5677_spi_copy_work(struct work_struct *work)
{
	struct rt5677_dsp *rt5677_dsp =
		container_of(work, struct rt5677_dsp, copy_work.work);
	struct snd_pcm_runtime *runtime;
	u32 mic_write_offset;
	size_t new_bytes, copy_bytes, period_bytes;
	unsigned int delay;
	int ret = 0;

	/* Ensure runtime->dma_area buffer does not go away while copying. */
	mutex_lock(&rt5677_dsp->dma_lock);
	if (!rt5677_dsp->substream) {
		dev_err(rt5677_dsp->dev, "No pcm substream\n");
		goto done;
	}

	runtime = rt5677_dsp->substream->runtime;

	if (rt5677_spi_mic_write_offset(&mic_write_offset)) {
		dev_err(rt5677_dsp->dev, "No mic_write_offset\n");
		goto done;
	}

	/* If this is the first time that we've asked for streaming data after
	 * a hotword is fired, we should start reading from the previous 2
	 * seconds of audio from wherever the mic_write_offset is currently.
	 */
	if (rt5677_dsp->new_hotword) {
		rt5677_dsp->new_hotword = false;
		/* See if buffer wraparound happens */
		if (mic_write_offset < RT5677_MIC_BUF_FIRST_READ_SIZE)
			rt5677_dsp->mic_read_offset = RT5677_MIC_BUF_BYTES -
					(RT5677_MIC_BUF_FIRST_READ_SIZE -
					mic_write_offset);
		else
			rt5677_dsp->mic_read_offset = mic_write_offset -
					RT5677_MIC_BUF_FIRST_READ_SIZE;
	}

	/* Calculate the amount of new samples in bytes */
	if (rt5677_dsp->mic_read_offset <= mic_write_offset)
		new_bytes = mic_write_offset - rt5677_dsp->mic_read_offset;
	else
		new_bytes = RT5677_MIC_BUF_BYTES + mic_write_offset
				- rt5677_dsp->mic_read_offset;

	/* Copy all new samples from DSP mic buffer, one period at a time */
	period_bytes = snd_pcm_lib_period_bytes(rt5677_dsp->substream);
	while (new_bytes) {
		copy_bytes = min(new_bytes, period_bytes
				- rt5677_dsp->avail_bytes);
		ret = rt5677_spi_copy(rt5677_dsp, copy_bytes);
		if (ret) {
			dev_err(rt5677_dsp->dev, "Copy failed %d\n", ret);
			goto done;
		}
		rt5677_dsp->avail_bytes += copy_bytes;
		if (rt5677_dsp->avail_bytes >= period_bytes) {
			snd_pcm_period_elapsed(rt5677_dsp->substream);
			rt5677_dsp->avail_bytes = 0;
		}
		new_bytes -= copy_bytes;
	}

	delay = bytes_to_frames(runtime, period_bytes) / (runtime->rate / 1000);
	schedule_delayed_work(&rt5677_dsp->copy_work, msecs_to_jiffies(delay));
done:
	mutex_unlock(&rt5677_dsp->dma_lock);
}

static int rt5677_spi_pcm_new(struct snd_soc_component *component,
			      struct snd_soc_pcm_runtime *rtd)
{
	snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, SNDRV_DMA_TYPE_VMALLOC,
					      NULL, 0, 0);
	return 0;
}

static int rt5677_spi_pcm_probe(struct snd_soc_component *component)
{
	struct rt5677_dsp *rt5677_dsp;

	rt5677_dsp = devm_kzalloc(component->dev, sizeof(*rt5677_dsp),
			GFP_KERNEL);
	if (!rt5677_dsp)
		return -ENOMEM;
	rt5677_dsp->dev = &g_spi->dev;
	mutex_init(&rt5677_dsp->dma_lock);
	INIT_DELAYED_WORK(&rt5677_dsp->copy_work, rt5677_spi_copy_work);

	snd_soc_component_set_drvdata(component, rt5677_dsp);
	return 0;
}

static const struct snd_soc_component_driver rt5677_spi_dai_component = {
	.name		= DRV_NAME,
	.probe		= rt5677_spi_pcm_probe,
	.open		= rt5677_spi_pcm_open,
	.close		= rt5677_spi_pcm_close,
	.hw_params	= rt5677_spi_hw_params,
	.hw_free	= rt5677_spi_hw_free,
	.prepare	= rt5677_spi_prepare,
	.pointer	= rt5677_spi_pcm_pointer,
	.pcm_construct	= rt5677_spi_pcm_new,
};

/* Select a suitable transfer command for the next transfer to ensure
 * the transfer address is always naturally aligned while minimizing
 * the total number of transfers required.
 *
 * 3 transfer commands are available:
 * RT5677_SPI_READ/WRITE_16:	Transfer 2 bytes
 * RT5677_SPI_READ/WRITE_32:	Transfer 4 bytes
 * RT5677_SPI_READ/WRITE_BURST:	Transfer any multiples of 8 bytes
 *
 * Note:
 * 16 Bit writes and reads are restricted to the address range
 * 0x18020000 ~ 0x18021000
 *
 * For example, reading 256 bytes at 0x60030004 uses the following commands:
 * 0x60030004 RT5677_SPI_READ_32	4 bytes
 * 0x60030008 RT5677_SPI_READ_BURST	240 bytes
 * 0x600300F8 RT5677_SPI_READ_BURST	8 bytes
 * 0x60030100 RT5677_SPI_READ_32	4 bytes
 *
 * Input:
 * @read: true for read commands; false for write commands
 * @align: alignment of the next transfer address
 * @remain: number of bytes remaining to transfer
 *
 * Output:
 * @len: number of bytes to transfer with the selected command
 * Returns the selected command
 */
static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len)
{
	u8 cmd;

	if (align == 4 || remain <= 4) {
		cmd = RT5677_SPI_READ_32;
		*len = 4;
	} else {
		cmd = RT5677_SPI_READ_BURST;
		*len = (((remain - 1) >> 3) + 1) << 3;
		*len = min_t(u32, *len, RT5677_SPI_BURST_LEN);
	}
	return read ? cmd : cmd + 1;
}

/* Copy dstlen bytes from src to dst, while reversing byte order for each word.
 * If srclen < dstlen, zeros are padded.
 */
static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen)
{
	u32 w, i, si;
	u32 word_size = min_t(u32, dstlen, 8);

	for (w = 0; w < dstlen; w += word_size) {
		for (i = 0; i < word_size && i + w < dstlen; i++) {
			si = w + word_size - i - 1;
			dst[w + i] = si < srclen ? src[si] : 0;
		}
	}
}

/* Read DSP address space using SPI. addr and len have to be 4-byte aligned. */
int rt5677_spi_read(u32 addr, void *rxbuf, size_t len)
{
	u32 offset;
	int status = 0;
	struct spi_transfer t[2];
	struct spi_message m;
	/* +4 bytes is for the DummyPhase following the AddressPhase */
	u8 header[RT5677_SPI_HEADER + 4];
	u8 body[RT5677_SPI_BURST_LEN];
	u8 spi_cmd;
	u8 *cb = rxbuf;

	if (!g_spi)
		return -ENODEV;

	if ((addr & 3) || (len & 3)) {
		dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len);
		return -EACCES;
	}

	memset(t, 0, sizeof(t));
	t[0].tx_buf = header;
	t[0].len = sizeof(header);
	t[0].speed_hz = RT5677_SPI_FREQ;
	t[1].rx_buf = body;
	t[1].speed_hz = RT5677_SPI_FREQ;
	spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));

	for (offset = 0; offset < len; offset += t[1].len) {
		spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7,
				len - offset, &t[1].len);

		/* Construct SPI message header */
		header[0] = spi_cmd;
		header[1] = ((addr + offset) & 0xff000000) >> 24;
		header[2] = ((addr + offset) & 0x00ff0000) >> 16;
		header[3] = ((addr + offset) & 0x0000ff00) >> 8;
		header[4] = ((addr + offset) & 0x000000ff) >> 0;

		mutex_lock(&spi_mutex);
		status |= spi_sync(g_spi, &m);
		mutex_unlock(&spi_mutex);


		/* Copy data back to caller buffer */
		rt5677_spi_reverse(cb + offset, len - offset, body, t[1].len);
	}
	return status;
}
EXPORT_SYMBOL_GPL(rt5677_spi_read);

/* Write DSP address space using SPI. addr has to be 4-byte aligned.
 * If len is not 4-byte aligned, then extra zeros are written at the end
 * as padding.
 */
int rt5677_spi_write(u32 addr, const void *txbuf, size_t len)
{
	u32 offset;
	int status = 0;
	struct spi_transfer t;
	struct spi_message m;
	/* +1 byte is for the DummyPhase following the DataPhase */
	u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1];
	u8 *body = buf + RT5677_SPI_HEADER;
	u8 spi_cmd;
	const u8 *cb = txbuf;

	if (!g_spi)
		return -ENODEV;

	if (addr & 3) {
		dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len);
		return -EACCES;
	}

	memset(&t, 0, sizeof(t));
	t.tx_buf = buf;
	t.speed_hz = RT5677_SPI_FREQ;
	spi_message_init_with_transfers(&m, &t, 1);

	for (offset = 0; offset < len;) {
		spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7,
				len - offset, &t.len);

		/* Construct SPI message header */
		buf[0] = spi_cmd;
		buf[1] = ((addr + offset) & 0xff000000) >> 24;
		buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
		buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
		buf[4] = ((addr + offset) & 0x000000ff) >> 0;

		/* Fetch data from caller buffer */
		rt5677_spi_reverse(body, t.len, cb + offset, len - offset);
		offset += t.len;
		t.len += RT5677_SPI_HEADER + 1;

		mutex_lock(&spi_mutex);
		status |= spi_sync(g_spi, &m);
		mutex_unlock(&spi_mutex);
	}
	return status;
}
EXPORT_SYMBOL_GPL(rt5677_spi_write);

int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw)
{
	return rt5677_spi_write(addr, fw->data, fw->size);
}
EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware);

void rt5677_spi_hotword_detected(void)
{
	struct rt5677_dsp *rt5677_dsp;

	if (!g_spi)
		return;

	rt5677_dsp = dev_get_drvdata(&g_spi->dev);
	if (!rt5677_dsp) {
		dev_err(&g_spi->dev, "Can't get rt5677_dsp\n");
		return;
	}

	mutex_lock(&rt5677_dsp->dma_lock);
	dev_info(rt5677_dsp->dev, "Hotword detected\n");
	rt5677_dsp->new_hotword = true;
	mutex_unlock(&rt5677_dsp->dma_lock);

	schedule_delayed_work(&rt5677_dsp->copy_work, 0);
}
EXPORT_SYMBOL_GPL(rt5677_spi_hotword_detected);

static int rt5677_spi_probe(struct spi_device *spi)
{
	int ret;

	g_spi = spi;

	ret = snd_soc_register_component(&spi->dev, &rt5677_spi_dai_component,
					 &rt5677_spi_dai, 1);
	if (ret < 0)
		dev_err(&spi->dev, "Failed to register component.\n");

	return ret;
}

static int rt5677_spi_remove(struct spi_device *spi)
{
	snd_soc_unregister_component(&spi->dev);
	return 0;
}

static const struct acpi_device_id rt5677_spi_acpi_id[] = {
	{ "RT5677AA", 0 },
	{ }
};
MODULE_DEVICE_TABLE(acpi, rt5677_spi_acpi_id);

static struct spi_driver rt5677_spi_driver = {
	.driver = {
		.name = DRV_NAME,
		.acpi_match_table = ACPI_PTR(rt5677_spi_acpi_id),
	},
	.probe = rt5677_spi_probe,
	.remove = rt5677_spi_remove,
};
module_spi_driver(rt5677_spi_driver);

MODULE_DESCRIPTION("ASoC RT5677 SPI driver");
MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
af48f1d0 OC	2	/*
	3	* rt5677-spi.c -- RT5677 ALSA SoC audio codec driver
	4	*
	5	* Copyright 2013 Realtek Semiconductor Corp.
	6	* Author: Oder Chiou <oder_chiou@realtek.com>
af48f1d0 OC	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/input.h>
	11	#include <linux/spi/spi.h>
	12	#include <linux/device.h>
	13	#include <linux/init.h>
	14	#include <linux/delay.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/irq.h>
	17	#include <linux/slab.h>
af48f1d0	18	#include <linux/sched.h>
af48f1d0	19	#include <linux/uaccess.h>
af48f1d0 OC	20	#include <linux/regulator/consumer.h>
	21	#include <linux/pm_qos.h>
	22	#include <linux/sysfs.h>
	23	#include <linux/clk.h>
	24	#include <linux/firmware.h>
2b070f67	25	#include <linux/acpi.h>
af48f1d0	26
a0e0d135 BZ	27	#include <sound/soc.h>
a0e0d135 BZ	28
af48f1d0 OC	29	#include "rt5677-spi.h"
af48f1d0 OC	30
b9960f6e CM	31	#define DRV_NAME "rt5677spi"
b9960f6e CM	32
7d4d443e BZ	33	#define RT5677_SPI_BURST_LEN 240
	34	#define RT5677_SPI_HEADER 5
	35	#define RT5677_SPI_FREQ 6000000
	36
	37	/* The AddressPhase and DataPhase of SPI commands are MSB first on the wire.
	38	* DataPhase word size of 16-bit commands is 2 bytes.
	39	* DataPhase word size of 32-bit commands is 4 bytes.
	40	* DataPhase word size of burst commands is 8 bytes.
	41	* The DSP CPU is little-endian.
	42	*/
	43	#define RT5677_SPI_WRITE_BURST 0x5
	44	#define RT5677_SPI_READ_BURST 0x4
	45	#define RT5677_SPI_WRITE_32 0x3
	46	#define RT5677_SPI_READ_32 0x2
	47	#define RT5677_SPI_WRITE_16 0x1
	48	#define RT5677_SPI_READ_16 0x0
	49
a0e0d135 BZ	50	#define RT5677_BUF_BYTES_TOTAL 0x20000
	51	#define RT5677_MIC_BUF_ADDR 0x60030000
	52	#define RT5677_MODEL_ADDR 0x5FFC9800
	53	#define RT5677_MIC_BUF_BYTES ((u32)(RT5677_BUF_BYTES_TOTAL - \
	54	sizeof(u32)))
	55	#define RT5677_MIC_BUF_FIRST_READ_SIZE 0x10000
	56
af48f1d0	57	static struct spi_device *g_spi;
7d4d443e	58	static DEFINE_MUTEX(spi_mutex);
af48f1d0	59
a0e0d135 BZ	60	struct rt5677_dsp {
	61	struct device *dev;
	62	struct delayed_work copy_work;
	63	struct mutex dma_lock;
	64	struct snd_pcm_substream *substream;
	65	size_t dma_offset; /* zero-based offset into runtime->dma_area */
	66	size_t avail_bytes; /* number of new bytes since last period */
	67	u32 mic_read_offset; /* zero-based offset into DSP's mic buffer */
	68	bool new_hotword; /* a new hotword is fired */
	69	};
	70
	71	static const struct snd_pcm_hardware rt5677_spi_pcm_hardware = {
	72	.info = SNDRV_PCM_INFO_MMAP \|
	73	SNDRV_PCM_INFO_MMAP_VALID \|
	74	SNDRV_PCM_INFO_INTERLEAVED,
	75	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	76	.period_bytes_min = PAGE_SIZE,
	77	.period_bytes_max = RT5677_BUF_BYTES_TOTAL / 8,
	78	.periods_min = 8,
	79	.periods_max = 8,
	80	.channels_min = 1,
	81	.channels_max = 1,
	82	.buffer_bytes_max = RT5677_BUF_BYTES_TOTAL,
	83	};
	84
	85	static struct snd_soc_dai_driver rt5677_spi_dai = {
	86	/* The DAI name "rt5677-dsp-cpu-dai" is not used. The actual DAI name
	87	* registered with ASoC is the name of the device "spi-RT5677AA:00",
	88	* because we only have one DAI. See snd_soc_register_dais().
	89	*/
	90	.name = "rt5677-dsp-cpu-dai",
	91	.id = 0,
	92	.capture = {
	93	.stream_name = "DSP Capture",
	94	.channels_min = 1,
	95	.channels_max = 1,
	96	.rates = SNDRV_PCM_RATE_16000,
	97	.formats = SNDRV_PCM_FMTBIT_S16_LE,
	98	},
	99	};
	100
	101	/* PCM for streaming audio from the DSP buffer */
	102	static int rt5677_spi_pcm_open(
	103	struct snd_soc_component *component,
	104	struct snd_pcm_substream *substream)
	105	{
	106	snd_soc_set_runtime_hwparams(substream, &rt5677_spi_pcm_hardware);
	107	return 0;
	108	}
	109
	110	static int rt5677_spi_pcm_close(
	111	struct snd_soc_component *component,
	112	struct snd_pcm_substream *substream)
	113	{
a0e0d135 BZ	114	struct rt5677_dsp *rt5677_dsp =
	115	snd_soc_component_get_drvdata(component);
	116
	117	cancel_delayed_work_sync(&rt5677_dsp->copy_work);
	118	return 0;
	119	}
	120
	121	static int rt5677_spi_hw_params(
	122	struct snd_soc_component *component,
	123	struct snd_pcm_substream *substream,
	124	struct snd_pcm_hw_params *hw_params)
	125	{
	126	struct rt5677_dsp *rt5677_dsp =
	127	snd_soc_component_get_drvdata(component);
	128	int ret;
	129
	130	mutex_lock(&rt5677_dsp->dma_lock);
f541220c	131	ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
a0e0d135 BZ	132	rt5677_dsp->substream = substream;
	133	mutex_unlock(&rt5677_dsp->dma_lock);
	134
	135	return ret;
	136	}
	137
	138	static int rt5677_spi_hw_free(
	139	struct snd_soc_component *component,
	140	struct snd_pcm_substream *substream)
	141	{
	142	struct rt5677_dsp *rt5677_dsp =
	143	snd_soc_component_get_drvdata(component);
	144
	145	mutex_lock(&rt5677_dsp->dma_lock);
6442793a	146	rt5677_dsp->substream = NULL;
a0e0d135 BZ	147	mutex_unlock(&rt5677_dsp->dma_lock);
a0e0d135 BZ	148
f541220c	149	return snd_pcm_lib_free_pages(substream);
a0e0d135 BZ	150	}
	151
	152	static int rt5677_spi_prepare(
	153	struct snd_soc_component *component,
	154	struct snd_pcm_substream *substream)
	155	{
	156	struct rt5677_dsp *rt5677_dsp =
	157	snd_soc_component_get_drvdata(component);
	158
	159	rt5677_dsp->dma_offset = 0;
	160	rt5677_dsp->avail_bytes = 0;
	161	return 0;
	162	}
	163
	164	static snd_pcm_uframes_t rt5677_spi_pcm_pointer(
	165	struct snd_soc_component *component,
	166	struct snd_pcm_substream *substream)
	167	{
	168	struct snd_pcm_runtime *runtime = substream->runtime;
	169	struct rt5677_dsp *rt5677_dsp =
	170	snd_soc_component_get_drvdata(component);
	171
	172	return bytes_to_frames(runtime, rt5677_dsp->dma_offset);
	173	}
	174
	175	static int rt5677_spi_mic_write_offset(u32 *mic_write_offset)
	176	{
	177	int ret;
	178	/* Grab the first 4 bytes that hold the write pointer on the
	179	* dsp, and check to make sure that it points somewhere inside the
	180	* buffer.
	181	*/
	182	ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR, mic_write_offset,
	183	sizeof(u32));
	184	if (ret)
	185	return ret;
	186	/* Adjust the offset so that it's zero-based */
	187	mic_write_offset = mic_write_offset - sizeof(u32);
	188	return *mic_write_offset < RT5677_MIC_BUF_BYTES ? 0 : -EFAULT;
	189	}
	190
	191	/*
	192	* Copy one contiguous block of audio samples from the DSP mic buffer to the
	193	* dma_area of the pcm runtime. The receiving buffer may wrap around.
	194	* @begin: start offset of the block to copy, in bytes.
	195	* @end: offset of the first byte after the block to copy, must be greater
	196	* than or equal to begin.
	197	*
	198	* Return: Zero if successful, or a negative error code on failure.
	199	*/
	200	static int rt5677_spi_copy_block(struct rt5677_dsp *rt5677_dsp,
	201	u32 begin, u32 end)
	202	{
	203	struct snd_pcm_runtime *runtime = rt5677_dsp->substream->runtime;
	204	size_t bytes_per_frame = frames_to_bytes(runtime, 1);
	205	size_t first_chunk_len, second_chunk_len;
	206	int ret;
	207
	208	if (begin > end \|\| runtime->dma_bytes < 2 * bytes_per_frame) {
	209	dev_err(rt5677_dsp->dev,
	210	"Invalid copy from (%u, %u), dma_area size %zu\n",
	211	begin, end, runtime->dma_bytes);
	212	return -EINVAL;
	213	}
214
215	/* The block to copy is empty */
216	if (begin == end)
217	return 0;
218
219	/* If the incoming chunk is too big for the receiving buffer, only the
220	* last "receiving buffer size - one frame" bytes are copied.
221	*/
222	if (end - begin > runtime->dma_bytes - bytes_per_frame)
223	begin = end - (runtime->dma_bytes - bytes_per_frame);
224
225	/* May need to split to two chunks, calculate the size of each */
226	first_chunk_len = end - begin;
227	second_chunk_len = 0;
228	if (rt5677_dsp->dma_offset + first_chunk_len > runtime->dma_bytes) {
229	/* Receiving buffer wrapped around */
230	second_chunk_len = first_chunk_len;
231	first_chunk_len = runtime->dma_bytes - rt5677_dsp->dma_offset;
232	second_chunk_len -= first_chunk_len;
233	}
234
235	/* Copy first chunk */
236	ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR + sizeof(u32) + begin,
237	runtime->dma_area + rt5677_dsp->dma_offset,
238	first_chunk_len);
239	if (ret)
240	return ret;
241	rt5677_dsp->dma_offset += first_chunk_len;
242	if (rt5677_dsp->dma_offset == runtime->dma_bytes)
243	rt5677_dsp->dma_offset = 0;
244
245	/* Copy second chunk */
246	if (second_chunk_len) {
247	ret = rt5677_spi_read(RT5677_MIC_BUF_ADDR + sizeof(u32) +
248	begin + first_chunk_len, runtime->dma_area,
249	second_chunk_len);
250	if (!ret)
251	rt5677_dsp->dma_offset = second_chunk_len;
252	}
253	return ret;
254	}
255
256	/*
257	* Copy a given amount of audio samples from the DSP mic buffer starting at
258	* mic_read_offset, to the dma_area of the pcm runtime. The source buffer may
259	* wrap around. mic_read_offset is updated after successful copy.
260	* @amount: amount of samples to copy, in bytes.
261	*
262	* Return: Zero if successful, or a negative error code on failure.
263	*/
264	static int rt5677_spi_copy(struct rt5677_dsp *rt5677_dsp, u32 amount)
265	{
266	int ret = 0;
267	u32 target;
268
269	if (amount == 0)
270	return ret;
271
272	target = rt5677_dsp->mic_read_offset + amount;
273	/* Copy the first chunk in DSP's mic buffer */
274	ret \|= rt5677_spi_copy_block(rt5677_dsp, rt5677_dsp->mic_read_offset,
275	min(target, RT5677_MIC_BUF_BYTES));
276
277	if (target >= RT5677_MIC_BUF_BYTES) {
278	/* Wrap around, copy the second chunk */
279	target -= RT5677_MIC_BUF_BYTES;
280	ret \|= rt5677_spi_copy_block(rt5677_dsp, 0, target);
281	}
282
283	if (!ret)
284	rt5677_dsp->mic_read_offset = target;
285	return ret;
286	}
287
288	/*
289	* A delayed work that streams audio samples from the DSP mic buffer to the
290	* dma_area of the pcm runtime via SPI.
291	*/
292	static void rt5677_spi_copy_work(struct work_struct *work)
293	{
294	struct rt5677_dsp *rt5677_dsp =
295	container_of(work, struct rt5677_dsp, copy_work.work);
296	struct snd_pcm_runtime *runtime;
297	u32 mic_write_offset;
298	size_t new_bytes, copy_bytes, period_bytes;
299	unsigned int delay;
300	int ret = 0;
301
302	/* Ensure runtime->dma_area buffer does not go away while copying. */
303	mutex_lock(&rt5677_dsp->dma_lock);
304	if (!rt5677_dsp->substream) {
305	dev_err(rt5677_dsp->dev, "No pcm substream\n");
306	goto done;
307	}
308
309	runtime = rt5677_dsp->substream->runtime;
310
311	if (rt5677_spi_mic_write_offset(&mic_write_offset)) {
312	dev_err(rt5677_dsp->dev, "No mic_write_offset\n");
313	goto done;
314	}
315
316	/* If this is the first time that we've asked for streaming data after
317	* a hotword is fired, we should start reading from the previous 2
318	* seconds of audio from wherever the mic_write_offset is currently.
319	*/
320	if (rt5677_dsp->new_hotword) {
321	rt5677_dsp->new_hotword = false;
322	/* See if buffer wraparound happens */
323	if (mic_write_offset < RT5677_MIC_BUF_FIRST_READ_SIZE)
324	rt5677_dsp->mic_read_offset = RT5677_MIC_BUF_BYTES -
325	(RT5677_MIC_BUF_FIRST_READ_SIZE -
326	mic_write_offset);
327	else
328	rt5677_dsp->mic_read_offset = mic_write_offset -
329	RT5677_MIC_BUF_FIRST_READ_SIZE;
330	}
331
332	/* Calculate the amount of new samples in bytes */
333	if (rt5677_dsp->mic_read_offset <= mic_write_offset)
334	new_bytes = mic_write_offset - rt5677_dsp->mic_read_offset;
335	else
336	new_bytes = RT5677_MIC_BUF_BYTES + mic_write_offset
337	- rt5677_dsp->mic_read_offset;
338
339	/* Copy all new samples from DSP mic buffer, one period at a time */
340	period_bytes = snd_pcm_lib_period_bytes(rt5677_dsp->substream);
341	while (new_bytes) {
342	copy_bytes = min(new_bytes, period_bytes
343	- rt5677_dsp->avail_bytes);
344	ret = rt5677_spi_copy(rt5677_dsp, copy_bytes);
345	if (ret) {
346	dev_err(rt5677_dsp->dev, "Copy failed %d\n", ret);
347	goto done;
348	}
349	rt5677_dsp->avail_bytes += copy_bytes;
350	if (rt5677_dsp->avail_bytes >= period_bytes) {
351	snd_pcm_period_elapsed(rt5677_dsp->substream);
352	rt5677_dsp->avail_bytes = 0;
353	}
354	new_bytes -= copy_bytes;
355	}
356
357	delay = bytes_to_frames(runtime, period_bytes) / (runtime->rate / 1000);
358	schedule_delayed_work(&rt5677_dsp->copy_work, msecs_to_jiffies(delay));
359	done:
360	mutex_unlock(&rt5677_dsp->dma_lock);
361	}
362
f541220c TI	363	static int rt5677_spi_pcm_new(struct snd_soc_component *component,
f541220c TI	364	struct snd_soc_pcm_runtime *rtd)
a0e0d135	365	{
f541220c TI	366	snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, SNDRV_DMA_TYPE_VMALLOC,
	367	NULL, 0, 0);
	368	return 0;
a0e0d135 BZ	369	}
	370
	371	static int rt5677_spi_pcm_probe(struct snd_soc_component *component)
	372	{
	373	struct rt5677_dsp *rt5677_dsp;
	374
	375	rt5677_dsp = devm_kzalloc(component->dev, sizeof(*rt5677_dsp),
	376	GFP_KERNEL);
f8a60435 CIK	377	if (!rt5677_dsp)
f8a60435 CIK	378	return -ENOMEM;
a0e0d135 BZ	379	rt5677_dsp->dev = &g_spi->dev;
	380	mutex_init(&rt5677_dsp->dma_lock);
	381	INIT_DELAYED_WORK(&rt5677_dsp->copy_work, rt5677_spi_copy_work);
	382
	383	snd_soc_component_set_drvdata(component, rt5677_dsp);
	384	return 0;
	385	}
	386
	387	static const struct snd_soc_component_driver rt5677_spi_dai_component = {
	388	.name = DRV_NAME,
	389	.probe = rt5677_spi_pcm_probe,
	390	.open = rt5677_spi_pcm_open,
	391	.close = rt5677_spi_pcm_close,
	392	.hw_params = rt5677_spi_hw_params,
	393	.hw_free = rt5677_spi_hw_free,
	394	.prepare = rt5677_spi_prepare,
	395	.pointer = rt5677_spi_pcm_pointer,
f541220c	396	.pcm_construct = rt5677_spi_pcm_new,
a0e0d135 BZ	397	};
a0e0d135 BZ	398
7d4d443e BZ	399	/* Select a suitable transfer command for the next transfer to ensure
	400	* the transfer address is always naturally aligned while minimizing
	401	* the total number of transfers required.
	402	*
	403	* 3 transfer commands are available:
	404	* RT5677_SPI_READ/WRITE_16: Transfer 2 bytes
	405	* RT5677_SPI_READ/WRITE_32: Transfer 4 bytes
	406	* RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes
	407	*
a46eb523 CM	408	* Note:
	409	* 16 Bit writes and reads are restricted to the address range
	410	* 0x18020000 ~ 0x18021000
	411	*
	412	* For example, reading 256 bytes at 0x60030004 uses the following commands:
7d4d443e BZ	413	* 0x60030004 RT5677_SPI_READ_32 4 bytes
	414	* 0x60030008 RT5677_SPI_READ_BURST 240 bytes
	415	* 0x600300F8 RT5677_SPI_READ_BURST 8 bytes
	416	* 0x60030100 RT5677_SPI_READ_32 4 bytes
af48f1d0	417	*
7d4d443e BZ	418	* Input:
	419	* @read: true for read commands; false for write commands
	420	* @align: alignment of the next transfer address
	421	* @remain: number of bytes remaining to transfer
af48f1d0	422	*
7d4d443e BZ	423	* Output:
	424	* @len: number of bytes to transfer with the selected command
	425	* Returns the selected command
af48f1d0	426	*/
7d4d443e	427	static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len)
af48f1d0	428	{
7d4d443e BZ	429	u8 cmd;
7d4d443e BZ	430
a46eb523	431	if (align == 4 \|\| remain <= 4) {
7d4d443e BZ	432	cmd = RT5677_SPI_READ_32;
	433	*len = 4;
	434	} else {
	435	cmd = RT5677_SPI_READ_BURST;
a46eb523 CM	436	*len = (((remain - 1) >> 3) + 1) << 3;
a46eb523 CM	437	len = min_t(u32, len, RT5677_SPI_BURST_LEN);
7d4d443e BZ	438	}
7d4d443e BZ	439	return read ? cmd : cmd + 1;
af48f1d0 OC	440	}
af48f1d0 OC	441
7d4d443e BZ	442	/* Copy dstlen bytes from src to dst, while reversing byte order for each word.
7d4d443e BZ	443	* If srclen < dstlen, zeros are padded.
af48f1d0	444	*/
7d4d443e	445	static void rt5677_spi_reverse(u8 dst, u32 dstlen, const u8 src, u32 srclen)
af48f1d0	446	{
7d4d443e BZ	447	u32 w, i, si;
	448	u32 word_size = min_t(u32, dstlen, 8);
	449
	450	for (w = 0; w < dstlen; w += word_size) {
7b8164c1	451	for (i = 0; i < word_size && i + w < dstlen; i++) {
7d4d443e BZ	452	si = w + word_size - i - 1;
7d4d443e BZ	453	dst[w + i] = si < srclen ? src[si] : 0;
af48f1d0	454	}
7d4d443e BZ	455	}
7d4d443e BZ	456	}
af48f1d0	457
a46eb523	458	/* Read DSP address space using SPI. addr and len have to be 4-byte aligned. */
7d4d443e BZ	459	int rt5677_spi_read(u32 addr, void *rxbuf, size_t len)
	460	{
	461	u32 offset;
	462	int status = 0;
	463	struct spi_transfer t[2];
	464	struct spi_message m;
	465	/* +4 bytes is for the DummyPhase following the AddressPhase */
	466	u8 header[RT5677_SPI_HEADER + 4];
	467	u8 body[RT5677_SPI_BURST_LEN];
	468	u8 spi_cmd;
	469	u8 *cb = rxbuf;
	470
	471	if (!g_spi)
	472	return -ENODEV;
	473
a46eb523	474	if ((addr & 3) \|\| (len & 3)) {
7d4d443e BZ	475	dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len);
	476	return -EACCES;
	477	}
af48f1d0	478
7d4d443e BZ	479	memset(t, 0, sizeof(t));
	480	t[0].tx_buf = header;
	481	t[0].len = sizeof(header);
	482	t[0].speed_hz = RT5677_SPI_FREQ;
	483	t[1].rx_buf = body;
	484	t[1].speed_hz = RT5677_SPI_FREQ;
	485	spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
	486
	487	for (offset = 0; offset < len; offset += t[1].len) {
	488	spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7,
	489	len - offset, &t[1].len);
	490
	491	/* Construct SPI message header */
	492	header[0] = spi_cmd;
	493	header[1] = ((addr + offset) & 0xff000000) >> 24;
	494	header[2] = ((addr + offset) & 0x00ff0000) >> 16;
	495	header[3] = ((addr + offset) & 0x0000ff00) >> 8;
	496	header[4] = ((addr + offset) & 0x000000ff) >> 0;
	497
	498	mutex_lock(&spi_mutex);
	499	status \|= spi_sync(g_spi, &m);
	500	mutex_unlock(&spi_mutex);
	501
7b8164c1	502
7d4d443e	503	/* Copy data back to caller buffer */
7b8164c1	504	rt5677_spi_reverse(cb + offset, len - offset, body, t[1].len);
7d4d443e BZ	505	}
	506	return status;
	507	}
	508	EXPORT_SYMBOL_GPL(rt5677_spi_read);
af48f1d0	509
a46eb523 CM	510	/* Write DSP address space using SPI. addr has to be 4-byte aligned.
a46eb523 CM	511	* If len is not 4-byte aligned, then extra zeros are written at the end
7d4d443e BZ	512	* as padding.
	513	*/
	514	int rt5677_spi_write(u32 addr, const void *txbuf, size_t len)
	515	{
a46eb523	516	u32 offset;
7d4d443e BZ	517	int status = 0;
	518	struct spi_transfer t;
	519	struct spi_message m;
	520	/* +1 byte is for the DummyPhase following the DataPhase */
	521	u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1];
	522	u8 *body = buf + RT5677_SPI_HEADER;
	523	u8 spi_cmd;
	524	const u8 *cb = txbuf;
	525
	526	if (!g_spi)
	527	return -ENODEV;
	528
a46eb523	529	if (addr & 3) {
7d4d443e BZ	530	dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len);
7d4d443e BZ	531	return -EACCES;
af48f1d0 OC	532	}
af48f1d0 OC	533
7d4d443e BZ	534	memset(&t, 0, sizeof(t));
	535	t.tx_buf = buf;
	536	t.speed_hz = RT5677_SPI_FREQ;
	537	spi_message_init_with_transfers(&m, &t, 1);
	538
a46eb523	539	for (offset = 0; offset < len;) {
7d4d443e	540	spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7,
a46eb523	541	len - offset, &t.len);
7d4d443e BZ	542
	543	/* Construct SPI message header */
	544	buf[0] = spi_cmd;
	545	buf[1] = ((addr + offset) & 0xff000000) >> 24;
	546	buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
	547	buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
	548	buf[4] = ((addr + offset) & 0x000000ff) >> 0;
	549
	550	/* Fetch data from caller buffer */
	551	rt5677_spi_reverse(body, t.len, cb + offset, len - offset);
	552	offset += t.len;
	553	t.len += RT5677_SPI_HEADER + 1;
	554
	555	mutex_lock(&spi_mutex);
	556	status \|= spi_sync(g_spi, &m);
	557	mutex_unlock(&spi_mutex);
	558	}
	559	return status;
	560	}
	561	EXPORT_SYMBOL_GPL(rt5677_spi_write);
af48f1d0	562
7d4d443e BZ	563	int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw)
	564	{
	565	return rt5677_spi_write(addr, fw->data, fw->size);
af48f1d0	566	}
7d4d443e	567	EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware);
af48f1d0	568
a0e0d135 BZ	569	void rt5677_spi_hotword_detected(void)
	570	{
	571	struct rt5677_dsp *rt5677_dsp;
	572
	573	if (!g_spi)
	574	return;
	575
	576	rt5677_dsp = dev_get_drvdata(&g_spi->dev);
	577	if (!rt5677_dsp) {
	578	dev_err(&g_spi->dev, "Can't get rt5677_dsp\n");
	579	return;
	580	}
	581
	582	mutex_lock(&rt5677_dsp->dma_lock);
	583	dev_info(rt5677_dsp->dev, "Hotword detected\n");
	584	rt5677_dsp->new_hotword = true;
	585	mutex_unlock(&rt5677_dsp->dma_lock);
	586
	587	schedule_delayed_work(&rt5677_dsp->copy_work, 0);
	588	}
	589	EXPORT_SYMBOL_GPL(rt5677_spi_hotword_detected);
	590
af48f1d0 OC	591	static int rt5677_spi_probe(struct spi_device *spi)
af48f1d0 OC	592	{
a0e0d135 BZ	593	int ret;
a0e0d135 BZ	594
af48f1d0	595	g_spi = spi;
a0e0d135 BZ	596
	597	ret = snd_soc_register_component(&spi->dev, &rt5677_spi_dai_component,
	598	&rt5677_spi_dai, 1);
	599	if (ret < 0)
	600	dev_err(&spi->dev, "Failed to register component.\n");
	601
	602	return ret;
	603	}
	604
	605	static int rt5677_spi_remove(struct spi_device *spi)
	606	{
	607	snd_soc_unregister_component(&spi->dev);
af48f1d0 OC	608	return 0;
	609	}
	610
2b070f67 OC	611	static const struct acpi_device_id rt5677_spi_acpi_id[] = {
	612	{ "RT5677AA", 0 },
	613	{ }
	614	};
	615	MODULE_DEVICE_TABLE(acpi, rt5677_spi_acpi_id);
	616
af48f1d0 OC	617	static struct spi_driver rt5677_spi_driver = {
af48f1d0 OC	618	.driver = {
b9960f6e	619	.name = DRV_NAME,
2b070f67	620	.acpi_match_table = ACPI_PTR(rt5677_spi_acpi_id),
af48f1d0 OC	621	},
af48f1d0 OC	622	.probe = rt5677_spi_probe,
a0e0d135	623	.remove = rt5677_spi_remove,
af48f1d0 OC	624	};
	625	module_spi_driver(rt5677_spi_driver);
	626
	627	MODULE_DESCRIPTION("ASoC RT5677 SPI driver");
	628	MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
	629	MODULE_LICENSE("GPL v2");