[linux-2.6-block.git] / sound / soc / codecs / rt5677-spi.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * rt5677-spi.c  --  RT5677 ALSA SoC audio codec driver
 *
 * Copyright 2013 Realtek Semiconductor Corp.
 * Author: Oder Chiou <oder_chiou@realtek.com>
 */

#include <linux/module.h>
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/uaccess.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_qos.h>
#include <linux/sysfs.h>
#include <linux/clk.h>
#include <linux/firmware.h>
#include <linux/acpi.h>

#include "rt5677-spi.h"

#define RT5677_SPI_BURST_LEN	240
#define RT5677_SPI_HEADER	5
#define RT5677_SPI_FREQ		6000000

/* The AddressPhase and DataPhase of SPI commands are MSB first on the wire.
 * DataPhase word size of 16-bit commands is 2 bytes.
 * DataPhase word size of 32-bit commands is 4 bytes.
 * DataPhase word size of burst commands is 8 bytes.
 * The DSP CPU is little-endian.
 */
#define RT5677_SPI_WRITE_BURST	0x5
#define RT5677_SPI_READ_BURST	0x4
#define RT5677_SPI_WRITE_32	0x3
#define RT5677_SPI_READ_32	0x2
#define RT5677_SPI_WRITE_16	0x1
#define RT5677_SPI_READ_16	0x0

static struct spi_device *g_spi;
static DEFINE_MUTEX(spi_mutex);

/* Select a suitable transfer command for the next transfer to ensure
 * the transfer address is always naturally aligned while minimizing
 * the total number of transfers required.
 *
 * 3 transfer commands are available:
 * RT5677_SPI_READ/WRITE_16:	Transfer 2 bytes
 * RT5677_SPI_READ/WRITE_32:	Transfer 4 bytes
 * RT5677_SPI_READ/WRITE_BURST:	Transfer any multiples of 8 bytes
 *
 * Note:
 * 16 Bit writes and reads are restricted to the address range
 * 0x18020000 ~ 0x18021000
 *
 * For example, reading 256 bytes at 0x60030004 uses the following commands:
 * 0x60030004 RT5677_SPI_READ_32	4 bytes
 * 0x60030008 RT5677_SPI_READ_BURST	240 bytes
 * 0x600300F8 RT5677_SPI_READ_BURST	8 bytes
 * 0x60030100 RT5677_SPI_READ_32	4 bytes
 *
 * Input:
 * @read: true for read commands; false for write commands
 * @align: alignment of the next transfer address
 * @remain: number of bytes remaining to transfer
 *
 * Output:
 * @len: number of bytes to transfer with the selected command
 * Returns the selected command
 */
static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len)
{
	u8 cmd;

	if (align == 4 || remain <= 4) {
		cmd = RT5677_SPI_READ_32;
		*len = 4;
	} else {
		cmd = RT5677_SPI_READ_BURST;
		*len = (((remain - 1) >> 3) + 1) << 3;
		*len = min_t(u32, *len, RT5677_SPI_BURST_LEN);
	}
	return read ? cmd : cmd + 1;
}

/* Copy dstlen bytes from src to dst, while reversing byte order for each word.
 * If srclen < dstlen, zeros are padded.
 */
static void rt5677_spi_reverse(u8 *dst, u32 dstlen, const u8 *src, u32 srclen)
{
	u32 w, i, si;
	u32 word_size = min_t(u32, dstlen, 8);

	for (w = 0; w < dstlen; w += word_size) {
		for (i = 0; i < word_size && i + w < dstlen; i++) {
			si = w + word_size - i - 1;
			dst[w + i] = si < srclen ? src[si] : 0;
		}
	}
}

/* Read DSP address space using SPI. addr and len have to be 4-byte aligned. */
int rt5677_spi_read(u32 addr, void *rxbuf, size_t len)
{
	u32 offset;
	int status = 0;
	struct spi_transfer t[2];
	struct spi_message m;
	/* +4 bytes is for the DummyPhase following the AddressPhase */
	u8 header[RT5677_SPI_HEADER + 4];
	u8 body[RT5677_SPI_BURST_LEN];
	u8 spi_cmd;
	u8 *cb = rxbuf;

	if (!g_spi)
		return -ENODEV;

	if ((addr & 3) || (len & 3)) {
		dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len);
		return -EACCES;
	}

	memset(t, 0, sizeof(t));
	t[0].tx_buf = header;
	t[0].len = sizeof(header);
	t[0].speed_hz = RT5677_SPI_FREQ;
	t[1].rx_buf = body;
	t[1].speed_hz = RT5677_SPI_FREQ;
	spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));

	for (offset = 0; offset < len; offset += t[1].len) {
		spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7,
				len - offset, &t[1].len);

		/* Construct SPI message header */
		header[0] = spi_cmd;
		header[1] = ((addr + offset) & 0xff000000) >> 24;
		header[2] = ((addr + offset) & 0x00ff0000) >> 16;
		header[3] = ((addr + offset) & 0x0000ff00) >> 8;
		header[4] = ((addr + offset) & 0x000000ff) >> 0;

		mutex_lock(&spi_mutex);
		status |= spi_sync(g_spi, &m);
		mutex_unlock(&spi_mutex);


		/* Copy data back to caller buffer */
		rt5677_spi_reverse(cb + offset, len - offset, body, t[1].len);
	}
	return status;
}
EXPORT_SYMBOL_GPL(rt5677_spi_read);

/* Write DSP address space using SPI. addr has to be 4-byte aligned.
 * If len is not 4-byte aligned, then extra zeros are written at the end
 * as padding.
 */
int rt5677_spi_write(u32 addr, const void *txbuf, size_t len)
{
	u32 offset;
	int status = 0;
	struct spi_transfer t;
	struct spi_message m;
	/* +1 byte is for the DummyPhase following the DataPhase */
	u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1];
	u8 *body = buf + RT5677_SPI_HEADER;
	u8 spi_cmd;
	const u8 *cb = txbuf;

	if (!g_spi)
		return -ENODEV;

	if (addr & 3) {
		dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len);
		return -EACCES;
	}

	memset(&t, 0, sizeof(t));
	t.tx_buf = buf;
	t.speed_hz = RT5677_SPI_FREQ;
	spi_message_init_with_transfers(&m, &t, 1);

	for (offset = 0; offset < len;) {
		spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7,
				len - offset, &t.len);

		/* Construct SPI message header */
		buf[0] = spi_cmd;
		buf[1] = ((addr + offset) & 0xff000000) >> 24;
		buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
		buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
		buf[4] = ((addr + offset) & 0x000000ff) >> 0;

		/* Fetch data from caller buffer */
		rt5677_spi_reverse(body, t.len, cb + offset, len - offset);
		offset += t.len;
		t.len += RT5677_SPI_HEADER + 1;

		mutex_lock(&spi_mutex);
		status |= spi_sync(g_spi, &m);
		mutex_unlock(&spi_mutex);
	}
	return status;
}
EXPORT_SYMBOL_GPL(rt5677_spi_write);

int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw)
{
	return rt5677_spi_write(addr, fw->data, fw->size);
}
EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware);

static int rt5677_spi_probe(struct spi_device *spi)
{
	g_spi = spi;
	return 0;
}

static const struct acpi_device_id rt5677_spi_acpi_id[] = {
	{ "RT5677AA", 0 },
	{ }
};
MODULE_DEVICE_TABLE(acpi, rt5677_spi_acpi_id);

static struct spi_driver rt5677_spi_driver = {
	.driver = {
		.name = "rt5677",
		.acpi_match_table = ACPI_PTR(rt5677_spi_acpi_id),
	},
	.probe = rt5677_spi_probe,
};
module_spi_driver(rt5677_spi_driver);

MODULE_DESCRIPTION("ASoC RT5677 SPI driver");
MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
af48f1d0 OC	2	/*
	3	* rt5677-spi.c -- RT5677 ALSA SoC audio codec driver
	4	*
	5	* Copyright 2013 Realtek Semiconductor Corp.
	6	* Author: Oder Chiou <oder_chiou@realtek.com>
af48f1d0 OC	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/input.h>
	11	#include <linux/spi/spi.h>
	12	#include <linux/device.h>
	13	#include <linux/init.h>
	14	#include <linux/delay.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/irq.h>
	17	#include <linux/slab.h>
af48f1d0	18	#include <linux/sched.h>
af48f1d0	19	#include <linux/uaccess.h>
af48f1d0 OC	20	#include <linux/regulator/consumer.h>
	21	#include <linux/pm_qos.h>
	22	#include <linux/sysfs.h>
	23	#include <linux/clk.h>
	24	#include <linux/firmware.h>
2b070f67	25	#include <linux/acpi.h>
af48f1d0 OC	26
	27	#include "rt5677-spi.h"
	28
7d4d443e BZ	29	#define RT5677_SPI_BURST_LEN 240
	30	#define RT5677_SPI_HEADER 5
	31	#define RT5677_SPI_FREQ 6000000
	32
	33	/* The AddressPhase and DataPhase of SPI commands are MSB first on the wire.
	34	* DataPhase word size of 16-bit commands is 2 bytes.
	35	* DataPhase word size of 32-bit commands is 4 bytes.
	36	* DataPhase word size of burst commands is 8 bytes.
	37	* The DSP CPU is little-endian.
	38	*/
	39	#define RT5677_SPI_WRITE_BURST 0x5
	40	#define RT5677_SPI_READ_BURST 0x4
	41	#define RT5677_SPI_WRITE_32 0x3
	42	#define RT5677_SPI_READ_32 0x2
	43	#define RT5677_SPI_WRITE_16 0x1
	44	#define RT5677_SPI_READ_16 0x0
	45
af48f1d0	46	static struct spi_device *g_spi;
7d4d443e	47	static DEFINE_MUTEX(spi_mutex);
af48f1d0	48
7d4d443e BZ	49	/* Select a suitable transfer command for the next transfer to ensure
	50	* the transfer address is always naturally aligned while minimizing
	51	* the total number of transfers required.
	52	*
	53	* 3 transfer commands are available:
	54	* RT5677_SPI_READ/WRITE_16: Transfer 2 bytes
	55	* RT5677_SPI_READ/WRITE_32: Transfer 4 bytes
	56	* RT5677_SPI_READ/WRITE_BURST: Transfer any multiples of 8 bytes
	57	*
a46eb523 CM	58	* Note:
	59	* 16 Bit writes and reads are restricted to the address range
	60	* 0x18020000 ~ 0x18021000
	61	*
	62	* For example, reading 256 bytes at 0x60030004 uses the following commands:
7d4d443e BZ	63	* 0x60030004 RT5677_SPI_READ_32 4 bytes
	64	* 0x60030008 RT5677_SPI_READ_BURST 240 bytes
	65	* 0x600300F8 RT5677_SPI_READ_BURST 8 bytes
	66	* 0x60030100 RT5677_SPI_READ_32 4 bytes
af48f1d0	67	*
7d4d443e BZ	68	* Input:
	69	* @read: true for read commands; false for write commands
	70	* @align: alignment of the next transfer address
	71	* @remain: number of bytes remaining to transfer
af48f1d0	72	*
7d4d443e BZ	73	* Output:
	74	* @len: number of bytes to transfer with the selected command
	75	* Returns the selected command
af48f1d0	76	*/
7d4d443e	77	static u8 rt5677_spi_select_cmd(bool read, u32 align, u32 remain, u32 *len)
af48f1d0	78	{
7d4d443e BZ	79	u8 cmd;
7d4d443e BZ	80
a46eb523	81	if (align == 4 \|\| remain <= 4) {
7d4d443e BZ	82	cmd = RT5677_SPI_READ_32;
	83	*len = 4;
	84	} else {
	85	cmd = RT5677_SPI_READ_BURST;
a46eb523 CM	86	*len = (((remain - 1) >> 3) + 1) << 3;
a46eb523 CM	87	len = min_t(u32, len, RT5677_SPI_BURST_LEN);
7d4d443e BZ	88	}
7d4d443e BZ	89	return read ? cmd : cmd + 1;
af48f1d0 OC	90	}
af48f1d0 OC	91
7d4d443e BZ	92	/* Copy dstlen bytes from src to dst, while reversing byte order for each word.
7d4d443e BZ	93	* If srclen < dstlen, zeros are padded.
af48f1d0	94	*/
7d4d443e	95	static void rt5677_spi_reverse(u8 dst, u32 dstlen, const u8 src, u32 srclen)
af48f1d0	96	{
7d4d443e BZ	97	u32 w, i, si;
	98	u32 word_size = min_t(u32, dstlen, 8);
	99
	100	for (w = 0; w < dstlen; w += word_size) {
7b8164c1	101	for (i = 0; i < word_size && i + w < dstlen; i++) {
7d4d443e BZ	102	si = w + word_size - i - 1;
7d4d443e BZ	103	dst[w + i] = si < srclen ? src[si] : 0;
af48f1d0	104	}
7d4d443e BZ	105	}
7d4d443e BZ	106	}
af48f1d0	107
a46eb523	108	/* Read DSP address space using SPI. addr and len have to be 4-byte aligned. */
7d4d443e BZ	109	int rt5677_spi_read(u32 addr, void *rxbuf, size_t len)
	110	{
	111	u32 offset;
	112	int status = 0;
	113	struct spi_transfer t[2];
	114	struct spi_message m;
	115	/* +4 bytes is for the DummyPhase following the AddressPhase */
	116	u8 header[RT5677_SPI_HEADER + 4];
	117	u8 body[RT5677_SPI_BURST_LEN];
	118	u8 spi_cmd;
	119	u8 *cb = rxbuf;
	120
	121	if (!g_spi)
	122	return -ENODEV;
	123
a46eb523	124	if ((addr & 3) \|\| (len & 3)) {
7d4d443e BZ	125	dev_err(&g_spi->dev, "Bad read align 0x%x(%zu)\n", addr, len);
	126	return -EACCES;
	127	}
af48f1d0	128
7d4d443e BZ	129	memset(t, 0, sizeof(t));
	130	t[0].tx_buf = header;
	131	t[0].len = sizeof(header);
	132	t[0].speed_hz = RT5677_SPI_FREQ;
	133	t[1].rx_buf = body;
	134	t[1].speed_hz = RT5677_SPI_FREQ;
	135	spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t));
	136
	137	for (offset = 0; offset < len; offset += t[1].len) {
	138	spi_cmd = rt5677_spi_select_cmd(true, (addr + offset) & 7,
	139	len - offset, &t[1].len);
	140
	141	/* Construct SPI message header */
	142	header[0] = spi_cmd;
	143	header[1] = ((addr + offset) & 0xff000000) >> 24;
	144	header[2] = ((addr + offset) & 0x00ff0000) >> 16;
	145	header[3] = ((addr + offset) & 0x0000ff00) >> 8;
	146	header[4] = ((addr + offset) & 0x000000ff) >> 0;
	147
	148	mutex_lock(&spi_mutex);
	149	status \|= spi_sync(g_spi, &m);
	150	mutex_unlock(&spi_mutex);
	151
7b8164c1	152
7d4d443e	153	/* Copy data back to caller buffer */
7b8164c1	154	rt5677_spi_reverse(cb + offset, len - offset, body, t[1].len);
7d4d443e BZ	155	}
	156	return status;
	157	}
	158	EXPORT_SYMBOL_GPL(rt5677_spi_read);
af48f1d0	159
a46eb523 CM	160	/* Write DSP address space using SPI. addr has to be 4-byte aligned.
a46eb523 CM	161	* If len is not 4-byte aligned, then extra zeros are written at the end
7d4d443e BZ	162	* as padding.
	163	*/
	164	int rt5677_spi_write(u32 addr, const void *txbuf, size_t len)
	165	{
a46eb523	166	u32 offset;
7d4d443e BZ	167	int status = 0;
	168	struct spi_transfer t;
	169	struct spi_message m;
	170	/* +1 byte is for the DummyPhase following the DataPhase */
	171	u8 buf[RT5677_SPI_HEADER + RT5677_SPI_BURST_LEN + 1];
	172	u8 *body = buf + RT5677_SPI_HEADER;
	173	u8 spi_cmd;
	174	const u8 *cb = txbuf;
	175
	176	if (!g_spi)
	177	return -ENODEV;
	178
a46eb523	179	if (addr & 3) {
7d4d443e BZ	180	dev_err(&g_spi->dev, "Bad write align 0x%x(%zu)\n", addr, len);
7d4d443e BZ	181	return -EACCES;
af48f1d0 OC	182	}
af48f1d0 OC	183
7d4d443e BZ	184	memset(&t, 0, sizeof(t));
	185	t.tx_buf = buf;
	186	t.speed_hz = RT5677_SPI_FREQ;
	187	spi_message_init_with_transfers(&m, &t, 1);
	188
a46eb523	189	for (offset = 0; offset < len;) {
7d4d443e	190	spi_cmd = rt5677_spi_select_cmd(false, (addr + offset) & 7,
a46eb523	191	len - offset, &t.len);
7d4d443e BZ	192
	193	/* Construct SPI message header */
	194	buf[0] = spi_cmd;
	195	buf[1] = ((addr + offset) & 0xff000000) >> 24;
	196	buf[2] = ((addr + offset) & 0x00ff0000) >> 16;
	197	buf[3] = ((addr + offset) & 0x0000ff00) >> 8;
	198	buf[4] = ((addr + offset) & 0x000000ff) >> 0;
	199
	200	/* Fetch data from caller buffer */
	201	rt5677_spi_reverse(body, t.len, cb + offset, len - offset);
	202	offset += t.len;
	203	t.len += RT5677_SPI_HEADER + 1;
	204
	205	mutex_lock(&spi_mutex);
	206	status \|= spi_sync(g_spi, &m);
	207	mutex_unlock(&spi_mutex);
	208	}
	209	return status;
	210	}
	211	EXPORT_SYMBOL_GPL(rt5677_spi_write);
af48f1d0	212
7d4d443e BZ	213	int rt5677_spi_write_firmware(u32 addr, const struct firmware *fw)
	214	{
	215	return rt5677_spi_write(addr, fw->data, fw->size);
af48f1d0	216	}
7d4d443e	217	EXPORT_SYMBOL_GPL(rt5677_spi_write_firmware);
af48f1d0 OC	218
	219	static int rt5677_spi_probe(struct spi_device *spi)
	220	{
	221	g_spi = spi;
	222	return 0;
	223	}
	224
2b070f67 OC	225	static const struct acpi_device_id rt5677_spi_acpi_id[] = {
	226	{ "RT5677AA", 0 },
	227	{ }
	228	};
	229	MODULE_DEVICE_TABLE(acpi, rt5677_spi_acpi_id);
	230
af48f1d0 OC	231	static struct spi_driver rt5677_spi_driver = {
	232	.driver = {
	233	.name = "rt5677",
2b070f67	234	.acpi_match_table = ACPI_PTR(rt5677_spi_acpi_id),
af48f1d0 OC	235	},
	236	.probe = rt5677_spi_probe,
	237	};
	238	module_spi_driver(rt5677_spi_driver);
	239
	240	MODULE_DESCRIPTION("ASoC RT5677 SPI driver");
	241	MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
	242	MODULE_LICENSE("GPL v2");