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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
[linux-2.6-block.git] / sound / soc / codecs / rt5665.c
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d2912cb1 1// SPDX-License-Identifier: GPL-2.0-only
33ada14a
BL		 2/*
3 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
4 *
5 * Copyright 2016 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
33ada14a
BL		 7 */
8
9#include <linux/module.h>
10#include <linux/moduleparam.h>
11#include <linux/init.h>
12#include <linux/delay.h>
13#include <linux/pm.h>
14#include <linux/i2c.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17#include <linux/acpi.h>
18#include <linux/gpio.h>
19#include <linux/of_gpio.h>
20#include <linux/regulator/consumer.h>
21#include <linux/mutex.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/jack.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/initval.h>
29#include <sound/tlv.h>
30#include <sound/rt5665.h>
31
32#include "rl6231.h"
33#include "rt5665.h"
34
35#define RT5665_NUM_SUPPLIES 3
36
37static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
38 "AVDD",
39 "MICVDD",
40 "VBAT",
41};
42
43struct rt5665_priv {
fab70c27 44 struct snd_soc_component *component;
33ada14a
BL		 45 struct rt5665_platform_data pdata;
46 struct regmap *regmap;
47 struct gpio_desc *gpiod_ldo1_en;
48 struct gpio_desc *gpiod_reset;
49 struct snd_soc_jack *hs_jack;
50 struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
51 struct delayed_work jack_detect_work;
52 struct delayed_work calibrate_work;
53 struct delayed_work jd_check_work;
54 struct mutex calibrate_mutex;
55
56 int sysclk;
57 int sysclk_src;
58 int lrck[RT5665_AIFS];
59 int bclk[RT5665_AIFS];
60 int master[RT5665_AIFS];
61 int id;
62
63 int pll_src;
64 int pll_in;
65 int pll_out;
66
67 int jack_type;
68 int irq_work_delay_time;
69 unsigned int sar_adc_value;
b059ca72 70 bool calibration_done;
33ada14a
BL		 71};
72
73static const struct reg_default rt5665_reg[] = {
74 {0x0000, 0x0000},
75 {0x0001, 0xc8c8},
76 {0x0002, 0x8080},
77 {0x0003, 0x8000},
78 {0x0004, 0xc80a},
79 {0x0005, 0x0000},
80 {0x0006, 0x0000},
81 {0x0007, 0x0000},
82 {0x000a, 0x0000},
83 {0x000b, 0x0000},
84 {0x000c, 0x0000},
85 {0x000d, 0x0000},
86 {0x000f, 0x0808},
87 {0x0010, 0x4040},
88 {0x0011, 0x0000},
89 {0x0012, 0x1404},
90 {0x0013, 0x1000},
91 {0x0014, 0xa00a},
92 {0x0015, 0x0404},
93 {0x0016, 0x0404},
94 {0x0017, 0x0011},
95 {0x0018, 0xafaf},
96 {0x0019, 0xafaf},
97 {0x001a, 0xafaf},
98 {0x001b, 0x0011},
99 {0x001c, 0x2f2f},
100 {0x001d, 0x2f2f},
101 {0x001e, 0x2f2f},
102 {0x001f, 0x0000},
103 {0x0020, 0x0000},
104 {0x0021, 0x0000},
105 {0x0022, 0x5757},
106 {0x0023, 0x0039},
107 {0x0026, 0xc0c0},
108 {0x0027, 0xc0c0},
109 {0x0028, 0xc0c0},
110 {0x0029, 0x8080},
111 {0x002a, 0xaaaa},
112 {0x002b, 0xaaaa},
113 {0x002c, 0xaba8},
114 {0x002d, 0x0000},
115 {0x002e, 0x0000},
116 {0x002f, 0x0000},
117 {0x0030, 0x0000},
118 {0x0031, 0x5000},
119 {0x0032, 0x0000},
120 {0x0033, 0x0000},
121 {0x0034, 0x0000},
122 {0x0035, 0x0000},
123 {0x003a, 0x0000},
124 {0x003b, 0x0000},
125 {0x003c, 0x00ff},
126 {0x003d, 0x0000},
127 {0x003e, 0x00ff},
128 {0x003f, 0x0000},
129 {0x0040, 0x0000},
130 {0x0041, 0x00ff},
131 {0x0042, 0x0000},
132 {0x0043, 0x00ff},
133 {0x0044, 0x0c0c},
134 {0x0049, 0xc00b},
135 {0x004a, 0x0000},
136 {0x004b, 0x031f},
137 {0x004d, 0x0000},
138 {0x004e, 0x001f},
139 {0x004f, 0x0000},
140 {0x0050, 0x001f},
141 {0x0052, 0xf000},
142 {0x0061, 0x0000},
143 {0x0062, 0x0000},
144 {0x0063, 0x003e},
145 {0x0064, 0x0000},
146 {0x0065, 0x0000},
147 {0x0066, 0x003f},
148 {0x0067, 0x0000},
149 {0x006b, 0x0000},
150 {0x006d, 0xff00},
151 {0x006e, 0x2808},
152 {0x006f, 0x000a},
153 {0x0070, 0x8000},
154 {0x0071, 0x8000},
155 {0x0072, 0x8000},
156 {0x0073, 0x7000},
157 {0x0074, 0x7770},
158 {0x0075, 0x0002},
159 {0x0076, 0x0001},
160 {0x0078, 0x00f0},
161 {0x0079, 0x0000},
162 {0x007a, 0x0000},
163 {0x007b, 0x0000},
164 {0x007c, 0x0000},
165 {0x007d, 0x0123},
166 {0x007e, 0x4500},
167 {0x007f, 0x8003},
168 {0x0080, 0x0000},
169 {0x0081, 0x0000},
170 {0x0082, 0x0000},
171 {0x0083, 0x0000},
172 {0x0084, 0x0000},
173 {0x0085, 0x0000},
174 {0x0086, 0x0008},
175 {0x0087, 0x0000},
176 {0x0088, 0x0000},
177 {0x0089, 0x0000},
178 {0x008a, 0x0000},
179 {0x008b, 0x0000},
180 {0x008c, 0x0003},
181 {0x008e, 0x0060},
182 {0x008f, 0x1000},
183 {0x0091, 0x0c26},
184 {0x0092, 0x0073},
185 {0x0093, 0x0000},
186 {0x0094, 0x0080},
187 {0x0098, 0x0000},
188 {0x0099, 0x0000},
189 {0x009a, 0x0007},
190 {0x009f, 0x0000},
191 {0x00a0, 0x0000},
192 {0x00a1, 0x0002},
193 {0x00a2, 0x0001},
194 {0x00a3, 0x0002},
195 {0x00a4, 0x0001},
196 {0x00ae, 0x2040},
197 {0x00af, 0x0000},
198 {0x00b6, 0x0000},
199 {0x00b7, 0x0000},
200 {0x00b8, 0x0000},
201 {0x00b9, 0x0000},
202 {0x00ba, 0x0002},
203 {0x00bb, 0x0000},
204 {0x00be, 0x0000},
205 {0x00c0, 0x0000},
206 {0x00c1, 0x0aaa},
207 {0x00c2, 0xaa80},
208 {0x00c3, 0x0003},
209 {0x00c4, 0x0000},
210 {0x00d0, 0x0000},
211 {0x00d1, 0x2244},
212 {0x00d3, 0x3300},
213 {0x00d4, 0x2200},
214 {0x00d9, 0x0809},
215 {0x00da, 0x0000},
216 {0x00db, 0x0008},
217 {0x00dc, 0x00c0},
218 {0x00dd, 0x6724},
219 {0x00de, 0x3131},
220 {0x00df, 0x0008},
221 {0x00e0, 0x4000},
222 {0x00e1, 0x3131},
223 {0x00e2, 0x600c},
224 {0x00ea, 0xb320},
225 {0x00eb, 0x0000},
226 {0x00ec, 0xb300},
227 {0x00ed, 0x0000},
228 {0x00ee, 0xb320},
229 {0x00ef, 0x0000},
230 {0x00f0, 0x0201},
231 {0x00f1, 0x0ddd},
232 {0x00f2, 0x0ddd},
233 {0x00f6, 0x0000},
234 {0x00f7, 0x0000},
235 {0x00f8, 0x0000},
236 {0x00fa, 0x0000},
237 {0x00fb, 0x0000},
238 {0x00fc, 0x0000},
239 {0x00fd, 0x0000},
240 {0x00fe, 0x10ec},
241 {0x00ff, 0x6451},
242 {0x0100, 0xaaaa},
243 {0x0101, 0x000a},
244 {0x010a, 0xaaaa},
245 {0x010b, 0xa0a0},
246 {0x010c, 0xaeae},
247 {0x010d, 0xaaaa},
248 {0x010e, 0xaaaa},
249 {0x010f, 0xaaaa},
250 {0x0110, 0xe002},
251 {0x0111, 0xa402},
252 {0x0112, 0xaaaa},
253 {0x0113, 0x2000},
254 {0x0117, 0x0f00},
255 {0x0125, 0x0410},
256 {0x0132, 0x0000},
257 {0x0133, 0x0000},
258 {0x0137, 0x5540},
259 {0x0138, 0x3700},
260 {0x0139, 0x79a1},
261 {0x013a, 0x2020},
262 {0x013b, 0x2020},
263 {0x013c, 0x2005},
264 {0x013f, 0x0000},
265 {0x0145, 0x0002},
266 {0x0146, 0x0000},
267 {0x0147, 0x0000},
268 {0x0148, 0x0000},
269 {0x0150, 0x0000},
270 {0x0160, 0x4eff},
271 {0x0161, 0x0080},
272 {0x0162, 0x0200},
273 {0x0163, 0x0800},
274 {0x0164, 0x0000},
275 {0x0165, 0x0000},
276 {0x0166, 0x0000},
277 {0x0167, 0x000f},
278 {0x0170, 0x4e87},
279 {0x0171, 0x0080},
280 {0x0172, 0x0200},
281 {0x0173, 0x0800},
282 {0x0174, 0x00ff},
283 {0x0175, 0x0000},
284 {0x0190, 0x413d},
285 {0x0191, 0x4139},
286 {0x0192, 0x4135},
287 {0x0193, 0x413d},
288 {0x0194, 0x0000},
289 {0x0195, 0x0000},
290 {0x0196, 0x0000},
291 {0x0197, 0x0000},
292 {0x0198, 0x0000},
293 {0x0199, 0x0000},
294 {0x01a0, 0x1e64},
295 {0x01a1, 0x06a3},
296 {0x01a2, 0x0000},
297 {0x01a3, 0x0000},
298 {0x01a4, 0x0000},
299 {0x01a5, 0x0000},
300 {0x01a6, 0x0000},
301 {0x01a7, 0x8000},
302 {0x01a8, 0x0000},
303 {0x01a9, 0x0000},
304 {0x01aa, 0x0000},
305 {0x01ab, 0x0000},
306 {0x01b5, 0x0000},
307 {0x01b6, 0x01c3},
308 {0x01b7, 0x02a0},
309 {0x01b8, 0x03e9},
310 {0x01b9, 0x1389},
311 {0x01ba, 0xc351},
312 {0x01bb, 0x0009},
313 {0x01bc, 0x0018},
314 {0x01bd, 0x002a},
315 {0x01be, 0x004c},
316 {0x01bf, 0x0097},
317 {0x01c0, 0x433d},
318 {0x01c1, 0x0000},
319 {0x01c2, 0x0000},
320 {0x01c3, 0x0000},
321 {0x01c4, 0x0000},
322 {0x01c5, 0x0000},
323 {0x01c6, 0x0000},
324 {0x01c7, 0x0000},
325 {0x01c8, 0x40af},
326 {0x01c9, 0x0702},
327 {0x01ca, 0x0000},
328 {0x01cb, 0x0000},
329 {0x01cc, 0x5757},
330 {0x01cd, 0x5757},
331 {0x01ce, 0x5757},
332 {0x01cf, 0x5757},
333 {0x01d0, 0x5757},
334 {0x01d1, 0x5757},
335 {0x01d2, 0x5757},
336 {0x01d3, 0x5757},
337 {0x01d4, 0x5757},
338 {0x01d5, 0x5757},
339 {0x01d6, 0x003c},
340 {0x01da, 0x0000},
341 {0x01db, 0x0000},
342 {0x01dc, 0x0000},
343 {0x01de, 0x7c00},
344 {0x01df, 0x0320},
345 {0x01e0, 0x06a1},
346 {0x01e1, 0x0000},
347 {0x01e2, 0x0000},
348 {0x01e3, 0x0000},
349 {0x01e4, 0x0000},
350 {0x01e6, 0x0001},
351 {0x01e7, 0x0000},
352 {0x01e8, 0x0000},
353 {0x01ea, 0xbf3f},
354 {0x01eb, 0x0000},
355 {0x01ec, 0x0000},
356 {0x01ed, 0x0000},
357 {0x01ee, 0x0000},
358 {0x01ef, 0x0000},
359 {0x01f0, 0x0000},
360 {0x01f1, 0x0000},
361 {0x01f2, 0x0000},
362 {0x01f3, 0x0000},
363 {0x01f4, 0x0000},
364 {0x0200, 0x0000},
365 {0x0201, 0x0000},
366 {0x0202, 0x0000},
367 {0x0203, 0x0000},
368 {0x0204, 0x0000},
369 {0x0205, 0x0000},
370 {0x0206, 0x0000},
371 {0x0207, 0x0000},
372 {0x0208, 0x0000},
373 {0x0210, 0x60b1},
374 {0x0211, 0xa005},
375 {0x0212, 0x024c},
376 {0x0213, 0xf7ff},
377 {0x0214, 0x024c},
378 {0x0215, 0x0102},
379 {0x0216, 0x00a3},
380 {0x0217, 0x0048},
381 {0x0218, 0xa2c0},
382 {0x0219, 0x0400},
383 {0x021a, 0x00c8},
384 {0x021b, 0x00c0},
385 {0x02ff, 0x0110},
386 {0x0300, 0x001f},
387 {0x0301, 0x032c},
388 {0x0302, 0x5f21},
389 {0x0303, 0x4000},
390 {0x0304, 0x4000},
391 {0x0305, 0x06d5},
392 {0x0306, 0x8000},
393 {0x0307, 0x0700},
394 {0x0310, 0x4560},
395 {0x0311, 0xa4a8},
396 {0x0312, 0x7418},
397 {0x0313, 0x0000},
398 {0x0314, 0x0006},
399 {0x0315, 0xffff},
400 {0x0316, 0xc400},
401 {0x0317, 0x0000},
402 {0x0330, 0x00a6},
403 {0x0331, 0x04c3},
404 {0x0332, 0x27c8},
405 {0x0333, 0xbf50},
406 {0x0334, 0x0045},
407 {0x0335, 0x0007},
408 {0x0336, 0x7418},
409 {0x0337, 0x0501},
410 {0x0338, 0x0000},
411 {0x0339, 0x0010},
412 {0x033a, 0x1010},
413 {0x03c0, 0x7e00},
414 {0x03c1, 0x8000},
415 {0x03c2, 0x8000},
416 {0x03c3, 0x8000},
417 {0x03c4, 0x8000},
418 {0x03c5, 0x8000},
419 {0x03c6, 0x8000},
420 {0x03c7, 0x8000},
421 {0x03c8, 0x8000},
422 {0x03c9, 0x8000},
423 {0x03ca, 0x8000},
424 {0x03cb, 0x8000},
425 {0x03cc, 0x8000},
426 {0x03d0, 0x0000},
427 {0x03d1, 0x0000},
428 {0x03d2, 0x0000},
429 {0x03d3, 0x0000},
430 {0x03d4, 0x2000},
431 {0x03d5, 0x2000},
432 {0x03d6, 0x0000},
433 {0x03d7, 0x0000},
434 {0x03d8, 0x2000},
435 {0x03d9, 0x2000},
436 {0x03da, 0x2000},
437 {0x03db, 0x2000},
438 {0x03dc, 0x0000},
439 {0x03dd, 0x0000},
440 {0x03de, 0x0000},
441 {0x03df, 0x2000},
442 {0x03e0, 0x0000},
443 {0x03e1, 0x0000},
444 {0x03e2, 0x0000},
445 {0x03e3, 0x0000},
446 {0x03e4, 0x0000},
447 {0x03e5, 0x0000},
448 {0x03e6, 0x0000},
449 {0x03e7, 0x0000},
450 {0x03e8, 0x0000},
451 {0x03e9, 0x0000},
452 {0x03ea, 0x0000},
453 {0x03eb, 0x0000},
454 {0x03ec, 0x0000},
455 {0x03ed, 0x0000},
456 {0x03ee, 0x0000},
457 {0x03ef, 0x0000},
458 {0x03f0, 0x0800},
459 {0x03f1, 0x0800},
460 {0x03f2, 0x0800},
461 {0x03f3, 0x0800},
462};
463
464static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
465{
466 switch (reg) {
467 case RT5665_RESET:
468 case RT5665_EJD_CTRL_2:
469 case RT5665_GPIO_STA:
470 case RT5665_INT_ST_1:
471 case RT5665_IL_CMD_1:
472 case RT5665_4BTN_IL_CMD_1:
473 case RT5665_PSV_IL_CMD_1:
474 case RT5665_AJD1_CTRL:
475 case RT5665_JD_CTRL_3:
476 case RT5665_STO_NG2_CTRL_1:
477 case RT5665_SAR_IL_CMD_4:
478 case RT5665_DEVICE_ID:
479 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
480 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
481 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
482 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
483 return true;
484 default:
485 return false;
486 }
487}
488
489static bool rt5665_readable_register(struct device *dev, unsigned int reg)
490{
491 switch (reg) {
492 case RT5665_RESET:
493 case RT5665_VENDOR_ID:
494 case RT5665_VENDOR_ID_1:
495 case RT5665_DEVICE_ID:
496 case RT5665_LOUT:
497 case RT5665_HP_CTRL_1:
498 case RT5665_HP_CTRL_2:
499 case RT5665_MONO_OUT:
500 case RT5665_HPL_GAIN:
501 case RT5665_HPR_GAIN:
502 case RT5665_MONO_GAIN:
503 case RT5665_CAL_BST_CTRL:
504 case RT5665_CBJ_BST_CTRL:
505 case RT5665_IN1_IN2:
506 case RT5665_IN3_IN4:
507 case RT5665_INL1_INR1_VOL:
508 case RT5665_EJD_CTRL_1:
509 case RT5665_EJD_CTRL_2:
510 case RT5665_EJD_CTRL_3:
511 case RT5665_EJD_CTRL_4:
512 case RT5665_EJD_CTRL_5:
513 case RT5665_EJD_CTRL_6:
514 case RT5665_EJD_CTRL_7:
515 case RT5665_DAC2_CTRL:
516 case RT5665_DAC2_DIG_VOL:
517 case RT5665_DAC1_DIG_VOL:
518 case RT5665_DAC3_DIG_VOL:
519 case RT5665_DAC3_CTRL:
520 case RT5665_STO1_ADC_DIG_VOL:
521 case RT5665_MONO_ADC_DIG_VOL:
522 case RT5665_STO2_ADC_DIG_VOL:
523 case RT5665_STO1_ADC_BOOST:
524 case RT5665_MONO_ADC_BOOST:
525 case RT5665_STO2_ADC_BOOST:
526 case RT5665_HP_IMP_GAIN_1:
527 case RT5665_HP_IMP_GAIN_2:
528 case RT5665_STO1_ADC_MIXER:
529 case RT5665_MONO_ADC_MIXER:
530 case RT5665_STO2_ADC_MIXER:
531 case RT5665_AD_DA_MIXER:
532 case RT5665_STO1_DAC_MIXER:
533 case RT5665_MONO_DAC_MIXER:
534 case RT5665_STO2_DAC_MIXER:
535 case RT5665_A_DAC1_MUX:
536 case RT5665_A_DAC2_MUX:
537 case RT5665_DIG_INF2_DATA:
538 case RT5665_DIG_INF3_DATA:
539 case RT5665_PDM_OUT_CTRL:
540 case RT5665_PDM_DATA_CTRL_1:
541 case RT5665_PDM_DATA_CTRL_2:
542 case RT5665_PDM_DATA_CTRL_3:
543 case RT5665_PDM_DATA_CTRL_4:
544 case RT5665_REC1_GAIN:
545 case RT5665_REC1_L1_MIXER:
546 case RT5665_REC1_L2_MIXER:
547 case RT5665_REC1_R1_MIXER:
548 case RT5665_REC1_R2_MIXER:
549 case RT5665_REC2_GAIN:
550 case RT5665_REC2_L1_MIXER:
551 case RT5665_REC2_L2_MIXER:
552 case RT5665_REC2_R1_MIXER:
553 case RT5665_REC2_R2_MIXER:
554 case RT5665_CAL_REC:
555 case RT5665_ALC_BACK_GAIN:
556 case RT5665_MONOMIX_GAIN:
557 case RT5665_MONOMIX_IN_GAIN:
558 case RT5665_OUT_L_GAIN:
559 case RT5665_OUT_L_MIXER:
560 case RT5665_OUT_R_GAIN:
561 case RT5665_OUT_R_MIXER:
562 case RT5665_LOUT_MIXER:
563 case RT5665_PWR_DIG_1:
564 case RT5665_PWR_DIG_2:
565 case RT5665_PWR_ANLG_1:
566 case RT5665_PWR_ANLG_2:
567 case RT5665_PWR_ANLG_3:
568 case RT5665_PWR_MIXER:
569 case RT5665_PWR_VOL:
570 case RT5665_CLK_DET:
571 case RT5665_HPF_CTRL1:
572 case RT5665_DMIC_CTRL_1:
573 case RT5665_DMIC_CTRL_2:
574 case RT5665_I2S1_SDP:
575 case RT5665_I2S2_SDP:
576 case RT5665_I2S3_SDP:
577 case RT5665_ADDA_CLK_1:
578 case RT5665_ADDA_CLK_2:
579 case RT5665_I2S1_F_DIV_CTRL_1:
580 case RT5665_I2S1_F_DIV_CTRL_2:
581 case RT5665_TDM_CTRL_1:
582 case RT5665_TDM_CTRL_2:
583 case RT5665_TDM_CTRL_3:
584 case RT5665_TDM_CTRL_4:
585 case RT5665_TDM_CTRL_5:
586 case RT5665_TDM_CTRL_6:
587 case RT5665_TDM_CTRL_7:
588 case RT5665_TDM_CTRL_8:
589 case RT5665_GLB_CLK:
590 case RT5665_PLL_CTRL_1:
591 case RT5665_PLL_CTRL_2:
592 case RT5665_ASRC_1:
593 case RT5665_ASRC_2:
594 case RT5665_ASRC_3:
595 case RT5665_ASRC_4:
596 case RT5665_ASRC_5:
597 case RT5665_ASRC_6:
598 case RT5665_ASRC_7:
599 case RT5665_ASRC_8:
600 case RT5665_ASRC_9:
601 case RT5665_ASRC_10:
602 case RT5665_DEPOP_1:
603 case RT5665_DEPOP_2:
604 case RT5665_HP_CHARGE_PUMP_1:
605 case RT5665_HP_CHARGE_PUMP_2:
606 case RT5665_MICBIAS_1:
607 case RT5665_MICBIAS_2:
608 case RT5665_ASRC_12:
609 case RT5665_ASRC_13:
610 case RT5665_ASRC_14:
611 case RT5665_RC_CLK_CTRL:
612 case RT5665_I2S_M_CLK_CTRL_1:
613 case RT5665_I2S2_F_DIV_CTRL_1:
614 case RT5665_I2S2_F_DIV_CTRL_2:
615 case RT5665_I2S3_F_DIV_CTRL_1:
616 case RT5665_I2S3_F_DIV_CTRL_2:
617 case RT5665_EQ_CTRL_1:
618 case RT5665_EQ_CTRL_2:
619 case RT5665_IRQ_CTRL_1:
620 case RT5665_IRQ_CTRL_2:
621 case RT5665_IRQ_CTRL_3:
622 case RT5665_IRQ_CTRL_4:
623 case RT5665_IRQ_CTRL_5:
624 case RT5665_IRQ_CTRL_6:
625 case RT5665_INT_ST_1:
626 case RT5665_GPIO_CTRL_1:
627 case RT5665_GPIO_CTRL_2:
628 case RT5665_GPIO_CTRL_3:
629 case RT5665_GPIO_CTRL_4:
630 case RT5665_GPIO_STA:
631 case RT5665_HP_AMP_DET_CTRL_1:
632 case RT5665_HP_AMP_DET_CTRL_2:
633 case RT5665_MID_HP_AMP_DET:
634 case RT5665_LOW_HP_AMP_DET:
635 case RT5665_SV_ZCD_1:
636 case RT5665_SV_ZCD_2:
637 case RT5665_IL_CMD_1:
638 case RT5665_IL_CMD_2:
639 case RT5665_IL_CMD_3:
640 case RT5665_IL_CMD_4:
641 case RT5665_4BTN_IL_CMD_1:
642 case RT5665_4BTN_IL_CMD_2:
643 case RT5665_4BTN_IL_CMD_3:
644 case RT5665_PSV_IL_CMD_1:
645 case RT5665_ADC_STO1_HP_CTRL_1:
646 case RT5665_ADC_STO1_HP_CTRL_2:
647 case RT5665_ADC_MONO_HP_CTRL_1:
648 case RT5665_ADC_MONO_HP_CTRL_2:
649 case RT5665_ADC_STO2_HP_CTRL_1:
650 case RT5665_ADC_STO2_HP_CTRL_2:
651 case RT5665_AJD1_CTRL:
652 case RT5665_JD1_THD:
653 case RT5665_JD2_THD:
654 case RT5665_JD_CTRL_1:
655 case RT5665_JD_CTRL_2:
656 case RT5665_JD_CTRL_3:
657 case RT5665_DIG_MISC:
658 case RT5665_DUMMY_2:
659 case RT5665_DUMMY_3:
660 case RT5665_DAC_ADC_DIG_VOL1:
661 case RT5665_DAC_ADC_DIG_VOL2:
662 case RT5665_BIAS_CUR_CTRL_1:
663 case RT5665_BIAS_CUR_CTRL_2:
664 case RT5665_BIAS_CUR_CTRL_3:
665 case RT5665_BIAS_CUR_CTRL_4:
666 case RT5665_BIAS_CUR_CTRL_5:
667 case RT5665_BIAS_CUR_CTRL_6:
668 case RT5665_BIAS_CUR_CTRL_7:
669 case RT5665_BIAS_CUR_CTRL_8:
670 case RT5665_BIAS_CUR_CTRL_9:
671 case RT5665_BIAS_CUR_CTRL_10:
672 case RT5665_VREF_REC_OP_FB_CAP_CTRL:
673 case RT5665_CHARGE_PUMP_1:
674 case RT5665_DIG_IN_CTRL_1:
675 case RT5665_DIG_IN_CTRL_2:
676 case RT5665_PAD_DRIVING_CTRL:
677 case RT5665_SOFT_RAMP_DEPOP:
678 case RT5665_PLL:
679 case RT5665_CHOP_DAC:
680 case RT5665_CHOP_ADC:
681 case RT5665_CALIB_ADC_CTRL:
682 case RT5665_VOL_TEST:
683 case RT5665_TEST_MODE_CTRL_1:
684 case RT5665_TEST_MODE_CTRL_2:
685 case RT5665_TEST_MODE_CTRL_3:
686 case RT5665_TEST_MODE_CTRL_4:
687 case RT5665_BASSBACK_CTRL:
688 case RT5665_STO_NG2_CTRL_1:
689 case RT5665_STO_NG2_CTRL_2:
690 case RT5665_STO_NG2_CTRL_3:
691 case RT5665_STO_NG2_CTRL_4:
692 case RT5665_STO_NG2_CTRL_5:
693 case RT5665_STO_NG2_CTRL_6:
694 case RT5665_STO_NG2_CTRL_7:
695 case RT5665_STO_NG2_CTRL_8:
696 case RT5665_MONO_NG2_CTRL_1:
697 case RT5665_MONO_NG2_CTRL_2:
698 case RT5665_MONO_NG2_CTRL_3:
699 case RT5665_MONO_NG2_CTRL_4:
700 case RT5665_MONO_NG2_CTRL_5:
701 case RT5665_MONO_NG2_CTRL_6:
702 case RT5665_STO1_DAC_SIL_DET:
703 case RT5665_MONOL_DAC_SIL_DET:
704 case RT5665_MONOR_DAC_SIL_DET:
705 case RT5665_STO2_DAC_SIL_DET:
706 case RT5665_SIL_PSV_CTRL1:
707 case RT5665_SIL_PSV_CTRL2:
708 case RT5665_SIL_PSV_CTRL3:
709 case RT5665_SIL_PSV_CTRL4:
710 case RT5665_SIL_PSV_CTRL5:
711 case RT5665_SIL_PSV_CTRL6:
712 case RT5665_MONO_AMP_CALIB_CTRL_1:
713 case RT5665_MONO_AMP_CALIB_CTRL_2:
714 case RT5665_MONO_AMP_CALIB_CTRL_3:
715 case RT5665_MONO_AMP_CALIB_CTRL_4:
716 case RT5665_MONO_AMP_CALIB_CTRL_5:
717 case RT5665_MONO_AMP_CALIB_CTRL_6:
718 case RT5665_MONO_AMP_CALIB_CTRL_7:
719 case RT5665_MONO_AMP_CALIB_STA1:
720 case RT5665_MONO_AMP_CALIB_STA2:
721 case RT5665_MONO_AMP_CALIB_STA3:
722 case RT5665_MONO_AMP_CALIB_STA4:
723 case RT5665_MONO_AMP_CALIB_STA6:
724 case RT5665_HP_IMP_SENS_CTRL_01:
725 case RT5665_HP_IMP_SENS_CTRL_02:
726 case RT5665_HP_IMP_SENS_CTRL_03:
727 case RT5665_HP_IMP_SENS_CTRL_04:
728 case RT5665_HP_IMP_SENS_CTRL_05:
729 case RT5665_HP_IMP_SENS_CTRL_06:
730 case RT5665_HP_IMP_SENS_CTRL_07:
731 case RT5665_HP_IMP_SENS_CTRL_08:
732 case RT5665_HP_IMP_SENS_CTRL_09:
733 case RT5665_HP_IMP_SENS_CTRL_10:
734 case RT5665_HP_IMP_SENS_CTRL_11:
735 case RT5665_HP_IMP_SENS_CTRL_12:
736 case RT5665_HP_IMP_SENS_CTRL_13:
737 case RT5665_HP_IMP_SENS_CTRL_14:
738 case RT5665_HP_IMP_SENS_CTRL_15:
739 case RT5665_HP_IMP_SENS_CTRL_16:
740 case RT5665_HP_IMP_SENS_CTRL_17:
741 case RT5665_HP_IMP_SENS_CTRL_18:
742 case RT5665_HP_IMP_SENS_CTRL_19:
743 case RT5665_HP_IMP_SENS_CTRL_20:
744 case RT5665_HP_IMP_SENS_CTRL_21:
745 case RT5665_HP_IMP_SENS_CTRL_22:
746 case RT5665_HP_IMP_SENS_CTRL_23:
747 case RT5665_HP_IMP_SENS_CTRL_24:
748 case RT5665_HP_IMP_SENS_CTRL_25:
749 case RT5665_HP_IMP_SENS_CTRL_26:
750 case RT5665_HP_IMP_SENS_CTRL_27:
751 case RT5665_HP_IMP_SENS_CTRL_28:
752 case RT5665_HP_IMP_SENS_CTRL_29:
753 case RT5665_HP_IMP_SENS_CTRL_30:
754 case RT5665_HP_IMP_SENS_CTRL_31:
755 case RT5665_HP_IMP_SENS_CTRL_32:
756 case RT5665_HP_IMP_SENS_CTRL_33:
757 case RT5665_HP_IMP_SENS_CTRL_34:
758 case RT5665_HP_LOGIC_CTRL_1:
759 case RT5665_HP_LOGIC_CTRL_2:
760 case RT5665_HP_LOGIC_CTRL_3:
761 case RT5665_HP_CALIB_CTRL_1:
762 case RT5665_HP_CALIB_CTRL_2:
763 case RT5665_HP_CALIB_CTRL_3:
764 case RT5665_HP_CALIB_CTRL_4:
765 case RT5665_HP_CALIB_CTRL_5:
766 case RT5665_HP_CALIB_CTRL_6:
767 case RT5665_HP_CALIB_CTRL_7:
768 case RT5665_HP_CALIB_CTRL_9:
769 case RT5665_HP_CALIB_CTRL_10:
770 case RT5665_HP_CALIB_CTRL_11:
771 case RT5665_HP_CALIB_STA_1:
772 case RT5665_HP_CALIB_STA_2:
773 case RT5665_HP_CALIB_STA_3:
774 case RT5665_HP_CALIB_STA_4:
775 case RT5665_HP_CALIB_STA_5:
776 case RT5665_HP_CALIB_STA_6:
777 case RT5665_HP_CALIB_STA_7:
778 case RT5665_HP_CALIB_STA_8:
779 case RT5665_HP_CALIB_STA_9:
780 case RT5665_HP_CALIB_STA_10:
781 case RT5665_HP_CALIB_STA_11:
782 case RT5665_PGM_TAB_CTRL1:
783 case RT5665_PGM_TAB_CTRL2:
784 case RT5665_PGM_TAB_CTRL3:
785 case RT5665_PGM_TAB_CTRL4:
786 case RT5665_PGM_TAB_CTRL5:
787 case RT5665_PGM_TAB_CTRL6:
788 case RT5665_PGM_TAB_CTRL7:
789 case RT5665_PGM_TAB_CTRL8:
790 case RT5665_PGM_TAB_CTRL9:
791 case RT5665_SAR_IL_CMD_1:
792 case RT5665_SAR_IL_CMD_2:
793 case RT5665_SAR_IL_CMD_3:
794 case RT5665_SAR_IL_CMD_4:
795 case RT5665_SAR_IL_CMD_5:
796 case RT5665_SAR_IL_CMD_6:
797 case RT5665_SAR_IL_CMD_7:
798 case RT5665_SAR_IL_CMD_8:
799 case RT5665_SAR_IL_CMD_9:
800 case RT5665_SAR_IL_CMD_10:
801 case RT5665_SAR_IL_CMD_11:
802 case RT5665_SAR_IL_CMD_12:
803 case RT5665_DRC1_CTRL_0:
804 case RT5665_DRC1_CTRL_1:
805 case RT5665_DRC1_CTRL_2:
806 case RT5665_DRC1_CTRL_3:
807 case RT5665_DRC1_CTRL_4:
808 case RT5665_DRC1_CTRL_5:
809 case RT5665_DRC1_CTRL_6:
810 case RT5665_DRC1_HARD_LMT_CTRL_1:
811 case RT5665_DRC1_HARD_LMT_CTRL_2:
812 case RT5665_DRC1_PRIV_1:
813 case RT5665_DRC1_PRIV_2:
814 case RT5665_DRC1_PRIV_3:
815 case RT5665_DRC1_PRIV_4:
816 case RT5665_DRC1_PRIV_5:
817 case RT5665_DRC1_PRIV_6:
818 case RT5665_DRC1_PRIV_7:
819 case RT5665_DRC1_PRIV_8:
820 case RT5665_ALC_PGA_CTRL_1:
821 case RT5665_ALC_PGA_CTRL_2:
822 case RT5665_ALC_PGA_CTRL_3:
823 case RT5665_ALC_PGA_CTRL_4:
824 case RT5665_ALC_PGA_CTRL_5:
825 case RT5665_ALC_PGA_CTRL_6:
826 case RT5665_ALC_PGA_CTRL_7:
827 case RT5665_ALC_PGA_CTRL_8:
828 case RT5665_ALC_PGA_STA_1:
829 case RT5665_ALC_PGA_STA_2:
830 case RT5665_ALC_PGA_STA_3:
831 case RT5665_EQ_AUTO_RCV_CTRL1:
832 case RT5665_EQ_AUTO_RCV_CTRL2:
833 case RT5665_EQ_AUTO_RCV_CTRL3:
834 case RT5665_EQ_AUTO_RCV_CTRL4:
835 case RT5665_EQ_AUTO_RCV_CTRL5:
836 case RT5665_EQ_AUTO_RCV_CTRL6:
837 case RT5665_EQ_AUTO_RCV_CTRL7:
838 case RT5665_EQ_AUTO_RCV_CTRL8:
839 case RT5665_EQ_AUTO_RCV_CTRL9:
840 case RT5665_EQ_AUTO_RCV_CTRL10:
841 case RT5665_EQ_AUTO_RCV_CTRL11:
842 case RT5665_EQ_AUTO_RCV_CTRL12:
843 case RT5665_EQ_AUTO_RCV_CTRL13:
844 case RT5665_ADC_L_EQ_LPF1_A1:
845 case RT5665_R_EQ_LPF1_A1:
846 case RT5665_L_EQ_LPF1_H0:
847 case RT5665_R_EQ_LPF1_H0:
848 case RT5665_L_EQ_BPF1_A1:
849 case RT5665_R_EQ_BPF1_A1:
850 case RT5665_L_EQ_BPF1_A2:
851 case RT5665_R_EQ_BPF1_A2:
852 case RT5665_L_EQ_BPF1_H0:
853 case RT5665_R_EQ_BPF1_H0:
854 case RT5665_L_EQ_BPF2_A1:
855 case RT5665_R_EQ_BPF2_A1:
856 case RT5665_L_EQ_BPF2_A2:
857 case RT5665_R_EQ_BPF2_A2:
858 case RT5665_L_EQ_BPF2_H0:
859 case RT5665_R_EQ_BPF2_H0:
860 case RT5665_L_EQ_BPF3_A1:
861 case RT5665_R_EQ_BPF3_A1:
862 case RT5665_L_EQ_BPF3_A2:
863 case RT5665_R_EQ_BPF3_A2:
864 case RT5665_L_EQ_BPF3_H0:
865 case RT5665_R_EQ_BPF3_H0:
866 case RT5665_L_EQ_BPF4_A1:
867 case RT5665_R_EQ_BPF4_A1:
868 case RT5665_L_EQ_BPF4_A2:
869 case RT5665_R_EQ_BPF4_A2:
870 case RT5665_L_EQ_BPF4_H0:
871 case RT5665_R_EQ_BPF4_H0:
872 case RT5665_L_EQ_HPF1_A1:
873 case RT5665_R_EQ_HPF1_A1:
874 case RT5665_L_EQ_HPF1_H0:
875 case RT5665_R_EQ_HPF1_H0:
876 case RT5665_L_EQ_PRE_VOL:
877 case RT5665_R_EQ_PRE_VOL:
878 case RT5665_L_EQ_POST_VOL:
879 case RT5665_R_EQ_POST_VOL:
880 case RT5665_SCAN_MODE_CTRL:
881 case RT5665_I2C_MODE:
882 return true;
883 default:
884 return false;
885 }
886}
887
888static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
889static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
890static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
891static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
892static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
893static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
894static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
895static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
896
897/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
898static const DECLARE_TLV_DB_RANGE(bst_tlv,
899 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
900 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
901 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
902 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
903 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
904 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
905 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
906);
907
908/* Interface data select */
909static const char * const rt5665_data_select[] = {
910 "L/R", "R/L", "L/L", "R/R"
911};
912
27a655c4 913static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
33ada14a
BL		 914 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
915
27a655c4 916static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
33ada14a
BL		 917 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
918
27a655c4 919static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
33ada14a
BL		 920 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
921
27a655c4 922static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
33ada14a
BL		 923 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
924
27a655c4 925static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
33ada14a
BL		 926 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
927
27a655c4 928static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
33ada14a
BL		 929 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
930
27a655c4 931static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
33ada14a
BL		 932 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
933
27a655c4 934static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
33ada14a
BL		 935 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
936
27a655c4 937static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
33ada14a
BL		 938 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
939
27a655c4 940static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
33ada14a
BL		 941 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
942
27a655c4 943static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
33ada14a
BL		 944 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
945
27a655c4 946static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
33ada14a
BL		 947 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
948
27a655c4 949static SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
33ada14a
BL		 950 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
951
27a655c4 952static SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
33ada14a
BL		 953 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
954
955static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
956 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
957
958static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
959 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
960
961static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
962 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
963
964static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
965 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
966
967static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
968 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
969
970static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
971 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
972
973static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
974 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
975
976static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
977 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
978
979static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
980 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
981
982static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
983 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
984
985static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
986 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
987
988static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
989 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
990
991static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
992 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
993
994static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
995 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
996
997static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
998 struct snd_ctl_elem_value *ucontrol)
999{
fab70c27 1000 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
33ada14a
BL		 1001 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1002
fab70c27
KM		 1003 if (snd_soc_component_read32(component, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1004 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
33ada14a 1005 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
fab70c27 1006 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
33ada14a
BL		 1007 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1008 }
1009
1010 return ret;
1011}
1012
1013static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1014 struct snd_ctl_elem_value *ucontrol)
1015{
fab70c27 1016 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
33ada14a
BL		 1017 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1018
fab70c27
KM		 1019 if (snd_soc_component_read32(component, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1020 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
33ada14a 1021 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
fab70c27 1022 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
33ada14a
BL		 1023 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1024 }
1025
1026 return ret;
1027}
1028
1029/**
1030 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
fab70c27 1031 * @component: SoC audio component device.
33ada14a
BL		 1032 * @filter_mask: mask of filters.
1033 * @clk_src: clock source
1034 *
1035 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
1036 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1037 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1038 * ASRC function will track i2s clock and generate a corresponding system clock
1039 * for codec. This function provides an API to select the clock source for a
1040 * set of filters specified by the mask. And the codec driver will turn on ASRC
1041 * for these filters if ASRC is selected as their clock source.
1042 */
fab70c27 1043int rt5665_sel_asrc_clk_src(struct snd_soc_component *component,
33ada14a
BL		 1044 unsigned int filter_mask, unsigned int clk_src)
1045{
1046 unsigned int asrc2_mask = 0;
1047 unsigned int asrc2_value = 0;
1048 unsigned int asrc3_mask = 0;
1049 unsigned int asrc3_value = 0;
1050
1051 switch (clk_src) {
1052 case RT5665_CLK_SEL_SYS:
1053 case RT5665_CLK_SEL_I2S1_ASRC:
1054 case RT5665_CLK_SEL_I2S2_ASRC:
1055 case RT5665_CLK_SEL_I2S3_ASRC:
1056 case RT5665_CLK_SEL_SYS2:
1057 case RT5665_CLK_SEL_SYS3:
1058 case RT5665_CLK_SEL_SYS4:
1059 break;
1060
1061 default:
1062 return -EINVAL;
1063 }
1064
1065 if (filter_mask & RT5665_DA_STEREO1_FILTER) {
1066 asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
1067 asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
1068 | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
1069 }
1070
1071 if (filter_mask & RT5665_DA_STEREO2_FILTER) {
1072 asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
1073 asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
1074 | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
1075 }
1076
1077 if (filter_mask & RT5665_DA_MONO_L_FILTER) {
1078 asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
1079 asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
1080 | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
1081 }
1082
1083 if (filter_mask & RT5665_DA_MONO_R_FILTER) {
1084 asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
1085 asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
1086 | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
1087 }
1088
1089 if (filter_mask & RT5665_AD_STEREO1_FILTER) {
1090 asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
1091 asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
1092 | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
1093 }
1094
1095 if (filter_mask & RT5665_AD_STEREO2_FILTER) {
1096 asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
1097 asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
1098 | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
1099 }
1100
1101 if (filter_mask & RT5665_AD_MONO_L_FILTER) {
1102 asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
1103 asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
1104 | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
1105 }
1106
1107 if (filter_mask & RT5665_AD_MONO_R_FILTER) {
1108 asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
1109 asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
1110 | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
1111 }
1112
1113 if (asrc2_mask)
fab70c27 1114 snd_soc_component_update_bits(component, RT5665_ASRC_2,
33ada14a
BL		 1115 asrc2_mask, asrc2_value);
1116
1117 if (asrc3_mask)
fab70c27 1118 snd_soc_component_update_bits(component, RT5665_ASRC_3,
33ada14a
BL		 1119 asrc3_mask, asrc3_value);
1120
1121 return 0;
1122}
1123EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
1124
fab70c27 1125static int rt5665_button_detect(struct snd_soc_component *component)
33ada14a
BL		 1126{
1127 int btn_type, val;
1128
fab70c27 1129 val = snd_soc_component_read32(component, RT5665_4BTN_IL_CMD_1);
33ada14a 1130 btn_type = val & 0xfff0;
fab70c27 1131 snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, val);
33ada14a
BL		 1132
1133 return btn_type;
1134}
1135
fab70c27 1136static void rt5665_enable_push_button_irq(struct snd_soc_component *component,
33ada14a
BL		 1137 bool enable)
1138{
1139 if (enable) {
fab70c27
KM		 1140 snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, 0x0003);
1141 snd_soc_component_update_bits(component, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
1142 snd_soc_component_write(component, RT5665_IL_CMD_1, 0x0048);
1143 snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
33ada14a
BL		 1144 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1145 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
fab70c27 1146 snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3,
33ada14a
BL		 1147 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1148 } else {
fab70c27 1149 snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3,
33ada14a 1150 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
fab70c27 1151 snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
33ada14a 1152 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
fab70c27 1153 snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
33ada14a
BL		 1154 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1155 }
1156}
1157
1158/**
1159 * rt5665_headset_detect - Detect headset.
fab70c27 1160 * @component: SoC audio component device.
33ada14a
BL		 1161 * @jack_insert: Jack insert or not.
1162 *
1163 * Detect whether is headset or not when jack inserted.
1164 *
1165 * Returns detect status.
1166 */
fab70c27 1167static int rt5665_headset_detect(struct snd_soc_component *component, int jack_insert)
33ada14a 1168{
fab70c27
KM		 1169 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
1170 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
33ada14a
BL		 1171 unsigned int sar_hs_type, val;
1172
1173 if (jack_insert) {
1174 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1175 snd_soc_dapm_sync(dapm);
1176
1177 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1178 0x100);
1179
1180 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1181 if (val & 0x4) {
1182 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1183 0x100, 0);
1184
1185 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1186 while (val & 0x4) {
1187 usleep_range(10000, 15000);
1188 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1189 &val);
1190 }
1191 }
1192
1193 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
39841944 1194 0x1a0, 0x120);
33ada14a 1195 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
39841944 1196 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
33ada14a
BL		 1197 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1198
39841944
BL		 1199 usleep_range(10000, 15000);
1200
fab70c27 1201 rt5665->sar_adc_value = snd_soc_component_read32(rt5665->component,
33ada14a
BL		 1202 RT5665_SAR_IL_CMD_4) & 0x7ff;
1203
1204 sar_hs_type = rt5665->pdata.sar_hs_type ?
1205 rt5665->pdata.sar_hs_type : 729;
1206
1207 if (rt5665->sar_adc_value > sar_hs_type) {
1208 rt5665->jack_type = SND_JACK_HEADSET;
fab70c27 1209 rt5665_enable_push_button_irq(component, true);
33ada14a
BL		 1210 } else {
1211 rt5665->jack_type = SND_JACK_HEADPHONE;
1212 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1213 0x2291);
1214 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1215 0x100, 0);
1216 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1217 snd_soc_dapm_sync(dapm);
1218 }
1219 } else {
1220 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1221 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1222 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1223 snd_soc_dapm_sync(dapm);
1224 if (rt5665->jack_type == SND_JACK_HEADSET)
fab70c27 1225 rt5665_enable_push_button_irq(component, false);
33ada14a
BL		 1226 rt5665->jack_type = 0;
1227 }
1228
fab70c27 1229 dev_dbg(component->dev, "jack_type = %d\n", rt5665->jack_type);
33ada14a
BL		 1230 return rt5665->jack_type;
1231}
1232
1233static irqreturn_t rt5665_irq(int irq, void *data)
1234{
1235 struct rt5665_priv *rt5665 = data;
1236
1237 mod_delayed_work(system_power_efficient_wq,
1238 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1239
1240 return IRQ_HANDLED;
1241}
1242
1243static void rt5665_jd_check_handler(struct work_struct *work)
1244{
1245 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
f1994a9c 1246 jd_check_work.work);
33ada14a 1247
fab70c27 1248 if (snd_soc_component_read32(rt5665->component, RT5665_AJD1_CTRL) & 0x0010) {
33ada14a 1249 /* jack out */
fab70c27 1250 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0);
33ada14a
BL		 1251
1252 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1253 SND_JACK_HEADSET |
1254 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1255 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1256 } else {
1257 schedule_delayed_work(&rt5665->jd_check_work, 500);
1258 }
1259}
1260
fab70c27 1261static int rt5665_set_jack_detect(struct snd_soc_component *component,
97c415a6 1262 struct snd_soc_jack *hs_jack, void *data)
33ada14a 1263{
fab70c27 1264 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
33ada14a
BL		 1265
1266 switch (rt5665->pdata.jd_src) {
1267 case RT5665_JD1:
1268 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1269 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1270 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1271 0xc000, 0xc000);
1272 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1273 RT5665_PWR_JD1, RT5665_PWR_JD1);
1274 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1275 break;
1276
1277 case RT5665_JD_NULL:
1278 break;
1279
1280 default:
fab70c27 1281 dev_warn(component->dev, "Wrong JD source\n");
33ada14a
BL		 1282 break;
1283 }
1284
1285 rt5665->hs_jack = hs_jack;
1286
1287 return 0;
1288}
33ada14a
BL		 1289
1290static void rt5665_jack_detect_handler(struct work_struct *work)
1291{
1292 struct rt5665_priv *rt5665 =
1293 container_of(work, struct rt5665_priv, jack_detect_work.work);
1294 int val, btn_type;
1295
fab70c27 1296 while (!rt5665->component) {
33ada14a
BL		 1297 pr_debug("%s codec = null\n", __func__);
1298 usleep_range(10000, 15000);
1299 }
1300
fab70c27 1301 while (!rt5665->component->card->instantiated) {
33ada14a
BL		 1302 pr_debug("%s\n", __func__);
1303 usleep_range(10000, 15000);
1304 }
1305
b059ca72
BL		 1306 while (!rt5665->calibration_done) {
1307 pr_debug("%s calibration not ready\n", __func__);
1308 usleep_range(10000, 15000);
1309 }
1310
33ada14a
BL		 1311 mutex_lock(&rt5665->calibrate_mutex);
1312
fab70c27 1313 val = snd_soc_component_read32(rt5665->component, RT5665_AJD1_CTRL) & 0x0010;
33ada14a
BL		 1314 if (!val) {
1315 /* jack in */
1316 if (rt5665->jack_type == 0) {
1317 /* jack was out, report jack type */
1318 rt5665->jack_type =
fab70c27 1319 rt5665_headset_detect(rt5665->component, 1);
33ada14a
BL		 1320 } else {
1321 /* jack is already in, report button event */
1322 rt5665->jack_type = SND_JACK_HEADSET;
fab70c27 1323 btn_type = rt5665_button_detect(rt5665->component);
33ada14a
BL		 1324 /**
1325 * rt5665 can report three kinds of button behavior,
1326 * one click, double click and hold. However,
1327 * currently we will report button pressed/released
1328 * event. So all the three button behaviors are
1329 * treated as button pressed.
1330 */
1331 switch (btn_type) {
1332 case 0x8000:
1333 case 0x4000:
1334 case 0x2000:
1335 rt5665->jack_type |= SND_JACK_BTN_0;
1336 break;
1337 case 0x1000:
1338 case 0x0800:
1339 case 0x0400:
1340 rt5665->jack_type |= SND_JACK_BTN_1;
1341 break;
1342 case 0x0200:
1343 case 0x0100:
1344 case 0x0080:
1345 rt5665->jack_type |= SND_JACK_BTN_2;
1346 break;
1347 case 0x0040:
1348 case 0x0020:
1349 case 0x0010:
1350 rt5665->jack_type |= SND_JACK_BTN_3;
1351 break;
1352 case 0x0000: /* unpressed */
1353 break;
1354 default:
1355 btn_type = 0;
fab70c27 1356 dev_err(rt5665->component->dev,
33ada14a
BL		 1357 "Unexpected button code 0x%04x\n",
1358 btn_type);
1359 break;
1360 }
1361 }
1362 } else {
1363 /* jack out */
fab70c27 1364 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0);
33ada14a
BL		 1365 }
1366
1367 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1368 SND_JACK_HEADSET |
1369 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1370 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1371
1372 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1373 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1374 schedule_delayed_work(&rt5665->jd_check_work, 0);
1375 else
1376 cancel_delayed_work_sync(&rt5665->jd_check_work);
1377
1378 mutex_unlock(&rt5665->calibrate_mutex);
1379}
1380
8bfa4268
BL		 1381static const char * const rt5665_clk_sync[] = {
1382 "I2S1_1", "I2S1_2", "I2S2", "I2S3", "IF2 Slave", "IF3 Slave"
1383};
1384
1385static const struct soc_enum rt5665_enum[] = {
1386 SOC_ENUM_SINGLE(RT5665_I2S1_SDP, 11, 5, rt5665_clk_sync),
1387 SOC_ENUM_SINGLE(RT5665_I2S2_SDP, 11, 5, rt5665_clk_sync),
1388 SOC_ENUM_SINGLE(RT5665_I2S3_SDP, 11, 5, rt5665_clk_sync),
1389};
1390
33ada14a
BL		 1391static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1392 /* Headphone Output Volume */
1393 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1394 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1395 rt5665_hp_vol_put, hp_vol_tlv),
1396
1397 /* Mono Output Volume */
1398 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1399 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1400 rt5665_mono_vol_put, mono_vol_tlv),
1401
b833786b
BL		 1402 SOC_SINGLE_TLV("MONOVOL Playback Volume", RT5665_MONO_OUT,
1403 RT5665_L_VOL_SFT, 39, 1, out_vol_tlv),
1404
33ada14a
BL		 1405 /* Output Volume */
1406 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1407 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1408
1409 /* DAC Digital Volume */
1410 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1411 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1412 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1413 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1414 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1415 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1416
1417 /* IN1/IN2/IN3/IN4 Volume */
1418 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1419 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1420 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1421 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1422 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1423 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1424 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1425 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1426 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1427 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1428
1429 /* INL/INR Volume Control */
1430 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1431 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1432
1433 /* ADC Digital Volume Control */
1434 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1435 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1436 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1437 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1438 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1439 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1440 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1441 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1442 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1443 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1444 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1445 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1446
1447 /* ADC Boost Volume Control */
1448 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1449 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1450 3, 0, adc_bst_tlv),
1451
1452 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1453 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1454 3, 0, adc_bst_tlv),
1455
1456 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1457 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1458 3, 0, adc_bst_tlv),
8bfa4268
BL		 1459
1460 /* I2S3 CLK Source */
1461 SOC_ENUM("I2S1 Master Clk Sel", rt5665_enum[0]),
1462 SOC_ENUM("I2S2 Master Clk Sel", rt5665_enum[1]),
1463 SOC_ENUM("I2S3 Master Clk Sel", rt5665_enum[2]),
33ada14a
BL		 1464};
1465
1466/**
1467 * set_dmic_clk - Set parameter of dmic.
1468 *
1469 * @w: DAPM widget.
1470 * @kcontrol: The kcontrol of this widget.
1471 * @event: Event id.
1472 *
1473 * Choose dmic clock between 1MHz and 3MHz.
1474 * It is better for clock to approximate 3MHz.
1475 */
1476static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1477 struct snd_kcontrol *kcontrol, int event)
1478{
fab70c27
KM		 1479 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1480 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
33ada14a
BL		 1481 int pd, idx = -EINVAL;
1482
1483 pd = rl6231_get_pre_div(rt5665->regmap,
1484 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1485 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1486
1487 if (idx < 0)
fab70c27 1488 dev_err(component->dev, "Failed to set DMIC clock\n");
33ada14a 1489 else {
fab70c27 1490 snd_soc_component_update_bits(component, RT5665_DMIC_CTRL_1,
33ada14a
BL		 1491 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1492 }
1493 return idx;
1494}
1495
1496static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1497 struct snd_kcontrol *kcontrol, int event)
1498{
fab70c27 1499 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
33ada14a
BL		 1500
1501 switch (event) {
1502 case SND_SOC_DAPM_PRE_PMU:
fab70c27 1503 snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1,
33ada14a
BL		 1504 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1505 RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1506 break;
1507 case SND_SOC_DAPM_POST_PMD:
fab70c27 1508 snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1,
33ada14a
BL		 1509 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1510 RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1511 break;
1512 default:
1513 return 0;
1514 }
1515
1516 return 0;
1517}
1518
1519static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1520 struct snd_soc_dapm_widget *sink)
1521{
1522 unsigned int val;
fab70c27 1523 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
33ada14a 1524
fab70c27 1525 val = snd_soc_component_read32(component, RT5665_GLB_CLK);
33ada14a
BL		 1526 val &= RT5665_SCLK_SRC_MASK;
1527 if (val == RT5665_SCLK_SRC_PLL1)
1528 return 1;
1529 else
1530 return 0;
1531}
1532
1533static int is_using_asrc(struct snd_soc_dapm_widget *w,
1534 struct snd_soc_dapm_widget *sink)
1535{
1536 unsigned int reg, shift, val;
fab70c27 1537 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
33ada14a
BL		 1538
1539 switch (w->shift) {
1540 case RT5665_ADC_MONO_R_ASRC_SFT:
1541 reg = RT5665_ASRC_3;
1542 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1543 break;
1544 case RT5665_ADC_MONO_L_ASRC_SFT:
1545 reg = RT5665_ASRC_3;
1546 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1547 break;
1548 case RT5665_ADC_STO1_ASRC_SFT:
1549 reg = RT5665_ASRC_3;
1550 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1551 break;
1552 case RT5665_ADC_STO2_ASRC_SFT:
1553 reg = RT5665_ASRC_3;
1554 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1555 break;
1556 case RT5665_DAC_MONO_R_ASRC_SFT:
1557 reg = RT5665_ASRC_2;
1558 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1559 break;
1560 case RT5665_DAC_MONO_L_ASRC_SFT:
1561 reg = RT5665_ASRC_2;
1562 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1563 break;
1564 case RT5665_DAC_STO1_ASRC_SFT:
1565 reg = RT5665_ASRC_2;
1566 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1567 break;
1568 case RT5665_DAC_STO2_ASRC_SFT:
1569 reg = RT5665_ASRC_2;
1570 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1571 break;
1572 default:
1573 return 0;
1574 }
1575
fab70c27 1576 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
33ada14a
BL		 1577 switch (val) {
1578 case RT5665_CLK_SEL_I2S1_ASRC:
1579 case RT5665_CLK_SEL_I2S2_ASRC:
1580 case RT5665_CLK_SEL_I2S3_ASRC:
1581 /* I2S_Pre_Div1 should be 1 in asrc mode */
fab70c27 1582 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
33ada14a
BL		 1583 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1584 return 1;
1585 default:
1586 return 0;
1587 }
1588
1589}
1590
1591/* Digital Mixer */
1592static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1593 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1594 RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1595 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1596 RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1597};
1598
1599static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1600 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1601 RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1602 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1603 RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1604};
1605
1606static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1607 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1608 RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1609 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1610 RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1611};
1612
1613static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1614 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1615 RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1616 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1617 RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1618};
1619
1620static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1621 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1622 RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1623 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1624 RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1625};
1626
1627static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1628 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1629 RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1630 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1631 RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1632};
1633
1634static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1635 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1636 RT5665_M_ADCMIX_L_SFT, 1, 1),
1637 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1638 RT5665_M_DAC1_L_SFT, 1, 1),
1639};
1640
1641static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1642 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1643 RT5665_M_ADCMIX_R_SFT, 1, 1),
1644 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1645 RT5665_M_DAC1_R_SFT, 1, 1),
1646};
1647
1648static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1649 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1650 RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1651 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1652 RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1653 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1654 RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1655 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1656 RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1657};
1658
1659static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1660 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1661 RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1662 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1663 RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1664 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1665 RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1666 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1667 RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1668};
1669
1670static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1671 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1672 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1673 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1674 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1675 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1676 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1677};
1678
1679static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1680 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1681 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1682 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1683 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1684 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1685 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1686};
1687
1688static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1689 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1690 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1691 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1692 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1693 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1694 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1695 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1696 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1697};
1698
1699static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1700 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1701 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1702 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1703 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1704 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1705 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1706 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1707 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1708};
1709
1710/* Analog Input Mixer */
1711static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1712 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1713 RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1714 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1715 RT5665_M_INL_RM1_L_SFT, 1, 1),
1716 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1717 RT5665_M_INR_RM1_L_SFT, 1, 1),
1718 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1719 RT5665_M_BST4_RM1_L_SFT, 1, 1),
1720 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1721 RT5665_M_BST3_RM1_L_SFT, 1, 1),
1722 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1723 RT5665_M_BST2_RM1_L_SFT, 1, 1),
1724 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1725 RT5665_M_BST1_RM1_L_SFT, 1, 1),
1726};
1727
1728static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1729 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1730 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1731 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1732 RT5665_M_INR_RM1_R_SFT, 1, 1),
1733 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1734 RT5665_M_BST4_RM1_R_SFT, 1, 1),
1735 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1736 RT5665_M_BST3_RM1_R_SFT, 1, 1),
1737 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1738 RT5665_M_BST2_RM1_R_SFT, 1, 1),
1739 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1740 RT5665_M_BST1_RM1_R_SFT, 1, 1),
1741};
1742
1743static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1744 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1745 RT5665_M_INL_RM2_L_SFT, 1, 1),
1746 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1747 RT5665_M_INR_RM2_L_SFT, 1, 1),
1748 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1749 RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1750 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1751 RT5665_M_BST4_RM2_L_SFT, 1, 1),
1752 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1753 RT5665_M_BST3_RM2_L_SFT, 1, 1),
1754 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1755 RT5665_M_BST2_RM2_L_SFT, 1, 1),
1756 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1757 RT5665_M_BST1_RM2_L_SFT, 1, 1),
1758};
1759
1760static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1761 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1762 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1763 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1764 RT5665_M_INL_RM2_R_SFT, 1, 1),
1765 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1766 RT5665_M_INR_RM2_R_SFT, 1, 1),
1767 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1768 RT5665_M_BST4_RM2_R_SFT, 1, 1),
1769 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1770 RT5665_M_BST3_RM2_R_SFT, 1, 1),
1771 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1772 RT5665_M_BST2_RM2_R_SFT, 1, 1),
1773 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1774 RT5665_M_BST1_RM2_R_SFT, 1, 1),
1775};
1776
1777static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1778 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1779 RT5665_M_DAC_L2_MM_SFT, 1, 1),
1780 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1781 RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1782 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1783 RT5665_M_BST1_MM_SFT, 1, 1),
1784 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1785 RT5665_M_BST2_MM_SFT, 1, 1),
1786 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1787 RT5665_M_BST3_MM_SFT, 1, 1),
1788};
1789
1790static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1791 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1792 RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1793 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1794 RT5665_M_IN_L_OM_L_SFT, 1, 1),
1795 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1796 RT5665_M_BST1_OM_L_SFT, 1, 1),
1797 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1798 RT5665_M_BST2_OM_L_SFT, 1, 1),
1799 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1800 RT5665_M_BST3_OM_L_SFT, 1, 1),
1801};
1802
1803static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1804 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1805 RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1806 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1807 RT5665_M_IN_R_OM_R_SFT, 1, 1),
1808 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1809 RT5665_M_BST2_OM_R_SFT, 1, 1),
1810 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1811 RT5665_M_BST3_OM_R_SFT, 1, 1),
1812 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1813 RT5665_M_BST4_OM_R_SFT, 1, 1),
1814};
1815
1816static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1817 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1818 RT5665_M_DAC_L2_MA_SFT, 1, 1),
1819 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1820 RT5665_M_MONOVOL_MA_SFT, 1, 1),
1821};
1822
1823static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1824 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1825 RT5665_M_DAC_L2_LM_SFT, 1, 1),
1826 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1827 RT5665_M_OV_L_LM_SFT, 1, 1),
1828};
1829
1830static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1831 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1832 RT5665_M_DAC_R2_LM_SFT, 1, 1),
1833 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1834 RT5665_M_OV_R_LM_SFT, 1, 1),
1835};
1836
1837/*DAC L2, DAC R2*/
1838/*MX-17 [6:4], MX-17 [2:0]*/
1839static const char * const rt5665_dac2_src[] = {
1840 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1841};
1842
27a655c4 1843static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1844 rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1845 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1846
1847static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1848 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1849
27a655c4 1850static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1851 rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1852 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1853
1854static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1855 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1856
1857/*DAC L3, DAC R3*/
1858/*MX-1B [6:4], MX-1B [2:0]*/
1859static const char * const rt5665_dac3_src[] = {
1860 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1861};
1862
27a655c4 1863static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1864 rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1865 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1866
1867static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1868 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1869
27a655c4 1870static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1871 rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1872 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1873
1874static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1875 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1876
1877/* STO1 ADC1 Source */
1878/* MX-26 [13] [5] */
1879static const char * const rt5665_sto1_adc1_src[] = {
1880 "DD Mux", "ADC"
1881};
1882
27a655c4 1883static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1884 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1885 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1886
1887static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1888 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1889
27a655c4 1890static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1891 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1892 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1893
1894static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1895 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1896
1897/* STO1 ADC Source */
1898/* MX-26 [11:10] [3:2] */
1899static const char * const rt5665_sto1_adc_src[] = {
1900 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1901};
1902
27a655c4 1903static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1904 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1905 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1906
1907static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1908 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1909
27a655c4 1910static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1911 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1912 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1913
1914static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1915 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1916
1917/* STO1 ADC2 Source */
1918/* MX-26 [12] [4] */
1919static const char * const rt5665_sto1_adc2_src[] = {
1920 "DAC MIX", "DMIC"
1921};
1922
27a655c4 1923static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1924 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1925 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1926
1927static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1928 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1929
27a655c4 1930static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1931 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1932 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1933
1934static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1935 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1936
1937/* STO1 DMIC Source */
1938/* MX-26 [8] */
1939static const char * const rt5665_sto1_dmic_src[] = {
1940 "DMIC1", "DMIC2"
1941};
1942
27a655c4 1943static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1944 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1945 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1946
1947static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1948 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1949
1950/* MX-26 [9] */
1951static const char * const rt5665_sto1_dd_l_src[] = {
1952 "STO2 DAC", "MONO DAC"
1953};
1954
27a655c4 1955static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1956 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1957 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1958
1959static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1960 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1961
1962/* MX-26 [1:0] */
1963static const char * const rt5665_sto1_dd_r_src[] = {
1964 "STO2 DAC", "MONO DAC", "AEC REF"
1965};
1966
27a655c4 1967static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1968 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1969 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1970
1971static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1972 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1973
1974/* MONO ADC L2 Source */
1975/* MX-27 [12] */
1976static const char * const rt5665_mono_adc_l2_src[] = {
1977 "DAC MIXL", "DMIC"
1978};
1979
27a655c4 1980static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1981 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1982 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1983
1984static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1985 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1986
1987
1988/* MONO ADC L1 Source */
1989/* MX-27 [13] */
1990static const char * const rt5665_mono_adc_l1_src[] = {
1991 "DD Mux", "ADC"
1992};
1993
27a655c4 1994static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 1995 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1996 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
1997
1998static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
1999 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
2000
2001/* MX-27 [9][1]*/
2002static const char * const rt5665_mono_dd_src[] = {
2003 "STO2 DAC", "MONO DAC"
2004};
2005
27a655c4 2006static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2007 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
2008 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
2009
2010static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
2011 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
2012
27a655c4 2013static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2014 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
2015 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
2016
2017static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
2018 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
2019
2020/* MONO ADC L Source, MONO ADC R Source*/
2021/* MX-27 [11:10], MX-27 [3:2] */
2022static const char * const rt5665_mono_adc_src[] = {
2023 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2024};
2025
27a655c4 2026static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2027 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
2028 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
2029
2030static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
2031 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
2032
27a655c4 2033static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2034 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
2035 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
2036
2037static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
2038 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
2039
2040/* MONO DMIC L Source */
2041/* MX-27 [8] */
2042static const char * const rt5665_mono_dmic_l_src[] = {
2043 "DMIC1 L", "DMIC2 L"
2044};
2045
27a655c4 2046static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2047 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
2048 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
2049
2050static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
2051 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
2052
2053/* MONO ADC R2 Source */
2054/* MX-27 [4] */
2055static const char * const rt5665_mono_adc_r2_src[] = {
2056 "DAC MIXR", "DMIC"
2057};
2058
27a655c4 2059static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2060 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
2061 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
2062
2063static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
2064 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
2065
2066/* MONO ADC R1 Source */
2067/* MX-27 [5] */
2068static const char * const rt5665_mono_adc_r1_src[] = {
2069 "DD Mux", "ADC"
2070};
2071
27a655c4 2072static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2073 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
2074 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
2075
2076static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
2077 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
2078
2079/* MONO DMIC R Source */
2080/* MX-27 [0] */
2081static const char * const rt5665_mono_dmic_r_src[] = {
2082 "DMIC1 R", "DMIC2 R"
2083};
2084
27a655c4 2085static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2086 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
2087 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
2088
2089static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
2090 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
2091
2092
2093/* STO2 ADC1 Source */
2094/* MX-28 [13] [5] */
2095static const char * const rt5665_sto2_adc1_src[] = {
2096 "DD Mux", "ADC"
2097};
2098
27a655c4 2099static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2100 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2101 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2102
2103static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2104 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2105
27a655c4 2106static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2107 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2108 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2109
2110static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2111 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2112
2113/* STO2 ADC Source */
2114/* MX-28 [11:10] [3:2] */
2115static const char * const rt5665_sto2_adc_src[] = {
2116 "ADC1 L", "ADC1 R", "ADC2 L"
2117};
2118
27a655c4 2119static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2120 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2121 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2122
2123static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2124 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2125
27a655c4 2126static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2127 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2128 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2129
2130static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2131 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2132
2133/* STO2 ADC2 Source */
2134/* MX-28 [12] [4] */
2135static const char * const rt5665_sto2_adc2_src[] = {
2136 "DAC MIX", "DMIC"
2137};
2138
27a655c4 2139static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2140 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2141 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2142
2143static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2144 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2145
27a655c4 2146static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2147 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2148 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2149
2150static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2151 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2152
2153/* STO2 DMIC Source */
2154/* MX-28 [8] */
2155static const char * const rt5665_sto2_dmic_src[] = {
2156 "DMIC1", "DMIC2"
2157};
2158
27a655c4 2159static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2160 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2161 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2162
2163static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2164 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2165
2166/* MX-28 [9] */
2167static const char * const rt5665_sto2_dd_l_src[] = {
2168 "STO2 DAC", "MONO DAC"
2169};
2170
27a655c4 2171static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2172 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2173 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2174
2175static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2176 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2177
2178/* MX-28 [1] */
2179static const char * const rt5665_sto2_dd_r_src[] = {
2180 "STO2 DAC", "MONO DAC"
2181};
2182
27a655c4 2183static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2184 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2185 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2186
2187static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2188 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2189
2190/* DAC R1 Source, DAC L1 Source*/
2191/* MX-29 [11:10], MX-29 [9:8]*/
2192static const char * const rt5665_dac1_src[] = {
2193 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2194};
2195
27a655c4 2196static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2197 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2198 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2199
2200static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2201 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2202
27a655c4 2203static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2204 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2205 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2206
2207static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2208 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2209
2210/* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2211/* MX-2D [13:12], MX-2D [9:8]*/
2212static const char * const rt5665_dig_dac_mix_src[] = {
2213 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2214};
2215
27a655c4 2216static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2217 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2218 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2219
2220static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2221 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2222
27a655c4 2223static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2224 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2225 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2226
2227static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2228 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2229
2230/* Analog DAC L1 Source, Analog DAC R1 Source*/
2231/* MX-2D [5:4], MX-2D [1:0]*/
2232static const char * const rt5665_alg_dac1_src[] = {
2233 "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2234};
2235
27a655c4 2236static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2237 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2238 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2239
2240static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2241 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2242
27a655c4 2243static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2244 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2245 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2246
2247static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2248 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2249
2250/* Analog DAC LR Source, Analog DAC R2 Source*/
2251/* MX-2E [5:4], MX-2E [0]*/
2252static const char * const rt5665_alg_dac2_src[] = {
2253 "Mono DAC Mixer", "DAC2"
2254};
2255
27a655c4 2256static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2257 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2258 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2259
2260static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2261 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2262
27a655c4 2263static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2264 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2265 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2266
2267static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2268 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2269
2270/* Interface2 ADC Data Input*/
2271/* MX-2F [14:12] */
2272static const char * const rt5665_if2_1_adc_in_src[] = {
2273 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2274 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2275};
2276
27a655c4 2277static SOC_ENUM_SINGLE_DECL(
33ada14a 2278 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
83749aba 2279 RT5665_IF2_1_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
33ada14a
BL		 2280
2281static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2282 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2283
2284/* MX-2F [6:4] */
2285static const char * const rt5665_if2_2_adc_in_src[] = {
2286 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2287 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2288};
2289
27a655c4 2290static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2291 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2292 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2293
2294static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2295 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2296
2297/* Interface3 ADC Data Input*/
2298/* MX-30 [6:4] */
2299static const char * const rt5665_if3_adc_in_src[] = {
2300 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2301 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2302};
2303
27a655c4 2304static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2305 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2306 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2307
2308static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2309 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2310
2311/* PDM 1 L/R*/
2312/* MX-31 [11:10] [9:8] */
2313static const char * const rt5665_pdm_src[] = {
2314 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2315};
2316
27a655c4 2317static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2318 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2319 RT5665_PDM1_L_SFT, rt5665_pdm_src);
2320
2321static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2322 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2323
27a655c4 2324static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2325 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2326 RT5665_PDM1_R_SFT, rt5665_pdm_src);
2327
2328static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2329 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2330
2331
2332/* I2S1 TDM ADCDAT Source */
2333/* MX-7a[10] */
2334static const char * const rt5665_if1_1_adc1_data_src[] = {
2335 "STO1 ADC", "IF2_1 DAC",
2336};
2337
27a655c4 2338static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2339 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2340 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2341
2342static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2343 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2344
2345/* MX-7a[9] */
2346static const char * const rt5665_if1_1_adc2_data_src[] = {
2347 "STO2 ADC", "IF2_2 DAC",
2348};
2349
27a655c4 2350static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2351 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2352 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2353
2354static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2355 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2356
2357/* MX-7a[8] */
2358static const char * const rt5665_if1_1_adc3_data_src[] = {
2359 "MONO ADC", "IF3 DAC",
2360};
2361
27a655c4 2362static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2363 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2364 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2365
2366static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2367 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2368
2369/* MX-7b[10] */
2370static const char * const rt5665_if1_2_adc1_data_src[] = {
2371 "STO1 ADC", "IF1 DAC",
2372};
2373
27a655c4 2374static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2375 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2376 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2377
2378static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2379 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2380
2381/* MX-7b[9] */
2382static const char * const rt5665_if1_2_adc2_data_src[] = {
2383 "STO2 ADC", "IF2_1 DAC",
2384};
2385
27a655c4 2386static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2387 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2388 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2389
2390static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2391 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2392
2393/* MX-7b[8] */
2394static const char * const rt5665_if1_2_adc3_data_src[] = {
2395 "MONO ADC", "IF2_2 DAC",
2396};
2397
27a655c4 2398static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2399 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2400 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2401
2402static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2403 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2404
2405/* MX-7b[7] */
2406static const char * const rt5665_if1_2_adc4_data_src[] = {
2407 "DAC1", "IF3 DAC",
2408};
2409
27a655c4 2410static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2411 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2412 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2413
2414static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2415 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2416
2417/* MX-7a[4:0] MX-7b[4:0] */
2418static const char * const rt5665_tdm_adc_data_src[] = {
2419 "1234", "1243", "1324", "1342", "1432", "1423",
2420 "2134", "2143", "2314", "2341", "2431", "2413",
2421 "3124", "3142", "3214", "3241", "3412", "3421",
2422 "4123", "4132", "4213", "4231", "4312", "4321"
2423};
2424
27a655c4 2425static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2426 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2427 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2428
2429static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2430 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2431
27a655c4 2432static SOC_ENUM_SINGLE_DECL(
33ada14a
BL		 2433 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2434 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2435
2436static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2437 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2438
2439/* Out Volume Switch */
2440static const struct snd_kcontrol_new monovol_switch =
2441 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2442
2443static const struct snd_kcontrol_new outvol_l_switch =
2444 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2445
2446static const struct snd_kcontrol_new outvol_r_switch =
2447 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2448
2449/* Out Switch */
2450static const struct snd_kcontrol_new mono_switch =
2451 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2452
2453static const struct snd_kcontrol_new hpo_switch =
2454 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2455 RT5665_VOL_L_SFT, 1, 0);
2456
2457static const struct snd_kcontrol_new lout_l_switch =
2458 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2459
2460static const struct snd_kcontrol_new lout_r_switch =
2461 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2462
2463static const struct snd_kcontrol_new pdm_l_switch =
2464 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2465 RT5665_M_PDM1_L_SFT, 1, 1);
2466
2467static const struct snd_kcontrol_new pdm_r_switch =
2468 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2469 RT5665_M_PDM1_R_SFT, 1, 1);
2470
2471static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2472 struct snd_kcontrol *kcontrol, int event)
2473{
fab70c27 2474 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
33ada14a
BL		 2475
2476 switch (event) {
2477 case SND_SOC_DAPM_PRE_PMU:
fab70c27 2478 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
33ada14a 2479 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
fab70c27 2480 snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
33ada14a 2481 0x0);
fab70c27
KM		 2482 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x10, 0x10);
2483 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x20, 0x20);
33ada14a
BL		 2484 break;
2485
2486 case SND_SOC_DAPM_POST_PMD:
fab70c27
KM		 2487 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x20, 0);
2488 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x10, 0);
2489 snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
33ada14a 2490 0x40);
fab70c27 2491 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
33ada14a
BL		 2492 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2493 break;
2494
2495 default:
2496 return 0;
2497 }
2498
2499 return 0;
2500
2501}
2502
2503static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2504 struct snd_kcontrol *kcontrol, int event)
2505{
fab70c27 2506 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
33ada14a
BL		 2507
2508 switch (event) {
2509 case SND_SOC_DAPM_PRE_PMU:
fab70c27 2510 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
33ada14a 2511 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
fab70c27 2512 snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, 0x0003);
33ada14a
BL		 2513 break;
2514
2515 case SND_SOC_DAPM_POST_PMD:
fab70c27
KM		 2516 snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2517 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
33ada14a
BL		 2518 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2519 break;
2520
2521 default:
2522 return 0;
2523 }
2524
2525 return 0;
2526
2527}
2528
2529static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2530 struct snd_kcontrol *kcontrol, int event)
2531{
fab70c27 2532 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
33ada14a
BL		 2533
2534 switch (event) {
2535 case SND_SOC_DAPM_POST_PMU:
fab70c27 2536 snd_soc_component_update_bits(component, RT5665_DEPOP_1,
33ada14a
BL		 2537 RT5665_PUMP_EN, RT5665_PUMP_EN);
2538 break;
2539
2540 case SND_SOC_DAPM_PRE_PMD:
fab70c27 2541 snd_soc_component_update_bits(component, RT5665_DEPOP_1,
33ada14a
BL		 2542 RT5665_PUMP_EN, 0);
2543 break;
2544
2545 default:
2546 return 0;
2547 }
2548
2549 return 0;
2550
2551}
2552
2553static int set_dmic_power(struct snd_soc_dapm_widget *w,
2554 struct snd_kcontrol *kcontrol, int event)
2555{
2556 switch (event) {
2557 case SND_SOC_DAPM_POST_PMU:
2558 /*Add delay to avoid pop noise*/
2559 msleep(150);
2560 break;
2561
2562 default:
2563 return 0;
2564 }
2565
2566 return 0;
2567}
2568
2569static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
2570 struct snd_kcontrol *kcontrol, int event)
2571{
fab70c27 2572 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
33ada14a
BL		 2573
2574 switch (event) {
2575 case SND_SOC_DAPM_PRE_PMU:
2576 switch (w->shift) {
2577 case RT5665_PWR_VREF1_BIT:
fab70c27 2578 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
33ada14a
BL		 2579 RT5665_PWR_FV1, 0);
2580 break;
2581
2582 case RT5665_PWR_VREF2_BIT:
fab70c27 2583 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
33ada14a
BL		 2584 RT5665_PWR_FV2, 0);
2585 break;
2586
2587 case RT5665_PWR_VREF3_BIT:
fab70c27 2588 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
33ada14a
BL		 2589 RT5665_PWR_FV3, 0);
2590 break;
2591
2592 default:
2593 break;
2594 }
2595 break;
2596
2597 case SND_SOC_DAPM_POST_PMU:
2598 usleep_range(15000, 20000);
2599 switch (w->shift) {
2600 case RT5665_PWR_VREF1_BIT:
fab70c27 2601 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
33ada14a
BL		 2602 RT5665_PWR_FV1, RT5665_PWR_FV1);
2603 break;
2604
2605 case RT5665_PWR_VREF2_BIT:
fab70c27 2606 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
33ada14a
BL		 2607 RT5665_PWR_FV2, RT5665_PWR_FV2);
2608 break;
2609
2610 case RT5665_PWR_VREF3_BIT:
fab70c27 2611 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
33ada14a
BL		 2612 RT5665_PWR_FV3, RT5665_PWR_FV3);
2613 break;
2614
2615 default:
2616 break;
2617 }
2618 break;
2619
2620 default:
2621 return 0;
2622 }
2623
2624 return 0;
2625}
2626
9b5d3865
BL		 2627static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w,
2628 struct snd_kcontrol *kcontrol, int event)
2629{
fab70c27 2630 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
b98ae9ad 2631 unsigned int val1, val2, mask1 = 0, mask2 = 0;
9b5d3865
BL		 2632
2633 switch (w->shift) {
2634 case RT5665_PWR_I2S2_1_BIT:
2635 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2636 RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK;
2637 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2638 RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1;
2639 break;
2640 case RT5665_PWR_I2S2_2_BIT:
2641 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2642 RT5665_GP8_PIN_MASK;
2643 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2644 RT5665_GP8_PIN_DACDAT2_2;
2645 mask2 = RT5665_GP9_PIN_MASK;
2646 val2 = RT5665_GP9_PIN_ADCDAT2_2;
2647 break;
2648 case RT5665_PWR_I2S3_BIT:
2649 mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK |
2650 RT5665_GP8_PIN_MASK;
2651 val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 |
2652 RT5665_GP8_PIN_DACDAT3;
2653 mask2 = RT5665_GP9_PIN_MASK;
2654 val2 = RT5665_GP9_PIN_ADCDAT3;
2655 break;
2656 }
2657 switch (event) {
2658 case SND_SOC_DAPM_PRE_PMU:
b98ae9ad 2659 if (mask1)
fab70c27 2660 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1,
b98ae9ad 2661 mask1, val1);
9b5d3865 2662 if (mask2)
fab70c27 2663 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2,
9b5d3865
BL		 2664 mask2, val2);
2665 break;
2666 case SND_SOC_DAPM_POST_PMD:
b98ae9ad 2667 if (mask1)
fab70c27 2668 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1,
b98ae9ad 2669 mask1, 0);
9b5d3865 2670 if (mask2)
fab70c27 2671 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2,
9b5d3865
BL		 2672 mask2, 0);
2673 break;
2674 default:
2675 return 0;
2676 }
2677
2678 return 0;
2679}
33ada14a
BL		 2680
2681static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2682 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2683 NULL, 0),
2684 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2685 NULL, 0),
2686 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2687 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2688 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2689 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2690 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2691 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2692 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2693 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2694
2695 /* ASRC */
2696 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2697 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2698 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2699 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2700 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2701 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2702 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2703 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2704 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2705 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2706 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2707 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2708 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2709 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2710 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2711 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
30b7d88d
BL		 2712 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5665_ASRC_1,
2713 RT5665_ADC_STO2_ASRC_SFT, 0, NULL, 0),
33ada14a
BL		 2714 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2715 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2716 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2717 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2718 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2719 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2720 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2721 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2722 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2723 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2724 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2725 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2726
2727 /* Input Side */
2728 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2729 0, NULL, 0),
2730 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2731 0, NULL, 0),
2732 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2733 0, NULL, 0),
2734
2735 /* Input Lines */
2736 SND_SOC_DAPM_INPUT("DMIC L1"),
2737 SND_SOC_DAPM_INPUT("DMIC R1"),
2738 SND_SOC_DAPM_INPUT("DMIC L2"),
2739 SND_SOC_DAPM_INPUT("DMIC R2"),
2740
2741 SND_SOC_DAPM_INPUT("IN1P"),
2742 SND_SOC_DAPM_INPUT("IN1N"),
2743 SND_SOC_DAPM_INPUT("IN2P"),
2744 SND_SOC_DAPM_INPUT("IN2N"),
2745 SND_SOC_DAPM_INPUT("IN3P"),
2746 SND_SOC_DAPM_INPUT("IN3N"),
2747 SND_SOC_DAPM_INPUT("IN4P"),
2748 SND_SOC_DAPM_INPUT("IN4N"),
2749
2750 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2751 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2752
2753 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2754 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2755 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2756 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2757 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2758 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2759
2760 /* Boost */
2761 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2762 0, 0, NULL, 0),
2763 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2764 0, 0, NULL, 0),
2765 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2766 0, 0, NULL, 0),
2767 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2768 0, 0, NULL, 0),
2769 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2770 0, 0, NULL, 0),
2771 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2772 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2773 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2774 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2775 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2776 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2777 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2778 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2779 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2780 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2781 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2782 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2783 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2784 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2785 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2786 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2787 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2788 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2789
2790
2791 /* Input Volume */
2792 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2793 0, NULL, 0),
2794 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2795 0, NULL, 0),
2796
2797 /* REC Mixer */
2798 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2799 ARRAY_SIZE(rt5665_rec1_l_mix)),
2800 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2801 ARRAY_SIZE(rt5665_rec1_r_mix)),
2802 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2803 ARRAY_SIZE(rt5665_rec2_l_mix)),
2804 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2805 ARRAY_SIZE(rt5665_rec2_r_mix)),
2806 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2807 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2808 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2809 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2810 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2811 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2812 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2813 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2814
2815 /* ADCs */
2816 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2817 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2818 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2819 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2820
2821 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2822 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2823 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2824 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2825 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2826 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2827 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2828 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2829 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2830 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2831 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2832 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2833
2834 /* ADC Mux */
2835 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2836 &rt5665_sto1_dmic_mux),
2837 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2838 &rt5665_sto1_dmic_mux),
2839 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2840 &rt5665_sto1_adc1l_mux),
2841 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2842 &rt5665_sto1_adc1r_mux),
2843 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2844 &rt5665_sto1_adc2l_mux),
2845 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2846 &rt5665_sto1_adc2r_mux),
2847 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2848 &rt5665_sto1_adcl_mux),
2849 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2850 &rt5665_sto1_adcr_mux),
2851 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2852 &rt5665_sto1_dd_l_mux),
2853 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2854 &rt5665_sto1_dd_r_mux),
2855 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2856 &rt5665_mono_adc_l2_mux),
2857 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2858 &rt5665_mono_adc_r2_mux),
2859 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2860 &rt5665_mono_adc_l1_mux),
2861 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2862 &rt5665_mono_adc_r1_mux),
2863 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2864 &rt5665_mono_dmic_l_mux),
2865 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2866 &rt5665_mono_dmic_r_mux),
2867 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2868 &rt5665_mono_adc_l_mux),
2869 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2870 &rt5665_mono_adc_r_mux),
2871 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2872 &rt5665_mono_dd_l_mux),
2873 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2874 &rt5665_mono_dd_r_mux),
2875 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2876 &rt5665_sto2_dmic_mux),
2877 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2878 &rt5665_sto2_dmic_mux),
2879 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2880 &rt5665_sto2_adc1l_mux),
2881 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2882 &rt5665_sto2_adc1r_mux),
2883 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2884 &rt5665_sto2_adc2l_mux),
2885 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2886 &rt5665_sto2_adc2r_mux),
2887 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2888 &rt5665_sto2_adcl_mux),
2889 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2890 &rt5665_sto2_adcr_mux),
2891 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2892 &rt5665_sto2_dd_l_mux),
2893 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2894 &rt5665_sto2_dd_r_mux),
2895 /* ADC Mixer */
2896 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2897 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2898 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2899 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2900 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2901 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2902 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2903 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2904 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2905 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2906 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2907 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2908 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2909 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2910 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2911 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2912 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2913 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2914 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2915 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2916 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2917 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2918 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2919 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2920 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2921 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2922
2923 /* ADC PGA */
2924 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2925 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2926 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2927
2928 /* Digital Interface */
2929 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2930 0, NULL, 0),
2931 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2932 0, NULL, 0),
2933 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
9b5d3865
BL		 2934 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2935 SND_SOC_DAPM_POST_PMD),
33ada14a 2936 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
9b5d3865
BL		 2937 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2938 SND_SOC_DAPM_POST_PMD),
33ada14a 2939 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
9b5d3865
BL		 2940 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2941 SND_SOC_DAPM_POST_PMD),
33ada14a
BL		 2942 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2943 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2944 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2945 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2946 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2947 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2948 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2949 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2950 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2951
2952 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2953 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2954 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2955 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2956 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2957 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2958 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2959 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2960
2961 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2962 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2963 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2964 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2965
2966 /* Digital Interface Select */
2967 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2968 &rt5665_if1_1_adc1_mux),
2969 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2970 &rt5665_if1_1_adc2_mux),
2971 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2972 &rt5665_if1_1_adc3_mux),
2973 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2974 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2975 &rt5665_if1_2_adc1_mux),
2976 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2977 &rt5665_if1_2_adc2_mux),
2978 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2979 &rt5665_if1_2_adc3_mux),
2980 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2981 &rt5665_if1_2_adc4_mux),
2982 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2983 &rt5665_tdm1_adc_mux),
2984 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2985 &rt5665_tdm1_adc_mux),
2986 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2987 &rt5665_tdm1_adc_mux),
2988 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2989 &rt5665_tdm1_adc_mux),
2990 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2991 &rt5665_tdm2_adc_mux),
2992 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2993 &rt5665_tdm2_adc_mux),
2994 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2995 &rt5665_tdm2_adc_mux),
2996 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2997 &rt5665_tdm2_adc_mux),
2998 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2999 &rt5665_if2_1_adc_in_mux),
3000 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
3001 &rt5665_if2_2_adc_in_mux),
3002 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
3003 &rt5665_if3_adc_in_mux),
3004 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3005 &rt5665_if1_1_01_adc_swap_mux),
3006 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3007 &rt5665_if1_1_01_adc_swap_mux),
3008 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3009 &rt5665_if1_1_23_adc_swap_mux),
3010 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3011 &rt5665_if1_1_23_adc_swap_mux),
3012 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3013 &rt5665_if1_1_45_adc_swap_mux),
3014 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3015 &rt5665_if1_1_45_adc_swap_mux),
3016 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3017 &rt5665_if1_1_67_adc_swap_mux),
3018 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3019 &rt5665_if1_1_67_adc_swap_mux),
3020 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3021 &rt5665_if1_2_01_adc_swap_mux),
3022 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3023 &rt5665_if1_2_01_adc_swap_mux),
3024 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3025 &rt5665_if1_2_23_adc_swap_mux),
3026 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3027 &rt5665_if1_2_23_adc_swap_mux),
3028 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3029 &rt5665_if1_2_45_adc_swap_mux),
3030 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3031 &rt5665_if1_2_45_adc_swap_mux),
3032 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3033 &rt5665_if1_2_67_adc_swap_mux),
3034 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3035 &rt5665_if1_2_67_adc_swap_mux),
3036 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3037 &rt5665_if2_1_dac_swap_mux),
3038 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3039 &rt5665_if2_1_adc_swap_mux),
3040 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3041 &rt5665_if2_2_dac_swap_mux),
3042 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3043 &rt5665_if2_2_adc_swap_mux),
3044 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3045 &rt5665_if3_dac_swap_mux),
3046 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3047 &rt5665_if3_adc_swap_mux),
3048
3049 /* Audio Interface */
3050 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
3051 0, SND_SOC_NOPM, 0, 0),
3052 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
3053 1, SND_SOC_NOPM, 0, 0),
3054 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
3055 2, SND_SOC_NOPM, 0, 0),
3056 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
3057 3, SND_SOC_NOPM, 0, 0),
3058 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
3059 4, SND_SOC_NOPM, 0, 0),
3060 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
3061 5, SND_SOC_NOPM, 0, 0),
3062 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
3063 6, SND_SOC_NOPM, 0, 0),
3064 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
3065 7, SND_SOC_NOPM, 0, 0),
3066 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
3067 0, SND_SOC_NOPM, 0, 0),
3068 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
3069 1, SND_SOC_NOPM, 0, 0),
3070 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
3071 2, SND_SOC_NOPM, 0, 0),
3072 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
3073 3, SND_SOC_NOPM, 0, 0),
3074 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
3075 4, SND_SOC_NOPM, 0, 0),
3076 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
3077 5, SND_SOC_NOPM, 0, 0),
3078 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
3079 6, SND_SOC_NOPM, 0, 0),
3080 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
3081 7, SND_SOC_NOPM, 0, 0),
3082 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
3083 0, SND_SOC_NOPM, 0, 0),
3084 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
3085 0, SND_SOC_NOPM, 0, 0),
3086 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
3087 0, SND_SOC_NOPM, 0, 0),
3088 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
3089 0, SND_SOC_NOPM, 0, 0),
3090 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
3091 0, SND_SOC_NOPM, 0, 0),
3092 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
3093 0, SND_SOC_NOPM, 0, 0),
3094 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
3095 0, SND_SOC_NOPM, 0, 0),
3096
3097 /* Output Side */
3098 /* DAC mixer before sound effect */
3099 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3100 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3101 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3102 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3103
3104 /* DAC channel Mux */
3105 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3106 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3107 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3108 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3109 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3110 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3111
3112 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3113 &rt5665_alg_dac_l1_mux),
3114 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3115 &rt5665_alg_dac_r1_mux),
3116 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3117 &rt5665_alg_dac_l2_mux),
3118 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3119 &rt5665_alg_dac_r2_mux),
3120
3121 /* DAC Mixer */
3122 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3123 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3124 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3125 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3126 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3127 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3128 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3129 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3130 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3131 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3132 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3133 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3134 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3135 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3136 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3137 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3138 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3139 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3140 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3141 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3142 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3143 &rt5665_dig_dac_mixl_mux),
3144 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3145 &rt5665_dig_dac_mixr_mux),
3146
3147 /* DACs */
3148 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3149 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3150
3151 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3152 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3153 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3154 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3155 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3156 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3157 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3158
3159 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3160 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3161 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3162 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3163
3164 /* OUT Mixer */
3165 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3166 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3167 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3168 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3169 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3170 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3171
3172 /* Output Volume */
3173 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3174 &monovol_switch),
3175 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3176 &outvol_l_switch),
3177 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3178 &outvol_r_switch),
3179
3180 /* MONO/HPO/LOUT */
3181 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3182 ARRAY_SIZE(rt5665_mono_mix)),
3183 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3184 ARRAY_SIZE(rt5665_lout_l_mix)),
3185 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3186 ARRAY_SIZE(rt5665_lout_r_mix)),
3187 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3188 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3189 SND_SOC_DAPM_PRE_PMU),
3190 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3191 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3192 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3193 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3194 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3195 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3196
3197 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3198 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3199 SND_SOC_DAPM_POST_PMD),
3200
3201 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3202 &mono_switch),
3203 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3204 &hpo_switch),
3205 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3206 &lout_l_switch),
3207 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3208 &lout_r_switch),
3209 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3210 &pdm_l_switch),
3211 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3212 &pdm_r_switch),
3213
3214 /* PDM */
3215 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3216 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3217 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3218 0, 1, &rt5665_pdm_l_mux),
3219 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3220 0, 1, &rt5665_pdm_r_mux),
3221
3222 /* CLK DET */
3223 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3224 0, NULL, 0),
3225 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3226 0, NULL, 0),
3227 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3228 0, NULL, 0),
3229 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3230 0, NULL, 0),
3231 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3232 0, NULL, 0),
3233
3234 /* Output Lines */
3235 SND_SOC_DAPM_OUTPUT("HPOL"),
3236 SND_SOC_DAPM_OUTPUT("HPOR"),
3237 SND_SOC_DAPM_OUTPUT("LOUTL"),
3238 SND_SOC_DAPM_OUTPUT("LOUTR"),
3239 SND_SOC_DAPM_OUTPUT("MONOOUT"),
3240 SND_SOC_DAPM_OUTPUT("PDML"),
3241 SND_SOC_DAPM_OUTPUT("PDMR"),
3242};
3243
3244static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3245 /*PLL*/
3246 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3247 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3248 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3249 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3250 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3251 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3252 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3253 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3254
3255 /*ASRC*/
3256 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
30b7d88d 3257 {"ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc},
33ada14a
BL		 3258 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3259 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3260 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3261 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3262 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3263 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
09b50c37
BL		 3264 {"I2S1 ASRC", NULL, "CLKDET"},
3265 {"I2S2 ASRC", NULL, "CLKDET"},
3266 {"I2S3 ASRC", NULL, "CLKDET"},
33ada14a
BL		 3267
3268 /*Vref*/
3269 {"Mic Det Power", NULL, "Vref2"},
3270 {"MICBIAS1", NULL, "Vref1"},
3271 {"MICBIAS1", NULL, "Vref2"},
3272 {"MICBIAS2", NULL, "Vref1"},
3273 {"MICBIAS2", NULL, "Vref2"},
3274 {"MICBIAS3", NULL, "Vref1"},
3275 {"MICBIAS3", NULL, "Vref2"},
3276
3277 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3278 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3279 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3280 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3281 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3282 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3283
3284 {"I2S1_1", NULL, "I2S1 ASRC"},
3285 {"I2S1_2", NULL, "I2S1 ASRC"},
3286 {"I2S2_1", NULL, "I2S2 ASRC"},
3287 {"I2S2_2", NULL, "I2S2 ASRC"},
3288 {"I2S3", NULL, "I2S3 ASRC"},
3289
3290 {"CLKDET SYS", NULL, "CLKDET"},
3291 {"CLKDET HP", NULL, "CLKDET"},
3292 {"CLKDET MONO", NULL, "CLKDET"},
3293 {"CLKDET LOUT", NULL, "CLKDET"},
3294
3295 {"IN1P", NULL, "LDO2"},
3296 {"IN2P", NULL, "LDO2"},
3297 {"IN3P", NULL, "LDO2"},
3298 {"IN4P", NULL, "LDO2"},
3299
3300 {"DMIC1", NULL, "DMIC L1"},
3301 {"DMIC1", NULL, "DMIC R1"},
3302 {"DMIC2", NULL, "DMIC L2"},
3303 {"DMIC2", NULL, "DMIC R2"},
3304
3305 {"BST1", NULL, "IN1P"},
3306 {"BST1", NULL, "IN1N"},
3307 {"BST1", NULL, "BST1 Power"},
3308 {"BST1", NULL, "BST1P Power"},
3309 {"BST2", NULL, "IN2P"},
3310 {"BST2", NULL, "IN2N"},
3311 {"BST2", NULL, "BST2 Power"},
3312 {"BST2", NULL, "BST2P Power"},
3313 {"BST3", NULL, "IN3P"},
3314 {"BST3", NULL, "IN3N"},
3315 {"BST3", NULL, "BST3 Power"},
3316 {"BST3", NULL, "BST3P Power"},
3317 {"BST4", NULL, "IN4P"},
3318 {"BST4", NULL, "IN4N"},
3319 {"BST4", NULL, "BST4 Power"},
3320 {"BST4", NULL, "BST4P Power"},
3321 {"BST1 CBJ", NULL, "IN1P"},
3322 {"BST1 CBJ", NULL, "IN1N"},
3323 {"BST1 CBJ", NULL, "CBJ Power"},
3324 {"CBJ Power", NULL, "Vref2"},
3325
3326 {"INL VOL", NULL, "IN3P"},
3327 {"INR VOL", NULL, "IN3N"},
3328
3329 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3330 {"RECMIX1L", "INL Switch", "INL VOL"},
3331 {"RECMIX1L", "INR Switch", "INR VOL"},
3332 {"RECMIX1L", "BST4 Switch", "BST4"},
3333 {"RECMIX1L", "BST3 Switch", "BST3"},
3334 {"RECMIX1L", "BST2 Switch", "BST2"},
3335 {"RECMIX1L", "BST1 Switch", "BST1"},
3336 {"RECMIX1L", NULL, "RECMIX1L Power"},
3337
3338 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3339 {"RECMIX1R", "INR Switch", "INR VOL"},
3340 {"RECMIX1R", "BST4 Switch", "BST4"},
3341 {"RECMIX1R", "BST3 Switch", "BST3"},
3342 {"RECMIX1R", "BST2 Switch", "BST2"},
3343 {"RECMIX1R", "BST1 Switch", "BST1"},
3344 {"RECMIX1R", NULL, "RECMIX1R Power"},
3345
3346 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3347 {"RECMIX2L", "INL Switch", "INL VOL"},
3348 {"RECMIX2L", "INR Switch", "INR VOL"},
3349 {"RECMIX2L", "BST4 Switch", "BST4"},
3350 {"RECMIX2L", "BST3 Switch", "BST3"},
3351 {"RECMIX2L", "BST2 Switch", "BST2"},
3352 {"RECMIX2L", "BST1 Switch", "BST1"},
3353 {"RECMIX2L", NULL, "RECMIX2L Power"},
3354
3355 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3356 {"RECMIX2R", "INL Switch", "INL VOL"},
3357 {"RECMIX2R", "INR Switch", "INR VOL"},
3358 {"RECMIX2R", "BST4 Switch", "BST4"},
3359 {"RECMIX2R", "BST3 Switch", "BST3"},
3360 {"RECMIX2R", "BST2 Switch", "BST2"},
3361 {"RECMIX2R", "BST1 Switch", "BST1"},
3362 {"RECMIX2R", NULL, "RECMIX2R Power"},
3363
3364 {"ADC1 L", NULL, "RECMIX1L"},
3365 {"ADC1 L", NULL, "ADC1 L Power"},
3366 {"ADC1 L", NULL, "ADC1 clock"},
3367 {"ADC1 R", NULL, "RECMIX1R"},
3368 {"ADC1 R", NULL, "ADC1 R Power"},
3369 {"ADC1 R", NULL, "ADC1 clock"},
3370
3371 {"ADC2 L", NULL, "RECMIX2L"},
3372 {"ADC2 L", NULL, "ADC2 L Power"},
3373 {"ADC2 L", NULL, "ADC2 clock"},
3374 {"ADC2 R", NULL, "RECMIX2R"},
3375 {"ADC2 R", NULL, "ADC2 R Power"},
3376 {"ADC2 R", NULL, "ADC2 clock"},
3377
3378 {"DMIC L1", NULL, "DMIC CLK"},
3379 {"DMIC L1", NULL, "DMIC1 Power"},
3380 {"DMIC R1", NULL, "DMIC CLK"},
3381 {"DMIC R1", NULL, "DMIC1 Power"},
3382 {"DMIC L2", NULL, "DMIC CLK"},
3383 {"DMIC L2", NULL, "DMIC2 Power"},
3384 {"DMIC R2", NULL, "DMIC CLK"},
3385 {"DMIC R2", NULL, "DMIC2 Power"},
3386
3387 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3388 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3389
3390 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3391 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3392
3393 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3394 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3395
3396 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3397 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3398
3399 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3400 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3401
3402 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3403 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3404
3405 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3406 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3407 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3408 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3409 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3410 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3411 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3412 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3413
3414 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3415 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3416
3417 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3418 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3419
3420 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3421 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3422 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3423 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3424
3425 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3426 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3427 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3428 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3429
3430 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3431 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3432 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3433 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3434
3435 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3436 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3437 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3438 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3439
3440 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3441 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3442
3443 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3444 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3445
3446 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3447 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3448 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3449 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3450
3451 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3452 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3453 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3454 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3455
3456 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3457 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3458 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3459 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3460 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3461 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3462
3463 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3464 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3465
3466 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3467 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3468
3469 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3470 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3471 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3472 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3473
3474 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3475 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3476 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3477 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3478
3479 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3480 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3481 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3482
3483 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3484 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3485 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3486
3487 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3488 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3489 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3490
3491 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3492 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3493 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3494
3495 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3496 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3497 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3498
3499 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3500 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3501 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3502
3503 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3504 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3505 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3506 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3507 {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3508 {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3509
3510 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3511 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3512 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3513 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3514 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3515 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3516 {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3517
3518 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3519 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3520 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3521 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3522 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3523 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3524 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3525 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3526
3527 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3528 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3529 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3530 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3531 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3532 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3533 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3534 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3535 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3536 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3537 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3538 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3539 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3540 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3541 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3542 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3543 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3544 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3545 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3546 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3547 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3548 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3549 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3550 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3551 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3552
3553 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3554 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3555 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3556 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3557 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3558 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3559 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3560 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3561 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3562 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3563 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3564 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3565 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3566 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3567 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3568 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3569 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3570 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3571 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3572 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3573 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3574 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3575 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3576 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3577 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3578
3579 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3580 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3581 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3582 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3583 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3584 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3585 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3586 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3587 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3588 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3589 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3590 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3591 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3592 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3593 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3594 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3595 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3596 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3597 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3598 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3599 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3600 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3601 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3602 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3603 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3604
3605 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3606 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3607 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3608 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3609 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3610 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3611 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3612 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3613 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3614 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3615 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3616 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3617 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3618 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3619 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3620 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3621 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3622 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3623 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3624 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3625 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3626 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3627 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3628 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3629 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3630
3631
3632 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3633 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3634 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3635 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3636 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3637 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3638 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3639 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3640 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3641 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3642 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3643 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3644 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3645 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3646 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3647 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3648 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3649 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3650 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3651 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3652 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3653 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3654 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3655 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3656 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3657
3658 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3659 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3660 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3661 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3662 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3663 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3664 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3665 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3666 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3667 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3668 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3669 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3670 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3671 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3672 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3673 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3674 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3675 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3676 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3677 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3678 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3679 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3680 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3681 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3682 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3683
3684 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3685 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3686 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3687 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3688 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3689 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3690 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3691 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3692 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3693 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3694 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3695 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3696 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3697 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3698 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3699 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3700 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3701 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3702 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3703 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3704 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3705 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3706 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3707 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3708 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3709
3710 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3711 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3712 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3713 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3714 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3715 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3716 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3717 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3718 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3719 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3720 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3721 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3722 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3723 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3724 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3725 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3726 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3727 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3728 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3729 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3730 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3731 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3732 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3733 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3734 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3735
3736 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3737 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3738 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3739 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3740 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3741 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3742 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3743 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3744 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3745 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3746 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3747 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3748 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3749 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3750 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3751 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3752 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3753 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3754 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3755 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3756 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3757 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3758 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3759 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3760 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3761 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3762 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3763 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3764 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3765 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3766 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3767 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3768
3769 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3770 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3771 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3772 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3773 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3774 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3775 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3776 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3777 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3778 {"IF2_1 ADC", NULL, "I2S2_1"},
3779
3780 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3781 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3782 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3783 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3784 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3785 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3786 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3787 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3788 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3789 {"IF2_2 ADC", NULL, "I2S2_2"},
3790
3791 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3792 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3793 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3794 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3795 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3796 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3797 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3798 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3799 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3800 {"IF3 ADC", NULL, "I2S3"},
3801
3802 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3803 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3804 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3805 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3806 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3807 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3808 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3809 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3810 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3811 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3812 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3813 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3814 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3815 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3816 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3817 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3818 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3819 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3820 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3821 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3822 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3823 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3824 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3825 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3826 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3827 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3828 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3829 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3830 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3831 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3832 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3833
3834 {"IF1 DAC1", NULL, "AIF1RX"},
3835 {"IF1 DAC2", NULL, "AIF1RX"},
3836 {"IF1 DAC3", NULL, "AIF1RX"},
3837 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3838 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3839 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3840 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3841 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3842 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3843 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3844 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3845 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3846 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3847 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3848 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3849 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3850 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3851 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3852
3853 {"IF1 DAC1", NULL, "I2S1_1"},
3854 {"IF1 DAC2", NULL, "I2S1_1"},
3855 {"IF1 DAC3", NULL, "I2S1_1"},
3856 {"IF2_1 DAC", NULL, "I2S2_1"},
3857 {"IF2_2 DAC", NULL, "I2S2_2"},
3858 {"IF3 DAC", NULL, "I2S3"},
3859
3860 {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3861 {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3862 {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3863 {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3864 {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3865 {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3866 {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3867 {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3868 {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3869 {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3870 {"IF3 DAC L", NULL, "IF3 DAC"},
3871 {"IF3 DAC R", NULL, "IF3 DAC"},
3872
3873 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3874 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3875 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3876 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3877 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3878
3879 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3880 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3881 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3882 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3883 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3884
3885 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3886 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3887 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3888 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3889
3890 {"DAC1 MIX", NULL, "DAC1 MIXL"},
3891 {"DAC1 MIX", NULL, "DAC1 MIXR"},
3892
3893 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3894 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3895 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3896 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3897 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3898 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3899
3900 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3901 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3902 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3903 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3904 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3905 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3906
3907 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3908 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3909 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3910 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3911 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3912 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3913
3914 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3915 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3916 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3917 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3918 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3919 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3920
3921 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3922 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3923 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3924 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3925
3926 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3927 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3928 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3929 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3930
3931 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3932 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3933 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3934
3935 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3936 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3937 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3938
3939 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3940 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3941 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3942 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3943 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3944 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3945 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3946 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3947
3948 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3949 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3950 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3951 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3952 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3953 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3954
3955 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3956 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3957 {"DAC L1 Source", "DMIC1", "DMIC L1"},
3958 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3959 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3960 {"DAC R1 Source", "DMIC1", "DMIC R1"},
3961
3962 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3963 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3964 {"DAC L2 Source", NULL, "DAC L2 Power"},
3965 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3966 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3967 {"DAC R2 Source", NULL, "DAC R2 Power"},
3968
3969 {"DAC L1", NULL, "DAC L1 Source"},
3970 {"DAC R1", NULL, "DAC R1 Source"},
3971 {"DAC L2", NULL, "DAC L2 Source"},
3972 {"DAC R2", NULL, "DAC R2 Source"},
3973
3974 {"DAC L1", NULL, "DAC 1 Clock"},
3975 {"DAC R1", NULL, "DAC 1 Clock"},
3976 {"DAC L2", NULL, "DAC 2 Clock"},
3977 {"DAC R2", NULL, "DAC 2 Clock"},
3978
3979 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3980 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3981 {"MONOVOL MIX", "BST1 Switch", "BST1"},
3982 {"MONOVOL MIX", "BST2 Switch", "BST2"},
3983 {"MONOVOL MIX", "BST3 Switch", "BST3"},
3984
3985 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3986 {"OUT MIXL", "INL Switch", "INL VOL"},
3987 {"OUT MIXL", "BST1 Switch", "BST1"},
3988 {"OUT MIXL", "BST2 Switch", "BST2"},
3989 {"OUT MIXL", "BST3 Switch", "BST3"},
3990 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3991 {"OUT MIXR", "INR Switch", "INR VOL"},
3992 {"OUT MIXR", "BST2 Switch", "BST2"},
3993 {"OUT MIXR", "BST3 Switch", "BST3"},
3994 {"OUT MIXR", "BST4 Switch", "BST4"},
3995
3996 {"MONOVOL", "Switch", "MONOVOL MIX"},
3997 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
3998 {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
3999 {"Mono Amp", NULL, "Mono MIX"},
4000 {"Mono Amp", NULL, "Vref2"},
8f365313 4001 {"Mono Amp", NULL, "Vref3"},
33ada14a
BL		 4002 {"Mono Amp", NULL, "CLKDET SYS"},
4003 {"Mono Amp", NULL, "CLKDET MONO"},
4004 {"Mono Playback", "Switch", "Mono Amp"},
4005 {"MONOOUT", NULL, "Mono Playback"},
4006
4007 {"HP Amp", NULL, "DAC L1"},
4008 {"HP Amp", NULL, "DAC R1"},
4009 {"HP Amp", NULL, "Charge Pump"},
4010 {"HP Amp", NULL, "CLKDET SYS"},
4011 {"HP Amp", NULL, "CLKDET HP"},
4012 {"HP Amp", NULL, "CBJ Power"},
4013 {"HP Amp", NULL, "Vref2"},
4014 {"HPO Playback", "Switch", "HP Amp"},
4015 {"HPOL", NULL, "HPO Playback"},
4016 {"HPOR", NULL, "HPO Playback"},
4017
4018 {"OUTVOL L", "Switch", "OUT MIXL"},
4019 {"OUTVOL R", "Switch", "OUT MIXR"},
4020 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
4021 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
4022 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
4023 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
4024 {"LOUT Amp", NULL, "LOUT L MIX"},
4025 {"LOUT Amp", NULL, "LOUT R MIX"},
4026 {"LOUT Amp", NULL, "Vref1"},
4027 {"LOUT Amp", NULL, "Vref2"},
4028 {"LOUT Amp", NULL, "CLKDET SYS"},
4029 {"LOUT Amp", NULL, "CLKDET LOUT"},
4030 {"LOUT L Playback", "Switch", "LOUT Amp"},
4031 {"LOUT R Playback", "Switch", "LOUT Amp"},
4032 {"LOUTL", NULL, "LOUT L Playback"},
4033 {"LOUTR", NULL, "LOUT R Playback"},
4034
4035 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
4036 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
4037 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
4038 {"PDM L Mux", NULL, "PDM Power"},
4039 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
4040 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
4041 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
4042 {"PDM R Mux", NULL, "PDM Power"},
4043 {"PDM L Playback", "Switch", "PDM L Mux"},
4044 {"PDM R Playback", "Switch", "PDM R Mux"},
4045 {"PDML", NULL, "PDM L Playback"},
4046 {"PDMR", NULL, "PDM R Playback"},
4047};
4048
948059dd
BL		 4049static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4050 unsigned int rx_mask, int slots, int slot_width)
4051{
fab70c27 4052 struct snd_soc_component *component = dai->component;
948059dd
BL		 4053 unsigned int val = 0;
4054
4055 if (rx_mask || tx_mask)
4056 val |= RT5665_I2S1_MODE_TDM;
4057
4058 switch (slots) {
4059 case 4:
4060 val |= RT5665_TDM_IN_CH_4;
4061 val |= RT5665_TDM_OUT_CH_4;
4062 break;
4063 case 6:
4064 val |= RT5665_TDM_IN_CH_6;
4065 val |= RT5665_TDM_OUT_CH_6;
4066 break;
4067 case 8:
4068 val |= RT5665_TDM_IN_CH_8;
4069 val |= RT5665_TDM_OUT_CH_8;
4070 break;
4071 case 2:
4072 break;
4073 default:
4074 return -EINVAL;
4075 }
4076
4077 switch (slot_width) {
4078 case 20:
4079 val |= RT5665_TDM_IN_LEN_20;
4080 val |= RT5665_TDM_OUT_LEN_20;
4081 break;
4082 case 24:
4083 val |= RT5665_TDM_IN_LEN_24;
4084 val |= RT5665_TDM_OUT_LEN_24;
4085 break;
4086 case 32:
4087 val |= RT5665_TDM_IN_LEN_32;
4088 val |= RT5665_TDM_OUT_LEN_32;
4089 break;
4090 case 16:
4091 break;
4092 default:
4093 return -EINVAL;
4094 }
4095
fab70c27 4096 snd_soc_component_update_bits(component, RT5665_TDM_CTRL_1,
948059dd
BL		 4097 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
4098 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
4099 RT5665_TDM_OUT_LEN_MASK, val);
4100
4101 return 0;
4102}
4103
4104
33ada14a
BL		 4105static int rt5665_hw_params(struct snd_pcm_substream *substream,
4106 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4107{
fab70c27
KM		 4108 struct snd_soc_component *component = dai->component;
4109 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
17febfa6 4110 unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100;
33ada14a
BL		 4111 int pre_div, frame_size;
4112
4113 rt5665->lrck[dai->id] = params_rate(params);
4114 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
4115 if (pre_div < 0) {
fab70c27
KM		 4116 dev_warn(component->dev, "Force using PLL");
4117 snd_soc_component_set_pll(component, 0, RT5665_PLL1_S_MCLK,
fa05899c 4118 rt5665->sysclk, rt5665->lrck[dai->id] * 512);
fab70c27 4119 snd_soc_component_set_sysclk(component, RT5665_SCLK_S_PLL1, 0,
fa05899c
BL		 4120 rt5665->lrck[dai->id] * 512, 0);
4121 pre_div = 1;
33ada14a
BL		 4122 }
4123 frame_size = snd_soc_params_to_frame_size(params);
4124 if (frame_size < 0) {
fab70c27 4125 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
33ada14a
BL		 4126 return -EINVAL;
4127 }
4128
4129 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
4130 rt5665->lrck[dai->id], pre_div, dai->id);
4131
4132 switch (params_width(params)) {
4133 case 16:
4134 val_bits = 0x0100;
4135 break;
4136 case 20:
4137 val_len |= RT5665_I2S_DL_20;
4138 val_bits = 0x1300;
4139 break;
4140 case 24:
4141 val_len |= RT5665_I2S_DL_24;
4142 val_bits = 0x2500;
4143 break;
4144 case 8:
4145 val_len |= RT5665_I2S_DL_8;
4146 break;
4147 default:
4148 return -EINVAL;
4149 }
4150
4151 switch (dai->id) {
4152 case RT5665_AIF1_1:
4153 case RT5665_AIF1_2:
948059dd
BL		 4154 if (params_channels(params) > 2)
4155 rt5665_set_tdm_slot(dai, 0xf, 0xf,
4156 params_channels(params), params_width(params));
17febfa6 4157 reg_clk = RT5665_ADDA_CLK_1;
33ada14a
BL		 4158 mask_clk = RT5665_I2S_PD1_MASK;
4159 val_clk = pre_div << RT5665_I2S_PD1_SFT;
fab70c27 4160 snd_soc_component_update_bits(component, RT5665_I2S1_SDP,
33ada14a
BL		 4161 RT5665_I2S_DL_MASK, val_len);
4162 break;
4163 case RT5665_AIF2_1:
4164 case RT5665_AIF2_2:
17febfa6 4165 reg_clk = RT5665_ADDA_CLK_2;
33ada14a
BL		 4166 mask_clk = RT5665_I2S_PD2_MASK;
4167 val_clk = pre_div << RT5665_I2S_PD2_SFT;
fab70c27 4168 snd_soc_component_update_bits(component, RT5665_I2S2_SDP,
33ada14a
BL		 4169 RT5665_I2S_DL_MASK, val_len);
4170 break;
4171 case RT5665_AIF3:
17febfa6 4172 reg_clk = RT5665_ADDA_CLK_2;
33ada14a
BL		 4173 mask_clk = RT5665_I2S_PD3_MASK;
4174 val_clk = pre_div << RT5665_I2S_PD3_SFT;
fab70c27 4175 snd_soc_component_update_bits(component, RT5665_I2S3_SDP,
33ada14a
BL		 4176 RT5665_I2S_DL_MASK, val_len);
4177 break;
4178 default:
fab70c27 4179 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
33ada14a
BL		 4180 return -EINVAL;
4181 }
4182
fab70c27
KM		 4183 snd_soc_component_update_bits(component, reg_clk, mask_clk, val_clk);
4184 snd_soc_component_update_bits(component, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
33ada14a
BL		 4185
4186 switch (rt5665->lrck[dai->id]) {
4187 case 192000:
fab70c27 4188 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
33ada14a
BL		 4189 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4190 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4191 break;
4192 case 96000:
fab70c27 4193 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
33ada14a
BL		 4194 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4195 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4196 break;
4197 default:
fab70c27 4198 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
33ada14a
BL		 4199 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4200 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4201 break;
4202 }
4203
01dfb1ec 4204 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
fab70c27 4205 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
01dfb1ec
BL		 4206 RT5665_I2S2_M_PD_MASK, pre_div << RT5665_I2S2_M_PD_SFT);
4207 }
4208 if (rt5665->master[RT5665_AIF3]) {
fab70c27 4209 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
01dfb1ec
BL		 4210 RT5665_I2S3_M_PD_MASK, pre_div << RT5665_I2S3_M_PD_SFT);
4211 }
4212
33ada14a
BL		 4213 return 0;
4214}
4215
4216static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4217{
fab70c27
KM		 4218 struct snd_soc_component *component = dai->component;
4219 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
33ada14a
BL		 4220 unsigned int reg_val = 0;
4221
4222 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4223 case SND_SOC_DAIFMT_CBM_CFM:
4224 rt5665->master[dai->id] = 1;
4225 break;
4226 case SND_SOC_DAIFMT_CBS_CFS:
4227 reg_val |= RT5665_I2S_MS_S;
4228 rt5665->master[dai->id] = 0;
4229 break;
4230 default:
4231 return -EINVAL;
4232 }
4233
4234 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4235 case SND_SOC_DAIFMT_NB_NF:
4236 break;
4237 case SND_SOC_DAIFMT_IB_NF:
4238 reg_val |= RT5665_I2S_BP_INV;
4239 break;
4240 default:
4241 return -EINVAL;
4242 }
4243
4244 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4245 case SND_SOC_DAIFMT_I2S:
4246 break;
4247 case SND_SOC_DAIFMT_LEFT_J:
4248 reg_val |= RT5665_I2S_DF_LEFT;
4249 break;
4250 case SND_SOC_DAIFMT_DSP_A:
4251 reg_val |= RT5665_I2S_DF_PCM_A;
4252 break;
4253 case SND_SOC_DAIFMT_DSP_B:
4254 reg_val |= RT5665_I2S_DF_PCM_B;
4255 break;
4256 default:
4257 return -EINVAL;
4258 }
4259
4260 switch (dai->id) {
4261 case RT5665_AIF1_1:
4262 case RT5665_AIF1_2:
fab70c27 4263 snd_soc_component_update_bits(component, RT5665_I2S1_SDP,
33ada14a
BL		 4264 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4265 RT5665_I2S_DF_MASK, reg_val);
4266 break;
4267 case RT5665_AIF2_1:
4268 case RT5665_AIF2_2:
fab70c27 4269 snd_soc_component_update_bits(component, RT5665_I2S2_SDP,
33ada14a
BL		 4270 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4271 RT5665_I2S_DF_MASK, reg_val);
4272 break;
4273 case RT5665_AIF3:
fab70c27 4274 snd_soc_component_update_bits(component, RT5665_I2S3_SDP,
33ada14a
BL		 4275 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4276 RT5665_I2S_DF_MASK, reg_val);
4277 break;
4278 default:
fab70c27 4279 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
33ada14a
BL		 4280 return -EINVAL;
4281 }
4282 return 0;
4283}
4284
fab70c27 4285static int rt5665_set_component_sysclk(struct snd_soc_component *component, int clk_id,
28d2ca39 4286 int source, unsigned int freq, int dir)
33ada14a 4287{
fab70c27 4288 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
01dfb1ec 4289 unsigned int reg_val = 0, src = 0;
33ada14a
BL		 4290
4291 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4292 return 0;
4293
4294 switch (clk_id) {
4295 case RT5665_SCLK_S_MCLK:
4296 reg_val |= RT5665_SCLK_SRC_MCLK;
01dfb1ec 4297 src = RT5665_CLK_SRC_MCLK;
33ada14a
BL		 4298 break;
4299 case RT5665_SCLK_S_PLL1:
4300 reg_val |= RT5665_SCLK_SRC_PLL1;
01dfb1ec 4301 src = RT5665_CLK_SRC_PLL1;
33ada14a
BL		 4302 break;
4303 case RT5665_SCLK_S_RCCLK:
4304 reg_val |= RT5665_SCLK_SRC_RCCLK;
01dfb1ec 4305 src = RT5665_CLK_SRC_RCCLK;
33ada14a
BL		 4306 break;
4307 default:
fab70c27 4308 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
33ada14a
BL		 4309 return -EINVAL;
4310 }
fab70c27 4311 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
33ada14a 4312 RT5665_SCLK_SRC_MASK, reg_val);
01dfb1ec
BL		 4313
4314 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
fab70c27 4315 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
01dfb1ec
BL		 4316 RT5665_I2S2_SRC_MASK, src << RT5665_I2S2_SRC_SFT);
4317 }
4318 if (rt5665->master[RT5665_AIF3]) {
fab70c27 4319 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
01dfb1ec
BL		 4320 RT5665_I2S3_SRC_MASK, src << RT5665_I2S3_SRC_SFT);
4321 }
4322
33ada14a
BL		 4323 rt5665->sysclk = freq;
4324 rt5665->sysclk_src = clk_id;
4325
fab70c27 4326 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
33ada14a
BL		 4327
4328 return 0;
4329}
4330
fab70c27 4331static int rt5665_set_component_pll(struct snd_soc_component *component, int pll_id,
ccd00d59
BL		 4332 int source, unsigned int freq_in,
4333 unsigned int freq_out)
33ada14a 4334{
fab70c27 4335 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
33ada14a
BL		 4336 struct rl6231_pll_code pll_code;
4337 int ret;
4338
ccd00d59 4339 if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
33ada14a
BL		 4340 freq_out == rt5665->pll_out)
4341 return 0;
4342
4343 if (!freq_in || !freq_out) {
fab70c27 4344 dev_dbg(component->dev, "PLL disabled\n");
33ada14a
BL		 4345
4346 rt5665->pll_in = 0;
4347 rt5665->pll_out = 0;
fab70c27 4348 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
33ada14a
BL		 4349 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4350 return 0;
4351 }
4352
ccd00d59 4353 switch (source) {
33ada14a 4354 case RT5665_PLL1_S_MCLK:
fab70c27 4355 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
33ada14a
BL		 4356 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4357 break;
4358 case RT5665_PLL1_S_BCLK1:
fab70c27 4359 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
33ada14a
BL		 4360 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4361 break;
4362 case RT5665_PLL1_S_BCLK2:
fab70c27 4363 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
33ada14a
BL		 4364 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4365 break;
4366 case RT5665_PLL1_S_BCLK3:
fab70c27 4367 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
33ada14a
BL		 4368 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4369 break;
4370 default:
fab70c27 4371 dev_err(component->dev, "Unknown PLL Source %d\n", source);
33ada14a
BL		 4372 return -EINVAL;
4373 }
4374
4375 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4376 if (ret < 0) {
fab70c27 4377 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
33ada14a
BL		 4378 return ret;
4379 }
4380
fab70c27 4381 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
33ada14a
BL		 4382 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4383 pll_code.n_code, pll_code.k_code);
4384
fab70c27 4385 snd_soc_component_write(component, RT5665_PLL_CTRL_1,
33ada14a 4386 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
fab70c27 4387 snd_soc_component_write(component, RT5665_PLL_CTRL_2,
33ada14a
BL		 4388 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
4389 pll_code.m_bp << RT5665_PLL_M_BP_SFT);
4390
4391 rt5665->pll_in = freq_in;
4392 rt5665->pll_out = freq_out;
ccd00d59 4393 rt5665->pll_src = source;
33ada14a
BL		 4394
4395 return 0;
4396}
4397
4398static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4399{
fab70c27
KM		 4400 struct snd_soc_component *component = dai->component;
4401 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
33ada14a 4402
fab70c27 4403 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
33ada14a
BL		 4404
4405 rt5665->bclk[dai->id] = ratio;
4406
4407 if (ratio == 64) {
4408 switch (dai->id) {
4409 case RT5665_AIF2_1:
4410 case RT5665_AIF2_2:
fab70c27 4411 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2,
33ada14a
BL		 4412 RT5665_I2S_BCLK_MS2_MASK,
4413 RT5665_I2S_BCLK_MS2_64);
4414 break;
4415 case RT5665_AIF3:
fab70c27 4416 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2,
33ada14a
BL		 4417 RT5665_I2S_BCLK_MS3_MASK,
4418 RT5665_I2S_BCLK_MS3_64);
4419 break;
4420 }
4421 }
4422
4423 return 0;
4424}
4425
fab70c27 4426static int rt5665_set_bias_level(struct snd_soc_component *component,
33ada14a
BL		 4427 enum snd_soc_bias_level level)
4428{
fab70c27 4429 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
33ada14a
BL		 4430
4431 switch (level) {
4432 case SND_SOC_BIAS_PREPARE:
4433 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4434 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4435 break;
4436
4437 case SND_SOC_BIAS_STANDBY:
4438 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4439 RT5665_PWR_LDO, RT5665_PWR_LDO);
4440 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4441 RT5665_PWR_MB, RT5665_PWR_MB);
4442 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4443 RT5665_DIG_GATE_CTRL, 0);
4444 break;
4445 case SND_SOC_BIAS_OFF:
4446 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4447 RT5665_PWR_LDO, 0);
4448 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4449 RT5665_PWR_MB, 0);
4450 break;
4451
4452 default:
4453 break;
4454 }
4455
4456 return 0;
4457}
4458
fab70c27 4459static int rt5665_probe(struct snd_soc_component *component)
33ada14a 4460{
fab70c27 4461 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
33ada14a 4462
fab70c27 4463 rt5665->component = component;
33ada14a
BL		 4464
4465 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4466
4467 return 0;
4468}
4469
fab70c27 4470static void rt5665_remove(struct snd_soc_component *component)
33ada14a 4471{
fab70c27 4472 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
33ada14a
BL		 4473
4474 regmap_write(rt5665->regmap, RT5665_RESET, 0);
33ada14a
BL		 4475}
4476
4477#ifdef CONFIG_PM
fab70c27 4478static int rt5665_suspend(struct snd_soc_component *component)
33ada14a 4479{
fab70c27 4480 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
33ada14a
BL		 4481
4482 regcache_cache_only(rt5665->regmap, true);
4483 regcache_mark_dirty(rt5665->regmap);
4484 return 0;
4485}
4486
fab70c27 4487static int rt5665_resume(struct snd_soc_component *component)
33ada14a 4488{
fab70c27 4489 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
33ada14a
BL		 4490
4491 regcache_cache_only(rt5665->regmap, false);
4492 regcache_sync(rt5665->regmap);
4493
4494 return 0;
4495}
4496#else
4497#define rt5665_suspend NULL
4498#define rt5665_resume NULL
4499#endif
4500
4501#define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4502#define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4503 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4504
4505static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4506 .hw_params = rt5665_hw_params,
4507 .set_fmt = rt5665_set_dai_fmt,
33ada14a 4508 .set_tdm_slot = rt5665_set_tdm_slot,
33ada14a
BL		 4509 .set_bclk_ratio = rt5665_set_bclk_ratio,
4510};
4511
4512static struct snd_soc_dai_driver rt5665_dai[] = {
4513 {
4514 .name = "rt5665-aif1_1",
4515 .id = RT5665_AIF1_1,
4516 .playback = {
4517 .stream_name = "AIF1 Playback",
4518 .channels_min = 1,
4519 .channels_max = 8,
4520 .rates = RT5665_STEREO_RATES,
4521 .formats = RT5665_FORMATS,
4522 },
4523 .capture = {
4524 .stream_name = "AIF1_1 Capture",
4525 .channels_min = 1,
4526 .channels_max = 8,
4527 .rates = RT5665_STEREO_RATES,
4528 .formats = RT5665_FORMATS,
4529 },
4530 .ops = &rt5665_aif_dai_ops,
4531 },
4532 {
4533 .name = "rt5665-aif1_2",
4534 .id = RT5665_AIF1_2,
4535 .capture = {
4536 .stream_name = "AIF1_2 Capture",
4537 .channels_min = 1,
4538 .channels_max = 8,
4539 .rates = RT5665_STEREO_RATES,
4540 .formats = RT5665_FORMATS,
4541 },
4542 .ops = &rt5665_aif_dai_ops,
4543 },
4544 {
4545 .name = "rt5665-aif2_1",
4546 .id = RT5665_AIF2_1,
4547 .playback = {
4548 .stream_name = "AIF2_1 Playback",
4549 .channels_min = 1,
4550 .channels_max = 2,
4551 .rates = RT5665_STEREO_RATES,
4552 .formats = RT5665_FORMATS,
4553 },
4554 .capture = {
4555 .stream_name = "AIF2_1 Capture",
4556 .channels_min = 1,
4557 .channels_max = 2,
4558 .rates = RT5665_STEREO_RATES,
4559 .formats = RT5665_FORMATS,
4560 },
4561 .ops = &rt5665_aif_dai_ops,
4562 },
4563 {
4564 .name = "rt5665-aif2_2",
4565 .id = RT5665_AIF2_2,
4566 .playback = {
4567 .stream_name = "AIF2_2 Playback",
4568 .channels_min = 1,
4569 .channels_max = 2,
4570 .rates = RT5665_STEREO_RATES,
4571 .formats = RT5665_FORMATS,
4572 },
4573 .capture = {
4574 .stream_name = "AIF2_2 Capture",
4575 .channels_min = 1,
4576 .channels_max = 2,
4577 .rates = RT5665_STEREO_RATES,
4578 .formats = RT5665_FORMATS,
4579 },
4580 .ops = &rt5665_aif_dai_ops,
4581 },
4582 {
4583 .name = "rt5665-aif3",
4584 .id = RT5665_AIF3,
4585 .playback = {
4586 .stream_name = "AIF3 Playback",
4587 .channels_min = 1,
4588 .channels_max = 2,
4589 .rates = RT5665_STEREO_RATES,
4590 .formats = RT5665_FORMATS,
4591 },
4592 .capture = {
4593 .stream_name = "AIF3 Capture",
4594 .channels_min = 1,
4595 .channels_max = 2,
4596 .rates = RT5665_STEREO_RATES,
4597 .formats = RT5665_FORMATS,
4598 },
4599 .ops = &rt5665_aif_dai_ops,
4600 },
4601};
4602
fab70c27
KM		 4603static const struct snd_soc_component_driver soc_component_dev_rt5665 = {
4604 .probe = rt5665_probe,
4605 .remove = rt5665_remove,
4606 .suspend = rt5665_suspend,
4607 .resume = rt5665_resume,
4608 .set_bias_level = rt5665_set_bias_level,
4609 .controls = rt5665_snd_controls,
4610 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4611 .dapm_widgets = rt5665_dapm_widgets,
4612 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4613 .dapm_routes = rt5665_dapm_routes,
4614 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
4615 .set_sysclk = rt5665_set_component_sysclk,
4616 .set_pll = rt5665_set_component_pll,
4617 .set_jack = rt5665_set_jack_detect,
4618 .use_pmdown_time = 1,
4619 .endianness = 1,
4620 .non_legacy_dai_naming = 1,
33ada14a
BL		 4621};
4622
4623
4624static const struct regmap_config rt5665_regmap = {
4625 .reg_bits = 16,
4626 .val_bits = 16,
4627 .max_register = 0x0400,
4628 .volatile_reg = rt5665_volatile_register,
4629 .readable_reg = rt5665_readable_register,
4630 .cache_type = REGCACHE_RBTREE,
4631 .reg_defaults = rt5665_reg,
4632 .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
1c96a2f6
DF		 4633 .use_single_read = true,
4634 .use_single_write = true,
33ada14a
BL		 4635};
4636
4637static const struct i2c_device_id rt5665_i2c_id[] = {
4638 {"rt5665", 0},
4639 {}
4640};
4641MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4642
4643static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4644{
4645 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4646 "realtek,in1-differential");
4647 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4648 "realtek,in2-differential");
4649 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4650 "realtek,in3-differential");
4651 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4652 "realtek,in4-differential");
4653
4654 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4655 &rt5665->pdata.dmic1_data_pin);
4656 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4657 &rt5665->pdata.dmic2_data_pin);
4658 of_property_read_u32(dev->of_node, "realtek,jd-src",
4659 &rt5665->pdata.jd_src);
4660
4661 rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
4662 "realtek,ldo1-en-gpios", 0);
4663
4664 return 0;
4665}
4666
4667static void rt5665_calibrate(struct rt5665_priv *rt5665)
4668{
4669 int value, count;
4670
4671 mutex_lock(&rt5665->calibrate_mutex);
4672
4673 regcache_cache_bypass(rt5665->regmap, true);
4674
4675 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4676 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4677 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4678 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4679 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4680 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4681 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4682 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4683 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4684 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4685 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4686 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4687 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4688 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4689 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4690 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4691 usleep_range(15000, 20000);
4692 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4693 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4694
4695 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4696 count = 0;
4697 while (true) {
4698 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4699 if (value & 0x8000)
4700 usleep_range(10000, 10005);
4701 else
4702 break;
4703
4704 if (count > 60) {
4705 pr_err("HP Calibration Failure\n");
4706 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4707 regcache_cache_bypass(rt5665->regmap, false);
0c95666f 4708 goto out_unlock;
33ada14a
BL		 4709 }
4710
4711 count++;
4712 }
4713
4714 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4715 count = 0;
4716 while (true) {
4717 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4718 if (value & 0x8000)
4719 usleep_range(10000, 10005);
4720 else
4721 break;
4722
4723 if (count > 60) {
4724 pr_err("MONO Calibration Failure\n");
4725 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4726 regcache_cache_bypass(rt5665->regmap, false);
0c95666f 4727 goto out_unlock;
33ada14a
BL		 4728 }
4729
4730 count++;
4731 }
4732
4733 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4734 regcache_cache_bypass(rt5665->regmap, false);
4735
4736 regcache_mark_dirty(rt5665->regmap);
4737 regcache_sync(rt5665->regmap);
4738
4739 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4740 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4741
0c95666f 4742out_unlock:
b059ca72 4743 rt5665->calibration_done = true;
33ada14a
BL		 4744 mutex_unlock(&rt5665->calibrate_mutex);
4745}
4746
4747static void rt5665_calibrate_handler(struct work_struct *work)
4748{
4749 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4750 calibrate_work.work);
4751
fab70c27 4752 while (!rt5665->component->card->instantiated) {
33ada14a
BL		 4753 pr_debug("%s\n", __func__);
4754 usleep_range(10000, 15000);
4755 }
4756
4757 rt5665_calibrate(rt5665);
4758}
4759
4760static int rt5665_i2c_probe(struct i2c_client *i2c,
4761 const struct i2c_device_id *id)
4762{
4763 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4764 struct rt5665_priv *rt5665;
4765 int i, ret;
4766 unsigned int val;
4767
4768 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4769 GFP_KERNEL);
4770
4771 if (rt5665 == NULL)
4772 return -ENOMEM;
4773
4774 i2c_set_clientdata(i2c, rt5665);
4775
4776 if (pdata)
4777 rt5665->pdata = *pdata;
4778 else
4779 rt5665_parse_dt(rt5665, &i2c->dev);
4780
4781 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
4782 rt5665->supplies[i].supply = rt5665_supply_names[i];
4783
4784 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
4785 rt5665->supplies);
4786 if (ret != 0) {
4787 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4788 return ret;
4789 }
4790
4791 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
4792 rt5665->supplies);
4793 if (ret != 0) {
4794 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4795 return ret;
4796 }
4797
4798 if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
f2826c1f
AL		 4799 if (devm_gpio_request_one(&i2c->dev, rt5665->pdata.ldo1_en,
4800 GPIOF_OUT_INIT_HIGH, "rt5665"))
33ada14a 4801 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
33ada14a
BL		 4802 }
4803
4804 /* Sleep for 300 ms miniumum */
4805 usleep_range(300000, 350000);
4806
4807 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4808 if (IS_ERR(rt5665->regmap)) {
4809 ret = PTR_ERR(rt5665->regmap);
4810 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4811 ret);
4812 return ret;
4813 }
4814
4815 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4816 if (val != DEVICE_ID) {
4817 dev_err(&i2c->dev,
4818 "Device with ID register %x is not rt5665\n", val);
4819 return -ENODEV;
4820 }
4821
4822 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4823 switch (val) {
4824 case 0x0:
4825 rt5665->id = CODEC_5666;
4826 break;
33ada14a
BL		 4827 case 0x3:
4828 default:
4829 rt5665->id = CODEC_5665;
4830 break;
4831 }
4832
4833 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4834
4835 /* line in diff mode*/
4836 if (rt5665->pdata.in1_diff)
4837 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4838 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4839 if (rt5665->pdata.in2_diff)
4840 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4841 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4842 if (rt5665->pdata.in3_diff)
4843 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4844 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4845 if (rt5665->pdata.in4_diff)
4846 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4847 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4848
4849 /* DMIC pin*/
4850 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4851 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4852 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4853 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4854 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4855 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4856 switch (rt5665->pdata.dmic1_data_pin) {
4857 case RT5665_DMIC1_DATA_IN2N:
4858 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4859 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4860 break;
4861
4862 case RT5665_DMIC1_DATA_GPIO4:
4863 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4864 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4865 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4866 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4867 break;
4868
4869 default:
4870 dev_dbg(&i2c->dev, "no DMIC1\n");
4871 break;
4872 }
4873
4874 switch (rt5665->pdata.dmic2_data_pin) {
4875 case RT5665_DMIC2_DATA_IN2P:
4876 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4877 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4878 break;
4879
4880 case RT5665_DMIC2_DATA_GPIO5:
4881 regmap_update_bits(rt5665->regmap,
4882 RT5665_DMIC_CTRL_1,
4883 RT5665_DMIC_2_DP_MASK,
4884 RT5665_DMIC_2_DP_GPIO5);
4885 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4886 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4887 break;
4888
4889 default:
4890 dev_dbg(&i2c->dev, "no DMIC2\n");
4891 break;
4892
4893 }
4894 }
4895
4896 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4897 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
39841944 4898 0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG);
33ada14a
BL		 4899 /* Work around for pow_pump */
4900 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4901 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4902
4903 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4904 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4905
4906 /* Set GPIO4,8 as input for combo jack */
4907 if (rt5665->id == CODEC_5666) {
4908 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4909 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4910 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4911 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4912 }
4913
4914 /* Enhance performance*/
4915 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4916 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
593dd5d9 4917 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
33ada14a
BL		 4918
4919 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4920 rt5665_jack_detect_handler);
4921 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4922 rt5665_calibrate_handler);
4923 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4924 rt5665_jd_check_handler);
4925
4926 mutex_init(&rt5665->calibrate_mutex);
4927
4928 if (i2c->irq) {
4929 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4930 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4931 | IRQF_ONESHOT, "rt5665", rt5665);
4932 if (ret)
4933 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4934
4935 }
4936
fab70c27
KM		 4937 return devm_snd_soc_register_component(&i2c->dev,
4938 &soc_component_dev_rt5665,
33ada14a
BL		 4939 rt5665_dai, ARRAY_SIZE(rt5665_dai));
4940}
4941
33ada14a
BL		 4942static void rt5665_i2c_shutdown(struct i2c_client *client)
4943{
4944 struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4945
4946 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4947}
4948
4949#ifdef CONFIG_OF
4950static const struct of_device_id rt5665_of_match[] = {
4951 {.compatible = "realtek,rt5665"},
4952 {.compatible = "realtek,rt5666"},
33ada14a
BL		 4953 {},
4954};
4955MODULE_DEVICE_TABLE(of, rt5665_of_match);
4956#endif
4957
4958#ifdef CONFIG_ACPI
abfedab1 4959static const struct acpi_device_id rt5665_acpi_match[] = {
33ada14a
BL		 4960 {"10EC5665", 0,},
4961 {"10EC5666", 0,},
33ada14a
BL		 4962 {},
4963};
4964MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4965#endif
4966
18fe7869 4967static struct i2c_driver rt5665_i2c_driver = {
33ada14a
BL		 4968 .driver = {
4969 .name = "rt5665",
4970 .of_match_table = of_match_ptr(rt5665_of_match),
4971 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4972 },
4973 .probe = rt5665_i2c_probe,
33ada14a
BL		 4974 .shutdown = rt5665_i2c_shutdown,
4975 .id_table = rt5665_i2c_id,
4976};
4977module_i2c_driver(rt5665_i2c_driver);
4978
4979MODULE_DESCRIPTION("ASoC RT5665 driver");
4980MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4981MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)