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Merge tag 'gcc-plugins-v5.2-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / sound / soc / codecs / rt5659.c
CommitLineData
d3cb2de2
BL		 1/*
2 * rt5659.c -- RT5659/RT5658 ALSA SoC audio codec driver
3 *
4 * Copyright 2015 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
c6f8769b 12#include <linux/clk.h>
d3cb2de2
BL		 13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
19#include <linux/platform_device.h>
20#include <linux/spi/spi.h>
21#include <linux/acpi.h>
22#include <linux/gpio.h>
23#include <linux/gpio/consumer.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/jack.h>
28#include <sound/soc.h>
29#include <sound/soc-dapm.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32#include <sound/rt5659.h>
33
34#include "rl6231.h"
35#include "rt5659.h"
36
37static const struct reg_default rt5659_reg[] = {
38 { 0x0000, 0x0000 },
39 { 0x0001, 0x4848 },
40 { 0x0002, 0x8080 },
41 { 0x0003, 0xc8c8 },
42 { 0x0004, 0xc80a },
43 { 0x0005, 0x0000 },
44 { 0x0006, 0x0000 },
45 { 0x0007, 0x0103 },
46 { 0x0008, 0x0080 },
47 { 0x0009, 0x0000 },
48 { 0x000a, 0x0000 },
49 { 0x000c, 0x0000 },
50 { 0x000d, 0x0000 },
51 { 0x000f, 0x0808 },
52 { 0x0010, 0x3080 },
53 { 0x0011, 0x4a00 },
54 { 0x0012, 0x4e00 },
55 { 0x0015, 0x42c1 },
56 { 0x0016, 0x0000 },
57 { 0x0018, 0x000b },
58 { 0x0019, 0xafaf },
59 { 0x001a, 0xafaf },
60 { 0x001b, 0x0011 },
61 { 0x001c, 0x2f2f },
62 { 0x001d, 0x2f2f },
63 { 0x001e, 0x2f2f },
64 { 0x001f, 0x0000 },
65 { 0x0020, 0x0000 },
66 { 0x0021, 0x0000 },
67 { 0x0022, 0x5757 },
68 { 0x0023, 0x0039 },
69 { 0x0026, 0xc060 },
70 { 0x0027, 0xd8d8 },
71 { 0x0029, 0x8080 },
72 { 0x002a, 0xaaaa },
73 { 0x002b, 0xaaaa },
74 { 0x002c, 0x00af },
75 { 0x002d, 0x0000 },
76 { 0x002f, 0x1002 },
77 { 0x0031, 0x5000 },
78 { 0x0032, 0x0000 },
79 { 0x0033, 0x0000 },
80 { 0x0034, 0x0000 },
81 { 0x0035, 0x0000 },
82 { 0x0036, 0x0000 },
83 { 0x003a, 0x0000 },
84 { 0x003b, 0x0000 },
85 { 0x003c, 0x007f },
86 { 0x003d, 0x0000 },
87 { 0x003e, 0x007f },
88 { 0x0040, 0x0808 },
89 { 0x0046, 0x001f },
90 { 0x0047, 0x001f },
91 { 0x0048, 0x0003 },
92 { 0x0049, 0xe061 },
93 { 0x004a, 0x0000 },
94 { 0x004b, 0x031f },
95 { 0x004d, 0x0000 },
96 { 0x004e, 0x001f },
97 { 0x004f, 0x0000 },
98 { 0x0050, 0x001f },
99 { 0x0052, 0xf000 },
100 { 0x0053, 0x0111 },
101 { 0x0054, 0x0064 },
102 { 0x0055, 0x0080 },
103 { 0x0056, 0xef0e },
104 { 0x0057, 0xf0f0 },
105 { 0x0058, 0xef0e },
106 { 0x0059, 0xf0f0 },
107 { 0x005a, 0xef0e },
108 { 0x005b, 0xf0f0 },
109 { 0x005c, 0xf000 },
110 { 0x005d, 0x0000 },
111 { 0x005e, 0x1f2c },
112 { 0x005f, 0x1f2c },
113 { 0x0060, 0x2717 },
114 { 0x0061, 0x0000 },
115 { 0x0062, 0x0000 },
116 { 0x0063, 0x003e },
117 { 0x0064, 0x0000 },
118 { 0x0065, 0x0000 },
119 { 0x0066, 0x0000 },
120 { 0x0067, 0x0000 },
121 { 0x006a, 0x0000 },
122 { 0x006b, 0x0000 },
123 { 0x006c, 0x0000 },
124 { 0x006e, 0x0000 },
125 { 0x006f, 0x0000 },
126 { 0x0070, 0x8000 },
127 { 0x0071, 0x8000 },
128 { 0x0072, 0x8000 },
129 { 0x0073, 0x1110 },
130 { 0x0074, 0xfe00 },
131 { 0x0075, 0x2409 },
132 { 0x0076, 0x000a },
133 { 0x0077, 0x00f0 },
134 { 0x0078, 0x0000 },
135 { 0x0079, 0x0000 },
136 { 0x007a, 0x0123 },
137 { 0x007b, 0x8003 },
138 { 0x0080, 0x0000 },
139 { 0x0081, 0x0000 },
140 { 0x0082, 0x0000 },
141 { 0x0083, 0x0000 },
142 { 0x0084, 0x0000 },
143 { 0x0085, 0x0000 },
144 { 0x0086, 0x0008 },
145 { 0x0087, 0x0000 },
146 { 0x0088, 0x0000 },
147 { 0x0089, 0x0000 },
148 { 0x008a, 0x0000 },
149 { 0x008b, 0x0000 },
150 { 0x008c, 0x0003 },
151 { 0x008e, 0x0000 },
152 { 0x008f, 0x1000 },
153 { 0x0090, 0x0646 },
154 { 0x0091, 0x0c16 },
155 { 0x0092, 0x0073 },
156 { 0x0093, 0x0000 },
157 { 0x0094, 0x0080 },
158 { 0x0097, 0x0000 },
159 { 0x0098, 0x0000 },
160 { 0x0099, 0x0000 },
161 { 0x009a, 0x0000 },
162 { 0x009b, 0x0000 },
163 { 0x009c, 0x007f },
164 { 0x009d, 0x0000 },
165 { 0x009e, 0x007f },
166 { 0x009f, 0x0000 },
167 { 0x00a0, 0x0060 },
168 { 0x00a1, 0x90a1 },
169 { 0x00ae, 0x2000 },
170 { 0x00af, 0x0000 },
171 { 0x00b0, 0x2000 },
172 { 0x00b1, 0x0000 },
173 { 0x00b2, 0x0000 },
174 { 0x00b6, 0x0000 },
175 { 0x00b7, 0x0000 },
176 { 0x00b8, 0x0000 },
177 { 0x00b9, 0x0000 },
178 { 0x00ba, 0x0000 },
179 { 0x00bb, 0x0000 },
180 { 0x00be, 0x0000 },
181 { 0x00bf, 0x0000 },
182 { 0x00c0, 0x0000 },
183 { 0x00c1, 0x0000 },
184 { 0x00c2, 0x0000 },
185 { 0x00c3, 0x0000 },
186 { 0x00c4, 0x0003 },
187 { 0x00c5, 0x0000 },
188 { 0x00cb, 0xa02f },
189 { 0x00cc, 0x0000 },
190 { 0x00cd, 0x0e02 },
191 { 0x00d6, 0x0000 },
192 { 0x00d7, 0x2244 },
193 { 0x00d9, 0x0809 },
194 { 0x00da, 0x0000 },
195 { 0x00db, 0x0008 },
196 { 0x00dc, 0x00c0 },
197 { 0x00dd, 0x6724 },
198 { 0x00de, 0x3131 },
199 { 0x00df, 0x0008 },
200 { 0x00e0, 0x4000 },
201 { 0x00e1, 0x3131 },
202 { 0x00e4, 0x400c },
203 { 0x00e5, 0x8031 },
204 { 0x00ea, 0xb320 },
205 { 0x00eb, 0x0000 },
206 { 0x00ec, 0xb300 },
207 { 0x00ed, 0x0000 },
208 { 0x00f0, 0x0000 },
209 { 0x00f1, 0x0202 },
210 { 0x00f2, 0x0ddd },
211 { 0x00f3, 0x0ddd },
212 { 0x00f4, 0x0ddd },
213 { 0x00f6, 0x0000 },
214 { 0x00f7, 0x0000 },
215 { 0x00f8, 0x0000 },
216 { 0x00f9, 0x0000 },
217 { 0x00fa, 0x8000 },
218 { 0x00fb, 0x0000 },
219 { 0x00fc, 0x0000 },
220 { 0x00fd, 0x0001 },
221 { 0x00fe, 0x10ec },
222 { 0x00ff, 0x6311 },
223 { 0x0100, 0xaaaa },
224 { 0x010a, 0xaaaa },
225 { 0x010b, 0x00a0 },
226 { 0x010c, 0xaeae },
227 { 0x010d, 0xaaaa },
228 { 0x010e, 0xaaa8 },
229 { 0x010f, 0xa0aa },
230 { 0x0110, 0xe02a },
231 { 0x0111, 0xa702 },
232 { 0x0112, 0xaaaa },
233 { 0x0113, 0x2800 },
234 { 0x0116, 0x0000 },
235 { 0x0117, 0x0f00 },
236 { 0x011a, 0x0020 },
237 { 0x011b, 0x0011 },
238 { 0x011c, 0x0150 },
239 { 0x011d, 0x0000 },
240 { 0x011e, 0x0000 },
241 { 0x011f, 0x0000 },
242 { 0x0120, 0x0000 },
243 { 0x0121, 0x009b },
244 { 0x0122, 0x5014 },
245 { 0x0123, 0x0421 },
246 { 0x0124, 0x7cea },
247 { 0x0125, 0x0420 },
248 { 0x0126, 0x5550 },
249 { 0x0132, 0x0000 },
250 { 0x0133, 0x0000 },
251 { 0x0137, 0x5055 },
252 { 0x0138, 0x3700 },
253 { 0x0139, 0x79a1 },
254 { 0x013a, 0x2020 },
255 { 0x013b, 0x2020 },
256 { 0x013c, 0x2005 },
257 { 0x013e, 0x1f00 },
258 { 0x013f, 0x0000 },
259 { 0x0145, 0x0002 },
260 { 0x0146, 0x0000 },
261 { 0x0147, 0x0000 },
262 { 0x0148, 0x0000 },
263 { 0x0150, 0x1813 },
264 { 0x0151, 0x0690 },
265 { 0x0152, 0x1c17 },
266 { 0x0153, 0x6883 },
267 { 0x0154, 0xd3ce },
268 { 0x0155, 0x352d },
269 { 0x0156, 0x00eb },
270 { 0x0157, 0x3717 },
271 { 0x0158, 0x4c6a },
272 { 0x0159, 0xe41b },
273 { 0x015a, 0x2a13 },
274 { 0x015b, 0xb600 },
275 { 0x015c, 0xc730 },
276 { 0x015d, 0x35d4 },
277 { 0x015e, 0x00bf },
278 { 0x0160, 0x0ec0 },
279 { 0x0161, 0x0020 },
280 { 0x0162, 0x0080 },
281 { 0x0163, 0x0800 },
282 { 0x0164, 0x0000 },
283 { 0x0165, 0x0000 },
284 { 0x0166, 0x0000 },
285 { 0x0167, 0x001f },
286 { 0x0170, 0x4e80 },
287 { 0x0171, 0x0020 },
288 { 0x0172, 0x0080 },
289 { 0x0173, 0x0800 },
290 { 0x0174, 0x000c },
291 { 0x0175, 0x0000 },
292 { 0x0190, 0x3300 },
293 { 0x0191, 0x2200 },
294 { 0x0192, 0x0000 },
295 { 0x01b0, 0x4b38 },
296 { 0x01b1, 0x0000 },
297 { 0x01b2, 0x0000 },
298 { 0x01b3, 0x0000 },
299 { 0x01c0, 0x0045 },
300 { 0x01c1, 0x0540 },
301 { 0x01c2, 0x0000 },
302 { 0x01c3, 0x0030 },
303 { 0x01c7, 0x0000 },
304 { 0x01c8, 0x5757 },
305 { 0x01c9, 0x5757 },
306 { 0x01ca, 0x5757 },
307 { 0x01cb, 0x5757 },
308 { 0x01cc, 0x5757 },
309 { 0x01cd, 0x5757 },
310 { 0x01ce, 0x006f },
311 { 0x01da, 0x0000 },
312 { 0x01db, 0x0000 },
313 { 0x01de, 0x7d00 },
314 { 0x01df, 0x10c0 },
315 { 0x01e0, 0x06a1 },
316 { 0x01e1, 0x0000 },
317 { 0x01e2, 0x0000 },
318 { 0x01e3, 0x0000 },
319 { 0x01e4, 0x0001 },
320 { 0x01e6, 0x0000 },
321 { 0x01e7, 0x0000 },
322 { 0x01e8, 0x0000 },
323 { 0x01ea, 0x0000 },
324 { 0x01eb, 0x0000 },
325 { 0x01ec, 0x0000 },
326 { 0x01ed, 0x0000 },
327 { 0x01ee, 0x0000 },
328 { 0x01ef, 0x0000 },
329 { 0x01f0, 0x0000 },
330 { 0x01f1, 0x0000 },
331 { 0x01f2, 0x0000 },
332 { 0x01f6, 0x1e04 },
333 { 0x01f7, 0x01a1 },
334 { 0x01f8, 0x0000 },
335 { 0x01f9, 0x0000 },
336 { 0x01fa, 0x0002 },
337 { 0x01fb, 0x0000 },
338 { 0x01fc, 0x0000 },
339 { 0x01fd, 0x0000 },
340 { 0x01fe, 0x0000 },
341 { 0x0200, 0x066c },
342 { 0x0201, 0x7fff },
343 { 0x0202, 0x7fff },
344 { 0x0203, 0x0000 },
345 { 0x0204, 0x0000 },
346 { 0x0205, 0x0000 },
347 { 0x0206, 0x0000 },
348 { 0x0207, 0x0000 },
349 { 0x0208, 0x0000 },
350 { 0x0256, 0x0000 },
351 { 0x0257, 0x0000 },
352 { 0x0258, 0x0000 },
353 { 0x0259, 0x0000 },
354 { 0x025a, 0x0000 },
355 { 0x025b, 0x3333 },
356 { 0x025c, 0x3333 },
357 { 0x025d, 0x3333 },
358 { 0x025e, 0x0000 },
359 { 0x025f, 0x0000 },
360 { 0x0260, 0x0000 },
361 { 0x0261, 0x0022 },
362 { 0x0262, 0x0300 },
363 { 0x0265, 0x1e80 },
364 { 0x0266, 0x0131 },
365 { 0x0267, 0x0003 },
366 { 0x0268, 0x0000 },
367 { 0x0269, 0x0000 },
368 { 0x026a, 0x0000 },
369 { 0x026b, 0x0000 },
370 { 0x026c, 0x0000 },
371 { 0x026d, 0x0000 },
372 { 0x026e, 0x0000 },
373 { 0x026f, 0x0000 },
374 { 0x0270, 0x0000 },
375 { 0x0271, 0x0000 },
376 { 0x0272, 0x0000 },
377 { 0x0273, 0x0000 },
378 { 0x0280, 0x0000 },
379 { 0x0281, 0x0000 },
380 { 0x0282, 0x0418 },
381 { 0x0283, 0x7fff },
382 { 0x0284, 0x7000 },
383 { 0x0290, 0x01d0 },
384 { 0x0291, 0x0100 },
385 { 0x02fa, 0x0000 },
386 { 0x02fb, 0x0000 },
387 { 0x02fc, 0x0000 },
388 { 0x0300, 0x001f },
389 { 0x0301, 0x032c },
390 { 0x0302, 0x5f21 },
391 { 0x0303, 0x4000 },
392 { 0x0304, 0x4000 },
393 { 0x0305, 0x0600 },
394 { 0x0306, 0x8000 },
395 { 0x0307, 0x0700 },
396 { 0x0308, 0x001f },
397 { 0x0309, 0x032c },
398 { 0x030a, 0x5f21 },
399 { 0x030b, 0x4000 },
400 { 0x030c, 0x4000 },
401 { 0x030d, 0x0600 },
402 { 0x030e, 0x8000 },
403 { 0x030f, 0x0700 },
404 { 0x0310, 0x4560 },
405 { 0x0311, 0xa4a8 },
406 { 0x0312, 0x7418 },
407 { 0x0313, 0x0000 },
408 { 0x0314, 0x0006 },
409 { 0x0315, 0x00ff },
410 { 0x0316, 0xc400 },
411 { 0x0317, 0x4560 },
412 { 0x0318, 0xa4a8 },
413 { 0x0319, 0x7418 },
414 { 0x031a, 0x0000 },
415 { 0x031b, 0x0006 },
416 { 0x031c, 0x00ff },
417 { 0x031d, 0xc400 },
418 { 0x0320, 0x0f20 },
419 { 0x0321, 0x8700 },
420 { 0x0322, 0x7dc2 },
421 { 0x0323, 0xa178 },
422 { 0x0324, 0x5383 },
423 { 0x0325, 0x7dc2 },
424 { 0x0326, 0xa178 },
425 { 0x0327, 0x5383 },
426 { 0x0328, 0x003e },
427 { 0x0329, 0x02c1 },
428 { 0x032a, 0xd37d },
429 { 0x0330, 0x00a6 },
430 { 0x0331, 0x04c3 },
431 { 0x0332, 0x27c8 },
432 { 0x0333, 0xbf50 },
433 { 0x0334, 0x0045 },
434 { 0x0335, 0x2007 },
435 { 0x0336, 0x7418 },
436 { 0x0337, 0x0501 },
437 { 0x0338, 0x0000 },
438 { 0x0339, 0x0010 },
439 { 0x033a, 0x1010 },
440 { 0x0340, 0x0800 },
441 { 0x0341, 0x0800 },
442 { 0x0342, 0x0800 },
443 { 0x0343, 0x0800 },
444 { 0x0344, 0x0000 },
445 { 0x0345, 0x0000 },
446 { 0x0346, 0x0000 },
447 { 0x0347, 0x0000 },
448 { 0x0348, 0x0000 },
449 { 0x0349, 0x0000 },
450 { 0x034a, 0x0000 },
451 { 0x034b, 0x0000 },
452 { 0x034c, 0x0000 },
453 { 0x034d, 0x0000 },
454 { 0x034e, 0x0000 },
455 { 0x034f, 0x0000 },
456 { 0x0350, 0x0000 },
457 { 0x0351, 0x0000 },
458 { 0x0352, 0x0000 },
459 { 0x0353, 0x0000 },
460 { 0x0354, 0x0000 },
461 { 0x0355, 0x0000 },
462 { 0x0356, 0x0000 },
463 { 0x0357, 0x0000 },
464 { 0x0358, 0x0000 },
465 { 0x0359, 0x0000 },
466 { 0x035a, 0x0000 },
467 { 0x035b, 0x0000 },
468 { 0x035c, 0x0000 },
469 { 0x035d, 0x0000 },
470 { 0x035e, 0x2000 },
471 { 0x035f, 0x0000 },
472 { 0x0360, 0x2000 },
473 { 0x0361, 0x2000 },
474 { 0x0362, 0x0000 },
475 { 0x0363, 0x2000 },
476 { 0x0364, 0x0200 },
477 { 0x0365, 0x0000 },
478 { 0x0366, 0x0000 },
479 { 0x0367, 0x0000 },
480 { 0x0368, 0x0000 },
481 { 0x0369, 0x0000 },
482 { 0x036a, 0x0000 },
483 { 0x036b, 0x0000 },
484 { 0x036c, 0x0000 },
485 { 0x036d, 0x0000 },
486 { 0x036e, 0x0200 },
487 { 0x036f, 0x0000 },
488 { 0x0370, 0x0000 },
489 { 0x0371, 0x0000 },
490 { 0x0372, 0x0000 },
491 { 0x0373, 0x0000 },
492 { 0x0374, 0x0000 },
493 { 0x0375, 0x0000 },
494 { 0x0376, 0x0000 },
495 { 0x0377, 0x0000 },
496 { 0x03d0, 0x0000 },
497 { 0x03d1, 0x0000 },
498 { 0x03d2, 0x0000 },
499 { 0x03d3, 0x0000 },
500 { 0x03d4, 0x2000 },
501 { 0x03d5, 0x2000 },
502 { 0x03d6, 0x0000 },
503 { 0x03d7, 0x0000 },
504 { 0x03d8, 0x2000 },
505 { 0x03d9, 0x2000 },
506 { 0x03da, 0x2000 },
507 { 0x03db, 0x2000 },
508 { 0x03dc, 0x0000 },
509 { 0x03dd, 0x0000 },
510 { 0x03de, 0x0000 },
511 { 0x03df, 0x2000 },
512 { 0x03e0, 0x0000 },
513 { 0x03e1, 0x0000 },
514 { 0x03e2, 0x0000 },
515 { 0x03e3, 0x0000 },
516 { 0x03e4, 0x0000 },
517 { 0x03e5, 0x0000 },
518 { 0x03e6, 0x0000 },
519 { 0x03e7, 0x0000 },
520 { 0x03e8, 0x0000 },
521 { 0x03e9, 0x0000 },
522 { 0x03ea, 0x0000 },
523 { 0x03eb, 0x0000 },
524 { 0x03ec, 0x0000 },
525 { 0x03ed, 0x0000 },
526 { 0x03ee, 0x0000 },
527 { 0x03ef, 0x0000 },
528 { 0x03f0, 0x0800 },
529 { 0x03f1, 0x0800 },
530 { 0x03f2, 0x0800 },
531 { 0x03f3, 0x0800 },
532};
533
534static bool rt5659_volatile_register(struct device *dev, unsigned int reg)
535{
536 switch (reg) {
537 case RT5659_RESET:
538 case RT5659_EJD_CTRL_2:
539 case RT5659_SILENCE_CTRL:
540 case RT5659_DAC2_DIG_VOL:
541 case RT5659_HP_IMP_GAIN_2:
542 case RT5659_PDM_OUT_CTRL:
543 case RT5659_PDM_DATA_CTRL_1:
544 case RT5659_PDM_DATA_CTRL_4:
545 case RT5659_HAPTIC_GEN_CTRL_1:
546 case RT5659_HAPTIC_GEN_CTRL_3:
547 case RT5659_HAPTIC_LPF_CTRL_3:
548 case RT5659_CLK_DET:
549 case RT5659_MICBIAS_1:
550 case RT5659_ASRC_11:
551 case RT5659_ADC_EQ_CTRL_1:
552 case RT5659_DAC_EQ_CTRL_1:
553 case RT5659_INT_ST_1:
554 case RT5659_INT_ST_2:
555 case RT5659_GPIO_STA:
556 case RT5659_SINE_GEN_CTRL_1:
557 case RT5659_IL_CMD_1:
558 case RT5659_4BTN_IL_CMD_1:
559 case RT5659_PSV_IL_CMD_1:
560 case RT5659_AJD1_CTRL:
561 case RT5659_AJD2_AJD3_CTRL:
562 case RT5659_JD_CTRL_3:
563 case RT5659_VENDOR_ID:
564 case RT5659_VENDOR_ID_1:
565 case RT5659_DEVICE_ID:
566 case RT5659_MEMORY_TEST:
567 case RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL:
568 case RT5659_VOL_TEST:
569 case RT5659_STO_NG2_CTRL_1:
570 case RT5659_STO_NG2_CTRL_5:
571 case RT5659_STO_NG2_CTRL_6:
572 case RT5659_STO_NG2_CTRL_7:
573 case RT5659_MONO_NG2_CTRL_1:
574 case RT5659_MONO_NG2_CTRL_5:
575 case RT5659_MONO_NG2_CTRL_6:
576 case RT5659_HP_IMP_SENS_CTRL_1:
577 case RT5659_HP_IMP_SENS_CTRL_3:
578 case RT5659_HP_IMP_SENS_CTRL_4:
579 case RT5659_HP_CALIB_CTRL_1:
580 case RT5659_HP_CALIB_CTRL_9:
581 case RT5659_HP_CALIB_STA_1:
582 case RT5659_HP_CALIB_STA_2:
583 case RT5659_HP_CALIB_STA_3:
584 case RT5659_HP_CALIB_STA_4:
585 case RT5659_HP_CALIB_STA_5:
586 case RT5659_HP_CALIB_STA_6:
587 case RT5659_HP_CALIB_STA_7:
588 case RT5659_HP_CALIB_STA_8:
589 case RT5659_HP_CALIB_STA_9:
590 case RT5659_MONO_AMP_CALIB_CTRL_1:
591 case RT5659_MONO_AMP_CALIB_CTRL_3:
592 case RT5659_MONO_AMP_CALIB_STA_1:
593 case RT5659_MONO_AMP_CALIB_STA_2:
594 case RT5659_MONO_AMP_CALIB_STA_3:
595 case RT5659_MONO_AMP_CALIB_STA_4:
596 case RT5659_SPK_PWR_LMT_STA_1:
597 case RT5659_SPK_PWR_LMT_STA_2:
598 case RT5659_SPK_PWR_LMT_STA_3:
599 case RT5659_SPK_PWR_LMT_STA_4:
600 case RT5659_SPK_PWR_LMT_STA_5:
601 case RT5659_SPK_PWR_LMT_STA_6:
602 case RT5659_SPK_DC_CAILB_CTRL_1:
603 case RT5659_SPK_DC_CAILB_STA_1:
604 case RT5659_SPK_DC_CAILB_STA_2:
605 case RT5659_SPK_DC_CAILB_STA_3:
606 case RT5659_SPK_DC_CAILB_STA_4:
607 case RT5659_SPK_DC_CAILB_STA_5:
608 case RT5659_SPK_DC_CAILB_STA_6:
609 case RT5659_SPK_DC_CAILB_STA_7:
610 case RT5659_SPK_DC_CAILB_STA_8:
611 case RT5659_SPK_DC_CAILB_STA_9:
612 case RT5659_SPK_DC_CAILB_STA_10:
613 case RT5659_SPK_VDD_STA_1:
614 case RT5659_SPK_VDD_STA_2:
615 case RT5659_SPK_DC_DET_CTRL_1:
616 case RT5659_PURE_DC_DET_CTRL_1:
617 case RT5659_PURE_DC_DET_CTRL_2:
618 case RT5659_DRC1_PRIV_1:
619 case RT5659_DRC1_PRIV_4:
620 case RT5659_DRC1_PRIV_5:
621 case RT5659_DRC1_PRIV_6:
622 case RT5659_DRC1_PRIV_7:
623 case RT5659_DRC2_PRIV_1:
624 case RT5659_DRC2_PRIV_4:
625 case RT5659_DRC2_PRIV_5:
626 case RT5659_DRC2_PRIV_6:
627 case RT5659_DRC2_PRIV_7:
628 case RT5659_ALC_PGA_STA_1:
629 case RT5659_ALC_PGA_STA_2:
630 case RT5659_ALC_PGA_STA_3:
631 return true;
632 default:
633 return false;
634 }
635}
636
637static bool rt5659_readable_register(struct device *dev, unsigned int reg)
638{
639 switch (reg) {
640 case RT5659_RESET:
641 case RT5659_SPO_VOL:
642 case RT5659_HP_VOL:
643 case RT5659_LOUT:
644 case RT5659_MONO_OUT:
645 case RT5659_HPL_GAIN:
646 case RT5659_HPR_GAIN:
647 case RT5659_MONO_GAIN:
648 case RT5659_SPDIF_CTRL_1:
649 case RT5659_SPDIF_CTRL_2:
650 case RT5659_CAL_BST_CTRL:
651 case RT5659_IN1_IN2:
652 case RT5659_IN3_IN4:
653 case RT5659_INL1_INR1_VOL:
654 case RT5659_EJD_CTRL_1:
655 case RT5659_EJD_CTRL_2:
656 case RT5659_EJD_CTRL_3:
657 case RT5659_SILENCE_CTRL:
658 case RT5659_PSV_CTRL:
659 case RT5659_SIDETONE_CTRL:
660 case RT5659_DAC1_DIG_VOL:
661 case RT5659_DAC2_DIG_VOL:
662 case RT5659_DAC_CTRL:
663 case RT5659_STO1_ADC_DIG_VOL:
664 case RT5659_MONO_ADC_DIG_VOL:
665 case RT5659_STO2_ADC_DIG_VOL:
666 case RT5659_STO1_BOOST:
667 case RT5659_MONO_BOOST:
668 case RT5659_STO2_BOOST:
669 case RT5659_HP_IMP_GAIN_1:
670 case RT5659_HP_IMP_GAIN_2:
671 case RT5659_STO1_ADC_MIXER:
672 case RT5659_MONO_ADC_MIXER:
673 case RT5659_AD_DA_MIXER:
674 case RT5659_STO_DAC_MIXER:
675 case RT5659_MONO_DAC_MIXER:
676 case RT5659_DIG_MIXER:
677 case RT5659_A_DAC_MUX:
678 case RT5659_DIG_INF23_DATA:
679 case RT5659_PDM_OUT_CTRL:
680 case RT5659_PDM_DATA_CTRL_1:
681 case RT5659_PDM_DATA_CTRL_2:
682 case RT5659_PDM_DATA_CTRL_3:
683 case RT5659_PDM_DATA_CTRL_4:
684 case RT5659_SPDIF_CTRL:
685 case RT5659_REC1_GAIN:
686 case RT5659_REC1_L1_MIXER:
687 case RT5659_REC1_L2_MIXER:
688 case RT5659_REC1_R1_MIXER:
689 case RT5659_REC1_R2_MIXER:
690 case RT5659_CAL_REC:
691 case RT5659_REC2_L1_MIXER:
692 case RT5659_REC2_L2_MIXER:
693 case RT5659_REC2_R1_MIXER:
694 case RT5659_REC2_R2_MIXER:
695 case RT5659_SPK_L_MIXER:
696 case RT5659_SPK_R_MIXER:
697 case RT5659_SPO_AMP_GAIN:
698 case RT5659_ALC_BACK_GAIN:
699 case RT5659_MONOMIX_GAIN:
700 case RT5659_MONOMIX_IN_GAIN:
701 case RT5659_OUT_L_GAIN:
702 case RT5659_OUT_L_MIXER:
703 case RT5659_OUT_R_GAIN:
704 case RT5659_OUT_R_MIXER:
705 case RT5659_LOUT_MIXER:
706 case RT5659_HAPTIC_GEN_CTRL_1:
707 case RT5659_HAPTIC_GEN_CTRL_2:
708 case RT5659_HAPTIC_GEN_CTRL_3:
709 case RT5659_HAPTIC_GEN_CTRL_4:
710 case RT5659_HAPTIC_GEN_CTRL_5:
711 case RT5659_HAPTIC_GEN_CTRL_6:
712 case RT5659_HAPTIC_GEN_CTRL_7:
713 case RT5659_HAPTIC_GEN_CTRL_8:
714 case RT5659_HAPTIC_GEN_CTRL_9:
715 case RT5659_HAPTIC_GEN_CTRL_10:
716 case RT5659_HAPTIC_GEN_CTRL_11:
717 case RT5659_HAPTIC_LPF_CTRL_1:
718 case RT5659_HAPTIC_LPF_CTRL_2:
719 case RT5659_HAPTIC_LPF_CTRL_3:
720 case RT5659_PWR_DIG_1:
721 case RT5659_PWR_DIG_2:
722 case RT5659_PWR_ANLG_1:
723 case RT5659_PWR_ANLG_2:
724 case RT5659_PWR_ANLG_3:
725 case RT5659_PWR_MIXER:
726 case RT5659_PWR_VOL:
727 case RT5659_PRIV_INDEX:
728 case RT5659_CLK_DET:
729 case RT5659_PRIV_DATA:
730 case RT5659_PRE_DIV_1:
731 case RT5659_PRE_DIV_2:
732 case RT5659_I2S1_SDP:
733 case RT5659_I2S2_SDP:
734 case RT5659_I2S3_SDP:
735 case RT5659_ADDA_CLK_1:
736 case RT5659_ADDA_CLK_2:
737 case RT5659_DMIC_CTRL_1:
738 case RT5659_DMIC_CTRL_2:
739 case RT5659_TDM_CTRL_1:
740 case RT5659_TDM_CTRL_2:
741 case RT5659_TDM_CTRL_3:
742 case RT5659_TDM_CTRL_4:
743 case RT5659_TDM_CTRL_5:
744 case RT5659_GLB_CLK:
745 case RT5659_PLL_CTRL_1:
746 case RT5659_PLL_CTRL_2:
747 case RT5659_ASRC_1:
748 case RT5659_ASRC_2:
749 case RT5659_ASRC_3:
750 case RT5659_ASRC_4:
751 case RT5659_ASRC_5:
752 case RT5659_ASRC_6:
753 case RT5659_ASRC_7:
754 case RT5659_ASRC_8:
755 case RT5659_ASRC_9:
756 case RT5659_ASRC_10:
757 case RT5659_DEPOP_1:
758 case RT5659_DEPOP_2:
759 case RT5659_DEPOP_3:
760 case RT5659_HP_CHARGE_PUMP_1:
761 case RT5659_HP_CHARGE_PUMP_2:
762 case RT5659_MICBIAS_1:
763 case RT5659_MICBIAS_2:
764 case RT5659_ASRC_11:
765 case RT5659_ASRC_12:
766 case RT5659_ASRC_13:
767 case RT5659_REC_M1_M2_GAIN_CTRL:
768 case RT5659_RC_CLK_CTRL:
769 case RT5659_CLASSD_CTRL_1:
770 case RT5659_CLASSD_CTRL_2:
771 case RT5659_ADC_EQ_CTRL_1:
772 case RT5659_ADC_EQ_CTRL_2:
773 case RT5659_DAC_EQ_CTRL_1:
774 case RT5659_DAC_EQ_CTRL_2:
775 case RT5659_DAC_EQ_CTRL_3:
776 case RT5659_IRQ_CTRL_1:
777 case RT5659_IRQ_CTRL_2:
778 case RT5659_IRQ_CTRL_3:
779 case RT5659_IRQ_CTRL_4:
780 case RT5659_IRQ_CTRL_5:
781 case RT5659_IRQ_CTRL_6:
782 case RT5659_INT_ST_1:
783 case RT5659_INT_ST_2:
784 case RT5659_GPIO_CTRL_1:
785 case RT5659_GPIO_CTRL_2:
786 case RT5659_GPIO_CTRL_3:
787 case RT5659_GPIO_CTRL_4:
788 case RT5659_GPIO_CTRL_5:
789 case RT5659_GPIO_STA:
790 case RT5659_SINE_GEN_CTRL_1:
791 case RT5659_SINE_GEN_CTRL_2:
792 case RT5659_SINE_GEN_CTRL_3:
793 case RT5659_HP_AMP_DET_CTRL_1:
794 case RT5659_HP_AMP_DET_CTRL_2:
795 case RT5659_SV_ZCD_1:
796 case RT5659_SV_ZCD_2:
797 case RT5659_IL_CMD_1:
798 case RT5659_IL_CMD_2:
799 case RT5659_IL_CMD_3:
800 case RT5659_IL_CMD_4:
801 case RT5659_4BTN_IL_CMD_1:
802 case RT5659_4BTN_IL_CMD_2:
803 case RT5659_4BTN_IL_CMD_3:
804 case RT5659_PSV_IL_CMD_1:
805 case RT5659_PSV_IL_CMD_2:
806 case RT5659_ADC_STO1_HP_CTRL_1:
807 case RT5659_ADC_STO1_HP_CTRL_2:
808 case RT5659_ADC_MONO_HP_CTRL_1:
809 case RT5659_ADC_MONO_HP_CTRL_2:
810 case RT5659_AJD1_CTRL:
811 case RT5659_AJD2_AJD3_CTRL:
812 case RT5659_JD1_THD:
813 case RT5659_JD2_THD:
814 case RT5659_JD3_THD:
815 case RT5659_JD_CTRL_1:
816 case RT5659_JD_CTRL_2:
817 case RT5659_JD_CTRL_3:
818 case RT5659_JD_CTRL_4:
819 case RT5659_DIG_MISC:
820 case RT5659_DUMMY_2:
821 case RT5659_DUMMY_3:
822 case RT5659_VENDOR_ID:
823 case RT5659_VENDOR_ID_1:
824 case RT5659_DEVICE_ID:
825 case RT5659_DAC_ADC_DIG_VOL:
826 case RT5659_BIAS_CUR_CTRL_1:
827 case RT5659_BIAS_CUR_CTRL_2:
828 case RT5659_BIAS_CUR_CTRL_3:
829 case RT5659_BIAS_CUR_CTRL_4:
830 case RT5659_BIAS_CUR_CTRL_5:
831 case RT5659_BIAS_CUR_CTRL_6:
832 case RT5659_BIAS_CUR_CTRL_7:
833 case RT5659_BIAS_CUR_CTRL_8:
834 case RT5659_BIAS_CUR_CTRL_9:
835 case RT5659_BIAS_CUR_CTRL_10:
836 case RT5659_MEMORY_TEST:
837 case RT5659_VREF_REC_OP_FB_CAP_CTRL:
838 case RT5659_CLASSD_0:
839 case RT5659_CLASSD_1:
840 case RT5659_CLASSD_2:
841 case RT5659_CLASSD_3:
842 case RT5659_CLASSD_4:
843 case RT5659_CLASSD_5:
844 case RT5659_CLASSD_6:
845 case RT5659_CLASSD_7:
846 case RT5659_CLASSD_8:
847 case RT5659_CLASSD_9:
848 case RT5659_CLASSD_10:
849 case RT5659_CHARGE_PUMP_1:
850 case RT5659_CHARGE_PUMP_2:
851 case RT5659_DIG_IN_CTRL_1:
852 case RT5659_DIG_IN_CTRL_2:
853 case RT5659_PAD_DRIVING_CTRL:
854 case RT5659_SOFT_RAMP_DEPOP:
855 case RT5659_PLL:
856 case RT5659_CHOP_DAC:
857 case RT5659_CHOP_ADC:
858 case RT5659_CALIB_ADC_CTRL:
859 case RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL:
860 case RT5659_VOL_TEST:
861 case RT5659_TEST_MODE_CTRL_1:
862 case RT5659_TEST_MODE_CTRL_2:
863 case RT5659_TEST_MODE_CTRL_3:
864 case RT5659_TEST_MODE_CTRL_4:
865 case RT5659_BASSBACK_CTRL:
866 case RT5659_MP3_PLUS_CTRL_1:
867 case RT5659_MP3_PLUS_CTRL_2:
868 case RT5659_MP3_HPF_A1:
869 case RT5659_MP3_HPF_A2:
870 case RT5659_MP3_HPF_H0:
871 case RT5659_MP3_LPF_H0:
872 case RT5659_3D_SPK_CTRL:
873 case RT5659_3D_SPK_COEF_1:
874 case RT5659_3D_SPK_COEF_2:
875 case RT5659_3D_SPK_COEF_3:
876 case RT5659_3D_SPK_COEF_4:
877 case RT5659_3D_SPK_COEF_5:
878 case RT5659_3D_SPK_COEF_6:
879 case RT5659_3D_SPK_COEF_7:
880 case RT5659_STO_NG2_CTRL_1:
881 case RT5659_STO_NG2_CTRL_2:
882 case RT5659_STO_NG2_CTRL_3:
883 case RT5659_STO_NG2_CTRL_4:
884 case RT5659_STO_NG2_CTRL_5:
885 case RT5659_STO_NG2_CTRL_6:
886 case RT5659_STO_NG2_CTRL_7:
887 case RT5659_STO_NG2_CTRL_8:
888 case RT5659_MONO_NG2_CTRL_1:
889 case RT5659_MONO_NG2_CTRL_2:
890 case RT5659_MONO_NG2_CTRL_3:
891 case RT5659_MONO_NG2_CTRL_4:
892 case RT5659_MONO_NG2_CTRL_5:
893 case RT5659_MONO_NG2_CTRL_6:
894 case RT5659_MID_HP_AMP_DET:
895 case RT5659_LOW_HP_AMP_DET:
896 case RT5659_LDO_CTRL:
897 case RT5659_HP_DECROSS_CTRL_1:
898 case RT5659_HP_DECROSS_CTRL_2:
899 case RT5659_HP_DECROSS_CTRL_3:
900 case RT5659_HP_DECROSS_CTRL_4:
901 case RT5659_HP_IMP_SENS_CTRL_1:
902 case RT5659_HP_IMP_SENS_CTRL_2:
903 case RT5659_HP_IMP_SENS_CTRL_3:
904 case RT5659_HP_IMP_SENS_CTRL_4:
905 case RT5659_HP_IMP_SENS_MAP_1:
906 case RT5659_HP_IMP_SENS_MAP_2:
907 case RT5659_HP_IMP_SENS_MAP_3:
908 case RT5659_HP_IMP_SENS_MAP_4:
909 case RT5659_HP_IMP_SENS_MAP_5:
910 case RT5659_HP_IMP_SENS_MAP_6:
911 case RT5659_HP_IMP_SENS_MAP_7:
912 case RT5659_HP_IMP_SENS_MAP_8:
913 case RT5659_HP_LOGIC_CTRL_1:
914 case RT5659_HP_LOGIC_CTRL_2:
915 case RT5659_HP_CALIB_CTRL_1:
916 case RT5659_HP_CALIB_CTRL_2:
917 case RT5659_HP_CALIB_CTRL_3:
918 case RT5659_HP_CALIB_CTRL_4:
919 case RT5659_HP_CALIB_CTRL_5:
920 case RT5659_HP_CALIB_CTRL_6:
921 case RT5659_HP_CALIB_CTRL_7:
922 case RT5659_HP_CALIB_CTRL_9:
923 case RT5659_HP_CALIB_CTRL_10:
924 case RT5659_HP_CALIB_CTRL_11:
925 case RT5659_HP_CALIB_STA_1:
926 case RT5659_HP_CALIB_STA_2:
927 case RT5659_HP_CALIB_STA_3:
928 case RT5659_HP_CALIB_STA_4:
929 case RT5659_HP_CALIB_STA_5:
930 case RT5659_HP_CALIB_STA_6:
931 case RT5659_HP_CALIB_STA_7:
932 case RT5659_HP_CALIB_STA_8:
933 case RT5659_HP_CALIB_STA_9:
934 case RT5659_MONO_AMP_CALIB_CTRL_1:
935 case RT5659_MONO_AMP_CALIB_CTRL_2:
936 case RT5659_MONO_AMP_CALIB_CTRL_3:
937 case RT5659_MONO_AMP_CALIB_CTRL_4:
938 case RT5659_MONO_AMP_CALIB_CTRL_5:
939 case RT5659_MONO_AMP_CALIB_STA_1:
940 case RT5659_MONO_AMP_CALIB_STA_2:
941 case RT5659_MONO_AMP_CALIB_STA_3:
942 case RT5659_MONO_AMP_CALIB_STA_4:
943 case RT5659_SPK_PWR_LMT_CTRL_1:
944 case RT5659_SPK_PWR_LMT_CTRL_2:
945 case RT5659_SPK_PWR_LMT_CTRL_3:
946 case RT5659_SPK_PWR_LMT_STA_1:
947 case RT5659_SPK_PWR_LMT_STA_2:
948 case RT5659_SPK_PWR_LMT_STA_3:
949 case RT5659_SPK_PWR_LMT_STA_4:
950 case RT5659_SPK_PWR_LMT_STA_5:
951 case RT5659_SPK_PWR_LMT_STA_6:
952 case RT5659_FLEX_SPK_BST_CTRL_1:
953 case RT5659_FLEX_SPK_BST_CTRL_2:
954 case RT5659_FLEX_SPK_BST_CTRL_3:
955 case RT5659_FLEX_SPK_BST_CTRL_4:
956 case RT5659_SPK_EX_LMT_CTRL_1:
957 case RT5659_SPK_EX_LMT_CTRL_2:
958 case RT5659_SPK_EX_LMT_CTRL_3:
959 case RT5659_SPK_EX_LMT_CTRL_4:
960 case RT5659_SPK_EX_LMT_CTRL_5:
961 case RT5659_SPK_EX_LMT_CTRL_6:
962 case RT5659_SPK_EX_LMT_CTRL_7:
963 case RT5659_ADJ_HPF_CTRL_1:
964 case RT5659_ADJ_HPF_CTRL_2:
965 case RT5659_SPK_DC_CAILB_CTRL_1:
966 case RT5659_SPK_DC_CAILB_CTRL_2:
967 case RT5659_SPK_DC_CAILB_CTRL_3:
968 case RT5659_SPK_DC_CAILB_CTRL_4:
969 case RT5659_SPK_DC_CAILB_CTRL_5:
970 case RT5659_SPK_DC_CAILB_STA_1:
971 case RT5659_SPK_DC_CAILB_STA_2:
972 case RT5659_SPK_DC_CAILB_STA_3:
973 case RT5659_SPK_DC_CAILB_STA_4:
974 case RT5659_SPK_DC_CAILB_STA_5:
975 case RT5659_SPK_DC_CAILB_STA_6:
976 case RT5659_SPK_DC_CAILB_STA_7:
977 case RT5659_SPK_DC_CAILB_STA_8:
978 case RT5659_SPK_DC_CAILB_STA_9:
979 case RT5659_SPK_DC_CAILB_STA_10:
980 case RT5659_SPK_VDD_STA_1:
981 case RT5659_SPK_VDD_STA_2:
982 case RT5659_SPK_DC_DET_CTRL_1:
983 case RT5659_SPK_DC_DET_CTRL_2:
984 case RT5659_SPK_DC_DET_CTRL_3:
985 case RT5659_PURE_DC_DET_CTRL_1:
986 case RT5659_PURE_DC_DET_CTRL_2:
987 case RT5659_DUMMY_4:
988 case RT5659_DUMMY_5:
989 case RT5659_DUMMY_6:
990 case RT5659_DRC1_CTRL_1:
991 case RT5659_DRC1_CTRL_2:
992 case RT5659_DRC1_CTRL_3:
993 case RT5659_DRC1_CTRL_4:
994 case RT5659_DRC1_CTRL_5:
995 case RT5659_DRC1_CTRL_6:
996 case RT5659_DRC1_HARD_LMT_CTRL_1:
997 case RT5659_DRC1_HARD_LMT_CTRL_2:
998 case RT5659_DRC2_CTRL_1:
999 case RT5659_DRC2_CTRL_2:
1000 case RT5659_DRC2_CTRL_3:
1001 case RT5659_DRC2_CTRL_4:
1002 case RT5659_DRC2_CTRL_5:
1003 case RT5659_DRC2_CTRL_6:
1004 case RT5659_DRC2_HARD_LMT_CTRL_1:
1005 case RT5659_DRC2_HARD_LMT_CTRL_2:
1006 case RT5659_DRC1_PRIV_1:
1007 case RT5659_DRC1_PRIV_2:
1008 case RT5659_DRC1_PRIV_3:
1009 case RT5659_DRC1_PRIV_4:
1010 case RT5659_DRC1_PRIV_5:
1011 case RT5659_DRC1_PRIV_6:
1012 case RT5659_DRC1_PRIV_7:
1013 case RT5659_DRC2_PRIV_1:
1014 case RT5659_DRC2_PRIV_2:
1015 case RT5659_DRC2_PRIV_3:
1016 case RT5659_DRC2_PRIV_4:
1017 case RT5659_DRC2_PRIV_5:
1018 case RT5659_DRC2_PRIV_6:
1019 case RT5659_DRC2_PRIV_7:
1020 case RT5659_MULTI_DRC_CTRL:
1021 case RT5659_CROSS_OVER_1:
1022 case RT5659_CROSS_OVER_2:
1023 case RT5659_CROSS_OVER_3:
1024 case RT5659_CROSS_OVER_4:
1025 case RT5659_CROSS_OVER_5:
1026 case RT5659_CROSS_OVER_6:
1027 case RT5659_CROSS_OVER_7:
1028 case RT5659_CROSS_OVER_8:
1029 case RT5659_CROSS_OVER_9:
1030 case RT5659_CROSS_OVER_10:
1031 case RT5659_ALC_PGA_CTRL_1:
1032 case RT5659_ALC_PGA_CTRL_2:
1033 case RT5659_ALC_PGA_CTRL_3:
1034 case RT5659_ALC_PGA_CTRL_4:
1035 case RT5659_ALC_PGA_CTRL_5:
1036 case RT5659_ALC_PGA_CTRL_6:
1037 case RT5659_ALC_PGA_CTRL_7:
1038 case RT5659_ALC_PGA_CTRL_8:
1039 case RT5659_ALC_PGA_STA_1:
1040 case RT5659_ALC_PGA_STA_2:
1041 case RT5659_ALC_PGA_STA_3:
1042 case RT5659_DAC_L_EQ_PRE_VOL:
1043 case RT5659_DAC_R_EQ_PRE_VOL:
1044 case RT5659_DAC_L_EQ_POST_VOL:
1045 case RT5659_DAC_R_EQ_POST_VOL:
1046 case RT5659_DAC_L_EQ_LPF1_A1:
1047 case RT5659_DAC_L_EQ_LPF1_H0:
1048 case RT5659_DAC_R_EQ_LPF1_A1:
1049 case RT5659_DAC_R_EQ_LPF1_H0:
1050 case RT5659_DAC_L_EQ_BPF2_A1:
1051 case RT5659_DAC_L_EQ_BPF2_A2:
1052 case RT5659_DAC_L_EQ_BPF2_H0:
1053 case RT5659_DAC_R_EQ_BPF2_A1:
1054 case RT5659_DAC_R_EQ_BPF2_A2:
1055 case RT5659_DAC_R_EQ_BPF2_H0:
1056 case RT5659_DAC_L_EQ_BPF3_A1:
1057 case RT5659_DAC_L_EQ_BPF3_A2:
1058 case RT5659_DAC_L_EQ_BPF3_H0:
1059 case RT5659_DAC_R_EQ_BPF3_A1:
1060 case RT5659_DAC_R_EQ_BPF3_A2:
1061 case RT5659_DAC_R_EQ_BPF3_H0:
1062 case RT5659_DAC_L_EQ_BPF4_A1:
1063 case RT5659_DAC_L_EQ_BPF4_A2:
1064 case RT5659_DAC_L_EQ_BPF4_H0:
1065 case RT5659_DAC_R_EQ_BPF4_A1:
1066 case RT5659_DAC_R_EQ_BPF4_A2:
1067 case RT5659_DAC_R_EQ_BPF4_H0:
1068 case RT5659_DAC_L_EQ_HPF1_A1:
1069 case RT5659_DAC_L_EQ_HPF1_H0:
1070 case RT5659_DAC_R_EQ_HPF1_A1:
1071 case RT5659_DAC_R_EQ_HPF1_H0:
1072 case RT5659_DAC_L_EQ_HPF2_A1:
1073 case RT5659_DAC_L_EQ_HPF2_A2:
1074 case RT5659_DAC_L_EQ_HPF2_H0:
1075 case RT5659_DAC_R_EQ_HPF2_A1:
1076 case RT5659_DAC_R_EQ_HPF2_A2:
1077 case RT5659_DAC_R_EQ_HPF2_H0:
1078 case RT5659_DAC_L_BI_EQ_BPF1_H0_1:
1079 case RT5659_DAC_L_BI_EQ_BPF1_H0_2:
1080 case RT5659_DAC_L_BI_EQ_BPF1_B1_1:
1081 case RT5659_DAC_L_BI_EQ_BPF1_B1_2:
1082 case RT5659_DAC_L_BI_EQ_BPF1_B2_1:
1083 case RT5659_DAC_L_BI_EQ_BPF1_B2_2:
1084 case RT5659_DAC_L_BI_EQ_BPF1_A1_1:
1085 case RT5659_DAC_L_BI_EQ_BPF1_A1_2:
1086 case RT5659_DAC_L_BI_EQ_BPF1_A2_1:
1087 case RT5659_DAC_L_BI_EQ_BPF1_A2_2:
1088 case RT5659_DAC_R_BI_EQ_BPF1_H0_1:
1089 case RT5659_DAC_R_BI_EQ_BPF1_H0_2:
1090 case RT5659_DAC_R_BI_EQ_BPF1_B1_1:
1091 case RT5659_DAC_R_BI_EQ_BPF1_B1_2:
1092 case RT5659_DAC_R_BI_EQ_BPF1_B2_1:
1093 case RT5659_DAC_R_BI_EQ_BPF1_B2_2:
1094 case RT5659_DAC_R_BI_EQ_BPF1_A1_1:
1095 case RT5659_DAC_R_BI_EQ_BPF1_A1_2:
1096 case RT5659_DAC_R_BI_EQ_BPF1_A2_1:
1097 case RT5659_DAC_R_BI_EQ_BPF1_A2_2:
1098 case RT5659_ADC_L_EQ_LPF1_A1:
1099 case RT5659_ADC_R_EQ_LPF1_A1:
1100 case RT5659_ADC_L_EQ_LPF1_H0:
1101 case RT5659_ADC_R_EQ_LPF1_H0:
1102 case RT5659_ADC_L_EQ_BPF1_A1:
1103 case RT5659_ADC_R_EQ_BPF1_A1:
1104 case RT5659_ADC_L_EQ_BPF1_A2:
1105 case RT5659_ADC_R_EQ_BPF1_A2:
1106 case RT5659_ADC_L_EQ_BPF1_H0:
1107 case RT5659_ADC_R_EQ_BPF1_H0:
1108 case RT5659_ADC_L_EQ_BPF2_A1:
1109 case RT5659_ADC_R_EQ_BPF2_A1:
1110 case RT5659_ADC_L_EQ_BPF2_A2:
1111 case RT5659_ADC_R_EQ_BPF2_A2:
1112 case RT5659_ADC_L_EQ_BPF2_H0:
1113 case RT5659_ADC_R_EQ_BPF2_H0:
1114 case RT5659_ADC_L_EQ_BPF3_A1:
1115 case RT5659_ADC_R_EQ_BPF3_A1:
1116 case RT5659_ADC_L_EQ_BPF3_A2:
1117 case RT5659_ADC_R_EQ_BPF3_A2:
1118 case RT5659_ADC_L_EQ_BPF3_H0:
1119 case RT5659_ADC_R_EQ_BPF3_H0:
1120 case RT5659_ADC_L_EQ_BPF4_A1:
1121 case RT5659_ADC_R_EQ_BPF4_A1:
1122 case RT5659_ADC_L_EQ_BPF4_A2:
1123 case RT5659_ADC_R_EQ_BPF4_A2:
1124 case RT5659_ADC_L_EQ_BPF4_H0:
1125 case RT5659_ADC_R_EQ_BPF4_H0:
1126 case RT5659_ADC_L_EQ_HPF1_A1:
1127 case RT5659_ADC_R_EQ_HPF1_A1:
1128 case RT5659_ADC_L_EQ_HPF1_H0:
1129 case RT5659_ADC_R_EQ_HPF1_H0:
1130 case RT5659_ADC_L_EQ_PRE_VOL:
1131 case RT5659_ADC_R_EQ_PRE_VOL:
1132 case RT5659_ADC_L_EQ_POST_VOL:
1133 case RT5659_ADC_R_EQ_POST_VOL:
1134 return true;
1135 default:
1136 return false;
1137 }
1138}
1139
1140static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2325, 75, 0);
1141static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
1142static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
1143static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
1144static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
1145static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
1146static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
1147
1148/* Interface data select */
1149static const char * const rt5659_data_select[] = {
1150 "L/R", "R/L", "L/L", "R/R"
1151};
1152
eae39b5f 1153static SOC_ENUM_SINGLE_DECL(rt5659_if1_01_adc_enum,
d3cb2de2
BL		 1154 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT01_SFT, rt5659_data_select);
1155
eae39b5f 1156static SOC_ENUM_SINGLE_DECL(rt5659_if1_23_adc_enum,
d3cb2de2
BL		 1157 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT23_SFT, rt5659_data_select);
1158
eae39b5f 1159static SOC_ENUM_SINGLE_DECL(rt5659_if1_45_adc_enum,
d3cb2de2
BL		 1160 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT45_SFT, rt5659_data_select);
1161
eae39b5f 1162static SOC_ENUM_SINGLE_DECL(rt5659_if1_67_adc_enum,
d3cb2de2
BL		 1163 RT5659_TDM_CTRL_2, RT5659_DS_ADC_SLOT67_SFT, rt5659_data_select);
1164
eae39b5f 1165static SOC_ENUM_SINGLE_DECL(rt5659_if2_dac_enum,
d3cb2de2
BL		 1166 RT5659_DIG_INF23_DATA, RT5659_IF2_DAC_SEL_SFT, rt5659_data_select);
1167
eae39b5f 1168static SOC_ENUM_SINGLE_DECL(rt5659_if2_adc_enum,
d3cb2de2
BL		 1169 RT5659_DIG_INF23_DATA, RT5659_IF2_ADC_SEL_SFT, rt5659_data_select);
1170
eae39b5f 1171static SOC_ENUM_SINGLE_DECL(rt5659_if3_dac_enum,
d3cb2de2
BL		 1172 RT5659_DIG_INF23_DATA, RT5659_IF3_DAC_SEL_SFT, rt5659_data_select);
1173
eae39b5f 1174static SOC_ENUM_SINGLE_DECL(rt5659_if3_adc_enum,
d3cb2de2
BL		 1175 RT5659_DIG_INF23_DATA, RT5659_IF3_ADC_SEL_SFT, rt5659_data_select);
1176
1177static const struct snd_kcontrol_new rt5659_if1_01_adc_swap_mux =
1178 SOC_DAPM_ENUM("IF1 01 ADC Swap Source", rt5659_if1_01_adc_enum);
1179
1180static const struct snd_kcontrol_new rt5659_if1_23_adc_swap_mux =
1181 SOC_DAPM_ENUM("IF1 23 ADC1 Swap Source", rt5659_if1_23_adc_enum);
1182
1183static const struct snd_kcontrol_new rt5659_if1_45_adc_swap_mux =
1184 SOC_DAPM_ENUM("IF1 45 ADC1 Swap Source", rt5659_if1_45_adc_enum);
1185
1186static const struct snd_kcontrol_new rt5659_if1_67_adc_swap_mux =
1187 SOC_DAPM_ENUM("IF1 67 ADC1 Swap Source", rt5659_if1_67_adc_enum);
1188
1189static const struct snd_kcontrol_new rt5659_if2_dac_swap_mux =
1190 SOC_DAPM_ENUM("IF2 DAC Swap Source", rt5659_if2_dac_enum);
1191
1192static const struct snd_kcontrol_new rt5659_if2_adc_swap_mux =
1193 SOC_DAPM_ENUM("IF2 ADC Swap Source", rt5659_if2_adc_enum);
1194
1195static const struct snd_kcontrol_new rt5659_if3_dac_swap_mux =
1196 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5659_if3_dac_enum);
1197
1198static const struct snd_kcontrol_new rt5659_if3_adc_swap_mux =
1199 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5659_if3_adc_enum);
1200
1201static const char * const rt5659_asrc_clk_src[] = {
1202 "clk_sysy_div_out", "clk_i2s1_track", "clk_i2s2_track",
1203 "clk_i2s3_track", "clk_sys2", "clk_sys3"
1204};
1205
1206static unsigned int rt5659_asrc_clk_map_values[] = {
1207 0, 1, 2, 3, 5, 6,
1208};
1209
eae39b5f 1210static SOC_VALUE_ENUM_SINGLE_DECL(
d3cb2de2
BL		 1211 rt5659_da_sto_asrc_enum, RT5659_ASRC_2, RT5659_DA_STO_T_SFT, 0x7,
1212 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1213
eae39b5f 1214static SOC_VALUE_ENUM_SINGLE_DECL(
d3cb2de2
BL		 1215 rt5659_da_monol_asrc_enum, RT5659_ASRC_2, RT5659_DA_MONO_L_T_SFT, 0x7,
1216 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1217
eae39b5f 1218static SOC_VALUE_ENUM_SINGLE_DECL(
d3cb2de2
BL		 1219 rt5659_da_monor_asrc_enum, RT5659_ASRC_2, RT5659_DA_MONO_R_T_SFT, 0x7,
1220 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1221
eae39b5f 1222static SOC_VALUE_ENUM_SINGLE_DECL(
d3cb2de2
BL		 1223 rt5659_ad_sto1_asrc_enum, RT5659_ASRC_2, RT5659_AD_STO1_T_SFT, 0x7,
1224 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1225
eae39b5f 1226static SOC_VALUE_ENUM_SINGLE_DECL(
d3cb2de2
BL		 1227 rt5659_ad_sto2_asrc_enum, RT5659_ASRC_3, RT5659_AD_STO2_T_SFT, 0x7,
1228 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1229
eae39b5f 1230static SOC_VALUE_ENUM_SINGLE_DECL(
d3cb2de2
BL		 1231 rt5659_ad_monol_asrc_enum, RT5659_ASRC_3, RT5659_AD_MONO_L_T_SFT, 0x7,
1232 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1233
eae39b5f 1234static SOC_VALUE_ENUM_SINGLE_DECL(
d3cb2de2
BL		 1235 rt5659_ad_monor_asrc_enum, RT5659_ASRC_3, RT5659_AD_MONO_R_T_SFT, 0x7,
1236 rt5659_asrc_clk_src, rt5659_asrc_clk_map_values);
1237
1238static int rt5659_hp_vol_put(struct snd_kcontrol *kcontrol,
1239 struct snd_ctl_elem_value *ucontrol)
1240{
de86a332 1241 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
d3cb2de2
BL		 1242 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1243
de86a332
KM		 1244 if (snd_soc_component_read32(component, RT5659_STO_NG2_CTRL_1) & RT5659_NG2_EN) {
1245 snd_soc_component_update_bits(component, RT5659_STO_NG2_CTRL_1,
d3cb2de2 1246 RT5659_NG2_EN_MASK, RT5659_NG2_DIS);
de86a332 1247 snd_soc_component_update_bits(component, RT5659_STO_NG2_CTRL_1,
d3cb2de2
BL		 1248 RT5659_NG2_EN_MASK, RT5659_NG2_EN);
1249 }
1250
1251 return ret;
1252}
1253
de86a332 1254static void rt5659_enable_push_button_irq(struct snd_soc_component *component,
d3cb2de2
BL		 1255 bool enable)
1256{
de86a332 1257 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
d3cb2de2
BL		 1258
1259 if (enable) {
de86a332 1260 snd_soc_component_write(component, RT5659_4BTN_IL_CMD_1, 0x000b);
d3cb2de2
BL		 1261
1262 /* MICBIAS1 and Mic Det Power for button detect*/
1263 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1264 snd_soc_dapm_force_enable_pin(dapm,
1265 "Mic Det Power");
1266 snd_soc_dapm_sync(dapm);
1267
de86a332 1268 snd_soc_component_update_bits(component, RT5659_PWR_ANLG_2,
d3cb2de2 1269 RT5659_PWR_MB1, RT5659_PWR_MB1);
de86a332 1270 snd_soc_component_update_bits(component, RT5659_PWR_VOL,
d3cb2de2
BL		 1271 RT5659_PWR_MIC_DET, RT5659_PWR_MIC_DET);
1272
de86a332 1273 snd_soc_component_update_bits(component, RT5659_IRQ_CTRL_2,
d3cb2de2 1274 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_EN);
de86a332 1275 snd_soc_component_update_bits(component, RT5659_4BTN_IL_CMD_2,
d3cb2de2
BL		 1276 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_EN);
1277 } else {
de86a332 1278 snd_soc_component_update_bits(component, RT5659_4BTN_IL_CMD_2,
d3cb2de2 1279 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_DIS);
de86a332 1280 snd_soc_component_update_bits(component, RT5659_IRQ_CTRL_2,
d3cb2de2
BL		 1281 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_DIS);
1282 /* MICBIAS1 and Mic Det Power for button detect*/
1283 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1284 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1285 snd_soc_dapm_sync(dapm);
1286 }
1287}
1288
1289/**
1290 * rt5659_headset_detect - Detect headset.
de86a332 1291 * @component: SoC audio component device.
d3cb2de2
BL		 1292 * @jack_insert: Jack insert or not.
1293 *
1294 * Detect whether is headset or not when jack inserted.
1295 *
1296 * Returns detect status.
1297 */
1298
de86a332 1299static int rt5659_headset_detect(struct snd_soc_component *component, int jack_insert)
d3cb2de2 1300{
de86a332 1301 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
d3cb2de2
BL		 1302 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1303 int reg_63;
1304
de86a332 1305 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
d3cb2de2
BL		 1306
1307 if (jack_insert) {
1308 snd_soc_dapm_force_enable_pin(dapm,
1309 "Mic Det Power");
1310 snd_soc_dapm_sync(dapm);
de86a332 1311 reg_63 = snd_soc_component_read32(component, RT5659_PWR_ANLG_1);
d3cb2de2 1312
de86a332 1313 snd_soc_component_update_bits(component, RT5659_PWR_ANLG_1,
d3cb2de2
BL		 1314 RT5659_PWR_VREF2 | RT5659_PWR_MB,
1315 RT5659_PWR_VREF2 | RT5659_PWR_MB);
1316 msleep(20);
de86a332 1317 snd_soc_component_update_bits(component, RT5659_PWR_ANLG_1,
d3cb2de2
BL		 1318 RT5659_PWR_FV2, RT5659_PWR_FV2);
1319
de86a332
KM		 1320 snd_soc_component_write(component, RT5659_EJD_CTRL_2, 0x4160);
1321 snd_soc_component_update_bits(component, RT5659_EJD_CTRL_1,
d3cb2de2
BL		 1322 0x20, 0x0);
1323 msleep(20);
de86a332 1324 snd_soc_component_update_bits(component, RT5659_EJD_CTRL_1,
d3cb2de2
BL		 1325 0x20, 0x20);
1326
1327 while (i < 5) {
1328 msleep(sleep_time[i]);
de86a332 1329 val = snd_soc_component_read32(component, RT5659_EJD_CTRL_2) & 0x0003;
d3cb2de2
BL		 1330 i++;
1331 if (val == 0x1 || val == 0x2 || val == 0x3)
1332 break;
1333 }
1334
1335 switch (val) {
1336 case 1:
1337 rt5659->jack_type = SND_JACK_HEADSET;
de86a332 1338 rt5659_enable_push_button_irq(component, true);
d3cb2de2
BL		 1339 break;
1340 default:
de86a332 1341 snd_soc_component_write(component, RT5659_PWR_ANLG_1, reg_63);
d3cb2de2
BL		 1342 rt5659->jack_type = SND_JACK_HEADPHONE;
1343 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1344 snd_soc_dapm_sync(dapm);
1345 break;
1346 }
1347 } else {
1348 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1349 snd_soc_dapm_sync(dapm);
1350 if (rt5659->jack_type == SND_JACK_HEADSET)
de86a332 1351 rt5659_enable_push_button_irq(component, false);
d3cb2de2
BL		 1352 rt5659->jack_type = 0;
1353 }
1354
de86a332 1355 dev_dbg(component->dev, "jack_type = %d\n", rt5659->jack_type);
d3cb2de2
BL		 1356 return rt5659->jack_type;
1357}
1358
de86a332 1359static int rt5659_button_detect(struct snd_soc_component *component)
d3cb2de2
BL		 1360{
1361 int btn_type, val;
1362
de86a332 1363 val = snd_soc_component_read32(component, RT5659_4BTN_IL_CMD_1);
d3cb2de2 1364 btn_type = val & 0xfff0;
de86a332 1365 snd_soc_component_write(component, RT5659_4BTN_IL_CMD_1, val);
d3cb2de2
BL		 1366
1367 return btn_type;
1368}
1369
1370static irqreturn_t rt5659_irq(int irq, void *data)
1371{
1372 struct rt5659_priv *rt5659 = data;
1373
1374 queue_delayed_work(system_power_efficient_wq,
1375 &rt5659->jack_detect_work, msecs_to_jiffies(250));
1376
1377 return IRQ_HANDLED;
1378}
1379
de86a332 1380int rt5659_set_jack_detect(struct snd_soc_component *component,
d3cb2de2
BL		 1381 struct snd_soc_jack *hs_jack)
1382{
de86a332 1383 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
d3cb2de2
BL		 1384
1385 rt5659->hs_jack = hs_jack;
1386
1387 rt5659_irq(0, rt5659);
1388
1389 return 0;
1390}
1391EXPORT_SYMBOL_GPL(rt5659_set_jack_detect);
1392
1393static void rt5659_jack_detect_work(struct work_struct *work)
1394{
1395 struct rt5659_priv *rt5659 =
1396 container_of(work, struct rt5659_priv, jack_detect_work.work);
1397 int val, btn_type, report = 0;
1398
de86a332 1399 if (!rt5659->component)
d3cb2de2
BL		 1400 return;
1401
de86a332 1402 val = snd_soc_component_read32(rt5659->component, RT5659_INT_ST_1) & 0x0080;
d3cb2de2
BL		 1403 if (!val) {
1404 /* jack in */
1405 if (rt5659->jack_type == 0) {
1406 /* jack was out, report jack type */
de86a332 1407 report = rt5659_headset_detect(rt5659->component, 1);
d3cb2de2
BL		 1408 } else {
1409 /* jack is already in, report button event */
1410 report = SND_JACK_HEADSET;
de86a332 1411 btn_type = rt5659_button_detect(rt5659->component);
d3cb2de2
BL		 1412 /**
1413 * rt5659 can report three kinds of button behavior,
1414 * one click, double click and hold. However,
1415 * currently we will report button pressed/released
1416 * event. So all the three button behaviors are
1417 * treated as button pressed.
1418 */
1419 switch (btn_type) {
1420 case 0x8000:
1421 case 0x4000:
1422 case 0x2000:
1423 report |= SND_JACK_BTN_0;
1424 break;
1425 case 0x1000:
1426 case 0x0800:
1427 case 0x0400:
1428 report |= SND_JACK_BTN_1;
1429 break;
1430 case 0x0200:
1431 case 0x0100:
1432 case 0x0080:
1433 report |= SND_JACK_BTN_2;
1434 break;
1435 case 0x0040:
1436 case 0x0020:
1437 case 0x0010:
1438 report |= SND_JACK_BTN_3;
1439 break;
1440 case 0x0000: /* unpressed */
1441 break;
1442 default:
1443 btn_type = 0;
de86a332 1444 dev_err(rt5659->component->dev,
d3cb2de2
BL		 1445 "Unexpected button code 0x%04x\n",
1446 btn_type);
1447 break;
1448 }
1449
1450 /* button release or spurious interrput*/
1451 if (btn_type == 0)
1452 report = rt5659->jack_type;
1453 }
1454 } else {
1455 /* jack out */
de86a332 1456 report = rt5659_headset_detect(rt5659->component, 0);
d3cb2de2
BL		 1457 }
1458
1459 snd_soc_jack_report(rt5659->hs_jack, report, SND_JACK_HEADSET |
1460 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1461 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1462}
1463
041e74b7 1464static void rt5659_jack_detect_intel_hd_header(struct work_struct *work)
1465{
1466 struct rt5659_priv *rt5659 =
1467 container_of(work, struct rt5659_priv, jack_detect_work.work);
1468 unsigned int value;
1469 bool hp_flag, mic_flag;
1470
1471 if (!rt5659->hs_jack)
1472 return;
1473
1474 /* headphone jack */
1475 regmap_read(rt5659->regmap, RT5659_GPIO_STA, &value);
1476 hp_flag = (!(value & 0x8)) ? true : false;
1477
1478 if (hp_flag != rt5659->hda_hp_plugged) {
1479 rt5659->hda_hp_plugged = hp_flag;
1480
1481 if (hp_flag) {
1482 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1,
1483 0x10, 0x0);
1484 rt5659->jack_type |= SND_JACK_HEADPHONE;
1485 } else {
1486 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1,
1487 0x10, 0x10);
1488 rt5659->jack_type = rt5659->jack_type &
1489 (~SND_JACK_HEADPHONE);
1490 }
1491
1492 snd_soc_jack_report(rt5659->hs_jack, rt5659->jack_type,
1493 SND_JACK_HEADPHONE);
1494 }
1495
1496 /* mic jack */
1497 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value);
1498 regmap_write(rt5659->regmap, RT5659_4BTN_IL_CMD_1, value);
1499 mic_flag = (value & 0x2000) ? true : false;
1500
1501 if (mic_flag != rt5659->hda_mic_plugged) {
1502 rt5659->hda_mic_plugged = mic_flag;
1503 if (mic_flag) {
1504 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
1505 0x2, 0x2);
1506 rt5659->jack_type |= SND_JACK_MICROPHONE;
1507 } else {
1508 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
1509 0x2, 0x0);
1510 rt5659->jack_type = rt5659->jack_type
1511 & (~SND_JACK_MICROPHONE);
1512 }
1513
1514 snd_soc_jack_report(rt5659->hs_jack, rt5659->jack_type,
1515 SND_JACK_MICROPHONE);
1516 }
1517}
1518
d3cb2de2
BL		 1519static const struct snd_kcontrol_new rt5659_snd_controls[] = {
1520 /* Speaker Output Volume */
1521 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5659_SPO_VOL,
1522 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 39, 1, out_vol_tlv),
1523
1524 /* Headphone Output Volume */
1525 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5659_HPL_GAIN,
1526 RT5659_HPR_GAIN, RT5659_G_HP_SFT, 31, 1, snd_soc_get_volsw,
1527 rt5659_hp_vol_put, hp_vol_tlv),
1528
1529 /* Mono Output Volume */
1530 SOC_SINGLE_TLV("Mono Playback Volume", RT5659_MONO_OUT,
1531 RT5659_L_VOL_SFT, 39, 1, out_vol_tlv),
1532
1533 /* Output Volume */
1534 SOC_DOUBLE_TLV("OUT Playback Volume", RT5659_LOUT,
1535 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 39, 1, out_vol_tlv),
1536
1537 /* DAC Digital Volume */
1538 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5659_DAC1_DIG_VOL,
1539 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 175, 0, dac_vol_tlv),
1540 SOC_DOUBLE("DAC1 Playback Switch", RT5659_AD_DA_MIXER,
1541 RT5659_M_DAC1_L_SFT, RT5659_M_DAC1_R_SFT, 1, 1),
1542
1543 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5659_DAC2_DIG_VOL,
1544 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 175, 0, dac_vol_tlv),
1545 SOC_DOUBLE("DAC2 Playback Switch", RT5659_DAC_CTRL,
1546 RT5659_M_DAC2_L_VOL_SFT, RT5659_M_DAC2_R_VOL_SFT, 1, 1),
1547
1548 /* IN1/IN2/IN3/IN4 Volume */
1549 SOC_SINGLE_TLV("IN1 Boost Volume", RT5659_IN1_IN2,
1550 RT5659_BST1_SFT, 69, 0, in_bst_tlv),
1551 SOC_SINGLE_TLV("IN2 Boost Volume", RT5659_IN1_IN2,
1552 RT5659_BST2_SFT, 69, 0, in_bst_tlv),
1553 SOC_SINGLE_TLV("IN3 Boost Volume", RT5659_IN3_IN4,
1554 RT5659_BST3_SFT, 69, 0, in_bst_tlv),
1555 SOC_SINGLE_TLV("IN4 Boost Volume", RT5659_IN3_IN4,
1556 RT5659_BST4_SFT, 69, 0, in_bst_tlv),
1557
1558 /* INL/INR Volume Control */
1559 SOC_DOUBLE_TLV("IN Capture Volume", RT5659_INL1_INR1_VOL,
1560 RT5659_INL_VOL_SFT, RT5659_INR_VOL_SFT, 31, 1, in_vol_tlv),
1561
1562 /* ADC Digital Volume Control */
1563 SOC_DOUBLE("STO1 ADC Capture Switch", RT5659_STO1_ADC_DIG_VOL,
1564 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
1565 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5659_STO1_ADC_DIG_VOL,
1566 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
1567 SOC_DOUBLE("Mono ADC Capture Switch", RT5659_MONO_ADC_DIG_VOL,
1568 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
1569 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5659_MONO_ADC_DIG_VOL,
1570 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
1571 SOC_DOUBLE("STO2 ADC Capture Switch", RT5659_STO2_ADC_DIG_VOL,
1572 RT5659_L_MUTE_SFT, RT5659_R_MUTE_SFT, 1, 1),
1573 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5659_STO2_ADC_DIG_VOL,
1574 RT5659_L_VOL_SFT, RT5659_R_VOL_SFT, 127, 0, adc_vol_tlv),
1575
1576 /* ADC Boost Volume Control */
1577 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5659_STO1_BOOST,
1578 RT5659_STO1_ADC_L_BST_SFT, RT5659_STO1_ADC_R_BST_SFT,
1579 3, 0, adc_bst_tlv),
1580
1581 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5659_MONO_BOOST,
1582 RT5659_MONO_ADC_L_BST_SFT, RT5659_MONO_ADC_R_BST_SFT,
1583 3, 0, adc_bst_tlv),
1584
1585 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5659_STO2_BOOST,
1586 RT5659_STO2_ADC_L_BST_SFT, RT5659_STO2_ADC_R_BST_SFT,
1587 3, 0, adc_bst_tlv),
1588
1589 SOC_SINGLE("DAC IF1 DAC1 L Data Switch", RT5659_TDM_CTRL_4, 12, 7, 0),
1590 SOC_SINGLE("DAC IF1 DAC1 R Data Switch", RT5659_TDM_CTRL_4, 8, 7, 0),
1591 SOC_SINGLE("DAC IF1 DAC2 L Data Switch", RT5659_TDM_CTRL_4, 4, 7, 0),
1592 SOC_SINGLE("DAC IF1 DAC2 R Data Switch", RT5659_TDM_CTRL_4, 0, 7, 0),
1593};
1594
1595/**
1596 * set_dmic_clk - Set parameter of dmic.
1597 *
1598 * @w: DAPM widget.
1599 * @kcontrol: The kcontrol of this widget.
1600 * @event: Event id.
1601 *
1602 * Choose dmic clock between 1MHz and 3MHz.
1603 * It is better for clock to approximate 3MHz.
1604 */
1605static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1606 struct snd_kcontrol *kcontrol, int event)
1607{
de86a332
KM		 1608 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1609 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
d3cb2de2
BL		 1610 int pd, idx = -EINVAL;
1611
1612 pd = rl6231_get_pre_div(rt5659->regmap,
1613 RT5659_ADDA_CLK_1, RT5659_I2S_PD1_SFT);
1614 idx = rl6231_calc_dmic_clk(rt5659->sysclk / pd);
1615
1616 if (idx < 0)
de86a332 1617 dev_err(component->dev, "Failed to set DMIC clock\n");
d3cb2de2 1618 else {
de86a332 1619 snd_soc_component_update_bits(component, RT5659_DMIC_CTRL_1,
d3cb2de2
BL		 1620 RT5659_DMIC_CLK_MASK, idx << RT5659_DMIC_CLK_SFT);
1621 }
1622 return idx;
1623}
1624
ce571b80 1625static int set_adc1_clk(struct snd_soc_dapm_widget *w,
d3cb2de2
BL		 1626 struct snd_kcontrol *kcontrol, int event)
1627{
de86a332 1628 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
d3cb2de2
BL		 1629
1630 switch (event) {
1631 case SND_SOC_DAPM_POST_PMU:
de86a332 1632 snd_soc_component_update_bits(component, RT5659_CHOP_ADC,
ce571b80
BL		 1633 RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK,
1634 RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK);
d3cb2de2
BL		 1635 break;
1636
1637 case SND_SOC_DAPM_PRE_PMD:
de86a332 1638 snd_soc_component_update_bits(component, RT5659_CHOP_ADC,
ce571b80
BL		 1639 RT5659_CKXEN_ADC1_MASK | RT5659_CKGEN_ADC1_MASK, 0);
1640 break;
1641
1642 default:
1643 return 0;
1644 }
1645
1646 return 0;
1647
1648}
1649
1650static int set_adc2_clk(struct snd_soc_dapm_widget *w,
1651 struct snd_kcontrol *kcontrol, int event)
1652{
1653 struct snd_soc_component *component =
1654 snd_soc_dapm_to_component(w->dapm);
1655
1656 switch (event) {
1657 case SND_SOC_DAPM_POST_PMU:
1658 snd_soc_component_update_bits(component, RT5659_CHOP_ADC,
1659 RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK,
1660 RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK);
1661 break;
1662
1663 case SND_SOC_DAPM_PRE_PMD:
1664 snd_soc_component_update_bits(component, RT5659_CHOP_ADC,
1665 RT5659_CKXEN_ADC2_MASK | RT5659_CKGEN_ADC2_MASK, 0);
d3cb2de2
BL		 1666 break;
1667
1668 default:
1669 return 0;
1670 }
1671
1672 return 0;
1673
1674}
1675
1676static int rt5659_charge_pump_event(struct snd_soc_dapm_widget *w,
1677 struct snd_kcontrol *kcontrol, int event)
1678{
de86a332 1679 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
d3cb2de2
BL		 1680
1681 switch (event) {
1682 case SND_SOC_DAPM_PRE_PMU:
1683 /* Depop */
de86a332 1684 snd_soc_component_write(component, RT5659_DEPOP_1, 0x0009);
d3cb2de2
BL		 1685 break;
1686 case SND_SOC_DAPM_POST_PMD:
de86a332 1687 snd_soc_component_write(component, RT5659_HP_CHARGE_PUMP_1, 0x0c16);
d3cb2de2
BL		 1688 break;
1689 default:
1690 return 0;
1691 }
1692
1693 return 0;
1694}
1695
1696static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1697 struct snd_soc_dapm_widget *sink)
1698{
1699 unsigned int val;
de86a332 1700 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
d3cb2de2 1701
de86a332 1702 val = snd_soc_component_read32(component, RT5659_GLB_CLK);
d3cb2de2
BL		 1703 val &= RT5659_SCLK_SRC_MASK;
1704 if (val == RT5659_SCLK_SRC_PLL1)
1705 return 1;
1706 else
1707 return 0;
1708}
1709
1710static int is_using_asrc(struct snd_soc_dapm_widget *w,
1711 struct snd_soc_dapm_widget *sink)
1712{
1713 unsigned int reg, shift, val;
de86a332 1714 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
d3cb2de2
BL		 1715
1716 switch (w->shift) {
1717 case RT5659_ADC_MONO_R_ASRC_SFT:
1718 reg = RT5659_ASRC_3;
1719 shift = RT5659_AD_MONO_R_T_SFT;
1720 break;
1721 case RT5659_ADC_MONO_L_ASRC_SFT:
1722 reg = RT5659_ASRC_3;
1723 shift = RT5659_AD_MONO_L_T_SFT;
1724 break;
1725 case RT5659_ADC_STO1_ASRC_SFT:
1726 reg = RT5659_ASRC_2;
1727 shift = RT5659_AD_STO1_T_SFT;
1728 break;
1729 case RT5659_DAC_MONO_R_ASRC_SFT:
1730 reg = RT5659_ASRC_2;
1731 shift = RT5659_DA_MONO_R_T_SFT;
1732 break;
1733 case RT5659_DAC_MONO_L_ASRC_SFT:
1734 reg = RT5659_ASRC_2;
1735 shift = RT5659_DA_MONO_L_T_SFT;
1736 break;
1737 case RT5659_DAC_STO_ASRC_SFT:
1738 reg = RT5659_ASRC_2;
1739 shift = RT5659_DA_STO_T_SFT;
1740 break;
1741 default:
1742 return 0;
1743 }
1744
de86a332 1745 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
d3cb2de2
BL		 1746 switch (val) {
1747 case 1:
1748 case 2:
1749 case 3:
1750 /* I2S_Pre_Div1 should be 1 in asrc mode */
de86a332 1751 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
d3cb2de2
BL		 1752 RT5659_I2S_PD1_MASK, RT5659_I2S_PD1_2);
1753 return 1;
1754 default:
1755 return 0;
1756 }
1757
1758}
1759
1760/* Digital Mixer */
1761static const struct snd_kcontrol_new rt5659_sto1_adc_l_mix[] = {
1762 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_STO1_ADC_MIXER,
1763 RT5659_M_STO1_ADC_L1_SFT, 1, 1),
1764 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_STO1_ADC_MIXER,
1765 RT5659_M_STO1_ADC_L2_SFT, 1, 1),
1766};
1767
1768static const struct snd_kcontrol_new rt5659_sto1_adc_r_mix[] = {
1769 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_STO1_ADC_MIXER,
1770 RT5659_M_STO1_ADC_R1_SFT, 1, 1),
1771 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_STO1_ADC_MIXER,
1772 RT5659_M_STO1_ADC_R2_SFT, 1, 1),
1773};
1774
1775static const struct snd_kcontrol_new rt5659_mono_adc_l_mix[] = {
1776 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_MONO_ADC_MIXER,
1777 RT5659_M_MONO_ADC_L1_SFT, 1, 1),
1778 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_MONO_ADC_MIXER,
1779 RT5659_M_MONO_ADC_L2_SFT, 1, 1),
1780};
1781
1782static const struct snd_kcontrol_new rt5659_mono_adc_r_mix[] = {
1783 SOC_DAPM_SINGLE("ADC1 Switch", RT5659_MONO_ADC_MIXER,
1784 RT5659_M_MONO_ADC_R1_SFT, 1, 1),
1785 SOC_DAPM_SINGLE("ADC2 Switch", RT5659_MONO_ADC_MIXER,
1786 RT5659_M_MONO_ADC_R2_SFT, 1, 1),
1787};
1788
1789static const struct snd_kcontrol_new rt5659_dac_l_mix[] = {
1790 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
1791 RT5659_M_ADCMIX_L_SFT, 1, 1),
1792 SOC_DAPM_SINGLE("DAC1 Switch", RT5659_AD_DA_MIXER,
1793 RT5659_M_DAC1_L_SFT, 1, 1),
1794};
1795
1796static const struct snd_kcontrol_new rt5659_dac_r_mix[] = {
1797 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5659_AD_DA_MIXER,
1798 RT5659_M_ADCMIX_R_SFT, 1, 1),
1799 SOC_DAPM_SINGLE("DAC1 Switch", RT5659_AD_DA_MIXER,
1800 RT5659_M_DAC1_R_SFT, 1, 1),
1801};
1802
1803static const struct snd_kcontrol_new rt5659_sto_dac_l_mix[] = {
1804 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_STO_DAC_MIXER,
1805 RT5659_M_DAC_L1_STO_L_SFT, 1, 1),
1806 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_STO_DAC_MIXER,
1807 RT5659_M_DAC_R1_STO_L_SFT, 1, 1),
1808 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_STO_DAC_MIXER,
1809 RT5659_M_DAC_L2_STO_L_SFT, 1, 1),
1810 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_STO_DAC_MIXER,
1811 RT5659_M_DAC_R2_STO_L_SFT, 1, 1),
1812};
1813
1814static const struct snd_kcontrol_new rt5659_sto_dac_r_mix[] = {
1815 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_STO_DAC_MIXER,
1816 RT5659_M_DAC_L1_STO_R_SFT, 1, 1),
1817 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_STO_DAC_MIXER,
1818 RT5659_M_DAC_R1_STO_R_SFT, 1, 1),
1819 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_STO_DAC_MIXER,
1820 RT5659_M_DAC_L2_STO_R_SFT, 1, 1),
1821 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_STO_DAC_MIXER,
1822 RT5659_M_DAC_R2_STO_R_SFT, 1, 1),
1823};
1824
1825static const struct snd_kcontrol_new rt5659_mono_dac_l_mix[] = {
1826 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_MONO_DAC_MIXER,
1827 RT5659_M_DAC_L1_MONO_L_SFT, 1, 1),
1828 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_MONO_DAC_MIXER,
1829 RT5659_M_DAC_R1_MONO_L_SFT, 1, 1),
1830 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONO_DAC_MIXER,
1831 RT5659_M_DAC_L2_MONO_L_SFT, 1, 1),
1832 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONO_DAC_MIXER,
1833 RT5659_M_DAC_R2_MONO_L_SFT, 1, 1),
1834};
1835
1836static const struct snd_kcontrol_new rt5659_mono_dac_r_mix[] = {
1837 SOC_DAPM_SINGLE("DAC L1 Switch", RT5659_MONO_DAC_MIXER,
1838 RT5659_M_DAC_L1_MONO_R_SFT, 1, 1),
1839 SOC_DAPM_SINGLE("DAC R1 Switch", RT5659_MONO_DAC_MIXER,
1840 RT5659_M_DAC_R1_MONO_R_SFT, 1, 1),
1841 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONO_DAC_MIXER,
1842 RT5659_M_DAC_L2_MONO_R_SFT, 1, 1),
1843 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONO_DAC_MIXER,
1844 RT5659_M_DAC_R2_MONO_R_SFT, 1, 1),
1845};
1846
1847/* Analog Input Mixer */
1848static const struct snd_kcontrol_new rt5659_rec1_l_mix[] = {
1849 SOC_DAPM_SINGLE("SPKVOLL Switch", RT5659_REC1_L2_MIXER,
1850 RT5659_M_SPKVOLL_RM1_L_SFT, 1, 1),
1851 SOC_DAPM_SINGLE("INL Switch", RT5659_REC1_L2_MIXER,
1852 RT5659_M_INL_RM1_L_SFT, 1, 1),
1853 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC1_L2_MIXER,
1854 RT5659_M_BST4_RM1_L_SFT, 1, 1),
1855 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC1_L2_MIXER,
1856 RT5659_M_BST3_RM1_L_SFT, 1, 1),
1857 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC1_L2_MIXER,
1858 RT5659_M_BST2_RM1_L_SFT, 1, 1),
1859 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC1_L2_MIXER,
1860 RT5659_M_BST1_RM1_L_SFT, 1, 1),
1861};
1862
1863static const struct snd_kcontrol_new rt5659_rec1_r_mix[] = {
1864 SOC_DAPM_SINGLE("HPOVOLR Switch", RT5659_REC1_L2_MIXER,
1865 RT5659_M_HPOVOLR_RM1_R_SFT, 1, 1),
1866 SOC_DAPM_SINGLE("INR Switch", RT5659_REC1_R2_MIXER,
1867 RT5659_M_INR_RM1_R_SFT, 1, 1),
1868 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC1_R2_MIXER,
1869 RT5659_M_BST4_RM1_R_SFT, 1, 1),
1870 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC1_R2_MIXER,
1871 RT5659_M_BST3_RM1_R_SFT, 1, 1),
1872 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC1_R2_MIXER,
1873 RT5659_M_BST2_RM1_R_SFT, 1, 1),
1874 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC1_R2_MIXER,
1875 RT5659_M_BST1_RM1_R_SFT, 1, 1),
1876};
1877
1878static const struct snd_kcontrol_new rt5659_rec2_l_mix[] = {
1879 SOC_DAPM_SINGLE("SPKVOLL Switch", RT5659_REC2_L2_MIXER,
1880 RT5659_M_SPKVOL_RM2_L_SFT, 1, 1),
1881 SOC_DAPM_SINGLE("OUTVOLL Switch", RT5659_REC2_L2_MIXER,
1882 RT5659_M_OUTVOLL_RM2_L_SFT, 1, 1),
1883 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC2_L2_MIXER,
1884 RT5659_M_BST4_RM2_L_SFT, 1, 1),
1885 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC2_L2_MIXER,
1886 RT5659_M_BST3_RM2_L_SFT, 1, 1),
1887 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC2_L2_MIXER,
1888 RT5659_M_BST2_RM2_L_SFT, 1, 1),
1889 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC2_L2_MIXER,
1890 RT5659_M_BST1_RM2_L_SFT, 1, 1),
1891};
1892
1893static const struct snd_kcontrol_new rt5659_rec2_r_mix[] = {
1894 SOC_DAPM_SINGLE("MONOVOL Switch", RT5659_REC2_R2_MIXER,
1895 RT5659_M_MONOVOL_RM2_R_SFT, 1, 1),
1896 SOC_DAPM_SINGLE("OUTVOLR Switch", RT5659_REC2_R2_MIXER,
1897 RT5659_M_OUTVOLR_RM2_R_SFT, 1, 1),
1898 SOC_DAPM_SINGLE("BST4 Switch", RT5659_REC2_R2_MIXER,
1899 RT5659_M_BST4_RM2_R_SFT, 1, 1),
1900 SOC_DAPM_SINGLE("BST3 Switch", RT5659_REC2_R2_MIXER,
1901 RT5659_M_BST3_RM2_R_SFT, 1, 1),
1902 SOC_DAPM_SINGLE("BST2 Switch", RT5659_REC2_R2_MIXER,
1903 RT5659_M_BST2_RM2_R_SFT, 1, 1),
1904 SOC_DAPM_SINGLE("BST1 Switch", RT5659_REC2_R2_MIXER,
1905 RT5659_M_BST1_RM2_R_SFT, 1, 1),
1906};
1907
1908static const struct snd_kcontrol_new rt5659_spk_l_mix[] = {
1909 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_SPK_L_MIXER,
1910 RT5659_M_DAC_L2_SM_L_SFT, 1, 1),
1911 SOC_DAPM_SINGLE("BST1 Switch", RT5659_SPK_L_MIXER,
1912 RT5659_M_BST1_SM_L_SFT, 1, 1),
1913 SOC_DAPM_SINGLE("INL Switch", RT5659_SPK_L_MIXER,
1914 RT5659_M_IN_L_SM_L_SFT, 1, 1),
1915 SOC_DAPM_SINGLE("INR Switch", RT5659_SPK_L_MIXER,
1916 RT5659_M_IN_R_SM_L_SFT, 1, 1),
1917 SOC_DAPM_SINGLE("BST3 Switch", RT5659_SPK_L_MIXER,
1918 RT5659_M_BST3_SM_L_SFT, 1, 1),
1919};
1920
1921static const struct snd_kcontrol_new rt5659_spk_r_mix[] = {
1922 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_SPK_R_MIXER,
1923 RT5659_M_DAC_R2_SM_R_SFT, 1, 1),
1924 SOC_DAPM_SINGLE("BST4 Switch", RT5659_SPK_R_MIXER,
1925 RT5659_M_BST4_SM_R_SFT, 1, 1),
1926 SOC_DAPM_SINGLE("INL Switch", RT5659_SPK_R_MIXER,
1927 RT5659_M_IN_L_SM_R_SFT, 1, 1),
1928 SOC_DAPM_SINGLE("INR Switch", RT5659_SPK_R_MIXER,
1929 RT5659_M_IN_R_SM_R_SFT, 1, 1),
1930 SOC_DAPM_SINGLE("BST3 Switch", RT5659_SPK_R_MIXER,
1931 RT5659_M_BST3_SM_R_SFT, 1, 1),
1932};
1933
1934static const struct snd_kcontrol_new rt5659_monovol_mix[] = {
1935 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONOMIX_IN_GAIN,
1936 RT5659_M_DAC_L2_MM_SFT, 1, 1),
1937 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_MONOMIX_IN_GAIN,
1938 RT5659_M_DAC_R2_MM_SFT, 1, 1),
1939 SOC_DAPM_SINGLE("BST1 Switch", RT5659_MONOMIX_IN_GAIN,
1940 RT5659_M_BST1_MM_SFT, 1, 1),
1941 SOC_DAPM_SINGLE("BST2 Switch", RT5659_MONOMIX_IN_GAIN,
1942 RT5659_M_BST2_MM_SFT, 1, 1),
1943 SOC_DAPM_SINGLE("BST3 Switch", RT5659_MONOMIX_IN_GAIN,
1944 RT5659_M_BST3_MM_SFT, 1, 1),
1945};
1946
1947static const struct snd_kcontrol_new rt5659_out_l_mix[] = {
1948 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_OUT_L_MIXER,
1949 RT5659_M_DAC_L2_OM_L_SFT, 1, 1),
1950 SOC_DAPM_SINGLE("INL Switch", RT5659_OUT_L_MIXER,
1951 RT5659_M_IN_L_OM_L_SFT, 1, 1),
1952 SOC_DAPM_SINGLE("BST1 Switch", RT5659_OUT_L_MIXER,
1953 RT5659_M_BST1_OM_L_SFT, 1, 1),
1954 SOC_DAPM_SINGLE("BST2 Switch", RT5659_OUT_L_MIXER,
1955 RT5659_M_BST2_OM_L_SFT, 1, 1),
1956 SOC_DAPM_SINGLE("BST3 Switch", RT5659_OUT_L_MIXER,
1957 RT5659_M_BST3_OM_L_SFT, 1, 1),
1958};
1959
1960static const struct snd_kcontrol_new rt5659_out_r_mix[] = {
1961 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_OUT_R_MIXER,
1962 RT5659_M_DAC_R2_OM_R_SFT, 1, 1),
1963 SOC_DAPM_SINGLE("INR Switch", RT5659_OUT_R_MIXER,
1964 RT5659_M_IN_R_OM_R_SFT, 1, 1),
1965 SOC_DAPM_SINGLE("BST2 Switch", RT5659_OUT_R_MIXER,
1966 RT5659_M_BST2_OM_R_SFT, 1, 1),
1967 SOC_DAPM_SINGLE("BST3 Switch", RT5659_OUT_R_MIXER,
1968 RT5659_M_BST3_OM_R_SFT, 1, 1),
1969 SOC_DAPM_SINGLE("BST4 Switch", RT5659_OUT_R_MIXER,
1970 RT5659_M_BST4_OM_R_SFT, 1, 1),
1971};
1972
1973static const struct snd_kcontrol_new rt5659_spo_l_mix[] = {
1974 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_SPO_AMP_GAIN,
1975 RT5659_M_DAC_L2_SPKOMIX_SFT, 1, 0),
1976 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5659_SPO_AMP_GAIN,
1977 RT5659_M_SPKVOLL_SPKOMIX_SFT, 1, 0),
1978};
1979
1980static const struct snd_kcontrol_new rt5659_spo_r_mix[] = {
1981 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_SPO_AMP_GAIN,
1982 RT5659_M_DAC_R2_SPKOMIX_SFT, 1, 0),
1983 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5659_SPO_AMP_GAIN,
1984 RT5659_M_SPKVOLR_SPKOMIX_SFT, 1, 0),
1985};
1986
1987static const struct snd_kcontrol_new rt5659_mono_mix[] = {
1988 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_MONOMIX_IN_GAIN,
1989 RT5659_M_DAC_L2_MA_SFT, 1, 1),
1990 SOC_DAPM_SINGLE("MONOVOL Switch", RT5659_MONOMIX_IN_GAIN,
1991 RT5659_M_MONOVOL_MA_SFT, 1, 1),
1992};
1993
1994static const struct snd_kcontrol_new rt5659_lout_l_mix[] = {
1995 SOC_DAPM_SINGLE("DAC L2 Switch", RT5659_LOUT_MIXER,
1996 RT5659_M_DAC_L2_LM_SFT, 1, 1),
1997 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5659_LOUT_MIXER,
1998 RT5659_M_OV_L_LM_SFT, 1, 1),
1999};
2000
2001static const struct snd_kcontrol_new rt5659_lout_r_mix[] = {
2002 SOC_DAPM_SINGLE("DAC R2 Switch", RT5659_LOUT_MIXER,
2003 RT5659_M_DAC_R2_LM_SFT, 1, 1),
2004 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5659_LOUT_MIXER,
2005 RT5659_M_OV_R_LM_SFT, 1, 1),
2006};
2007
2008/*DAC L2, DAC R2*/
2009/*MX-1B [6:4], MX-1B [2:0]*/
2010static const char * const rt5659_dac2_src[] = {
2011 "IF1 DAC2", "IF2 DAC", "IF3 DAC", "Mono ADC MIX"
2012};
2013
eae39b5f 2014static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2015 rt5659_dac_l2_enum, RT5659_DAC_CTRL,
2016 RT5659_DAC_L2_SEL_SFT, rt5659_dac2_src);
2017
2018static const struct snd_kcontrol_new rt5659_dac_l2_mux =
2019 SOC_DAPM_ENUM("DAC L2 Source", rt5659_dac_l2_enum);
2020
eae39b5f 2021static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2022 rt5659_dac_r2_enum, RT5659_DAC_CTRL,
2023 RT5659_DAC_R2_SEL_SFT, rt5659_dac2_src);
2024
2025static const struct snd_kcontrol_new rt5659_dac_r2_mux =
2026 SOC_DAPM_ENUM("DAC R2 Source", rt5659_dac_r2_enum);
2027
2028
2029/* STO1 ADC1 Source */
2030/* MX-26 [13] */
2031static const char * const rt5659_sto1_adc1_src[] = {
2032 "DAC MIX", "ADC"
2033};
2034
eae39b5f 2035static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2036 rt5659_sto1_adc1_enum, RT5659_STO1_ADC_MIXER,
2037 RT5659_STO1_ADC1_SRC_SFT, rt5659_sto1_adc1_src);
2038
2039static const struct snd_kcontrol_new rt5659_sto1_adc1_mux =
2040 SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5659_sto1_adc1_enum);
2041
2042/* STO1 ADC Source */
2043/* MX-26 [12] */
2044static const char * const rt5659_sto1_adc_src[] = {
2045 "ADC1", "ADC2"
2046};
2047
eae39b5f 2048static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2049 rt5659_sto1_adc_enum, RT5659_STO1_ADC_MIXER,
2050 RT5659_STO1_ADC_SRC_SFT, rt5659_sto1_adc_src);
2051
2052static const struct snd_kcontrol_new rt5659_sto1_adc_mux =
2053 SOC_DAPM_ENUM("Stereo1 ADC Source", rt5659_sto1_adc_enum);
2054
2055/* STO1 ADC2 Source */
2056/* MX-26 [11] */
2057static const char * const rt5659_sto1_adc2_src[] = {
2058 "DAC MIX", "DMIC"
2059};
2060
eae39b5f 2061static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2062 rt5659_sto1_adc2_enum, RT5659_STO1_ADC_MIXER,
2063 RT5659_STO1_ADC2_SRC_SFT, rt5659_sto1_adc2_src);
2064
2065static const struct snd_kcontrol_new rt5659_sto1_adc2_mux =
2066 SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5659_sto1_adc2_enum);
2067
2068/* STO1 DMIC Source */
2069/* MX-26 [8] */
2070static const char * const rt5659_sto1_dmic_src[] = {
2071 "DMIC1", "DMIC2"
2072};
2073
eae39b5f 2074static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2075 rt5659_sto1_dmic_enum, RT5659_STO1_ADC_MIXER,
2076 RT5659_STO1_DMIC_SRC_SFT, rt5659_sto1_dmic_src);
2077
2078static const struct snd_kcontrol_new rt5659_sto1_dmic_mux =
2079 SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5659_sto1_dmic_enum);
2080
2081
2082/* MONO ADC L2 Source */
2083/* MX-27 [12] */
2084static const char * const rt5659_mono_adc_l2_src[] = {
2085 "Mono DAC MIXL", "DMIC"
2086};
2087
eae39b5f 2088static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2089 rt5659_mono_adc_l2_enum, RT5659_MONO_ADC_MIXER,
2090 RT5659_MONO_ADC_L2_SRC_SFT, rt5659_mono_adc_l2_src);
2091
2092static const struct snd_kcontrol_new rt5659_mono_adc_l2_mux =
2093 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5659_mono_adc_l2_enum);
2094
2095
2096/* MONO ADC L1 Source */
2097/* MX-27 [11] */
2098static const char * const rt5659_mono_adc_l1_src[] = {
2099 "Mono DAC MIXL", "ADC"
2100};
2101
eae39b5f 2102static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2103 rt5659_mono_adc_l1_enum, RT5659_MONO_ADC_MIXER,
2104 RT5659_MONO_ADC_L1_SRC_SFT, rt5659_mono_adc_l1_src);
2105
2106static const struct snd_kcontrol_new rt5659_mono_adc_l1_mux =
2107 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5659_mono_adc_l1_enum);
2108
2109/* MONO ADC L Source, MONO ADC R Source*/
2110/* MX-27 [10:9], MX-27 [2:1] */
2111static const char * const rt5659_mono_adc_src[] = {
2112 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2113};
2114
eae39b5f 2115static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2116 rt5659_mono_adc_l_enum, RT5659_MONO_ADC_MIXER,
2117 RT5659_MONO_ADC_L_SRC_SFT, rt5659_mono_adc_src);
2118
2119static const struct snd_kcontrol_new rt5659_mono_adc_l_mux =
2120 SOC_DAPM_ENUM("Mono ADC L Source", rt5659_mono_adc_l_enum);
2121
eae39b5f 2122static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2123 rt5659_mono_adcr_enum, RT5659_MONO_ADC_MIXER,
2124 RT5659_MONO_ADC_R_SRC_SFT, rt5659_mono_adc_src);
2125
2126static const struct snd_kcontrol_new rt5659_mono_adc_r_mux =
2127 SOC_DAPM_ENUM("Mono ADC R Source", rt5659_mono_adcr_enum);
2128
2129/* MONO DMIC L Source */
2130/* MX-27 [8] */
2131static const char * const rt5659_mono_dmic_l_src[] = {
2132 "DMIC1 L", "DMIC2 L"
2133};
2134
eae39b5f 2135static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2136 rt5659_mono_dmic_l_enum, RT5659_MONO_ADC_MIXER,
2137 RT5659_MONO_DMIC_L_SRC_SFT, rt5659_mono_dmic_l_src);
2138
2139static const struct snd_kcontrol_new rt5659_mono_dmic_l_mux =
2140 SOC_DAPM_ENUM("Mono DMIC L Source", rt5659_mono_dmic_l_enum);
2141
2142/* MONO ADC R2 Source */
2143/* MX-27 [4] */
2144static const char * const rt5659_mono_adc_r2_src[] = {
2145 "Mono DAC MIXR", "DMIC"
2146};
2147
eae39b5f 2148static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2149 rt5659_mono_adc_r2_enum, RT5659_MONO_ADC_MIXER,
2150 RT5659_MONO_ADC_R2_SRC_SFT, rt5659_mono_adc_r2_src);
2151
2152static const struct snd_kcontrol_new rt5659_mono_adc_r2_mux =
2153 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5659_mono_adc_r2_enum);
2154
2155/* MONO ADC R1 Source */
2156/* MX-27 [3] */
2157static const char * const rt5659_mono_adc_r1_src[] = {
2158 "Mono DAC MIXR", "ADC"
2159};
2160
eae39b5f 2161static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2162 rt5659_mono_adc_r1_enum, RT5659_MONO_ADC_MIXER,
2163 RT5659_MONO_ADC_R1_SRC_SFT, rt5659_mono_adc_r1_src);
2164
2165static const struct snd_kcontrol_new rt5659_mono_adc_r1_mux =
2166 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5659_mono_adc_r1_enum);
2167
2168/* MONO DMIC R Source */
2169/* MX-27 [0] */
2170static const char * const rt5659_mono_dmic_r_src[] = {
2171 "DMIC1 R", "DMIC2 R"
2172};
2173
eae39b5f 2174static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2175 rt5659_mono_dmic_r_enum, RT5659_MONO_ADC_MIXER,
2176 RT5659_MONO_DMIC_R_SRC_SFT, rt5659_mono_dmic_r_src);
2177
2178static const struct snd_kcontrol_new rt5659_mono_dmic_r_mux =
2179 SOC_DAPM_ENUM("Mono DMIC R Source", rt5659_mono_dmic_r_enum);
2180
2181
2182/* DAC R1 Source, DAC L1 Source*/
2183/* MX-29 [11:10], MX-29 [9:8]*/
2184static const char * const rt5659_dac1_src[] = {
2185 "IF1 DAC1", "IF2 DAC", "IF3 DAC"
2186};
2187
eae39b5f 2188static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2189 rt5659_dac_r1_enum, RT5659_AD_DA_MIXER,
2190 RT5659_DAC1_R_SEL_SFT, rt5659_dac1_src);
2191
2192static const struct snd_kcontrol_new rt5659_dac_r1_mux =
2193 SOC_DAPM_ENUM("DAC R1 Source", rt5659_dac_r1_enum);
2194
eae39b5f 2195static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2196 rt5659_dac_l1_enum, RT5659_AD_DA_MIXER,
2197 RT5659_DAC1_L_SEL_SFT, rt5659_dac1_src);
2198
2199static const struct snd_kcontrol_new rt5659_dac_l1_mux =
2200 SOC_DAPM_ENUM("DAC L1 Source", rt5659_dac_l1_enum);
2201
2202/* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2203/* MX-2C [6], MX-2C [4]*/
2204static const char * const rt5659_dig_dac_mix_src[] = {
2205 "Stereo DAC Mixer", "Mono DAC Mixer"
2206};
2207
eae39b5f 2208static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2209 rt5659_dig_dac_mixl_enum, RT5659_DIG_MIXER,
2210 RT5659_DAC_MIX_L_SFT, rt5659_dig_dac_mix_src);
2211
2212static const struct snd_kcontrol_new rt5659_dig_dac_mixl_mux =
2213 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5659_dig_dac_mixl_enum);
2214
eae39b5f 2215static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2216 rt5659_dig_dac_mixr_enum, RT5659_DIG_MIXER,
2217 RT5659_DAC_MIX_R_SFT, rt5659_dig_dac_mix_src);
2218
2219static const struct snd_kcontrol_new rt5659_dig_dac_mixr_mux =
2220 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5659_dig_dac_mixr_enum);
2221
2222/* Analog DAC L1 Source, Analog DAC R1 Source*/
2223/* MX-2D [3], MX-2D [2]*/
2224static const char * const rt5659_alg_dac1_src[] = {
2225 "DAC", "Stereo DAC Mixer"
2226};
2227
eae39b5f 2228static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2229 rt5659_alg_dac_l1_enum, RT5659_A_DAC_MUX,
2230 RT5659_A_DACL1_SFT, rt5659_alg_dac1_src);
2231
2232static const struct snd_kcontrol_new rt5659_alg_dac_l1_mux =
2233 SOC_DAPM_ENUM("Analog DACL1 Source", rt5659_alg_dac_l1_enum);
2234
eae39b5f 2235static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2236 rt5659_alg_dac_r1_enum, RT5659_A_DAC_MUX,
2237 RT5659_A_DACR1_SFT, rt5659_alg_dac1_src);
2238
2239static const struct snd_kcontrol_new rt5659_alg_dac_r1_mux =
2240 SOC_DAPM_ENUM("Analog DACR1 Source", rt5659_alg_dac_r1_enum);
2241
2242/* Analog DAC LR Source, Analog DAC R2 Source*/
2243/* MX-2D [1], MX-2D [0]*/
2244static const char * const rt5659_alg_dac2_src[] = {
2245 "Stereo DAC Mixer", "Mono DAC Mixer"
2246};
2247
eae39b5f 2248static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2249 rt5659_alg_dac_l2_enum, RT5659_A_DAC_MUX,
2250 RT5659_A_DACL2_SFT, rt5659_alg_dac2_src);
2251
2252static const struct snd_kcontrol_new rt5659_alg_dac_l2_mux =
2253 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5659_alg_dac_l2_enum);
2254
eae39b5f 2255static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2256 rt5659_alg_dac_r2_enum, RT5659_A_DAC_MUX,
2257 RT5659_A_DACR2_SFT, rt5659_alg_dac2_src);
2258
2259static const struct snd_kcontrol_new rt5659_alg_dac_r2_mux =
2260 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5659_alg_dac_r2_enum);
2261
2262/* Interface2 ADC Data Input*/
2263/* MX-2F [13:12] */
2264static const char * const rt5659_if2_adc_in_src[] = {
2265 "IF_ADC1", "IF_ADC2", "DAC_REF", "IF_ADC3"
2266};
2267
eae39b5f 2268static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2269 rt5659_if2_adc_in_enum, RT5659_DIG_INF23_DATA,
2270 RT5659_IF2_ADC_IN_SFT, rt5659_if2_adc_in_src);
2271
2272static const struct snd_kcontrol_new rt5659_if2_adc_in_mux =
2273 SOC_DAPM_ENUM("IF2 ADC IN Source", rt5659_if2_adc_in_enum);
2274
2275/* Interface3 ADC Data Input*/
2276/* MX-2F [1:0] */
2277static const char * const rt5659_if3_adc_in_src[] = {
2278 "IF_ADC1", "IF_ADC2", "DAC_REF", "Stereo2_ADC_L/R"
2279};
2280
eae39b5f 2281static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2282 rt5659_if3_adc_in_enum, RT5659_DIG_INF23_DATA,
2283 RT5659_IF3_ADC_IN_SFT, rt5659_if3_adc_in_src);
2284
2285static const struct snd_kcontrol_new rt5659_if3_adc_in_mux =
2286 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5659_if3_adc_in_enum);
2287
2288/* PDM 1 L/R*/
2289/* MX-31 [15] [13] */
2290static const char * const rt5659_pdm_src[] = {
2291 "Mono DAC", "Stereo DAC"
2292};
2293
eae39b5f 2294static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2295 rt5659_pdm_l_enum, RT5659_PDM_OUT_CTRL,
2296 RT5659_PDM1_L_SFT, rt5659_pdm_src);
2297
2298static const struct snd_kcontrol_new rt5659_pdm_l_mux =
2299 SOC_DAPM_ENUM("PDM L Source", rt5659_pdm_l_enum);
2300
eae39b5f 2301static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2302 rt5659_pdm_r_enum, RT5659_PDM_OUT_CTRL,
2303 RT5659_PDM1_R_SFT, rt5659_pdm_src);
2304
2305static const struct snd_kcontrol_new rt5659_pdm_r_mux =
2306 SOC_DAPM_ENUM("PDM R Source", rt5659_pdm_r_enum);
2307
2308/* SPDIF Output source*/
2309/* MX-36 [1:0] */
2310static const char * const rt5659_spdif_src[] = {
2311 "IF1_DAC1", "IF1_DAC2", "IF2_DAC", "IF3_DAC"
2312};
2313
eae39b5f 2314static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2315 rt5659_spdif_enum, RT5659_SPDIF_CTRL,
2316 RT5659_SPDIF_SEL_SFT, rt5659_spdif_src);
2317
2318static const struct snd_kcontrol_new rt5659_spdif_mux =
2319 SOC_DAPM_ENUM("SPDIF Source", rt5659_spdif_enum);
2320
2321/* I2S1 TDM ADCDAT Source */
2322/* MX-78[4:0] */
2323static const char * const rt5659_rx_adc_data_src[] = {
2324 "AD1:AD2:DAC:NUL", "AD1:AD2:NUL:DAC", "AD1:DAC:AD2:NUL",
2325 "AD1:DAC:NUL:AD2", "AD1:NUL:DAC:AD2", "AD1:NUL:AD2:DAC",
2326 "AD2:AD1:DAC:NUL", "AD2:AD1:NUL:DAC", "AD2:DAC:AD1:NUL",
2327 "AD2:DAC:NUL:AD1", "AD2:NUL:DAC:AD1", "AD1:NUL:AD1:DAC",
2328 "DAC:AD1:AD2:NUL", "DAC:AD1:NUL:AD2", "DAC:AD2:AD1:NUL",
2329 "DAC:AD2:NUL:AD1", "DAC:NUL:DAC:AD2", "DAC:NUL:AD2:DAC",
2330 "NUL:AD1:AD2:DAC", "NUL:AD1:DAC:AD2", "NUL:AD2:AD1:DAC",
2331 "NUL:AD2:DAC:AD1", "NUL:DAC:DAC:AD2", "NUL:DAC:AD2:DAC"
2332};
2333
eae39b5f 2334static SOC_ENUM_SINGLE_DECL(
d3cb2de2
BL		 2335 rt5659_rx_adc_data_enum, RT5659_TDM_CTRL_2,
2336 RT5659_ADCDAT_SRC_SFT, rt5659_rx_adc_data_src);
2337
2338static const struct snd_kcontrol_new rt5659_rx_adc_dac_mux =
2339 SOC_DAPM_ENUM("TDM ADCDAT Source", rt5659_rx_adc_data_enum);
2340
2341/* Out Volume Switch */
2342static const struct snd_kcontrol_new spkvol_l_switch =
2343 SOC_DAPM_SINGLE("Switch", RT5659_SPO_VOL, RT5659_VOL_L_SFT, 1, 1);
2344
2345static const struct snd_kcontrol_new spkvol_r_switch =
2346 SOC_DAPM_SINGLE("Switch", RT5659_SPO_VOL, RT5659_VOL_R_SFT, 1, 1);
2347
2348static const struct snd_kcontrol_new monovol_switch =
2349 SOC_DAPM_SINGLE("Switch", RT5659_MONO_OUT, RT5659_VOL_L_SFT, 1, 1);
2350
2351static const struct snd_kcontrol_new outvol_l_switch =
2352 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_VOL_L_SFT, 1, 1);
2353
2354static const struct snd_kcontrol_new outvol_r_switch =
2355 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_VOL_R_SFT, 1, 1);
2356
2357/* Out Switch */
2358static const struct snd_kcontrol_new spo_switch =
2359 SOC_DAPM_SINGLE("Switch", RT5659_CLASSD_2, RT5659_M_RF_DIG_SFT, 1, 1);
2360
2361static const struct snd_kcontrol_new mono_switch =
2362 SOC_DAPM_SINGLE("Switch", RT5659_MONO_OUT, RT5659_L_MUTE_SFT, 1, 1);
2363
2364static const struct snd_kcontrol_new hpo_l_switch =
2365 SOC_DAPM_SINGLE("Switch", RT5659_HP_VOL, RT5659_L_MUTE_SFT, 1, 1);
2366
2367static const struct snd_kcontrol_new hpo_r_switch =
2368 SOC_DAPM_SINGLE("Switch", RT5659_HP_VOL, RT5659_R_MUTE_SFT, 1, 1);
2369
2370static const struct snd_kcontrol_new lout_l_switch =
2371 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_L_MUTE_SFT, 1, 1);
2372
2373static const struct snd_kcontrol_new lout_r_switch =
2374 SOC_DAPM_SINGLE("Switch", RT5659_LOUT, RT5659_R_MUTE_SFT, 1, 1);
2375
2376static const struct snd_kcontrol_new pdm_l_switch =
2377 SOC_DAPM_SINGLE("Switch", RT5659_PDM_OUT_CTRL, RT5659_M_PDM1_L_SFT, 1,
2378 1);
2379
2380static const struct snd_kcontrol_new pdm_r_switch =
2381 SOC_DAPM_SINGLE("Switch", RT5659_PDM_OUT_CTRL, RT5659_M_PDM1_R_SFT, 1,
2382 1);
2383
2384static int rt5659_spk_event(struct snd_soc_dapm_widget *w,
2385 struct snd_kcontrol *kcontrol, int event)
2386{
de86a332 2387 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
d3cb2de2
BL		 2388
2389 switch (event) {
2390 case SND_SOC_DAPM_PRE_PMU:
de86a332 2391 snd_soc_component_update_bits(component, RT5659_CLASSD_CTRL_1,
d3cb2de2 2392 RT5659_POW_CLSD_DB_MASK, RT5659_POW_CLSD_DB_EN);
de86a332 2393 snd_soc_component_update_bits(component, RT5659_CLASSD_2,
d3cb2de2 2394 RT5659_M_RI_DIG, RT5659_M_RI_DIG);
de86a332
KM		 2395 snd_soc_component_write(component, RT5659_CLASSD_1, 0x0803);
2396 snd_soc_component_write(component, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000);
d3cb2de2
BL		 2397 break;
2398
2399 case SND_SOC_DAPM_POST_PMD:
de86a332
KM		 2400 snd_soc_component_write(component, RT5659_CLASSD_1, 0x0011);
2401 snd_soc_component_update_bits(component, RT5659_CLASSD_2,
d3cb2de2 2402 RT5659_M_RI_DIG, 0x0);
de86a332
KM		 2403 snd_soc_component_write(component, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003);
2404 snd_soc_component_update_bits(component, RT5659_CLASSD_CTRL_1,
d3cb2de2
BL		 2405 RT5659_POW_CLSD_DB_MASK, RT5659_POW_CLSD_DB_DIS);
2406 break;
2407
2408 default:
2409 return 0;
2410 }
2411
2412 return 0;
2413
2414}
2415
2416static int rt5659_mono_event(struct snd_soc_dapm_widget *w,
2417 struct snd_kcontrol *kcontrol, int event)
2418{
de86a332 2419 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
d3cb2de2
BL		 2420
2421 switch (event) {
2422 case SND_SOC_DAPM_PRE_PMU:
de86a332 2423 snd_soc_component_write(component, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00);
d3cb2de2
BL		 2424 break;
2425
2426 case SND_SOC_DAPM_POST_PMD:
de86a332 2427 snd_soc_component_write(component, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04);
d3cb2de2
BL		 2428 break;
2429
2430 default:
2431 return 0;
2432 }
2433
2434 return 0;
2435
2436}
2437
2438static int rt5659_hp_event(struct snd_soc_dapm_widget *w,
2439 struct snd_kcontrol *kcontrol, int event)
2440{
de86a332 2441 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
d3cb2de2
BL		 2442
2443 switch (event) {
2444 case SND_SOC_DAPM_POST_PMU:
de86a332
KM		 2445 snd_soc_component_write(component, RT5659_HP_CHARGE_PUMP_1, 0x0e1e);
2446 snd_soc_component_update_bits(component, RT5659_DEPOP_1, 0x0010, 0x0010);
d3cb2de2
BL		 2447 break;
2448
2449 case SND_SOC_DAPM_PRE_PMD:
de86a332 2450 snd_soc_component_write(component, RT5659_DEPOP_1, 0x0000);
d3cb2de2
BL		 2451 break;
2452
2453 default:
2454 return 0;
2455 }
2456
2457 return 0;
2458}
2459
2460static int set_dmic_power(struct snd_soc_dapm_widget *w,
2461 struct snd_kcontrol *kcontrol, int event)
2462{
2463 switch (event) {
2464 case SND_SOC_DAPM_POST_PMU:
2465 /*Add delay to avoid pop noise*/
2466 msleep(450);
2467 break;
2468
2469 default:
2470 return 0;
2471 }
2472
2473 return 0;
2474}
2475
2476static const struct snd_soc_dapm_widget rt5659_dapm_widgets[] = {
2477 SND_SOC_DAPM_SUPPLY("LDO2", RT5659_PWR_ANLG_3, RT5659_PWR_LDO2_BIT, 0,
2478 NULL, 0),
2479 SND_SOC_DAPM_SUPPLY("PLL", RT5659_PWR_ANLG_3, RT5659_PWR_PLL_BIT, 0,
2480 NULL, 0),
2481 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5659_PWR_VOL,
2482 RT5659_PWR_MIC_DET_BIT, 0, NULL, 0),
2483 SND_SOC_DAPM_SUPPLY("Mono Vref", RT5659_PWR_ANLG_1,
2484 RT5659_PWR_VREF3_BIT, 0, NULL, 0),
2485
2486 /* ASRC */
2487 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5659_ASRC_1,
2488 RT5659_I2S1_ASRC_SFT, 0, NULL, 0),
2489 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5659_ASRC_1,
2490 RT5659_I2S2_ASRC_SFT, 0, NULL, 0),
2491 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5659_ASRC_1,
2492 RT5659_I2S3_ASRC_SFT, 0, NULL, 0),
2493 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5659_ASRC_1,
2494 RT5659_DAC_STO_ASRC_SFT, 0, NULL, 0),
2495 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5659_ASRC_1,
2496 RT5659_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2497 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5659_ASRC_1,
2498 RT5659_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2499 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5659_ASRC_1,
2500 RT5659_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2501 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5659_ASRC_1,
2502 RT5659_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2503 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5659_ASRC_1,
2504 RT5659_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2505
2506 /* Input Side */
2507 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5659_PWR_ANLG_2, RT5659_PWR_MB1_BIT,
2508 0, NULL, 0),
2509 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5659_PWR_ANLG_2, RT5659_PWR_MB2_BIT,
2510 0, NULL, 0),
2511 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5659_PWR_ANLG_2, RT5659_PWR_MB3_BIT,
2512 0, NULL, 0),
2513
2514 /* Input Lines */
2515 SND_SOC_DAPM_INPUT("DMIC L1"),
2516 SND_SOC_DAPM_INPUT("DMIC R1"),
2517 SND_SOC_DAPM_INPUT("DMIC L2"),
2518 SND_SOC_DAPM_INPUT("DMIC R2"),
2519
2520 SND_SOC_DAPM_INPUT("IN1P"),
2521 SND_SOC_DAPM_INPUT("IN1N"),
2522 SND_SOC_DAPM_INPUT("IN2P"),
2523 SND_SOC_DAPM_INPUT("IN2N"),
2524 SND_SOC_DAPM_INPUT("IN3P"),
2525 SND_SOC_DAPM_INPUT("IN3N"),
2526 SND_SOC_DAPM_INPUT("IN4P"),
2527 SND_SOC_DAPM_INPUT("IN4N"),
2528
2529 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2530 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2531
2532 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2533 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2534 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5659_DMIC_CTRL_1,
2535 RT5659_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2536 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5659_DMIC_CTRL_1,
2537 RT5659_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2538
2539 /* Boost */
2540 SND_SOC_DAPM_PGA("BST1", RT5659_PWR_ANLG_2,
2541 RT5659_PWR_BST1_P_BIT, 0, NULL, 0),
2542 SND_SOC_DAPM_PGA("BST2", RT5659_PWR_ANLG_2,
2543 RT5659_PWR_BST2_P_BIT, 0, NULL, 0),
2544 SND_SOC_DAPM_PGA("BST3", RT5659_PWR_ANLG_2,
2545 RT5659_PWR_BST3_P_BIT, 0, NULL, 0),
2546 SND_SOC_DAPM_PGA("BST4", RT5659_PWR_ANLG_2,
2547 RT5659_PWR_BST4_P_BIT, 0, NULL, 0),
2548 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5659_PWR_ANLG_2,
2549 RT5659_PWR_BST1_BIT, 0, NULL, 0),
2550 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5659_PWR_ANLG_2,
2551 RT5659_PWR_BST2_BIT, 0, NULL, 0),
2552 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5659_PWR_ANLG_2,
2553 RT5659_PWR_BST3_BIT, 0, NULL, 0),
2554 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5659_PWR_ANLG_2,
2555 RT5659_PWR_BST4_BIT, 0, NULL, 0),
2556
2557
2558 /* Input Volume */
2559 SND_SOC_DAPM_PGA("INL VOL", RT5659_PWR_VOL, RT5659_PWR_IN_L_BIT,
2560 0, NULL, 0),
2561 SND_SOC_DAPM_PGA("INR VOL", RT5659_PWR_VOL, RT5659_PWR_IN_R_BIT,
2562 0, NULL, 0),
2563
2564 /* REC Mixer */
2565 SND_SOC_DAPM_MIXER("RECMIX1L", RT5659_PWR_MIXER, RT5659_PWR_RM1_L_BIT,
2566 0, rt5659_rec1_l_mix, ARRAY_SIZE(rt5659_rec1_l_mix)),
2567 SND_SOC_DAPM_MIXER("RECMIX1R", RT5659_PWR_MIXER, RT5659_PWR_RM1_R_BIT,
2568 0, rt5659_rec1_r_mix, ARRAY_SIZE(rt5659_rec1_r_mix)),
2569 SND_SOC_DAPM_MIXER("RECMIX2L", RT5659_PWR_MIXER, RT5659_PWR_RM2_L_BIT,
2570 0, rt5659_rec2_l_mix, ARRAY_SIZE(rt5659_rec2_l_mix)),
2571 SND_SOC_DAPM_MIXER("RECMIX2R", RT5659_PWR_MIXER, RT5659_PWR_RM2_R_BIT,
2572 0, rt5659_rec2_r_mix, ARRAY_SIZE(rt5659_rec2_r_mix)),
2573
2574 /* ADCs */
2575 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2576 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2577 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2578 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2579
2580 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5659_PWR_DIG_1,
2581 RT5659_PWR_ADC_L1_BIT, 0, NULL, 0),
2582 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5659_PWR_DIG_1,
2583 RT5659_PWR_ADC_R1_BIT, 0, NULL, 0),
3795e0c7 2584 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5659_PWR_DIG_1,
d3cb2de2 2585 RT5659_PWR_ADC_L2_BIT, 0, NULL, 0),
3795e0c7 2586 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5659_PWR_DIG_1,
d3cb2de2 2587 RT5659_PWR_ADC_R2_BIT, 0, NULL, 0),
ce571b80 2588 SND_SOC_DAPM_SUPPLY("ADC1 clock", SND_SOC_NOPM, 0, 0, set_adc1_clk,
d3cb2de2 2589 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
ce571b80 2590 SND_SOC_DAPM_SUPPLY("ADC2 clock", SND_SOC_NOPM, 0, 0, set_adc2_clk,
d3cb2de2
BL		 2591 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2592
2593 /* ADC Mux */
2594 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2595 &rt5659_sto1_dmic_mux),
2596 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2597 &rt5659_sto1_dmic_mux),
2598 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2599 &rt5659_sto1_adc1_mux),
2600 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2601 &rt5659_sto1_adc1_mux),
2602 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2603 &rt5659_sto1_adc2_mux),
2604 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2605 &rt5659_sto1_adc2_mux),
2606 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2607 &rt5659_sto1_adc_mux),
2608 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2609 &rt5659_sto1_adc_mux),
2610 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2611 &rt5659_mono_adc_l2_mux),
2612 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2613 &rt5659_mono_adc_r2_mux),
2614 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2615 &rt5659_mono_adc_l1_mux),
2616 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2617 &rt5659_mono_adc_r1_mux),
2618 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2619 &rt5659_mono_dmic_l_mux),
2620 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2621 &rt5659_mono_dmic_r_mux),
2622 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2623 &rt5659_mono_adc_l_mux),
2624 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2625 &rt5659_mono_adc_r_mux),
2626 /* ADC Mixer */
2627 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5659_PWR_DIG_2,
2628 RT5659_PWR_ADC_S1F_BIT, 0, NULL, 0),
2629 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5659_PWR_DIG_2,
2630 RT5659_PWR_ADC_S2F_BIT, 0, NULL, 0),
2631 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", SND_SOC_NOPM,
2632 0, 0, rt5659_sto1_adc_l_mix,
2633 ARRAY_SIZE(rt5659_sto1_adc_l_mix)),
2634 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", SND_SOC_NOPM,
2635 0, 0, rt5659_sto1_adc_r_mix,
2636 ARRAY_SIZE(rt5659_sto1_adc_r_mix)),
2637 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5659_PWR_DIG_2,
2638 RT5659_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2639 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5659_MONO_ADC_DIG_VOL,
2640 RT5659_L_MUTE_SFT, 1, rt5659_mono_adc_l_mix,
2641 ARRAY_SIZE(rt5659_mono_adc_l_mix)),
2642 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5659_PWR_DIG_2,
2643 RT5659_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2644 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5659_MONO_ADC_DIG_VOL,
2645 RT5659_R_MUTE_SFT, 1, rt5659_mono_adc_r_mix,
2646 ARRAY_SIZE(rt5659_mono_adc_r_mix)),
2647
2648 /* ADC PGA */
2649 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2650 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2651 SND_SOC_DAPM_PGA("IF_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2652 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2653 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2654 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2655 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2656 SND_SOC_DAPM_PGA("Stereo2 ADC LR", SND_SOC_NOPM, 0, 0, NULL, 0),
2657
2658 SND_SOC_DAPM_PGA("Stereo1 ADC Volume L", RT5659_STO1_ADC_DIG_VOL,
2659 RT5659_L_MUTE_SFT, 1, NULL, 0),
2660 SND_SOC_DAPM_PGA("Stereo1 ADC Volume R", RT5659_STO1_ADC_DIG_VOL,
2661 RT5659_R_MUTE_SFT, 1, NULL, 0),
2662
2663 /* Digital Interface */
2664 SND_SOC_DAPM_SUPPLY("I2S1", RT5659_PWR_DIG_1, RT5659_PWR_I2S1_BIT,
2665 0, NULL, 0),
2666 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2667 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2668 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2669 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2670 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2671 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2672 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2673 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2674 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2675 SND_SOC_DAPM_SUPPLY("I2S2", RT5659_PWR_DIG_1, RT5659_PWR_I2S2_BIT, 0,
2676 NULL, 0),
2677 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2678 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2679 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2680 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2681 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2682 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2683 SND_SOC_DAPM_SUPPLY("I2S3", RT5659_PWR_DIG_1, RT5659_PWR_I2S3_BIT, 0,
2684 NULL, 0),
2685 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2686 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2687 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2688 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2689 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2690 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2691
2692 /* Digital Interface Select */
2693 SND_SOC_DAPM_PGA("TDM AD1:AD2:DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2694 SND_SOC_DAPM_PGA("TDM AD2:DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2695 SND_SOC_DAPM_MUX("TDM Data Mux", SND_SOC_NOPM, 0, 0,
2696 &rt5659_rx_adc_dac_mux),
2697 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, 0, 0,
2698 &rt5659_if2_adc_in_mux),
2699 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2700 &rt5659_if3_adc_in_mux),
2701 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2702 &rt5659_if1_01_adc_swap_mux),
2703 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2704 &rt5659_if1_23_adc_swap_mux),
2705 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2706 &rt5659_if1_45_adc_swap_mux),
2707 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2708 &rt5659_if1_67_adc_swap_mux),
2709 SND_SOC_DAPM_MUX("IF2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2710 &rt5659_if2_dac_swap_mux),
2711 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2712 &rt5659_if2_adc_swap_mux),
2713 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2714 &rt5659_if3_dac_swap_mux),
2715 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2716 &rt5659_if3_adc_swap_mux),
2717
2718 /* Audio Interface */
2719 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2720 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2721 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2722 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2723 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
2724 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
2725
2726 /* Output Side */
2727 /* DAC mixer before sound effect */
2728 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2729 rt5659_dac_l_mix, ARRAY_SIZE(rt5659_dac_l_mix)),
2730 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2731 rt5659_dac_r_mix, ARRAY_SIZE(rt5659_dac_r_mix)),
2732
2733 /* DAC channel Mux */
2734 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l1_mux),
2735 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r1_mux),
2736 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_l2_mux),
2737 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5659_dac_r2_mux),
2738
2739 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
2740 &rt5659_alg_dac_l1_mux),
2741 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
2742 &rt5659_alg_dac_r1_mux),
2743 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
2744 &rt5659_alg_dac_l2_mux),
2745 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
2746 &rt5659_alg_dac_r2_mux),
2747
2748 /* DAC Mixer */
2749 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5659_PWR_DIG_2,
2750 RT5659_PWR_DAC_S1F_BIT, 0, NULL, 0),
2751 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5659_PWR_DIG_2,
2752 RT5659_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2753 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5659_PWR_DIG_2,
2754 RT5659_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2755 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2756 rt5659_sto_dac_l_mix, ARRAY_SIZE(rt5659_sto_dac_l_mix)),
2757 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2758 rt5659_sto_dac_r_mix, ARRAY_SIZE(rt5659_sto_dac_r_mix)),
2759 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2760 rt5659_mono_dac_l_mix, ARRAY_SIZE(rt5659_mono_dac_l_mix)),
2761 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2762 rt5659_mono_dac_r_mix, ARRAY_SIZE(rt5659_mono_dac_r_mix)),
2763 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
2764 &rt5659_dig_dac_mixl_mux),
2765 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
2766 &rt5659_dig_dac_mixr_mux),
2767
2768 /* DACs */
2769 SND_SOC_DAPM_SUPPLY_S("DAC L1 Power", 1, RT5659_PWR_DIG_1,
2770 RT5659_PWR_DAC_L1_BIT, 0, NULL, 0),
2771 SND_SOC_DAPM_SUPPLY_S("DAC R1 Power", 1, RT5659_PWR_DIG_1,
2772 RT5659_PWR_DAC_R1_BIT, 0, NULL, 0),
2773 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
2774 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
2775
2776 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5659_PWR_DIG_1,
2777 RT5659_PWR_DAC_L2_BIT, 0, NULL, 0),
2778 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5659_PWR_DIG_1,
2779 RT5659_PWR_DAC_R2_BIT, 0, NULL, 0),
2780 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
2781 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
2782 SND_SOC_DAPM_PGA("DAC_REF", SND_SOC_NOPM, 0, 0, NULL, 0),
2783
2784 /* OUT Mixer */
2785 SND_SOC_DAPM_MIXER("SPK MIXL", RT5659_PWR_MIXER, RT5659_PWR_SM_L_BIT,
2786 0, rt5659_spk_l_mix, ARRAY_SIZE(rt5659_spk_l_mix)),
2787 SND_SOC_DAPM_MIXER("SPK MIXR", RT5659_PWR_MIXER, RT5659_PWR_SM_R_BIT,
2788 0, rt5659_spk_r_mix, ARRAY_SIZE(rt5659_spk_r_mix)),
2789 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5659_PWR_MIXER, RT5659_PWR_MM_BIT,
2790 0, rt5659_monovol_mix, ARRAY_SIZE(rt5659_monovol_mix)),
2791 SND_SOC_DAPM_MIXER("OUT MIXL", RT5659_PWR_MIXER, RT5659_PWR_OM_L_BIT,
2792 0, rt5659_out_l_mix, ARRAY_SIZE(rt5659_out_l_mix)),
2793 SND_SOC_DAPM_MIXER("OUT MIXR", RT5659_PWR_MIXER, RT5659_PWR_OM_R_BIT,
2794 0, rt5659_out_r_mix, ARRAY_SIZE(rt5659_out_r_mix)),
2795
2796 /* Output Volume */
2797 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5659_PWR_VOL, RT5659_PWR_SV_L_BIT, 0,
2798 &spkvol_l_switch),
2799 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5659_PWR_VOL, RT5659_PWR_SV_R_BIT, 0,
2800 &spkvol_r_switch),
2801 SND_SOC_DAPM_SWITCH("MONOVOL", RT5659_PWR_VOL, RT5659_PWR_MV_BIT, 0,
2802 &monovol_switch),
2803 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5659_PWR_VOL, RT5659_PWR_OV_L_BIT, 0,
2804 &outvol_l_switch),
2805 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5659_PWR_VOL, RT5659_PWR_OV_R_BIT, 0,
2806 &outvol_r_switch),
2807
2808 /* SPO/MONO/HPO/LOUT */
2809 SND_SOC_DAPM_MIXER("SPO L MIX", SND_SOC_NOPM, 0, 0, rt5659_spo_l_mix,
2810 ARRAY_SIZE(rt5659_spo_l_mix)),
2811 SND_SOC_DAPM_MIXER("SPO R MIX", SND_SOC_NOPM, 0, 0, rt5659_spo_r_mix,
2812 ARRAY_SIZE(rt5659_spo_r_mix)),
2813 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5659_mono_mix,
2814 ARRAY_SIZE(rt5659_mono_mix)),
2815 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5659_lout_l_mix,
2816 ARRAY_SIZE(rt5659_lout_l_mix)),
2817 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5659_lout_r_mix,
2818 ARRAY_SIZE(rt5659_lout_r_mix)),
2819
2820 SND_SOC_DAPM_PGA_S("SPK Amp", 1, RT5659_PWR_DIG_1, RT5659_PWR_CLS_D_BIT,
2821 0, rt5659_spk_event, SND_SOC_DAPM_POST_PMD |
2822 SND_SOC_DAPM_PRE_PMU),
2823 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5659_PWR_ANLG_1, RT5659_PWR_MA_BIT,
2824 0, rt5659_mono_event, SND_SOC_DAPM_POST_PMD |
2825 SND_SOC_DAPM_PRE_PMU),
2826 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5659_hp_event,
2827 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
d1e84308
BL		 2828 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5659_PWR_ANLG_1, RT5659_PWR_LM_BIT,
2829 0, NULL, 0),
d3cb2de2
BL		 2830
2831 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
2832 rt5659_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
2833 SND_SOC_DAPM_POST_PMD),
2834
2835 SND_SOC_DAPM_SWITCH("SPO Playback", SND_SOC_NOPM, 0, 0, &spo_switch),
2836 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
2837 &mono_switch),
2838 SND_SOC_DAPM_SWITCH("HPO L Playback", SND_SOC_NOPM, 0, 0,
2839 &hpo_l_switch),
2840 SND_SOC_DAPM_SWITCH("HPO R Playback", SND_SOC_NOPM, 0, 0,
2841 &hpo_r_switch),
2842 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
2843 &lout_l_switch),
2844 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
2845 &lout_r_switch),
2846 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
2847 &pdm_l_switch),
2848 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
2849 &pdm_r_switch),
2850
2851 /* PDM */
2852 SND_SOC_DAPM_SUPPLY("PDM Power", RT5659_PWR_DIG_2,
2853 RT5659_PWR_PDM1_BIT, 0, NULL, 0),
2854 SND_SOC_DAPM_MUX("PDM L Mux", RT5659_PDM_OUT_CTRL,
2855 RT5659_M_PDM1_L_SFT, 1, &rt5659_pdm_l_mux),
2856 SND_SOC_DAPM_MUX("PDM R Mux", RT5659_PDM_OUT_CTRL,
2857 RT5659_M_PDM1_R_SFT, 1, &rt5659_pdm_r_mux),
2858
2859 /* SPDIF */
2860 SND_SOC_DAPM_MUX("SPDIF Mux", SND_SOC_NOPM, 0, 0, &rt5659_spdif_mux),
2861
2862 SND_SOC_DAPM_SUPPLY("SYS CLK DET", RT5659_CLK_DET, 3, 0, NULL, 0),
2863 SND_SOC_DAPM_SUPPLY("CLKDET", RT5659_CLK_DET, 0, 0, NULL, 0),
2864
2865 /* Output Lines */
2866 SND_SOC_DAPM_OUTPUT("HPOL"),
2867 SND_SOC_DAPM_OUTPUT("HPOR"),
2868 SND_SOC_DAPM_OUTPUT("SPOL"),
2869 SND_SOC_DAPM_OUTPUT("SPOR"),
2870 SND_SOC_DAPM_OUTPUT("LOUTL"),
2871 SND_SOC_DAPM_OUTPUT("LOUTR"),
2872 SND_SOC_DAPM_OUTPUT("MONOOUT"),
2873 SND_SOC_DAPM_OUTPUT("PDML"),
2874 SND_SOC_DAPM_OUTPUT("PDMR"),
2875 SND_SOC_DAPM_OUTPUT("SPDIF"),
2876};
2877
2878static const struct snd_soc_dapm_route rt5659_dapm_routes[] = {
2879 /*PLL*/
2880 { "ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll },
2881 { "ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll },
2882 { "ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll },
2883 { "ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll },
2884 { "DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll },
2885 { "DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll },
2886 { "DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll },
2887
2888 /*ASRC*/
2889 { "ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2890 { "ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc },
2891 { "ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc },
2892 { "DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc },
2893 { "DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc },
2894 { "DAC Stereo1 Filter", NULL, "DAC STO ASRC", is_using_asrc },
2895
2896 { "SYS CLK DET", NULL, "CLKDET" },
2897
2898 { "I2S1", NULL, "I2S1 ASRC" },
2899 { "I2S2", NULL, "I2S2 ASRC" },
2900 { "I2S3", NULL, "I2S3 ASRC" },
2901
d3cb2de2
BL		 2902 { "DMIC1", NULL, "DMIC L1" },
2903 { "DMIC1", NULL, "DMIC R1" },
2904 { "DMIC2", NULL, "DMIC L2" },
2905 { "DMIC2", NULL, "DMIC R2" },
2906
2907 { "BST1", NULL, "IN1P" },
2908 { "BST1", NULL, "IN1N" },
2909 { "BST1", NULL, "BST1 Power" },
2910 { "BST2", NULL, "IN2P" },
2911 { "BST2", NULL, "IN2N" },
2912 { "BST2", NULL, "BST2 Power" },
2913 { "BST3", NULL, "IN3P" },
2914 { "BST3", NULL, "IN3N" },
2915 { "BST3", NULL, "BST3 Power" },
2916 { "BST4", NULL, "IN4P" },
2917 { "BST4", NULL, "IN4N" },
2918 { "BST4", NULL, "BST4 Power" },
2919
2920 { "INL VOL", NULL, "IN2P" },
2921 { "INR VOL", NULL, "IN2N" },
2922
2923 { "RECMIX1L", "SPKVOLL Switch", "SPKVOL L" },
2924 { "RECMIX1L", "INL Switch", "INL VOL" },
2925 { "RECMIX1L", "BST4 Switch", "BST4" },
2926 { "RECMIX1L", "BST3 Switch", "BST3" },
2927 { "RECMIX1L", "BST2 Switch", "BST2" },
2928 { "RECMIX1L", "BST1 Switch", "BST1" },
2929
2930 { "RECMIX1R", "HPOVOLR Switch", "HPO R Playback" },
2931 { "RECMIX1R", "INR Switch", "INR VOL" },
2932 { "RECMIX1R", "BST4 Switch", "BST4" },
2933 { "RECMIX1R", "BST3 Switch", "BST3" },
2934 { "RECMIX1R", "BST2 Switch", "BST2" },
2935 { "RECMIX1R", "BST1 Switch", "BST1" },
2936
2937 { "RECMIX2L", "SPKVOLL Switch", "SPKVOL L" },
2938 { "RECMIX2L", "OUTVOLL Switch", "OUTVOL L" },
2939 { "RECMIX2L", "BST4 Switch", "BST4" },
2940 { "RECMIX2L", "BST3 Switch", "BST3" },
2941 { "RECMIX2L", "BST2 Switch", "BST2" },
2942 { "RECMIX2L", "BST1 Switch", "BST1" },
2943
2944 { "RECMIX2R", "MONOVOL Switch", "MONOVOL" },
2945 { "RECMIX2R", "OUTVOLR Switch", "OUTVOL R" },
2946 { "RECMIX2R", "BST4 Switch", "BST4" },
2947 { "RECMIX2R", "BST3 Switch", "BST3" },
2948 { "RECMIX2R", "BST2 Switch", "BST2" },
2949 { "RECMIX2R", "BST1 Switch", "BST1" },
2950
2951 { "ADC1 L", NULL, "RECMIX1L" },
2952 { "ADC1 L", NULL, "ADC1 L Power" },
2953 { "ADC1 L", NULL, "ADC1 clock" },
2954 { "ADC1 R", NULL, "RECMIX1R" },
2955 { "ADC1 R", NULL, "ADC1 R Power" },
2956 { "ADC1 R", NULL, "ADC1 clock" },
2957
2958 { "ADC2 L", NULL, "RECMIX2L" },
2959 { "ADC2 L", NULL, "ADC2 L Power" },
2960 { "ADC2 L", NULL, "ADC2 clock" },
2961 { "ADC2 R", NULL, "RECMIX2R" },
2962 { "ADC2 R", NULL, "ADC2 R Power" },
2963 { "ADC2 R", NULL, "ADC2 clock" },
2964
2965 { "DMIC L1", NULL, "DMIC CLK" },
2966 { "DMIC L1", NULL, "DMIC1 Power" },
2967 { "DMIC R1", NULL, "DMIC CLK" },
2968 { "DMIC R1", NULL, "DMIC1 Power" },
2969 { "DMIC L2", NULL, "DMIC CLK" },
2970 { "DMIC L2", NULL, "DMIC2 Power" },
2971 { "DMIC R2", NULL, "DMIC CLK" },
2972 { "DMIC R2", NULL, "DMIC2 Power" },
2973
2974 { "Stereo1 DMIC L Mux", "DMIC1", "DMIC L1" },
2975 { "Stereo1 DMIC L Mux", "DMIC2", "DMIC L2" },
2976
2977 { "Stereo1 DMIC R Mux", "DMIC1", "DMIC R1" },
2978 { "Stereo1 DMIC R Mux", "DMIC2", "DMIC R2" },
2979
2980 { "Mono DMIC L Mux", "DMIC1 L", "DMIC L1" },
2981 { "Mono DMIC L Mux", "DMIC2 L", "DMIC L2" },
2982
2983 { "Mono DMIC R Mux", "DMIC1 R", "DMIC R1" },
2984 { "Mono DMIC R Mux", "DMIC2 R", "DMIC R2" },
2985
2986 { "Stereo1 ADC L Mux", "ADC1", "ADC1 L" },
2987 { "Stereo1 ADC L Mux", "ADC2", "ADC2 L" },
2988 { "Stereo1 ADC R Mux", "ADC1", "ADC1 R" },
2989 { "Stereo1 ADC R Mux", "ADC2", "ADC2 R" },
2990
2991 { "Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux" },
2992 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2993 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux" },
2994 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2995
2996 { "Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux" },
2997 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2998 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux" },
2999 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
3000
3001 { "Mono ADC L Mux", "ADC1 L", "ADC1 L" },
3002 { "Mono ADC L Mux", "ADC1 R", "ADC1 R" },
3003 { "Mono ADC L Mux", "ADC2 L", "ADC2 L" },
3004 { "Mono ADC L Mux", "ADC2 R", "ADC2 R" },
3005
3006 { "Mono ADC R Mux", "ADC1 L", "ADC1 L" },
3007 { "Mono ADC R Mux", "ADC1 R", "ADC1 R" },
3008 { "Mono ADC R Mux", "ADC2 L", "ADC2 L" },
3009 { "Mono ADC R Mux", "ADC2 R", "ADC2 R" },
3010
3011 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
3012 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
3013 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
3014 { "Mono ADC L1 Mux", "ADC", "Mono ADC L Mux" },
3015
3016 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
3017 { "Mono ADC R1 Mux", "ADC", "Mono ADC R Mux" },
3018 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
3019 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
3020
3021 { "Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
3022 { "Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
3023 { "Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter" },
3024
3025 { "Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
3026 { "Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
3027 { "Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter" },
3028
3029 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
3030 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
3031 { "Mono ADC MIXL", NULL, "ADC Mono Left Filter" },
3032
3033 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
3034 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
3035 { "Mono ADC MIXR", NULL, "ADC Mono Right Filter" },
3036
3037 { "Stereo1 ADC Volume L", NULL, "Stereo1 ADC MIXL" },
3038 { "Stereo1 ADC Volume R", NULL, "Stereo1 ADC MIXR" },
3039
3040 { "IF_ADC1", NULL, "Stereo1 ADC Volume L" },
3041 { "IF_ADC1", NULL, "Stereo1 ADC Volume R" },
3042 { "IF_ADC2", NULL, "Mono ADC MIXL" },
3043 { "IF_ADC2", NULL, "Mono ADC MIXR" },
3044
3045 { "TDM AD1:AD2:DAC", NULL, "IF_ADC1" },
3046 { "TDM AD1:AD2:DAC", NULL, "IF_ADC2" },
3047 { "TDM AD1:AD2:DAC", NULL, "DAC_REF" },
3048 { "TDM AD2:DAC", NULL, "IF_ADC2" },
3049 { "TDM AD2:DAC", NULL, "DAC_REF" },
3050 { "TDM Data Mux", "AD1:AD2:DAC:NUL", "TDM AD1:AD2:DAC" },
3051 { "TDM Data Mux", "AD1:AD2:NUL:DAC", "TDM AD1:AD2:DAC" },
3052 { "TDM Data Mux", "AD1:DAC:AD2:NUL", "TDM AD1:AD2:DAC" },
3053 { "TDM Data Mux", "AD1:DAC:NUL:AD2", "TDM AD1:AD2:DAC" },
3054 { "TDM Data Mux", "AD1:NUL:DAC:AD2", "TDM AD1:AD2:DAC" },
3055 { "TDM Data Mux", "AD1:NUL:AD2:DAC", "TDM AD1:AD2:DAC" },
3056 { "TDM Data Mux", "AD2:AD1:DAC:NUL", "TDM AD1:AD2:DAC" },
3057 { "TDM Data Mux", "AD2:AD1:NUL:DAC", "TDM AD1:AD2:DAC" },
3058 { "TDM Data Mux", "AD2:DAC:AD1:NUL", "TDM AD1:AD2:DAC" },
3059 { "TDM Data Mux", "AD2:DAC:NUL:AD1", "TDM AD1:AD2:DAC" },
3060 { "TDM Data Mux", "AD2:NUL:DAC:AD1", "TDM AD1:AD2:DAC" },
3061 { "TDM Data Mux", "AD1:NUL:AD1:DAC", "TDM AD1:AD2:DAC" },
3062 { "TDM Data Mux", "DAC:AD1:AD2:NUL", "TDM AD1:AD2:DAC" },
3063 { "TDM Data Mux", "DAC:AD1:NUL:AD2", "TDM AD1:AD2:DAC" },
3064 { "TDM Data Mux", "DAC:AD2:AD1:NUL", "TDM AD1:AD2:DAC" },
3065 { "TDM Data Mux", "DAC:AD2:NUL:AD1", "TDM AD1:AD2:DAC" },
3066 { "TDM Data Mux", "DAC:NUL:DAC:AD2", "TDM AD2:DAC" },
3067 { "TDM Data Mux", "DAC:NUL:AD2:DAC", "TDM AD2:DAC" },
3068 { "TDM Data Mux", "NUL:AD1:AD2:DAC", "TDM AD1:AD2:DAC" },
3069 { "TDM Data Mux", "NUL:AD1:DAC:AD2", "TDM AD1:AD2:DAC" },
3070 { "TDM Data Mux", "NUL:AD2:AD1:DAC", "TDM AD1:AD2:DAC" },
3071 { "TDM Data Mux", "NUL:AD2:DAC:AD1", "TDM AD1:AD2:DAC" },
3072 { "TDM Data Mux", "NUL:DAC:DAC:AD2", "TDM AD2:DAC" },
3073 { "TDM Data Mux", "NUL:DAC:AD2:DAC", "TDM AD2:DAC" },
3074 { "IF1 01 ADC Swap Mux", "L/R", "TDM Data Mux" },
3075 { "IF1 01 ADC Swap Mux", "R/L", "TDM Data Mux" },
3076 { "IF1 01 ADC Swap Mux", "L/L", "TDM Data Mux" },
3077 { "IF1 01 ADC Swap Mux", "R/R", "TDM Data Mux" },
3078 { "IF1 23 ADC Swap Mux", "L/R", "TDM Data Mux" },
3079 { "IF1 23 ADC Swap Mux", "R/L", "TDM Data Mux" },
3080 { "IF1 23 ADC Swap Mux", "L/L", "TDM Data Mux" },
3081 { "IF1 23 ADC Swap Mux", "R/R", "TDM Data Mux" },
3082 { "IF1 45 ADC Swap Mux", "L/R", "TDM Data Mux" },
3083 { "IF1 45 ADC Swap Mux", "R/L", "TDM Data Mux" },
3084 { "IF1 45 ADC Swap Mux", "L/L", "TDM Data Mux" },
3085 { "IF1 45 ADC Swap Mux", "R/R", "TDM Data Mux" },
3086 { "IF1 67 ADC Swap Mux", "L/R", "TDM Data Mux" },
3087 { "IF1 67 ADC Swap Mux", "R/L", "TDM Data Mux" },
3088 { "IF1 67 ADC Swap Mux", "L/L", "TDM Data Mux" },
3089 { "IF1 67 ADC Swap Mux", "R/R", "TDM Data Mux" },
3090 { "IF1 ADC", NULL, "IF1 01 ADC Swap Mux" },
3091 { "IF1 ADC", NULL, "IF1 23 ADC Swap Mux" },
3092 { "IF1 ADC", NULL, "IF1 45 ADC Swap Mux" },
3093 { "IF1 ADC", NULL, "IF1 67 ADC Swap Mux" },
3094 { "IF1 ADC", NULL, "I2S1" },
3095
3096 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
3097 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
3098 { "IF2 ADC Mux", "IF_ADC3", "IF_ADC3" },
3099 { "IF2 ADC Mux", "DAC_REF", "DAC_REF" },
3100 { "IF2 ADC", NULL, "IF2 ADC Mux"},
3101 { "IF2 ADC", NULL, "I2S2" },
3102
3103 { "IF3 ADC Mux", "IF_ADC1", "IF_ADC1" },
3104 { "IF3 ADC Mux", "IF_ADC2", "IF_ADC2" },
3105 { "IF3 ADC Mux", "Stereo2_ADC_L/R", "Stereo2 ADC LR" },
3106 { "IF3 ADC Mux", "DAC_REF", "DAC_REF" },
3107 { "IF3 ADC", NULL, "IF3 ADC Mux"},
3108 { "IF3 ADC", NULL, "I2S3" },
3109
3110 { "AIF1TX", NULL, "IF1 ADC" },
3111 { "IF2 ADC Swap Mux", "L/R", "IF2 ADC" },
3112 { "IF2 ADC Swap Mux", "R/L", "IF2 ADC" },
3113 { "IF2 ADC Swap Mux", "L/L", "IF2 ADC" },
3114 { "IF2 ADC Swap Mux", "R/R", "IF2 ADC" },
3115 { "AIF2TX", NULL, "IF2 ADC Swap Mux" },
3116 { "IF3 ADC Swap Mux", "L/R", "IF3 ADC" },
3117 { "IF3 ADC Swap Mux", "R/L", "IF3 ADC" },
3118 { "IF3 ADC Swap Mux", "L/L", "IF3 ADC" },
3119 { "IF3 ADC Swap Mux", "R/R", "IF3 ADC" },
3120 { "AIF3TX", NULL, "IF3 ADC Swap Mux" },
3121
3122 { "IF1 DAC1", NULL, "AIF1RX" },
3123 { "IF1 DAC2", NULL, "AIF1RX" },
3124 { "IF2 DAC Swap Mux", "L/R", "AIF2RX" },
3125 { "IF2 DAC Swap Mux", "R/L", "AIF2RX" },
3126 { "IF2 DAC Swap Mux", "L/L", "AIF2RX" },
3127 { "IF2 DAC Swap Mux", "R/R", "AIF2RX" },
3128 { "IF2 DAC", NULL, "IF2 DAC Swap Mux" },
3129 { "IF3 DAC Swap Mux", "L/R", "AIF3RX" },
3130 { "IF3 DAC Swap Mux", "R/L", "AIF3RX" },
3131 { "IF3 DAC Swap Mux", "L/L", "AIF3RX" },
3132 { "IF3 DAC Swap Mux", "R/R", "AIF3RX" },
3133 { "IF3 DAC", NULL, "IF3 DAC Swap Mux" },
3134
3135 { "IF1 DAC1", NULL, "I2S1" },
3136 { "IF1 DAC2", NULL, "I2S1" },
3137 { "IF2 DAC", NULL, "I2S2" },
3138 { "IF3 DAC", NULL, "I2S3" },
3139
3140 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
3141 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
3142 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
3143 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
3144 { "IF2 DAC L", NULL, "IF2 DAC" },
3145 { "IF2 DAC R", NULL, "IF2 DAC" },
3146 { "IF3 DAC L", NULL, "IF3 DAC" },
3147 { "IF3 DAC R", NULL, "IF3 DAC" },
3148
3149 { "DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L" },
3150 { "DAC L1 Mux", "IF2 DAC", "IF2 DAC L" },
3151 { "DAC L1 Mux", "IF3 DAC", "IF3 DAC L" },
3152 { "DAC L1 Mux", NULL, "DAC Stereo1 Filter" },
3153
3154 { "DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R" },
3155 { "DAC R1 Mux", "IF2 DAC", "IF2 DAC R" },
3156 { "DAC R1 Mux", "IF3 DAC", "IF3 DAC R" },
3157 { "DAC R1 Mux", NULL, "DAC Stereo1 Filter" },
3158
3159 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC Volume L" },
3160 { "DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux" },
3161 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC Volume R" },
3162 { "DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux" },
3163
3164 { "DAC_REF", NULL, "DAC1 MIXL" },
3165 { "DAC_REF", NULL, "DAC1 MIXR" },
3166
3167 { "DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L" },
3168 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
3169 { "DAC L2 Mux", "IF3 DAC", "IF3 DAC L" },
3170 { "DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL" },
3171 { "DAC L2 Mux", NULL, "DAC Mono Left Filter" },
3172
3173 { "DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R" },
3174 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
3175 { "DAC R2 Mux", "IF3 DAC", "IF3 DAC R" },
3176 { "DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR" },
3177 { "DAC R2 Mux", NULL, "DAC Mono Right Filter" },
3178
3179 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
3180 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
3181 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" },
3182 { "Stereo DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" },
3183
3184 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
3185 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
3186 { "Stereo DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" },
3187 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" },
3188
3189 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
3190 { "Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
3191 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux" },
3192 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux" },
3193 { "Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
3194 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
3195 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux" },
3196 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux" },
3197
3198 { "DAC MIXL", "Stereo DAC Mixer", "Stereo DAC MIXL" },
3199 { "DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL" },
3200 { "DAC MIXR", "Stereo DAC Mixer", "Stereo DAC MIXR" },
3201 { "DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR" },
3202
3203 { "DAC L1 Source", NULL, "DAC L1 Power" },
3204 { "DAC L1 Source", "DAC", "DAC1 MIXL" },
3205 { "DAC L1 Source", "Stereo DAC Mixer", "Stereo DAC MIXL" },
3206 { "DAC R1 Source", NULL, "DAC R1 Power" },
3207 { "DAC R1 Source", "DAC", "DAC1 MIXR" },
3208 { "DAC R1 Source", "Stereo DAC Mixer", "Stereo DAC MIXR" },
3209 { "DAC L2 Source", "Stereo DAC Mixer", "Stereo DAC MIXL" },
3210 { "DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL" },
3211 { "DAC L2 Source", NULL, "DAC L2 Power" },
3212 { "DAC R2 Source", "Stereo DAC Mixer", "Stereo DAC MIXR" },
3213 { "DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR" },
3214 { "DAC R2 Source", NULL, "DAC R2 Power" },
3215
3216 { "DAC L1", NULL, "DAC L1 Source" },
3217 { "DAC R1", NULL, "DAC R1 Source" },
3218 { "DAC L2", NULL, "DAC L2 Source" },
3219 { "DAC R2", NULL, "DAC R2 Source" },
3220
3221 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
3222 { "SPK MIXL", "BST1 Switch", "BST1" },
3223 { "SPK MIXL", "INL Switch", "INL VOL" },
3224 { "SPK MIXL", "INR Switch", "INR VOL" },
3225 { "SPK MIXL", "BST3 Switch", "BST3" },
3226 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
3227 { "SPK MIXR", "BST4 Switch", "BST4" },
3228 { "SPK MIXR", "INL Switch", "INL VOL" },
3229 { "SPK MIXR", "INR Switch", "INR VOL" },
3230 { "SPK MIXR", "BST3 Switch", "BST3" },
3231
3232 { "MONOVOL MIX", "DAC L2 Switch", "DAC L2" },
3233 { "MONOVOL MIX", "DAC R2 Switch", "DAC R2" },
3234 { "MONOVOL MIX", "BST1 Switch", "BST1" },
3235 { "MONOVOL MIX", "BST2 Switch", "BST2" },
3236 { "MONOVOL MIX", "BST3 Switch", "BST3" },
3237
3238 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
3239 { "OUT MIXL", "INL Switch", "INL VOL" },
3240 { "OUT MIXL", "BST1 Switch", "BST1" },
3241 { "OUT MIXL", "BST2 Switch", "BST2" },
3242 { "OUT MIXL", "BST3 Switch", "BST3" },
3243 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
3244 { "OUT MIXR", "INR Switch", "INR VOL" },
3245 { "OUT MIXR", "BST2 Switch", "BST2" },
3246 { "OUT MIXR", "BST3 Switch", "BST3" },
3247 { "OUT MIXR", "BST4 Switch", "BST4" },
3248
3249 { "SPKVOL L", "Switch", "SPK MIXL" },
3250 { "SPKVOL R", "Switch", "SPK MIXR" },
3251 { "SPO L MIX", "DAC L2 Switch", "DAC L2" },
3252 { "SPO L MIX", "SPKVOL L Switch", "SPKVOL L" },
3253 { "SPO R MIX", "DAC R2 Switch", "DAC R2" },
3254 { "SPO R MIX", "SPKVOL R Switch", "SPKVOL R" },
3255 { "SPK Amp", NULL, "SPO L MIX" },
3256 { "SPK Amp", NULL, "SPO R MIX" },
3257 { "SPK Amp", NULL, "SYS CLK DET" },
3258 { "SPO Playback", "Switch", "SPK Amp" },
3259 { "SPOL", NULL, "SPO Playback" },
3260 { "SPOR", NULL, "SPO Playback" },
3261
3262 { "MONOVOL", "Switch", "MONOVOL MIX" },
3263 { "Mono MIX", "DAC L2 Switch", "DAC L2" },
3264 { "Mono MIX", "MONOVOL Switch", "MONOVOL" },
3265 { "Mono Amp", NULL, "Mono MIX" },
3266 { "Mono Amp", NULL, "Mono Vref" },
3267 { "Mono Amp", NULL, "SYS CLK DET" },
3268 { "Mono Playback", "Switch", "Mono Amp" },
3269 { "MONOOUT", NULL, "Mono Playback" },
3270
3271 { "HP Amp", NULL, "DAC L1" },
3272 { "HP Amp", NULL, "DAC R1" },
3273 { "HP Amp", NULL, "Charge Pump" },
3274 { "HP Amp", NULL, "SYS CLK DET" },
3275 { "HPO L Playback", "Switch", "HP Amp"},
3276 { "HPO R Playback", "Switch", "HP Amp"},
3277 { "HPOL", NULL, "HPO L Playback" },
3278 { "HPOR", NULL, "HPO R Playback" },
3279
3280 { "OUTVOL L", "Switch", "OUT MIXL" },
3281 { "OUTVOL R", "Switch", "OUT MIXR" },
3282 { "LOUT L MIX", "DAC L2 Switch", "DAC L2" },
3283 { "LOUT L MIX", "OUTVOL L Switch", "OUTVOL L" },
3284 { "LOUT R MIX", "DAC R2 Switch", "DAC R2" },
3285 { "LOUT R MIX", "OUTVOL R Switch", "OUTVOL R" },
3286 { "LOUT Amp", NULL, "LOUT L MIX" },
3287 { "LOUT Amp", NULL, "LOUT R MIX" },
a6189d37 3288 { "LOUT Amp", NULL, "Charge Pump" },
d3cb2de2
BL		 3289 { "LOUT Amp", NULL, "SYS CLK DET" },
3290 { "LOUT L Playback", "Switch", "LOUT Amp" },
3291 { "LOUT R Playback", "Switch", "LOUT Amp" },
3292 { "LOUTL", NULL, "LOUT L Playback" },
3293 { "LOUTR", NULL, "LOUT R Playback" },
3294
3295 { "PDM L Mux", "Mono DAC", "Mono DAC MIXL" },
3296 { "PDM L Mux", "Stereo DAC", "Stereo DAC MIXL" },
3297 { "PDM L Mux", NULL, "PDM Power" },
3298 { "PDM R Mux", "Mono DAC", "Mono DAC MIXR" },
3299 { "PDM R Mux", "Stereo DAC", "Stereo DAC MIXR" },
3300 { "PDM R Mux", NULL, "PDM Power" },
3301 { "PDM L Playback", "Switch", "PDM L Mux" },
3302 { "PDM R Playback", "Switch", "PDM R Mux" },
3303 { "PDML", NULL, "PDM L Playback" },
3304 { "PDMR", NULL, "PDM R Playback" },
3305
3306 { "SPDIF Mux", "IF3_DAC", "IF3 DAC" },
3307 { "SPDIF Mux", "IF2_DAC", "IF2 DAC" },
3308 { "SPDIF Mux", "IF1_DAC2", "IF1 DAC2" },
3309 { "SPDIF Mux", "IF1_DAC1", "IF1 DAC1" },
3310 { "SPDIF", NULL, "SPDIF Mux" },
3311};
3312
3313static int rt5659_hw_params(struct snd_pcm_substream *substream,
3314 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3315{
de86a332
KM		 3316 struct snd_soc_component *component = dai->component;
3317 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
d3cb2de2
BL		 3318 unsigned int val_len = 0, val_clk, mask_clk;
3319 int pre_div, frame_size;
3320
3321 rt5659->lrck[dai->id] = params_rate(params);
3322 pre_div = rl6231_get_clk_info(rt5659->sysclk, rt5659->lrck[dai->id]);
3323 if (pre_div < 0) {
de86a332 3324 dev_err(component->dev, "Unsupported clock setting %d for DAI %d\n",
d3cb2de2
BL		 3325 rt5659->lrck[dai->id], dai->id);
3326 return -EINVAL;
3327 }
3328 frame_size = snd_soc_params_to_frame_size(params);
3329 if (frame_size < 0) {
de86a332 3330 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
d3cb2de2
BL		 3331 return -EINVAL;
3332 }
3333
3334 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
3335 rt5659->lrck[dai->id], pre_div, dai->id);
3336
3337 switch (params_width(params)) {
3338 case 16:
3339 break;
3340 case 20:
3341 val_len |= RT5659_I2S_DL_20;
3342 break;
3343 case 24:
3344 val_len |= RT5659_I2S_DL_24;
3345 break;
3346 case 8:
3347 val_len |= RT5659_I2S_DL_8;
3348 break;
3349 default:
3350 return -EINVAL;
3351 }
3352
3353 switch (dai->id) {
3354 case RT5659_AIF1:
3355 mask_clk = RT5659_I2S_PD1_MASK;
3356 val_clk = pre_div << RT5659_I2S_PD1_SFT;
de86a332 3357 snd_soc_component_update_bits(component, RT5659_I2S1_SDP,
d3cb2de2
BL		 3358 RT5659_I2S_DL_MASK, val_len);
3359 break;
3360 case RT5659_AIF2:
3361 mask_clk = RT5659_I2S_PD2_MASK;
3362 val_clk = pre_div << RT5659_I2S_PD2_SFT;
de86a332 3363 snd_soc_component_update_bits(component, RT5659_I2S2_SDP,
d3cb2de2
BL		 3364 RT5659_I2S_DL_MASK, val_len);
3365 break;
3366 case RT5659_AIF3:
3367 mask_clk = RT5659_I2S_PD3_MASK;
3368 val_clk = pre_div << RT5659_I2S_PD3_SFT;
de86a332 3369 snd_soc_component_update_bits(component, RT5659_I2S3_SDP,
d3cb2de2
BL		 3370 RT5659_I2S_DL_MASK, val_len);
3371 break;
3372 default:
de86a332 3373 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
d3cb2de2
BL		 3374 return -EINVAL;
3375 }
3376
de86a332 3377 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1, mask_clk, val_clk);
d3cb2de2
BL		 3378
3379 switch (rt5659->lrck[dai->id]) {
3380 case 192000:
de86a332 3381 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
d3cb2de2
BL		 3382 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_32);
3383 break;
3384 case 96000:
de86a332 3385 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
d3cb2de2
BL		 3386 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_64);
3387 break;
3388 default:
de86a332 3389 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
d3cb2de2
BL		 3390 RT5659_DAC_OSR_MASK, RT5659_DAC_OSR_128);
3391 break;
3392 }
3393
3394 return 0;
3395}
3396
3397static int rt5659_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
3398{
de86a332
KM		 3399 struct snd_soc_component *component = dai->component;
3400 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
d3cb2de2
BL		 3401 unsigned int reg_val = 0;
3402
3403 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
3404 case SND_SOC_DAIFMT_CBM_CFM:
3405 rt5659->master[dai->id] = 1;
3406 break;
3407 case SND_SOC_DAIFMT_CBS_CFS:
3408 reg_val |= RT5659_I2S_MS_S;
3409 rt5659->master[dai->id] = 0;
3410 break;
3411 default:
3412 return -EINVAL;
3413 }
3414
3415 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
3416 case SND_SOC_DAIFMT_NB_NF:
3417 break;
3418 case SND_SOC_DAIFMT_IB_NF:
3419 reg_val |= RT5659_I2S_BP_INV;
3420 break;
3421 default:
3422 return -EINVAL;
3423 }
3424
3425 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
3426 case SND_SOC_DAIFMT_I2S:
3427 break;
3428 case SND_SOC_DAIFMT_LEFT_J:
3429 reg_val |= RT5659_I2S_DF_LEFT;
3430 break;
3431 case SND_SOC_DAIFMT_DSP_A:
3432 reg_val |= RT5659_I2S_DF_PCM_A;
3433 break;
3434 case SND_SOC_DAIFMT_DSP_B:
3435 reg_val |= RT5659_I2S_DF_PCM_B;
3436 break;
3437 default:
3438 return -EINVAL;
3439 }
3440
3441 switch (dai->id) {
3442 case RT5659_AIF1:
de86a332 3443 snd_soc_component_update_bits(component, RT5659_I2S1_SDP,
d3cb2de2
BL		 3444 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
3445 RT5659_I2S_DF_MASK, reg_val);
3446 break;
3447 case RT5659_AIF2:
de86a332 3448 snd_soc_component_update_bits(component, RT5659_I2S2_SDP,
d3cb2de2
BL		 3449 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
3450 RT5659_I2S_DF_MASK, reg_val);
3451 break;
3452 case RT5659_AIF3:
de86a332 3453 snd_soc_component_update_bits(component, RT5659_I2S3_SDP,
d3cb2de2
BL		 3454 RT5659_I2S_MS_MASK | RT5659_I2S_BP_MASK |
3455 RT5659_I2S_DF_MASK, reg_val);
3456 break;
3457 default:
de86a332 3458 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
d3cb2de2
BL		 3459 return -EINVAL;
3460 }
3461 return 0;
3462}
3463
de86a332 3464static int rt5659_set_component_sysclk(struct snd_soc_component *component, int clk_id,
fe01e5e8 3465 int source, unsigned int freq, int dir)
d3cb2de2 3466{
de86a332 3467 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
d3cb2de2
BL		 3468 unsigned int reg_val = 0;
3469
3470 if (freq == rt5659->sysclk && clk_id == rt5659->sysclk_src)
3471 return 0;
3472
3473 switch (clk_id) {
3474 case RT5659_SCLK_S_MCLK:
3475 reg_val |= RT5659_SCLK_SRC_MCLK;
3476 break;
3477 case RT5659_SCLK_S_PLL1:
3478 reg_val |= RT5659_SCLK_SRC_PLL1;
3479 break;
3480 case RT5659_SCLK_S_RCCLK:
3481 reg_val |= RT5659_SCLK_SRC_RCCLK;
3482 break;
3483 default:
de86a332 3484 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
d3cb2de2
BL		 3485 return -EINVAL;
3486 }
de86a332 3487 snd_soc_component_update_bits(component, RT5659_GLB_CLK,
d3cb2de2
BL		 3488 RT5659_SCLK_SRC_MASK, reg_val);
3489 rt5659->sysclk = freq;
3490 rt5659->sysclk_src = clk_id;
3491
de86a332 3492 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
fe01e5e8 3493 freq, clk_id);
d3cb2de2
BL		 3494
3495 return 0;
3496}
3497
de86a332 3498static int rt5659_set_component_pll(struct snd_soc_component *component, int pll_id,
c8a04b5d
BL		 3499 int source, unsigned int freq_in,
3500 unsigned int freq_out)
d3cb2de2 3501{
de86a332 3502 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
d3cb2de2
BL		 3503 struct rl6231_pll_code pll_code;
3504 int ret;
3505
c8a04b5d 3506 if (source == rt5659->pll_src && freq_in == rt5659->pll_in &&
d3cb2de2
BL		 3507 freq_out == rt5659->pll_out)
3508 return 0;
3509
3510 if (!freq_in || !freq_out) {
de86a332 3511 dev_dbg(component->dev, "PLL disabled\n");
d3cb2de2
BL		 3512
3513 rt5659->pll_in = 0;
3514 rt5659->pll_out = 0;
de86a332 3515 snd_soc_component_update_bits(component, RT5659_GLB_CLK,
d3cb2de2
BL		 3516 RT5659_SCLK_SRC_MASK, RT5659_SCLK_SRC_MCLK);
3517 return 0;
3518 }
3519
c8a04b5d 3520 switch (source) {
d3cb2de2 3521 case RT5659_PLL1_S_MCLK:
de86a332 3522 snd_soc_component_update_bits(component, RT5659_GLB_CLK,
d3cb2de2
BL		 3523 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_MCLK);
3524 break;
3525 case RT5659_PLL1_S_BCLK1:
de86a332 3526 snd_soc_component_update_bits(component, RT5659_GLB_CLK,
d3cb2de2
BL		 3527 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK1);
3528 break;
3529 case RT5659_PLL1_S_BCLK2:
de86a332 3530 snd_soc_component_update_bits(component, RT5659_GLB_CLK,
d3cb2de2
BL		 3531 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK2);
3532 break;
3533 case RT5659_PLL1_S_BCLK3:
de86a332 3534 snd_soc_component_update_bits(component, RT5659_GLB_CLK,
d3cb2de2
BL		 3535 RT5659_PLL1_SRC_MASK, RT5659_PLL1_SRC_BCLK3);
3536 break;
3537 default:
de86a332 3538 dev_err(component->dev, "Unknown PLL source %d\n", source);
d3cb2de2
BL		 3539 return -EINVAL;
3540 }
3541
3542 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
3543 if (ret < 0) {
de86a332 3544 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
d3cb2de2
BL		 3545 return ret;
3546 }
3547
de86a332 3548 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
d3cb2de2
BL		 3549 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
3550 pll_code.n_code, pll_code.k_code);
3551
de86a332 3552 snd_soc_component_write(component, RT5659_PLL_CTRL_1,
d3cb2de2 3553 pll_code.n_code << RT5659_PLL_N_SFT | pll_code.k_code);
de86a332 3554 snd_soc_component_write(component, RT5659_PLL_CTRL_2,
d3cb2de2
BL		 3555 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5659_PLL_M_SFT |
3556 pll_code.m_bp << RT5659_PLL_M_BP_SFT);
3557
3558 rt5659->pll_in = freq_in;
3559 rt5659->pll_out = freq_out;
c8a04b5d 3560 rt5659->pll_src = source;
d3cb2de2
BL		 3561
3562 return 0;
3563}
3564
3565static int rt5659_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3566 unsigned int rx_mask, int slots, int slot_width)
3567{
de86a332 3568 struct snd_soc_component *component = dai->component;
d3cb2de2
BL		 3569 unsigned int val = 0;
3570
3571 if (rx_mask || tx_mask)
3572 val |= (1 << 15);
3573
3574 switch (slots) {
3575 case 4:
3576 val |= (1 << 10);
3577 val |= (1 << 8);
3578 break;
3579 case 6:
3580 val |= (2 << 10);
3581 val |= (2 << 8);
3582 break;
3583 case 8:
3584 val |= (3 << 10);
3585 val |= (3 << 8);
3586 break;
3587 case 2:
3588 break;
3589 default:
3590 return -EINVAL;
3591 }
3592
3593 switch (slot_width) {
3594 case 20:
3595 val |= (1 << 6);
3596 val |= (1 << 4);
3597 break;
3598 case 24:
3599 val |= (2 << 6);
3600 val |= (2 << 4);
3601 break;
3602 case 32:
3603 val |= (3 << 6);
3604 val |= (3 << 4);
3605 break;
3606 case 16:
3607 break;
3608 default:
3609 return -EINVAL;
3610 }
3611
de86a332 3612 snd_soc_component_update_bits(component, RT5659_TDM_CTRL_1, 0x8ff0, val);
d3cb2de2
BL		 3613
3614 return 0;
3615}
3616
3617static int rt5659_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
3618{
de86a332
KM		 3619 struct snd_soc_component *component = dai->component;
3620 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
d3cb2de2 3621
de86a332 3622 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
d3cb2de2
BL		 3623
3624 rt5659->bclk[dai->id] = ratio;
3625
3626 if (ratio == 64) {
3627 switch (dai->id) {
3628 case RT5659_AIF2:
de86a332 3629 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
d3cb2de2
BL		 3630 RT5659_I2S_BCLK_MS2_MASK,
3631 RT5659_I2S_BCLK_MS2_64);
3632 break;
3633 case RT5659_AIF3:
de86a332 3634 snd_soc_component_update_bits(component, RT5659_ADDA_CLK_1,
d3cb2de2
BL		 3635 RT5659_I2S_BCLK_MS3_MASK,
3636 RT5659_I2S_BCLK_MS3_64);
3637 break;
3638 }
3639 }
3640
3641 return 0;
3642}
3643
de86a332 3644static int rt5659_set_bias_level(struct snd_soc_component *component,
d3cb2de2
BL		 3645 enum snd_soc_bias_level level)
3646{
de86a332
KM		 3647 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3648 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
c6f8769b 3649 int ret;
d3cb2de2
BL		 3650
3651 switch (level) {
3652 case SND_SOC_BIAS_PREPARE:
3653 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC,
3654 RT5659_DIG_GATE_CTRL, RT5659_DIG_GATE_CTRL);
3655 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1,
3656 RT5659_PWR_LDO, RT5659_PWR_LDO);
3657 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
3658 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2,
3659 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2);
3660 msleep(20);
3661 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
3662 RT5659_PWR_FV1 | RT5659_PWR_FV2,
3663 RT5659_PWR_FV1 | RT5659_PWR_FV2);
3664 break;
3665
c6f8769b
NC		 3666 case SND_SOC_BIAS_STANDBY:
3667 if (dapm->bias_level == SND_SOC_BIAS_OFF) {
3668 ret = clk_prepare_enable(rt5659->mclk);
3669 if (ret) {
de86a332 3670 dev_err(component->dev,
c6f8769b
NC		 3671 "failed to enable MCLK: %d\n", ret);
3672 return ret;
3673 }
3674 }
3675 break;
3676
d3cb2de2
BL		 3677 case SND_SOC_BIAS_OFF:
3678 regmap_update_bits(rt5659->regmap, RT5659_PWR_DIG_1,
3679 RT5659_PWR_LDO, 0);
3680 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
3681 RT5659_PWR_MB | RT5659_PWR_VREF1 | RT5659_PWR_VREF2
3682 | RT5659_PWR_FV1 | RT5659_PWR_FV2,
3683 RT5659_PWR_MB | RT5659_PWR_VREF2);
3684 regmap_update_bits(rt5659->regmap, RT5659_DIG_MISC,
3685 RT5659_DIG_GATE_CTRL, 0);
c6f8769b 3686 clk_disable_unprepare(rt5659->mclk);
d3cb2de2
BL		 3687 break;
3688
3689 default:
3690 break;
3691 }
3692
3693 return 0;
3694}
3695
de86a332 3696static int rt5659_probe(struct snd_soc_component *component)
d3cb2de2 3697{
de86a332 3698 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
d3cb2de2 3699
de86a332 3700 rt5659->component = component;
d3cb2de2
BL		 3701
3702 return 0;
3703}
3704
de86a332 3705static void rt5659_remove(struct snd_soc_component *component)
d3cb2de2 3706{
de86a332 3707 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
d3cb2de2
BL		 3708
3709 regmap_write(rt5659->regmap, RT5659_RESET, 0);
d3cb2de2
BL		 3710}
3711
3712#ifdef CONFIG_PM
de86a332 3713static int rt5659_suspend(struct snd_soc_component *component)
d3cb2de2 3714{
de86a332 3715 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
d3cb2de2
BL		 3716
3717 regcache_cache_only(rt5659->regmap, true);
3718 regcache_mark_dirty(rt5659->regmap);
3719 return 0;
3720}
3721
de86a332 3722static int rt5659_resume(struct snd_soc_component *component)
d3cb2de2 3723{
de86a332 3724 struct rt5659_priv *rt5659 = snd_soc_component_get_drvdata(component);
d3cb2de2
BL		 3725
3726 regcache_cache_only(rt5659->regmap, false);
3727 regcache_sync(rt5659->regmap);
3728
3729 return 0;
3730}
3731#else
3732#define rt5659_suspend NULL
3733#define rt5659_resume NULL
3734#endif
3735
3736#define RT5659_STEREO_RATES SNDRV_PCM_RATE_8000_192000
3737#define RT5659_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3738 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3739
3740static const struct snd_soc_dai_ops rt5659_aif_dai_ops = {
3741 .hw_params = rt5659_hw_params,
3742 .set_fmt = rt5659_set_dai_fmt,
d3cb2de2 3743 .set_tdm_slot = rt5659_set_tdm_slot,
d3cb2de2
BL		 3744 .set_bclk_ratio = rt5659_set_bclk_ratio,
3745};
3746
3747static struct snd_soc_dai_driver rt5659_dai[] = {
3748 {
3749 .name = "rt5659-aif1",
3750 .id = RT5659_AIF1,
3751 .playback = {
3752 .stream_name = "AIF1 Playback",
3753 .channels_min = 1,
3754 .channels_max = 2,
3755 .rates = RT5659_STEREO_RATES,
3756 .formats = RT5659_FORMATS,
3757 },
3758 .capture = {
3759 .stream_name = "AIF1 Capture",
3760 .channels_min = 1,
3761 .channels_max = 2,
3762 .rates = RT5659_STEREO_RATES,
3763 .formats = RT5659_FORMATS,
3764 },
3765 .ops = &rt5659_aif_dai_ops,
3766 },
3767 {
3768 .name = "rt5659-aif2",
3769 .id = RT5659_AIF2,
3770 .playback = {
3771 .stream_name = "AIF2 Playback",
3772 .channels_min = 1,
3773 .channels_max = 2,
3774 .rates = RT5659_STEREO_RATES,
3775 .formats = RT5659_FORMATS,
3776 },
3777 .capture = {
3778 .stream_name = "AIF2 Capture",
3779 .channels_min = 1,
3780 .channels_max = 2,
3781 .rates = RT5659_STEREO_RATES,
3782 .formats = RT5659_FORMATS,
3783 },
3784 .ops = &rt5659_aif_dai_ops,
3785 },
3786 {
3787 .name = "rt5659-aif3",
3788 .id = RT5659_AIF3,
3789 .playback = {
3790 .stream_name = "AIF3 Playback",
3791 .channels_min = 1,
3792 .channels_max = 2,
3793 .rates = RT5659_STEREO_RATES,
3794 .formats = RT5659_FORMATS,
3795 },
3796 .capture = {
3797 .stream_name = "AIF3 Capture",
3798 .channels_min = 1,
3799 .channels_max = 2,
3800 .rates = RT5659_STEREO_RATES,
3801 .formats = RT5659_FORMATS,
3802 },
3803 .ops = &rt5659_aif_dai_ops,
3804 },
3805};
3806
de86a332
KM		 3807static const struct snd_soc_component_driver soc_component_dev_rt5659 = {
3808 .probe = rt5659_probe,
3809 .remove = rt5659_remove,
3810 .suspend = rt5659_suspend,
3811 .resume = rt5659_resume,
3812 .set_bias_level = rt5659_set_bias_level,
3813 .controls = rt5659_snd_controls,
3814 .num_controls = ARRAY_SIZE(rt5659_snd_controls),
3815 .dapm_widgets = rt5659_dapm_widgets,
3816 .num_dapm_widgets = ARRAY_SIZE(rt5659_dapm_widgets),
3817 .dapm_routes = rt5659_dapm_routes,
3818 .num_dapm_routes = ARRAY_SIZE(rt5659_dapm_routes),
3819 .set_sysclk = rt5659_set_component_sysclk,
3820 .set_pll = rt5659_set_component_pll,
3821 .use_pmdown_time = 1,
3822 .endianness = 1,
3823 .non_legacy_dai_naming = 1,
d3cb2de2
BL		 3824};
3825
3826
3827static const struct regmap_config rt5659_regmap = {
3828 .reg_bits = 16,
3829 .val_bits = 16,
3830 .max_register = 0x0400,
3831 .volatile_reg = rt5659_volatile_register,
3832 .readable_reg = rt5659_readable_register,
3833 .cache_type = REGCACHE_RBTREE,
3834 .reg_defaults = rt5659_reg,
3835 .num_reg_defaults = ARRAY_SIZE(rt5659_reg),
3836};
3837
3838static const struct i2c_device_id rt5659_i2c_id[] = {
3839 { "rt5658", 0 },
3840 { "rt5659", 0 },
3841 { }
3842};
3843MODULE_DEVICE_TABLE(i2c, rt5659_i2c_id);
3844
3845static int rt5659_parse_dt(struct rt5659_priv *rt5659, struct device *dev)
3846{
3847 rt5659->pdata.in1_diff = device_property_read_bool(dev,
3848 "realtek,in1-differential");
3849 rt5659->pdata.in3_diff = device_property_read_bool(dev,
3850 "realtek,in3-differential");
3851 rt5659->pdata.in4_diff = device_property_read_bool(dev,
3852 "realtek,in4-differential");
3853
3854
3855 device_property_read_u32(dev, "realtek,dmic1-data-pin",
3856 &rt5659->pdata.dmic1_data_pin);
3857 device_property_read_u32(dev, "realtek,dmic2-data-pin",
3858 &rt5659->pdata.dmic2_data_pin);
3859 device_property_read_u32(dev, "realtek,jd-src",
3860 &rt5659->pdata.jd_src);
3861
3862 return 0;
3863}
3864
3865static void rt5659_calibrate(struct rt5659_priv *rt5659)
3866{
3867 int value, count;
3868
3869 /* Calibrate HPO Start */
3870 /* Fine tune HP Performance */
3871 regmap_write(rt5659->regmap, RT5659_BIAS_CUR_CTRL_8, 0xa502);
3872 regmap_write(rt5659->regmap, RT5659_CHOP_DAC, 0x3030);
3873
3874 regmap_write(rt5659->regmap, RT5659_PRE_DIV_1, 0xef00);
3875 regmap_write(rt5659->regmap, RT5659_PRE_DIV_2, 0xeffc);
3876 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0280);
3877 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0001);
3878 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x8000);
3879
3880 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xaa7e);
3881 msleep(60);
3882 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe7e);
3883 msleep(50);
3884 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0004);
3885 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0400);
3886 msleep(50);
3887 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0080);
3888 usleep_range(10000, 10005);
3889 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0009);
3890 msleep(50);
3891 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0f80);
3892 msleep(50);
3893 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0e16);
3894 msleep(50);
3895
3896 /* Enalbe K ADC Power And Clock */
3897 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0505);
3898 msleep(50);
3899 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0184);
3900 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x3c05);
3901 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c1);
3902
3903 /* K Headphone */
3904 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
3905 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x5100);
3906 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0014);
3907 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0xd100);
3908 msleep(60);
3909
3910 /* Manual K ADC Offset */
3911 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
3912 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4900);
3913 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0016);
3914 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1,
3915 0x8000, 0x8000);
3916
3917 count = 0;
3918 while (true) {
3919 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value);
3920 if (value & 0x8000)
3921 usleep_range(10000, 10005);
3922 else
3923 break;
3924
3925 if (count > 30) {
de86a332 3926 dev_err(rt5659->component->dev,
d3cb2de2
BL		 3927 "HP Calibration 1 Failure\n");
3928 return;
3929 }
3930
3931 count++;
3932 }
3933
3934 /* Manual K Internal Path Offset */
3935 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x2cc1);
3936 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x0000);
3937 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, 0x4500);
3938 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x001f);
3939 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_1,
3940 0x8000, 0x8000);
3941
3942 count = 0;
3943 while (true) {
3944 regmap_read(rt5659->regmap, RT5659_HP_CALIB_CTRL_1, &value);
3945 if (value & 0x8000)
3946 usleep_range(10000, 10005);
3947 else
3948 break;
3949
3950 if (count > 85) {
de86a332 3951 dev_err(rt5659->component->dev,
d3cb2de2
BL		 3952 "HP Calibration 2 Failure\n");
3953 return;
3954 }
3955
3956 count++;
3957 }
3958
3959 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_7, 0x0000);
3960 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0);
3961 /* Calibrate HPO End */
3962
3963 /* Calibrate SPO Start */
3964 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021);
3965 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0260);
3966 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x3000);
3967 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0xc000);
3968 regmap_write(rt5659->regmap, RT5659_A_DAC_MUX, 0x000c);
3969 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x8000);
3970 regmap_write(rt5659->regmap, RT5659_SPO_VOL, 0x0808);
3971 regmap_write(rt5659->regmap, RT5659_SPK_L_MIXER, 0x001e);
3972 regmap_write(rt5659->regmap, RT5659_SPK_R_MIXER, 0x001e);
3973 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0803);
3974 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0554);
3975 regmap_write(rt5659->regmap, RT5659_SPO_AMP_GAIN, 0x1103);
3976
3977 /* Enalbe K ADC Power And Clock */
3978 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0909);
3979 regmap_update_bits(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x0001,
3980 0x0001);
3981
3982 /* Start Calibration */
3983 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0000);
3984 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x0021);
3985 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1, 0x3e80);
3986 regmap_update_bits(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_1,
3987 0x8000, 0x8000);
3988
3989 count = 0;
3990 while (true) {
3991 regmap_read(rt5659->regmap,
3992 RT5659_SPK_DC_CAILB_CTRL_1, &value);
3993 if (value & 0x8000)
3994 usleep_range(10000, 10005);
3995 else
3996 break;
3997
3998 if (count > 10) {
de86a332 3999 dev_err(rt5659->component->dev,
d3cb2de2
BL		 4000 "SPK Calibration Failure\n");
4001 return;
4002 }
4003
4004 count++;
4005 }
4006 /* Calibrate SPO End */
4007
4008 /* Calibrate MONO Start */
4009 regmap_write(rt5659->regmap, RT5659_DIG_MISC, 0x0000);
4010 regmap_write(rt5659->regmap, RT5659_MONOMIX_IN_GAIN, 0x021f);
4011 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0x480a);
4012 /* MONO NG2 GAIN 5dB */
4013 regmap_write(rt5659->regmap, RT5659_MONO_GAIN, 0x0003);
4014 regmap_write(rt5659->regmap, RT5659_MONO_NG2_CTRL_5, 0x0009);
4015
4016 /* Start Calibration */
4017 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x000f);
4018 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e00);
4019 regmap_update_bits(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1,
4020 0x8000, 0x8000);
4021
4022 count = 0;
4023 while (true) {
4024 regmap_read(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1,
4025 &value);
4026 if (value & 0x8000)
4027 usleep_range(10000, 10005);
4028 else
4029 break;
4030
4031 if (count > 35) {
de86a332 4032 dev_err(rt5659->component->dev,
d3cb2de2
BL		 4033 "Mono Calibration Failure\n");
4034 return;
4035 }
4036
4037 count++;
4038 }
4039
4040 regmap_write(rt5659->regmap, RT5659_SPK_DC_CAILB_CTRL_3, 0x0003);
4041 /* Calibrate MONO End */
4042
4043 /* Power Off */
4044 regmap_write(rt5659->regmap, RT5659_CAL_REC, 0x0808);
4045 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_3, 0x0000);
4046 regmap_write(rt5659->regmap, RT5659_CALIB_ADC_CTRL, 0x2005);
4047 regmap_write(rt5659->regmap, RT5659_HP_CALIB_CTRL_2, 0x20c0);
4048 regmap_write(rt5659->regmap, RT5659_DEPOP_1, 0x0000);
4049 regmap_write(rt5659->regmap, RT5659_CLASSD_1, 0x0011);
4050 regmap_write(rt5659->regmap, RT5659_CLASSD_2, 0x0150);
4051 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0xfe3e);
4052 regmap_write(rt5659->regmap, RT5659_MONO_OUT, 0xc80a);
4053 regmap_write(rt5659->regmap, RT5659_MONO_AMP_CALIB_CTRL_1, 0x1e04);
4054 regmap_write(rt5659->regmap, RT5659_PWR_MIXER, 0x0000);
4055 regmap_write(rt5659->regmap, RT5659_PWR_VOL, 0x0000);
4056 regmap_write(rt5659->regmap, RT5659_PWR_DIG_1, 0x0000);
4057 regmap_write(rt5659->regmap, RT5659_PWR_DIG_2, 0x0000);
4058 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_1, 0x003e);
4059 regmap_write(rt5659->regmap, RT5659_CLASSD_CTRL_1, 0x0060);
4060 regmap_write(rt5659->regmap, RT5659_CLASSD_0, 0x2021);
4061 regmap_write(rt5659->regmap, RT5659_GLB_CLK, 0x0000);
4062 regmap_write(rt5659->regmap, RT5659_MICBIAS_2, 0x0080);
4063 regmap_write(rt5659->regmap, RT5659_HP_VOL, 0x8080);
4064 regmap_write(rt5659->regmap, RT5659_HP_CHARGE_PUMP_1, 0x0c16);
4065}
4066
2fa0b7fd 4067static void rt5659_intel_hd_header_probe_setup(struct rt5659_priv *rt5659)
041e74b7 4068{
4069 int value;
4070
4071 regmap_read(rt5659->regmap, RT5659_GPIO_STA, &value);
4072 if (!(value & 0x8)) {
4073 rt5659->hda_hp_plugged = true;
4074 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1,
4075 0x10, 0x0);
4076 } else {
4077 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_1,
4078 0x10, 0x10);
4079 }
4080
4081 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
4082 RT5659_PWR_VREF2 | RT5659_PWR_MB,
4083 RT5659_PWR_VREF2 | RT5659_PWR_MB);
4084 msleep(20);
4085 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
4086 RT5659_PWR_FV2, RT5659_PWR_FV2);
4087
4088 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_3, RT5659_PWR_LDO2,
4089 RT5659_PWR_LDO2);
4090 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_2, RT5659_PWR_MB1,
4091 RT5659_PWR_MB1);
4092 regmap_update_bits(rt5659->regmap, RT5659_PWR_VOL, RT5659_PWR_MIC_DET,
4093 RT5659_PWR_MIC_DET);
4094 msleep(20);
4095
4096 regmap_update_bits(rt5659->regmap, RT5659_4BTN_IL_CMD_2,
4097 RT5659_4BTN_IL_MASK, RT5659_4BTN_IL_EN);
4098 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value);
4099 regmap_write(rt5659->regmap, RT5659_4BTN_IL_CMD_1, value);
4100 regmap_read(rt5659->regmap, RT5659_4BTN_IL_CMD_1, &value);
4101
4102 if (value & 0x2000) {
4103 rt5659->hda_mic_plugged = true;
4104 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
4105 0x2, 0x2);
4106 } else {
4107 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
4108 0x2, 0x0);
4109 }
4110
4111 regmap_update_bits(rt5659->regmap, RT5659_IRQ_CTRL_2,
4112 RT5659_IL_IRQ_MASK, RT5659_IL_IRQ_EN);
4113}
4114
d3cb2de2
BL		 4115static int rt5659_i2c_probe(struct i2c_client *i2c,
4116 const struct i2c_device_id *id)
4117{
4118 struct rt5659_platform_data *pdata = dev_get_platdata(&i2c->dev);
4119 struct rt5659_priv *rt5659;
4120 int ret;
4121 unsigned int val;
4122
4123 rt5659 = devm_kzalloc(&i2c->dev, sizeof(struct rt5659_priv),
4124 GFP_KERNEL);
4125
4126 if (rt5659 == NULL)
4127 return -ENOMEM;
4128
d3cb2de2
BL		 4129 i2c_set_clientdata(i2c, rt5659);
4130
4131 if (pdata)
4132 rt5659->pdata = *pdata;
4133 else
4134 rt5659_parse_dt(rt5659, &i2c->dev);
4135
4136 rt5659->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev, "ldo1-en",
4137 GPIOD_OUT_HIGH);
4138 if (IS_ERR(rt5659->gpiod_ldo1_en))
4139 dev_warn(&i2c->dev, "Request ldo1-en GPIO failed\n");
4140
4141 rt5659->gpiod_reset = devm_gpiod_get_optional(&i2c->dev, "reset",
4142 GPIOD_OUT_HIGH);
4143
4144 /* Sleep for 300 ms miniumum */
11b4ad96 4145 msleep(300);
d3cb2de2
BL		 4146
4147 rt5659->regmap = devm_regmap_init_i2c(i2c, &rt5659_regmap);
4148 if (IS_ERR(rt5659->regmap)) {
4149 ret = PTR_ERR(rt5659->regmap);
4150 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4151 ret);
4152 return ret;
4153 }
4154
4155 regmap_read(rt5659->regmap, RT5659_DEVICE_ID, &val);
4156 if (val != DEVICE_ID) {
4157 dev_err(&i2c->dev,
4158 "Device with ID register %x is not rt5659\n", val);
4159 return -ENODEV;
4160 }
4161
4162 regmap_write(rt5659->regmap, RT5659_RESET, 0);
4163
c6f8769b
NC		 4164 /* Check if MCLK provided */
4165 rt5659->mclk = devm_clk_get(&i2c->dev, "mclk");
4166 if (IS_ERR(rt5659->mclk)) {
4167 if (PTR_ERR(rt5659->mclk) != -ENOENT)
4168 return PTR_ERR(rt5659->mclk);
4169 /* Otherwise mark the mclk pointer to NULL */
4170 rt5659->mclk = NULL;
4171 }
4172
d3cb2de2
BL		 4173 rt5659_calibrate(rt5659);
4174
4175 /* line in diff mode*/
4176 if (rt5659->pdata.in1_diff)
4177 regmap_update_bits(rt5659->regmap, RT5659_IN1_IN2,
4178 RT5659_IN1_DF_MASK, RT5659_IN1_DF_MASK);
4179 if (rt5659->pdata.in3_diff)
4180 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4,
4181 RT5659_IN3_DF_MASK, RT5659_IN3_DF_MASK);
4182 if (rt5659->pdata.in4_diff)
4183 regmap_update_bits(rt5659->regmap, RT5659_IN3_IN4,
4184 RT5659_IN4_DF_MASK, RT5659_IN4_DF_MASK);
4185
4186 /* DMIC pin*/
4187 if (rt5659->pdata.dmic1_data_pin != RT5659_DMIC1_NULL ||
4188 rt5659->pdata.dmic2_data_pin != RT5659_DMIC2_NULL) {
4189 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4190 RT5659_GP2_PIN_MASK, RT5659_GP2_PIN_DMIC1_SCL);
4191
4192 switch (rt5659->pdata.dmic1_data_pin) {
4193 case RT5659_DMIC1_DATA_IN2N:
4194 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4195 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_IN2N);
4196 break;
4197
4198 case RT5659_DMIC1_DATA_GPIO5:
4199 regmap_update_bits(rt5659->regmap,
4200 RT5659_GPIO_CTRL_3,
4201 RT5659_I2S2_PIN_MASK,
4202 RT5659_I2S2_PIN_GPIO);
4203 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4204 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO5);
4205 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4206 RT5659_GP5_PIN_MASK, RT5659_GP5_PIN_DMIC1_SDA);
4207 break;
4208
4209 case RT5659_DMIC1_DATA_GPIO9:
4210 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4211 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO9);
4212 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4213 RT5659_GP9_PIN_MASK, RT5659_GP9_PIN_DMIC1_SDA);
4214 break;
4215
4216 case RT5659_DMIC1_DATA_GPIO11:
4217 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4218 RT5659_DMIC_1_DP_MASK, RT5659_DMIC_1_DP_GPIO11);
4219 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4220 RT5659_GP11_PIN_MASK,
4221 RT5659_GP11_PIN_DMIC1_SDA);
4222 break;
4223
4224 default:
4225 dev_dbg(&i2c->dev, "no DMIC1\n");
4226 break;
4227 }
4228
4229 switch (rt5659->pdata.dmic2_data_pin) {
4230 case RT5659_DMIC2_DATA_IN2P:
4231 regmap_update_bits(rt5659->regmap,
4232 RT5659_DMIC_CTRL_1,
4233 RT5659_DMIC_2_DP_MASK,
4234 RT5659_DMIC_2_DP_IN2P);
4235 break;
4236
4237 case RT5659_DMIC2_DATA_GPIO6:
4238 regmap_update_bits(rt5659->regmap,
4239 RT5659_DMIC_CTRL_1,
4240 RT5659_DMIC_2_DP_MASK,
4241 RT5659_DMIC_2_DP_GPIO6);
4242 regmap_update_bits(rt5659->regmap,
4243 RT5659_GPIO_CTRL_1,
4244 RT5659_GP6_PIN_MASK,
4245 RT5659_GP6_PIN_DMIC2_SDA);
4246 break;
4247
4248 case RT5659_DMIC2_DATA_GPIO10:
4249 regmap_update_bits(rt5659->regmap,
4250 RT5659_DMIC_CTRL_1,
4251 RT5659_DMIC_2_DP_MASK,
4252 RT5659_DMIC_2_DP_GPIO10);
4253 regmap_update_bits(rt5659->regmap,
4254 RT5659_GPIO_CTRL_1,
4255 RT5659_GP10_PIN_MASK,
4256 RT5659_GP10_PIN_DMIC2_SDA);
4257 break;
4258
4259 case RT5659_DMIC2_DATA_GPIO12:
4260 regmap_update_bits(rt5659->regmap,
4261 RT5659_DMIC_CTRL_1,
4262 RT5659_DMIC_2_DP_MASK,
4263 RT5659_DMIC_2_DP_GPIO12);
4264 regmap_update_bits(rt5659->regmap,
4265 RT5659_GPIO_CTRL_1,
4266 RT5659_GP12_PIN_MASK,
4267 RT5659_GP12_PIN_DMIC2_SDA);
4268 break;
4269
4270 default:
4271 dev_dbg(&i2c->dev, "no DMIC2\n");
4272 break;
4273
4274 }
4275 } else {
4276 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4277 RT5659_GP2_PIN_MASK | RT5659_GP5_PIN_MASK |
4278 RT5659_GP9_PIN_MASK | RT5659_GP11_PIN_MASK |
4279 RT5659_GP6_PIN_MASK | RT5659_GP10_PIN_MASK |
4280 RT5659_GP12_PIN_MASK,
4281 RT5659_GP2_PIN_GPIO2 | RT5659_GP5_PIN_GPIO5 |
4282 RT5659_GP9_PIN_GPIO9 | RT5659_GP11_PIN_GPIO11 |
4283 RT5659_GP6_PIN_GPIO6 | RT5659_GP10_PIN_GPIO10 |
4284 RT5659_GP12_PIN_GPIO12);
4285 regmap_update_bits(rt5659->regmap, RT5659_DMIC_CTRL_1,
4286 RT5659_DMIC_1_DP_MASK | RT5659_DMIC_2_DP_MASK,
4287 RT5659_DMIC_1_DP_IN2N | RT5659_DMIC_2_DP_IN2P);
4288 }
4289
4290 switch (rt5659->pdata.jd_src) {
4291 case RT5659_JD3:
4292 regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0xa880);
4293 regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x9000);
4294 regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_1, 0xc800);
4295 regmap_update_bits(rt5659->regmap, RT5659_PWR_ANLG_1,
4296 RT5659_PWR_MB, RT5659_PWR_MB);
4297 regmap_write(rt5659->regmap, RT5659_PWR_ANLG_2, 0x0001);
4298 regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_2, 0x0040);
041e74b7 4299 INIT_DELAYED_WORK(&rt5659->jack_detect_work,
4300 rt5659_jack_detect_work);
d3cb2de2 4301 break;
041e74b7 4302 case RT5659_JD_HDA_HEADER:
4303 regmap_write(rt5659->regmap, RT5659_GPIO_CTRL_3, 0x8000);
4304 regmap_write(rt5659->regmap, RT5659_RC_CLK_CTRL, 0x0900);
4305 regmap_write(rt5659->regmap, RT5659_EJD_CTRL_1, 0x70c0);
4306 regmap_write(rt5659->regmap, RT5659_JD_CTRL_1, 0x2000);
4307 regmap_write(rt5659->regmap, RT5659_IRQ_CTRL_1, 0x0040);
4308 INIT_DELAYED_WORK(&rt5659->jack_detect_work,
4309 rt5659_jack_detect_intel_hd_header);
4310 rt5659_intel_hd_header_probe_setup(rt5659);
d3cb2de2
BL		 4311 break;
4312 default:
d3cb2de2
BL		 4313 break;
4314 }
4315
1ca2cf8c
AL		 4316 if (i2c->irq) {
4317 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4318 rt5659_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
d3cb2de2
BL		 4319 | IRQF_ONESHOT, "rt5659", rt5659);
4320 if (ret)
4321 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4322
38d16f79
NC		 4323 /* Enable IRQ output for GPIO1 pin any way */
4324 regmap_update_bits(rt5659->regmap, RT5659_GPIO_CTRL_1,
4325 RT5659_GP1_PIN_MASK, RT5659_GP1_PIN_IRQ);
d3cb2de2
BL		 4326 }
4327
de86a332
KM		 4328 return devm_snd_soc_register_component(&i2c->dev,
4329 &soc_component_dev_rt5659,
d3cb2de2 4330 rt5659_dai, ARRAY_SIZE(rt5659_dai));
d3cb2de2
BL		 4331}
4332
c62db3d5 4333static void rt5659_i2c_shutdown(struct i2c_client *client)
d3cb2de2
BL		 4334{
4335 struct rt5659_priv *rt5659 = i2c_get_clientdata(client);
4336
4337 regmap_write(rt5659->regmap, RT5659_RESET, 0);
4338}
4339
2256b8d2 4340#ifdef CONFIG_OF
d3cb2de2
BL		 4341static const struct of_device_id rt5659_of_match[] = {
4342 { .compatible = "realtek,rt5658", },
4343 { .compatible = "realtek,rt5659", },
2256b8d2 4344 { },
d3cb2de2 4345};
2256b8d2
AB		 4346MODULE_DEVICE_TABLE(of, rt5659_of_match);
4347#endif
d3cb2de2 4348
2256b8d2 4349#ifdef CONFIG_ACPI
f36544a4 4350static const struct acpi_device_id rt5659_acpi_match[] = {
2256b8d2
AB		 4351 { "10EC5658", 0, },
4352 { "10EC5659", 0, },
4353 { },
d3cb2de2
BL		 4354};
4355MODULE_DEVICE_TABLE(acpi, rt5659_acpi_match);
2256b8d2 4356#endif
d3cb2de2 4357
0230f088 4358static struct i2c_driver rt5659_i2c_driver = {
d3cb2de2
BL		 4359 .driver = {
4360 .name = "rt5659",
2256b8d2 4361 .of_match_table = of_match_ptr(rt5659_of_match),
d3cb2de2
BL		 4362 .acpi_match_table = ACPI_PTR(rt5659_acpi_match),
4363 },
4364 .probe = rt5659_i2c_probe,
d3cb2de2
BL		 4365 .shutdown = rt5659_i2c_shutdown,
4366 .id_table = rt5659_i2c_id,
4367};
4368module_i2c_driver(rt5659_i2c_driver);
4369
4370MODULE_DESCRIPTION("ASoC RT5659 driver");
4371MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4372MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)