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1319b2f6 OC |
1 | /* |
2 | * rt5645.c -- RT5645 ALSA SoC audio codec driver | |
3 | * | |
4 | * Copyright 2013 Realtek Semiconductor Corp. | |
5 | * Author: Bard Liao <bardliao@realtek.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/moduleparam.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/spi/spi.h> | |
f3fa1bbd | 20 | #include <linux/gpio.h> |
baf2a0e1 | 21 | #include <linux/gpio/consumer.h> |
3168c201 | 22 | #include <linux/acpi.h> |
78c34fd4 | 23 | #include <linux/dmi.h> |
9fc114c5 | 24 | #include <linux/regulator/consumer.h> |
1319b2f6 OC |
25 | #include <sound/core.h> |
26 | #include <sound/pcm.h> | |
27 | #include <sound/pcm_params.h> | |
28 | #include <sound/jack.h> | |
29 | #include <sound/soc.h> | |
30 | #include <sound/soc-dapm.h> | |
31 | #include <sound/initval.h> | |
32 | #include <sound/tlv.h> | |
33 | ||
49ef7925 | 34 | #include "rl6231.h" |
1319b2f6 OC |
35 | #include "rt5645.h" |
36 | ||
37 | #define RT5645_DEVICE_ID 0x6308 | |
5c4ca99d | 38 | #define RT5650_DEVICE_ID 0x6419 |
1319b2f6 OC |
39 | |
40 | #define RT5645_PR_RANGE_BASE (0xff + 1) | |
41 | #define RT5645_PR_SPACING 0x100 | |
42 | ||
43 | #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING)) | |
44 | ||
be77b38a OC |
45 | #define RT5645_HWEQ_NUM 57 |
46 | ||
1319b2f6 OC |
47 | static const struct regmap_range_cfg rt5645_ranges[] = { |
48 | { | |
49 | .name = "PR", | |
50 | .range_min = RT5645_PR_BASE, | |
51 | .range_max = RT5645_PR_BASE + 0xf8, | |
52 | .selector_reg = RT5645_PRIV_INDEX, | |
53 | .selector_mask = 0xff, | |
54 | .selector_shift = 0x0, | |
55 | .window_start = RT5645_PRIV_DATA, | |
56 | .window_len = 0x1, | |
57 | }, | |
58 | }; | |
59 | ||
8019ff6c | 60 | static const struct reg_sequence init_list[] = { |
1319b2f6 | 61 | {RT5645_PR_BASE + 0x3d, 0x3600}, |
4809b96e OC |
62 | {RT5645_PR_BASE + 0x1c, 0xfd20}, |
63 | {RT5645_PR_BASE + 0x20, 0x611f}, | |
64 | {RT5645_PR_BASE + 0x21, 0x4040}, | |
65 | {RT5645_PR_BASE + 0x23, 0x0004}, | |
1319b2f6 | 66 | }; |
1319b2f6 | 67 | |
8019ff6c | 68 | static const struct reg_sequence rt5650_init_list[] = { |
5c4ca99d BL |
69 | {0xf6, 0x0100}, |
70 | }; | |
71 | ||
1319b2f6 OC |
72 | static const struct reg_default rt5645_reg[] = { |
73 | { 0x00, 0x0000 }, | |
74 | { 0x01, 0xc8c8 }, | |
75 | { 0x02, 0xc8c8 }, | |
76 | { 0x03, 0xc8c8 }, | |
77 | { 0x0a, 0x0002 }, | |
78 | { 0x0b, 0x2827 }, | |
79 | { 0x0c, 0xe000 }, | |
80 | { 0x0d, 0x0000 }, | |
81 | { 0x0e, 0x0000 }, | |
82 | { 0x0f, 0x0808 }, | |
83 | { 0x14, 0x3333 }, | |
84 | { 0x16, 0x4b00 }, | |
85 | { 0x18, 0x018b }, | |
86 | { 0x19, 0xafaf }, | |
87 | { 0x1a, 0xafaf }, | |
88 | { 0x1b, 0x0001 }, | |
89 | { 0x1c, 0x2f2f }, | |
90 | { 0x1d, 0x2f2f }, | |
91 | { 0x1e, 0x0000 }, | |
92 | { 0x20, 0x0000 }, | |
93 | { 0x27, 0x7060 }, | |
94 | { 0x28, 0x7070 }, | |
95 | { 0x29, 0x8080 }, | |
96 | { 0x2a, 0x5656 }, | |
97 | { 0x2b, 0x5454 }, | |
98 | { 0x2c, 0xaaa0 }, | |
5c4ca99d | 99 | { 0x2d, 0x0000 }, |
1319b2f6 OC |
100 | { 0x2f, 0x1002 }, |
101 | { 0x31, 0x5000 }, | |
102 | { 0x32, 0x0000 }, | |
103 | { 0x33, 0x0000 }, | |
104 | { 0x34, 0x0000 }, | |
105 | { 0x35, 0x0000 }, | |
106 | { 0x3b, 0x0000 }, | |
107 | { 0x3c, 0x007f }, | |
108 | { 0x3d, 0x0000 }, | |
109 | { 0x3e, 0x007f }, | |
110 | { 0x3f, 0x0000 }, | |
111 | { 0x40, 0x001f }, | |
112 | { 0x41, 0x0000 }, | |
113 | { 0x42, 0x001f }, | |
114 | { 0x45, 0x6000 }, | |
115 | { 0x46, 0x003e }, | |
116 | { 0x47, 0x003e }, | |
117 | { 0x48, 0xf807 }, | |
118 | { 0x4a, 0x0004 }, | |
119 | { 0x4d, 0x0000 }, | |
120 | { 0x4e, 0x0000 }, | |
121 | { 0x4f, 0x01ff }, | |
122 | { 0x50, 0x0000 }, | |
123 | { 0x51, 0x0000 }, | |
124 | { 0x52, 0x01ff }, | |
125 | { 0x53, 0xf000 }, | |
126 | { 0x56, 0x0111 }, | |
127 | { 0x57, 0x0064 }, | |
128 | { 0x58, 0xef0e }, | |
129 | { 0x59, 0xf0f0 }, | |
130 | { 0x5a, 0xef0e }, | |
131 | { 0x5b, 0xf0f0 }, | |
132 | { 0x5c, 0xef0e }, | |
133 | { 0x5d, 0xf0f0 }, | |
134 | { 0x5e, 0xf000 }, | |
135 | { 0x5f, 0x0000 }, | |
136 | { 0x61, 0x0300 }, | |
137 | { 0x62, 0x0000 }, | |
138 | { 0x63, 0x00c2 }, | |
139 | { 0x64, 0x0000 }, | |
140 | { 0x65, 0x0000 }, | |
141 | { 0x66, 0x0000 }, | |
142 | { 0x6a, 0x0000 }, | |
143 | { 0x6c, 0x0aaa }, | |
144 | { 0x70, 0x8000 }, | |
145 | { 0x71, 0x8000 }, | |
146 | { 0x72, 0x8000 }, | |
147 | { 0x73, 0x7770 }, | |
148 | { 0x74, 0x3e00 }, | |
149 | { 0x75, 0x2409 }, | |
150 | { 0x76, 0x000a }, | |
151 | { 0x77, 0x0c00 }, | |
152 | { 0x78, 0x0000 }, | |
df078d29 | 153 | { 0x79, 0x0123 }, |
1319b2f6 OC |
154 | { 0x80, 0x0000 }, |
155 | { 0x81, 0x0000 }, | |
156 | { 0x82, 0x0000 }, | |
157 | { 0x83, 0x0000 }, | |
158 | { 0x84, 0x0000 }, | |
159 | { 0x85, 0x0000 }, | |
160 | { 0x8a, 0x0000 }, | |
161 | { 0x8e, 0x0004 }, | |
162 | { 0x8f, 0x1100 }, | |
163 | { 0x90, 0x0646 }, | |
164 | { 0x91, 0x0c06 }, | |
165 | { 0x93, 0x0000 }, | |
166 | { 0x94, 0x0200 }, | |
167 | { 0x95, 0x0000 }, | |
168 | { 0x9a, 0x2184 }, | |
169 | { 0x9b, 0x010a }, | |
170 | { 0x9c, 0x0aea }, | |
171 | { 0x9d, 0x000c }, | |
172 | { 0x9e, 0x0400 }, | |
173 | { 0xa0, 0xa0a8 }, | |
174 | { 0xa1, 0x0059 }, | |
175 | { 0xa2, 0x0001 }, | |
176 | { 0xae, 0x6000 }, | |
177 | { 0xaf, 0x0000 }, | |
178 | { 0xb0, 0x6000 }, | |
179 | { 0xb1, 0x0000 }, | |
180 | { 0xb2, 0x0000 }, | |
181 | { 0xb3, 0x001f }, | |
182 | { 0xb4, 0x020c }, | |
183 | { 0xb5, 0x1f00 }, | |
184 | { 0xb6, 0x0000 }, | |
185 | { 0xbb, 0x0000 }, | |
186 | { 0xbc, 0x0000 }, | |
187 | { 0xbd, 0x0000 }, | |
188 | { 0xbe, 0x0000 }, | |
189 | { 0xbf, 0x3100 }, | |
190 | { 0xc0, 0x0000 }, | |
191 | { 0xc1, 0x0000 }, | |
192 | { 0xc2, 0x0000 }, | |
193 | { 0xc3, 0x2000 }, | |
194 | { 0xcd, 0x0000 }, | |
195 | { 0xce, 0x0000 }, | |
196 | { 0xcf, 0x1813 }, | |
197 | { 0xd0, 0x0690 }, | |
198 | { 0xd1, 0x1c17 }, | |
199 | { 0xd3, 0xb320 }, | |
200 | { 0xd4, 0x0000 }, | |
201 | { 0xd6, 0x0400 }, | |
202 | { 0xd9, 0x0809 }, | |
203 | { 0xda, 0x0000 }, | |
204 | { 0xdb, 0x0003 }, | |
205 | { 0xdc, 0x0049 }, | |
206 | { 0xdd, 0x001b }, | |
5c4ca99d BL |
207 | { 0xdf, 0x0008 }, |
208 | { 0xe0, 0x4000 }, | |
1319b2f6 OC |
209 | { 0xe6, 0x8000 }, |
210 | { 0xe7, 0x0200 }, | |
211 | { 0xec, 0xb300 }, | |
212 | { 0xed, 0x0000 }, | |
213 | { 0xf0, 0x001f }, | |
214 | { 0xf1, 0x020c }, | |
215 | { 0xf2, 0x1f00 }, | |
216 | { 0xf3, 0x0000 }, | |
217 | { 0xf4, 0x4000 }, | |
218 | { 0xf8, 0x0000 }, | |
219 | { 0xf9, 0x0000 }, | |
220 | { 0xfa, 0x2060 }, | |
221 | { 0xfb, 0x4040 }, | |
222 | { 0xfc, 0x0000 }, | |
223 | { 0xfd, 0x0002 }, | |
224 | { 0xfe, 0x10ec }, | |
225 | { 0xff, 0x6308 }, | |
226 | }; | |
227 | ||
49abc6cd BL |
228 | static const struct reg_default rt5650_reg[] = { |
229 | { 0x00, 0x0000 }, | |
230 | { 0x01, 0xc8c8 }, | |
231 | { 0x02, 0xc8c8 }, | |
232 | { 0x03, 0xc8c8 }, | |
233 | { 0x0a, 0x0002 }, | |
234 | { 0x0b, 0x2827 }, | |
235 | { 0x0c, 0xe000 }, | |
236 | { 0x0d, 0x0000 }, | |
237 | { 0x0e, 0x0000 }, | |
238 | { 0x0f, 0x0808 }, | |
239 | { 0x14, 0x3333 }, | |
240 | { 0x16, 0x4b00 }, | |
241 | { 0x18, 0x018b }, | |
242 | { 0x19, 0xafaf }, | |
243 | { 0x1a, 0xafaf }, | |
244 | { 0x1b, 0x0001 }, | |
245 | { 0x1c, 0x2f2f }, | |
246 | { 0x1d, 0x2f2f }, | |
247 | { 0x1e, 0x0000 }, | |
248 | { 0x20, 0x0000 }, | |
249 | { 0x27, 0x7060 }, | |
250 | { 0x28, 0x7070 }, | |
251 | { 0x29, 0x8080 }, | |
252 | { 0x2a, 0x5656 }, | |
253 | { 0x2b, 0x5454 }, | |
254 | { 0x2c, 0xaaa0 }, | |
255 | { 0x2d, 0x0000 }, | |
256 | { 0x2f, 0x1002 }, | |
257 | { 0x31, 0x5000 }, | |
258 | { 0x32, 0x0000 }, | |
259 | { 0x33, 0x0000 }, | |
260 | { 0x34, 0x0000 }, | |
261 | { 0x35, 0x0000 }, | |
262 | { 0x3b, 0x0000 }, | |
263 | { 0x3c, 0x007f }, | |
264 | { 0x3d, 0x0000 }, | |
265 | { 0x3e, 0x007f }, | |
266 | { 0x3f, 0x0000 }, | |
267 | { 0x40, 0x001f }, | |
268 | { 0x41, 0x0000 }, | |
269 | { 0x42, 0x001f }, | |
270 | { 0x45, 0x6000 }, | |
271 | { 0x46, 0x003e }, | |
272 | { 0x47, 0x003e }, | |
273 | { 0x48, 0xf807 }, | |
274 | { 0x4a, 0x0004 }, | |
275 | { 0x4d, 0x0000 }, | |
276 | { 0x4e, 0x0000 }, | |
277 | { 0x4f, 0x01ff }, | |
278 | { 0x50, 0x0000 }, | |
279 | { 0x51, 0x0000 }, | |
280 | { 0x52, 0x01ff }, | |
281 | { 0x53, 0xf000 }, | |
282 | { 0x56, 0x0111 }, | |
283 | { 0x57, 0x0064 }, | |
284 | { 0x58, 0xef0e }, | |
285 | { 0x59, 0xf0f0 }, | |
286 | { 0x5a, 0xef0e }, | |
287 | { 0x5b, 0xf0f0 }, | |
288 | { 0x5c, 0xef0e }, | |
289 | { 0x5d, 0xf0f0 }, | |
290 | { 0x5e, 0xf000 }, | |
291 | { 0x5f, 0x0000 }, | |
292 | { 0x61, 0x0300 }, | |
293 | { 0x62, 0x0000 }, | |
294 | { 0x63, 0x00c2 }, | |
295 | { 0x64, 0x0000 }, | |
296 | { 0x65, 0x0000 }, | |
297 | { 0x66, 0x0000 }, | |
298 | { 0x6a, 0x0000 }, | |
299 | { 0x6c, 0x0aaa }, | |
300 | { 0x70, 0x8000 }, | |
301 | { 0x71, 0x8000 }, | |
302 | { 0x72, 0x8000 }, | |
303 | { 0x73, 0x7770 }, | |
304 | { 0x74, 0x3e00 }, | |
305 | { 0x75, 0x2409 }, | |
306 | { 0x76, 0x000a }, | |
307 | { 0x77, 0x0c00 }, | |
308 | { 0x78, 0x0000 }, | |
309 | { 0x79, 0x0123 }, | |
310 | { 0x7a, 0x0123 }, | |
311 | { 0x80, 0x0000 }, | |
312 | { 0x81, 0x0000 }, | |
313 | { 0x82, 0x0000 }, | |
314 | { 0x83, 0x0000 }, | |
315 | { 0x84, 0x0000 }, | |
316 | { 0x85, 0x0000 }, | |
317 | { 0x8a, 0x0000 }, | |
318 | { 0x8e, 0x0004 }, | |
319 | { 0x8f, 0x1100 }, | |
320 | { 0x90, 0x0646 }, | |
321 | { 0x91, 0x0c06 }, | |
322 | { 0x93, 0x0000 }, | |
323 | { 0x94, 0x0200 }, | |
324 | { 0x95, 0x0000 }, | |
325 | { 0x9a, 0x2184 }, | |
326 | { 0x9b, 0x010a }, | |
327 | { 0x9c, 0x0aea }, | |
328 | { 0x9d, 0x000c }, | |
329 | { 0x9e, 0x0400 }, | |
330 | { 0xa0, 0xa0a8 }, | |
331 | { 0xa1, 0x0059 }, | |
332 | { 0xa2, 0x0001 }, | |
333 | { 0xae, 0x6000 }, | |
334 | { 0xaf, 0x0000 }, | |
335 | { 0xb0, 0x6000 }, | |
336 | { 0xb1, 0x0000 }, | |
337 | { 0xb2, 0x0000 }, | |
338 | { 0xb3, 0x001f }, | |
339 | { 0xb4, 0x020c }, | |
340 | { 0xb5, 0x1f00 }, | |
341 | { 0xb6, 0x0000 }, | |
342 | { 0xbb, 0x0000 }, | |
343 | { 0xbc, 0x0000 }, | |
344 | { 0xbd, 0x0000 }, | |
345 | { 0xbe, 0x0000 }, | |
346 | { 0xbf, 0x3100 }, | |
347 | { 0xc0, 0x0000 }, | |
348 | { 0xc1, 0x0000 }, | |
349 | { 0xc2, 0x0000 }, | |
350 | { 0xc3, 0x2000 }, | |
351 | { 0xcd, 0x0000 }, | |
352 | { 0xce, 0x0000 }, | |
353 | { 0xcf, 0x1813 }, | |
354 | { 0xd0, 0x0690 }, | |
355 | { 0xd1, 0x1c17 }, | |
356 | { 0xd3, 0xb320 }, | |
357 | { 0xd4, 0x0000 }, | |
358 | { 0xd6, 0x0400 }, | |
359 | { 0xd9, 0x0809 }, | |
360 | { 0xda, 0x0000 }, | |
361 | { 0xdb, 0x0003 }, | |
362 | { 0xdc, 0x0049 }, | |
363 | { 0xdd, 0x001b }, | |
364 | { 0xdf, 0x0008 }, | |
365 | { 0xe0, 0x4000 }, | |
366 | { 0xe6, 0x8000 }, | |
367 | { 0xe7, 0x0200 }, | |
368 | { 0xec, 0xb300 }, | |
369 | { 0xed, 0x0000 }, | |
370 | { 0xf0, 0x001f }, | |
371 | { 0xf1, 0x020c }, | |
372 | { 0xf2, 0x1f00 }, | |
373 | { 0xf3, 0x0000 }, | |
374 | { 0xf4, 0x4000 }, | |
375 | { 0xf8, 0x0000 }, | |
376 | { 0xf9, 0x0000 }, | |
377 | { 0xfa, 0x2060 }, | |
378 | { 0xfb, 0x4040 }, | |
379 | { 0xfc, 0x0000 }, | |
380 | { 0xfd, 0x0002 }, | |
381 | { 0xfe, 0x10ec }, | |
382 | { 0xff, 0x6308 }, | |
383 | }; | |
384 | ||
be77b38a OC |
385 | struct rt5645_eq_param_s { |
386 | unsigned short reg; | |
387 | unsigned short val; | |
388 | }; | |
389 | ||
9fc114c5 KC |
390 | static const char *const rt5645_supply_names[] = { |
391 | "avdd", | |
392 | "cpvdd", | |
393 | }; | |
394 | ||
395 | struct rt5645_priv { | |
396 | struct snd_soc_codec *codec; | |
397 | struct rt5645_platform_data pdata; | |
398 | struct regmap *regmap; | |
399 | struct i2c_client *i2c; | |
400 | struct gpio_desc *gpiod_hp_det; | |
401 | struct snd_soc_jack *hp_jack; | |
402 | struct snd_soc_jack *mic_jack; | |
403 | struct snd_soc_jack *btn_jack; | |
7099ee85 | 404 | struct delayed_work jack_detect_work, rcclock_work; |
9fc114c5 | 405 | struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)]; |
be77b38a | 406 | struct rt5645_eq_param_s *eq_param; |
7ff6319e | 407 | struct timer_list btn_check_timer; |
9fc114c5 KC |
408 | |
409 | int codec_type; | |
410 | int sysclk; | |
411 | int sysclk_src; | |
412 | int lrck[RT5645_AIFS]; | |
413 | int bclk[RT5645_AIFS]; | |
414 | int master[RT5645_AIFS]; | |
415 | ||
416 | int pll_src; | |
417 | int pll_in; | |
418 | int pll_out; | |
419 | ||
420 | int jack_type; | |
421 | bool en_button_func; | |
588cd850 | 422 | bool hp_on; |
9fc114c5 KC |
423 | }; |
424 | ||
1319b2f6 OC |
425 | static int rt5645_reset(struct snd_soc_codec *codec) |
426 | { | |
427 | return snd_soc_write(codec, RT5645_RESET, 0); | |
428 | } | |
429 | ||
430 | static bool rt5645_volatile_register(struct device *dev, unsigned int reg) | |
431 | { | |
432 | int i; | |
433 | ||
434 | for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { | |
435 | if (reg >= rt5645_ranges[i].range_min && | |
436 | reg <= rt5645_ranges[i].range_max) { | |
437 | return true; | |
438 | } | |
439 | } | |
440 | ||
441 | switch (reg) { | |
442 | case RT5645_RESET: | |
443 | case RT5645_PRIV_DATA: | |
444 | case RT5645_IN1_CTRL1: | |
445 | case RT5645_IN1_CTRL2: | |
446 | case RT5645_IN1_CTRL3: | |
447 | case RT5645_A_JD_CTRL1: | |
448 | case RT5645_ADC_EQ_CTRL1: | |
449 | case RT5645_EQ_CTRL1: | |
450 | case RT5645_ALC_CTRL_1: | |
451 | case RT5645_IRQ_CTRL2: | |
452 | case RT5645_IRQ_CTRL3: | |
453 | case RT5645_INT_IRQ_ST: | |
454 | case RT5645_IL_CMD: | |
5c4ca99d | 455 | case RT5650_4BTN_IL_CMD1: |
1319b2f6 OC |
456 | case RT5645_VENDOR_ID: |
457 | case RT5645_VENDOR_ID1: | |
458 | case RT5645_VENDOR_ID2: | |
71bfa9b4 | 459 | return true; |
1319b2f6 | 460 | default: |
71bfa9b4 | 461 | return false; |
1319b2f6 OC |
462 | } |
463 | } | |
464 | ||
465 | static bool rt5645_readable_register(struct device *dev, unsigned int reg) | |
466 | { | |
467 | int i; | |
468 | ||
469 | for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) { | |
470 | if (reg >= rt5645_ranges[i].range_min && | |
471 | reg <= rt5645_ranges[i].range_max) { | |
472 | return true; | |
473 | } | |
474 | } | |
475 | ||
476 | switch (reg) { | |
477 | case RT5645_RESET: | |
478 | case RT5645_SPK_VOL: | |
479 | case RT5645_HP_VOL: | |
480 | case RT5645_LOUT1: | |
481 | case RT5645_IN1_CTRL1: | |
482 | case RT5645_IN1_CTRL2: | |
483 | case RT5645_IN1_CTRL3: | |
484 | case RT5645_IN2_CTRL: | |
485 | case RT5645_INL1_INR1_VOL: | |
486 | case RT5645_SPK_FUNC_LIM: | |
487 | case RT5645_ADJ_HPF_CTRL: | |
488 | case RT5645_DAC1_DIG_VOL: | |
489 | case RT5645_DAC2_DIG_VOL: | |
490 | case RT5645_DAC_CTRL: | |
491 | case RT5645_STO1_ADC_DIG_VOL: | |
492 | case RT5645_MONO_ADC_DIG_VOL: | |
493 | case RT5645_ADC_BST_VOL1: | |
494 | case RT5645_ADC_BST_VOL2: | |
495 | case RT5645_STO1_ADC_MIXER: | |
496 | case RT5645_MONO_ADC_MIXER: | |
497 | case RT5645_AD_DA_MIXER: | |
498 | case RT5645_STO_DAC_MIXER: | |
499 | case RT5645_MONO_DAC_MIXER: | |
500 | case RT5645_DIG_MIXER: | |
5c4ca99d | 501 | case RT5650_A_DAC_SOUR: |
1319b2f6 OC |
502 | case RT5645_DIG_INF1_DATA: |
503 | case RT5645_PDM_OUT_CTRL: | |
504 | case RT5645_REC_L1_MIXER: | |
505 | case RT5645_REC_L2_MIXER: | |
506 | case RT5645_REC_R1_MIXER: | |
507 | case RT5645_REC_R2_MIXER: | |
508 | case RT5645_HPMIXL_CTRL: | |
509 | case RT5645_HPOMIXL_CTRL: | |
510 | case RT5645_HPMIXR_CTRL: | |
511 | case RT5645_HPOMIXR_CTRL: | |
512 | case RT5645_HPO_MIXER: | |
513 | case RT5645_SPK_L_MIXER: | |
514 | case RT5645_SPK_R_MIXER: | |
515 | case RT5645_SPO_MIXER: | |
516 | case RT5645_SPO_CLSD_RATIO: | |
517 | case RT5645_OUT_L1_MIXER: | |
518 | case RT5645_OUT_R1_MIXER: | |
519 | case RT5645_OUT_L_GAIN1: | |
520 | case RT5645_OUT_L_GAIN2: | |
521 | case RT5645_OUT_R_GAIN1: | |
522 | case RT5645_OUT_R_GAIN2: | |
523 | case RT5645_LOUT_MIXER: | |
524 | case RT5645_HAPTIC_CTRL1: | |
525 | case RT5645_HAPTIC_CTRL2: | |
526 | case RT5645_HAPTIC_CTRL3: | |
527 | case RT5645_HAPTIC_CTRL4: | |
528 | case RT5645_HAPTIC_CTRL5: | |
529 | case RT5645_HAPTIC_CTRL6: | |
530 | case RT5645_HAPTIC_CTRL7: | |
531 | case RT5645_HAPTIC_CTRL8: | |
532 | case RT5645_HAPTIC_CTRL9: | |
533 | case RT5645_HAPTIC_CTRL10: | |
534 | case RT5645_PWR_DIG1: | |
535 | case RT5645_PWR_DIG2: | |
536 | case RT5645_PWR_ANLG1: | |
537 | case RT5645_PWR_ANLG2: | |
538 | case RT5645_PWR_MIXER: | |
539 | case RT5645_PWR_VOL: | |
540 | case RT5645_PRIV_INDEX: | |
541 | case RT5645_PRIV_DATA: | |
542 | case RT5645_I2S1_SDP: | |
543 | case RT5645_I2S2_SDP: | |
544 | case RT5645_ADDA_CLK1: | |
545 | case RT5645_ADDA_CLK2: | |
546 | case RT5645_DMIC_CTRL1: | |
547 | case RT5645_DMIC_CTRL2: | |
548 | case RT5645_TDM_CTRL_1: | |
549 | case RT5645_TDM_CTRL_2: | |
df078d29 | 550 | case RT5645_TDM_CTRL_3: |
1fcb76db | 551 | case RT5650_TDM_CTRL_4: |
1319b2f6 OC |
552 | case RT5645_GLB_CLK: |
553 | case RT5645_PLL_CTRL1: | |
554 | case RT5645_PLL_CTRL2: | |
555 | case RT5645_ASRC_1: | |
556 | case RT5645_ASRC_2: | |
557 | case RT5645_ASRC_3: | |
558 | case RT5645_ASRC_4: | |
559 | case RT5645_DEPOP_M1: | |
560 | case RT5645_DEPOP_M2: | |
561 | case RT5645_DEPOP_M3: | |
b1d42598 | 562 | case RT5645_CHARGE_PUMP: |
1319b2f6 OC |
563 | case RT5645_MICBIAS: |
564 | case RT5645_A_JD_CTRL1: | |
565 | case RT5645_VAD_CTRL4: | |
566 | case RT5645_CLSD_OUT_CTRL: | |
567 | case RT5645_ADC_EQ_CTRL1: | |
568 | case RT5645_ADC_EQ_CTRL2: | |
569 | case RT5645_EQ_CTRL1: | |
570 | case RT5645_EQ_CTRL2: | |
571 | case RT5645_ALC_CTRL_1: | |
572 | case RT5645_ALC_CTRL_2: | |
573 | case RT5645_ALC_CTRL_3: | |
574 | case RT5645_ALC_CTRL_4: | |
575 | case RT5645_ALC_CTRL_5: | |
576 | case RT5645_JD_CTRL: | |
577 | case RT5645_IRQ_CTRL1: | |
578 | case RT5645_IRQ_CTRL2: | |
579 | case RT5645_IRQ_CTRL3: | |
580 | case RT5645_INT_IRQ_ST: | |
581 | case RT5645_GPIO_CTRL1: | |
582 | case RT5645_GPIO_CTRL2: | |
583 | case RT5645_GPIO_CTRL3: | |
584 | case RT5645_BASS_BACK: | |
585 | case RT5645_MP3_PLUS1: | |
586 | case RT5645_MP3_PLUS2: | |
587 | case RT5645_ADJ_HPF1: | |
588 | case RT5645_ADJ_HPF2: | |
589 | case RT5645_HP_CALIB_AMP_DET: | |
590 | case RT5645_SV_ZCD1: | |
591 | case RT5645_SV_ZCD2: | |
592 | case RT5645_IL_CMD: | |
593 | case RT5645_IL_CMD2: | |
594 | case RT5645_IL_CMD3: | |
5c4ca99d BL |
595 | case RT5650_4BTN_IL_CMD1: |
596 | case RT5650_4BTN_IL_CMD2: | |
1319b2f6 OC |
597 | case RT5645_DRC1_HL_CTRL1: |
598 | case RT5645_DRC2_HL_CTRL1: | |
599 | case RT5645_ADC_MONO_HP_CTRL1: | |
600 | case RT5645_ADC_MONO_HP_CTRL2: | |
601 | case RT5645_DRC2_CTRL1: | |
602 | case RT5645_DRC2_CTRL2: | |
603 | case RT5645_DRC2_CTRL3: | |
604 | case RT5645_DRC2_CTRL4: | |
605 | case RT5645_DRC2_CTRL5: | |
606 | case RT5645_JD_CTRL3: | |
607 | case RT5645_JD_CTRL4: | |
608 | case RT5645_GEN_CTRL1: | |
609 | case RT5645_GEN_CTRL2: | |
610 | case RT5645_GEN_CTRL3: | |
611 | case RT5645_VENDOR_ID: | |
612 | case RT5645_VENDOR_ID1: | |
613 | case RT5645_VENDOR_ID2: | |
71bfa9b4 | 614 | return true; |
1319b2f6 | 615 | default: |
71bfa9b4 | 616 | return false; |
1319b2f6 OC |
617 | } |
618 | } | |
619 | ||
620 | static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0); | |
177e1e1f | 621 | static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); |
1319b2f6 | 622 | static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0); |
177e1e1f | 623 | static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); |
1319b2f6 OC |
624 | static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0); |
625 | ||
626 | /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */ | |
6d698a83 | 627 | static const DECLARE_TLV_DB_RANGE(bst_tlv, |
1319b2f6 OC |
628 | 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0), |
629 | 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0), | |
630 | 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0), | |
631 | 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0), | |
632 | 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0), | |
633 | 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0), | |
6d698a83 LPC |
634 | 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0) |
635 | ); | |
1319b2f6 | 636 | |
e29fd55d OC |
637 | /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */ |
638 | static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv, | |
639 | 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0), | |
640 | 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0), | |
641 | 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0), | |
642 | 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0) | |
643 | ); | |
644 | ||
be77b38a OC |
645 | static int rt5645_hweq_info(struct snd_kcontrol *kcontrol, |
646 | struct snd_ctl_elem_info *uinfo) | |
647 | { | |
648 | uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; | |
649 | uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s); | |
650 | ||
651 | return 0; | |
652 | } | |
653 | ||
654 | static int rt5645_hweq_get(struct snd_kcontrol *kcontrol, | |
655 | struct snd_ctl_elem_value *ucontrol) | |
656 | { | |
657 | struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); | |
658 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); | |
659 | struct rt5645_eq_param_s *eq_param = | |
660 | (struct rt5645_eq_param_s *)ucontrol->value.bytes.data; | |
661 | int i; | |
662 | ||
663 | for (i = 0; i < RT5645_HWEQ_NUM; i++) { | |
664 | eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg); | |
665 | eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val); | |
666 | } | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
671 | static bool rt5645_validate_hweq(unsigned short reg) | |
672 | { | |
673 | if ((reg >= 0x1a4 && reg <= 0x1cd) | (reg >= 0x1e5 && reg <= 0x1f8) | | |
674 | (reg == RT5645_EQ_CTRL2)) | |
675 | return true; | |
676 | ||
677 | return false; | |
678 | } | |
679 | ||
680 | static int rt5645_hweq_put(struct snd_kcontrol *kcontrol, | |
681 | struct snd_ctl_elem_value *ucontrol) | |
682 | { | |
683 | struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); | |
684 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); | |
685 | struct rt5645_eq_param_s *eq_param = | |
686 | (struct rt5645_eq_param_s *)ucontrol->value.bytes.data; | |
687 | int i; | |
688 | ||
689 | for (i = 0; i < RT5645_HWEQ_NUM; i++) { | |
690 | eq_param[i].reg = be16_to_cpu(eq_param[i].reg); | |
691 | eq_param[i].val = be16_to_cpu(eq_param[i].val); | |
692 | } | |
693 | ||
694 | /* The final setting of the table should be RT5645_EQ_CTRL2 */ | |
695 | for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) { | |
696 | if (eq_param[i].reg == 0) | |
697 | continue; | |
698 | else if (eq_param[i].reg != RT5645_EQ_CTRL2) | |
699 | return 0; | |
700 | else | |
701 | break; | |
702 | } | |
703 | ||
704 | for (i = 0; i < RT5645_HWEQ_NUM; i++) { | |
705 | if (!rt5645_validate_hweq(eq_param[i].reg) && | |
706 | eq_param[i].reg != 0) | |
707 | return 0; | |
708 | else if (eq_param[i].reg == 0) | |
709 | break; | |
710 | } | |
711 | ||
712 | memcpy(rt5645->eq_param, eq_param, | |
713 | RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s)); | |
714 | ||
715 | return 0; | |
716 | } | |
717 | ||
718 | #define RT5645_HWEQ(xname) \ | |
719 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
720 | .info = rt5645_hweq_info, \ | |
721 | .get = rt5645_hweq_get, \ | |
722 | .put = rt5645_hweq_put \ | |
723 | } | |
724 | ||
7099ee85 OC |
725 | static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol, |
726 | struct snd_ctl_elem_value *ucontrol) | |
727 | { | |
728 | struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); | |
729 | struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component); | |
730 | int ret; | |
731 | ||
7099ee85 OC |
732 | regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, |
733 | RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU); | |
734 | ||
735 | ret = snd_soc_put_volsw(kcontrol, ucontrol); | |
736 | ||
6e5b143c | 737 | mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work, |
7099ee85 OC |
738 | msecs_to_jiffies(200)); |
739 | ||
740 | return ret; | |
741 | } | |
742 | ||
1319b2f6 OC |
743 | static const struct snd_kcontrol_new rt5645_snd_controls[] = { |
744 | /* Speaker Output Volume */ | |
745 | SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL, | |
746 | RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), | |
7099ee85 OC |
747 | SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL, |
748 | RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw, | |
749 | rt5645_spk_put_volsw, out_vol_tlv), | |
1319b2f6 | 750 | |
e29fd55d OC |
751 | /* ClassD modulator Speaker Gain Ratio */ |
752 | SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO, | |
753 | RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv), | |
754 | ||
1319b2f6 | 755 | /* Headphone Output Volume */ |
692768c4 | 756 | SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL, |
1319b2f6 | 757 | RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), |
692768c4 | 758 | SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL, |
1319b2f6 OC |
759 | RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), |
760 | ||
761 | /* OUTPUT Control */ | |
762 | SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1, | |
763 | RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), | |
764 | SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1, | |
765 | RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1), | |
766 | SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1, | |
767 | RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv), | |
768 | ||
769 | /* DAC Digital Volume */ | |
770 | SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL, | |
771 | RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1), | |
772 | SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL, | |
177e1e1f | 773 | RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), |
1319b2f6 | 774 | SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL, |
177e1e1f | 775 | RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv), |
1319b2f6 OC |
776 | |
777 | /* IN1/IN2 Control */ | |
778 | SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1, | |
b28785fa | 779 | RT5645_BST_SFT1, 12, 0, bst_tlv), |
1319b2f6 OC |
780 | SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL, |
781 | RT5645_BST_SFT2, 8, 0, bst_tlv), | |
782 | ||
783 | /* INL/INR Volume Control */ | |
784 | SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL, | |
785 | RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv), | |
786 | ||
787 | /* ADC Digital Volume Control */ | |
788 | SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL, | |
789 | RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), | |
790 | SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL, | |
177e1e1f | 791 | RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), |
1319b2f6 OC |
792 | SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL, |
793 | RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1), | |
794 | SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL, | |
177e1e1f | 795 | RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv), |
1319b2f6 OC |
796 | |
797 | /* ADC Boost Volume Control */ | |
8c1a9d63 | 798 | SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1, |
1319b2f6 OC |
799 | RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0, |
800 | adc_bst_tlv), | |
8c1a9d63 OC |
801 | SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2, |
802 | RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0, | |
1319b2f6 OC |
803 | adc_bst_tlv), |
804 | ||
805 | /* I2S2 function select */ | |
806 | SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT, | |
807 | 1, 1), | |
be77b38a | 808 | RT5645_HWEQ("Speaker HWEQ"), |
1319b2f6 OC |
809 | }; |
810 | ||
811 | /** | |
812 | * set_dmic_clk - Set parameter of dmic. | |
813 | * | |
814 | * @w: DAPM widget. | |
815 | * @kcontrol: The kcontrol of this widget. | |
816 | * @event: Event id. | |
817 | * | |
1319b2f6 OC |
818 | */ |
819 | static int set_dmic_clk(struct snd_soc_dapm_widget *w, | |
820 | struct snd_kcontrol *kcontrol, int event) | |
821 | { | |
c5f596cb | 822 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
1319b2f6 | 823 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); |
00a6d6e5 | 824 | int idx, rate; |
1319b2f6 | 825 | |
00a6d6e5 OC |
826 | rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap, |
827 | RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT); | |
828 | idx = rl6231_calc_dmic_clk(rate); | |
1319b2f6 OC |
829 | if (idx < 0) |
830 | dev_err(codec->dev, "Failed to set DMIC clock\n"); | |
831 | else | |
832 | snd_soc_update_bits(codec, RT5645_DMIC_CTRL1, | |
833 | RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT); | |
834 | return idx; | |
835 | } | |
836 | ||
837 | static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source, | |
838 | struct snd_soc_dapm_widget *sink) | |
839 | { | |
c5f596cb | 840 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); |
1319b2f6 OC |
841 | unsigned int val; |
842 | ||
c5f596cb | 843 | val = snd_soc_read(codec, RT5645_GLB_CLK); |
1319b2f6 OC |
844 | val &= RT5645_SCLK_SRC_MASK; |
845 | if (val == RT5645_SCLK_SRC_PLL1) | |
846 | return 1; | |
847 | else | |
848 | return 0; | |
849 | } | |
850 | ||
9e268353 BL |
851 | static int is_using_asrc(struct snd_soc_dapm_widget *source, |
852 | struct snd_soc_dapm_widget *sink) | |
853 | { | |
c5f596cb | 854 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm); |
9e268353 BL |
855 | unsigned int reg, shift, val; |
856 | ||
857 | switch (source->shift) { | |
858 | case 0: | |
859 | reg = RT5645_ASRC_3; | |
860 | shift = 0; | |
861 | break; | |
862 | case 1: | |
863 | reg = RT5645_ASRC_3; | |
864 | shift = 4; | |
865 | break; | |
866 | case 3: | |
867 | reg = RT5645_ASRC_2; | |
868 | shift = 0; | |
869 | break; | |
870 | case 8: | |
871 | reg = RT5645_ASRC_2; | |
872 | shift = 4; | |
873 | break; | |
874 | case 9: | |
875 | reg = RT5645_ASRC_2; | |
876 | shift = 8; | |
877 | break; | |
878 | case 10: | |
879 | reg = RT5645_ASRC_2; | |
880 | shift = 12; | |
881 | break; | |
882 | default: | |
883 | return 0; | |
884 | } | |
885 | ||
c5f596cb | 886 | val = (snd_soc_read(codec, reg) >> shift) & 0xf; |
9e268353 BL |
887 | switch (val) { |
888 | case 1: | |
889 | case 2: | |
890 | case 3: | |
891 | case 4: | |
892 | return 1; | |
893 | default: | |
894 | return 0; | |
895 | } | |
896 | ||
897 | } | |
898 | ||
be77b38a OC |
899 | static int rt5645_enable_hweq(struct snd_soc_codec *codec) |
900 | { | |
901 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
902 | int i; | |
903 | ||
904 | for (i = 0; i < RT5645_HWEQ_NUM; i++) { | |
905 | if (rt5645_validate_hweq(rt5645->eq_param[i].reg)) | |
906 | regmap_write(rt5645->regmap, rt5645->eq_param[i].reg, | |
907 | rt5645->eq_param[i].val); | |
908 | else | |
909 | break; | |
910 | } | |
911 | ||
912 | return 0; | |
913 | } | |
914 | ||
79080a8b FY |
915 | /** |
916 | * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters | |
917 | * @codec: SoC audio codec device. | |
918 | * @filter_mask: mask of filters. | |
919 | * @clk_src: clock source | |
920 | * | |
921 | * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can | |
922 | * only support standard 32fs or 64fs i2s format, ASRC should be enabled to | |
923 | * support special i2s clock format such as Intel's 100fs(100 * sampling rate). | |
924 | * ASRC function will track i2s clock and generate a corresponding system clock | |
925 | * for codec. This function provides an API to select the clock source for a | |
926 | * set of filters specified by the mask. And the codec driver will turn on ASRC | |
927 | * for these filters if ASRC is selected as their clock source. | |
928 | */ | |
929 | int rt5645_sel_asrc_clk_src(struct snd_soc_codec *codec, | |
930 | unsigned int filter_mask, unsigned int clk_src) | |
931 | { | |
932 | unsigned int asrc2_mask = 0; | |
933 | unsigned int asrc2_value = 0; | |
934 | unsigned int asrc3_mask = 0; | |
935 | unsigned int asrc3_value = 0; | |
936 | ||
937 | switch (clk_src) { | |
938 | case RT5645_CLK_SEL_SYS: | |
939 | case RT5645_CLK_SEL_I2S1_ASRC: | |
940 | case RT5645_CLK_SEL_I2S2_ASRC: | |
941 | case RT5645_CLK_SEL_SYS2: | |
942 | break; | |
943 | ||
944 | default: | |
945 | return -EINVAL; | |
946 | } | |
947 | ||
948 | if (filter_mask & RT5645_DA_STEREO_FILTER) { | |
949 | asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK; | |
950 | asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK) | |
951 | | (clk_src << RT5645_DA_STO_CLK_SEL_SFT); | |
952 | } | |
953 | ||
954 | if (filter_mask & RT5645_DA_MONO_L_FILTER) { | |
955 | asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK; | |
956 | asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK) | |
957 | | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT); | |
958 | } | |
959 | ||
960 | if (filter_mask & RT5645_DA_MONO_R_FILTER) { | |
961 | asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK; | |
962 | asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK) | |
963 | | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT); | |
964 | } | |
965 | ||
966 | if (filter_mask & RT5645_AD_STEREO_FILTER) { | |
967 | asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK; | |
968 | asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK) | |
969 | | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT); | |
970 | } | |
971 | ||
972 | if (filter_mask & RT5645_AD_MONO_L_FILTER) { | |
973 | asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK; | |
974 | asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK) | |
975 | | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT); | |
976 | } | |
977 | ||
978 | if (filter_mask & RT5645_AD_MONO_R_FILTER) { | |
979 | asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK; | |
980 | asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK) | |
981 | | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT); | |
982 | } | |
983 | ||
984 | if (asrc2_mask) | |
985 | snd_soc_update_bits(codec, RT5645_ASRC_2, | |
986 | asrc2_mask, asrc2_value); | |
987 | ||
988 | if (asrc3_mask) | |
989 | snd_soc_update_bits(codec, RT5645_ASRC_3, | |
990 | asrc3_mask, asrc3_value); | |
991 | ||
992 | return 0; | |
993 | } | |
994 | EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src); | |
995 | ||
1319b2f6 OC |
996 | /* Digital Mixer */ |
997 | static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = { | |
998 | SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, | |
999 | RT5645_M_ADC_L1_SFT, 1, 1), | |
1000 | SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, | |
1001 | RT5645_M_ADC_L2_SFT, 1, 1), | |
1002 | }; | |
1003 | ||
1004 | static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = { | |
1005 | SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER, | |
1006 | RT5645_M_ADC_R1_SFT, 1, 1), | |
1007 | SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER, | |
1008 | RT5645_M_ADC_R2_SFT, 1, 1), | |
1009 | }; | |
1010 | ||
1011 | static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = { | |
1012 | SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, | |
1013 | RT5645_M_MONO_ADC_L1_SFT, 1, 1), | |
1014 | SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, | |
1015 | RT5645_M_MONO_ADC_L2_SFT, 1, 1), | |
1016 | }; | |
1017 | ||
1018 | static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = { | |
1019 | SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER, | |
1020 | RT5645_M_MONO_ADC_R1_SFT, 1, 1), | |
1021 | SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER, | |
1022 | RT5645_M_MONO_ADC_R2_SFT, 1, 1), | |
1023 | }; | |
1024 | ||
1025 | static const struct snd_kcontrol_new rt5645_dac_l_mix[] = { | |
1026 | SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, | |
1027 | RT5645_M_ADCMIX_L_SFT, 1, 1), | |
21cb13e7 | 1028 | SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, |
1319b2f6 OC |
1029 | RT5645_M_DAC1_L_SFT, 1, 1), |
1030 | }; | |
1031 | ||
1032 | static const struct snd_kcontrol_new rt5645_dac_r_mix[] = { | |
1033 | SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER, | |
1034 | RT5645_M_ADCMIX_R_SFT, 1, 1), | |
21cb13e7 | 1035 | SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER, |
1319b2f6 OC |
1036 | RT5645_M_DAC1_R_SFT, 1, 1), |
1037 | }; | |
1038 | ||
1039 | static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = { | |
1040 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, | |
1041 | RT5645_M_DAC_L1_SFT, 1, 1), | |
1042 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER, | |
1043 | RT5645_M_DAC_L2_SFT, 1, 1), | |
1044 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, | |
1045 | RT5645_M_DAC_R1_STO_L_SFT, 1, 1), | |
1046 | }; | |
1047 | ||
1048 | static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = { | |
1049 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER, | |
1050 | RT5645_M_DAC_R1_SFT, 1, 1), | |
1051 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER, | |
1052 | RT5645_M_DAC_R2_SFT, 1, 1), | |
1053 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER, | |
1054 | RT5645_M_DAC_L1_STO_R_SFT, 1, 1), | |
1055 | }; | |
1056 | ||
1057 | static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = { | |
1058 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER, | |
1059 | RT5645_M_DAC_L1_MONO_L_SFT, 1, 1), | |
1060 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, | |
1061 | RT5645_M_DAC_L2_MONO_L_SFT, 1, 1), | |
1062 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, | |
1063 | RT5645_M_DAC_R2_MONO_L_SFT, 1, 1), | |
1064 | }; | |
1065 | ||
1066 | static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = { | |
1067 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER, | |
1068 | RT5645_M_DAC_R1_MONO_R_SFT, 1, 1), | |
1069 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER, | |
1070 | RT5645_M_DAC_R2_MONO_R_SFT, 1, 1), | |
1071 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER, | |
1072 | RT5645_M_DAC_L2_MONO_R_SFT, 1, 1), | |
1073 | }; | |
1074 | ||
1075 | static const struct snd_kcontrol_new rt5645_dig_l_mix[] = { | |
1076 | SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER, | |
1077 | RT5645_M_STO_L_DAC_L_SFT, 1, 1), | |
1078 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, | |
1079 | RT5645_M_DAC_L2_DAC_L_SFT, 1, 1), | |
1080 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, | |
1081 | RT5645_M_DAC_R2_DAC_L_SFT, 1, 1), | |
1082 | }; | |
1083 | ||
1084 | static const struct snd_kcontrol_new rt5645_dig_r_mix[] = { | |
1085 | SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER, | |
1086 | RT5645_M_STO_R_DAC_R_SFT, 1, 1), | |
1087 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER, | |
1088 | RT5645_M_DAC_R2_DAC_R_SFT, 1, 1), | |
1089 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER, | |
1090 | RT5645_M_DAC_L2_DAC_R_SFT, 1, 1), | |
1091 | }; | |
1092 | ||
1093 | /* Analog Input Mixer */ | |
1094 | static const struct snd_kcontrol_new rt5645_rec_l_mix[] = { | |
1095 | SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER, | |
1096 | RT5645_M_HP_L_RM_L_SFT, 1, 1), | |
1097 | SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER, | |
1098 | RT5645_M_IN_L_RM_L_SFT, 1, 1), | |
1099 | SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER, | |
1100 | RT5645_M_BST2_RM_L_SFT, 1, 1), | |
1101 | SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER, | |
1102 | RT5645_M_BST1_RM_L_SFT, 1, 1), | |
1103 | SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER, | |
1104 | RT5645_M_OM_L_RM_L_SFT, 1, 1), | |
1105 | }; | |
1106 | ||
1107 | static const struct snd_kcontrol_new rt5645_rec_r_mix[] = { | |
1108 | SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER, | |
1109 | RT5645_M_HP_R_RM_R_SFT, 1, 1), | |
1110 | SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER, | |
1111 | RT5645_M_IN_R_RM_R_SFT, 1, 1), | |
1112 | SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER, | |
1113 | RT5645_M_BST2_RM_R_SFT, 1, 1), | |
1114 | SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER, | |
1115 | RT5645_M_BST1_RM_R_SFT, 1, 1), | |
1116 | SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER, | |
1117 | RT5645_M_OM_R_RM_R_SFT, 1, 1), | |
1118 | }; | |
1119 | ||
1120 | static const struct snd_kcontrol_new rt5645_spk_l_mix[] = { | |
1121 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER, | |
1122 | RT5645_M_DAC_L1_SM_L_SFT, 1, 1), | |
1123 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER, | |
1124 | RT5645_M_DAC_L2_SM_L_SFT, 1, 1), | |
1125 | SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER, | |
1126 | RT5645_M_IN_L_SM_L_SFT, 1, 1), | |
1127 | SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER, | |
1128 | RT5645_M_BST1_L_SM_L_SFT, 1, 1), | |
1129 | }; | |
1130 | ||
1131 | static const struct snd_kcontrol_new rt5645_spk_r_mix[] = { | |
1132 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER, | |
1133 | RT5645_M_DAC_R1_SM_R_SFT, 1, 1), | |
1134 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER, | |
1135 | RT5645_M_DAC_R2_SM_R_SFT, 1, 1), | |
1136 | SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER, | |
1137 | RT5645_M_IN_R_SM_R_SFT, 1, 1), | |
1138 | SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER, | |
1139 | RT5645_M_BST2_R_SM_R_SFT, 1, 1), | |
1140 | }; | |
1141 | ||
1142 | static const struct snd_kcontrol_new rt5645_out_l_mix[] = { | |
1143 | SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER, | |
1144 | RT5645_M_BST1_OM_L_SFT, 1, 1), | |
1145 | SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER, | |
1146 | RT5645_M_IN_L_OM_L_SFT, 1, 1), | |
1147 | SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER, | |
1148 | RT5645_M_DAC_L2_OM_L_SFT, 1, 1), | |
1149 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER, | |
1150 | RT5645_M_DAC_L1_OM_L_SFT, 1, 1), | |
1151 | }; | |
1152 | ||
1153 | static const struct snd_kcontrol_new rt5645_out_r_mix[] = { | |
1154 | SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER, | |
1155 | RT5645_M_BST2_OM_R_SFT, 1, 1), | |
1156 | SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER, | |
1157 | RT5645_M_IN_R_OM_R_SFT, 1, 1), | |
1158 | SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER, | |
1159 | RT5645_M_DAC_R2_OM_R_SFT, 1, 1), | |
1160 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER, | |
1161 | RT5645_M_DAC_R1_OM_R_SFT, 1, 1), | |
1162 | }; | |
1163 | ||
1164 | static const struct snd_kcontrol_new rt5645_spo_l_mix[] = { | |
1165 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, | |
1166 | RT5645_M_DAC_R1_SPM_L_SFT, 1, 1), | |
1167 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER, | |
1168 | RT5645_M_DAC_L1_SPM_L_SFT, 1, 1), | |
1169 | SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, | |
1170 | RT5645_M_SV_R_SPM_L_SFT, 1, 1), | |
1171 | SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER, | |
1172 | RT5645_M_SV_L_SPM_L_SFT, 1, 1), | |
1173 | }; | |
1174 | ||
1175 | static const struct snd_kcontrol_new rt5645_spo_r_mix[] = { | |
1176 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER, | |
1177 | RT5645_M_DAC_R1_SPM_R_SFT, 1, 1), | |
1178 | SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER, | |
1179 | RT5645_M_SV_R_SPM_R_SFT, 1, 1), | |
1180 | }; | |
1181 | ||
1182 | static const struct snd_kcontrol_new rt5645_hpo_mix[] = { | |
1183 | SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER, | |
1184 | RT5645_M_DAC1_HM_SFT, 1, 1), | |
1185 | SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER, | |
1186 | RT5645_M_HPVOL_HM_SFT, 1, 1), | |
1187 | }; | |
1188 | ||
1189 | static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = { | |
1190 | SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL, | |
1191 | RT5645_M_DAC1_HV_SFT, 1, 1), | |
1192 | SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL, | |
1193 | RT5645_M_DAC2_HV_SFT, 1, 1), | |
1194 | SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL, | |
1195 | RT5645_M_IN_HV_SFT, 1, 1), | |
1196 | SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL, | |
1197 | RT5645_M_BST1_HV_SFT, 1, 1), | |
1198 | }; | |
1199 | ||
1200 | static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = { | |
1201 | SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL, | |
1202 | RT5645_M_DAC1_HV_SFT, 1, 1), | |
1203 | SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL, | |
1204 | RT5645_M_DAC2_HV_SFT, 1, 1), | |
1205 | SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL, | |
1206 | RT5645_M_IN_HV_SFT, 1, 1), | |
1207 | SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL, | |
1208 | RT5645_M_BST2_HV_SFT, 1, 1), | |
1209 | }; | |
1210 | ||
1211 | static const struct snd_kcontrol_new rt5645_lout_mix[] = { | |
1212 | SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER, | |
1213 | RT5645_M_DAC_L1_LM_SFT, 1, 1), | |
1214 | SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER, | |
1215 | RT5645_M_DAC_R1_LM_SFT, 1, 1), | |
1216 | SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER, | |
1217 | RT5645_M_OV_L_LM_SFT, 1, 1), | |
1218 | SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER, | |
1219 | RT5645_M_OV_R_LM_SFT, 1, 1), | |
1220 | }; | |
1221 | ||
1222 | /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */ | |
1223 | static const char * const rt5645_dac1_src[] = { | |
1224 | "IF1 DAC", "IF2 DAC", "IF3 DAC" | |
1225 | }; | |
1226 | ||
1227 | static SOC_ENUM_SINGLE_DECL( | |
1228 | rt5645_dac1l_enum, RT5645_AD_DA_MIXER, | |
1229 | RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src); | |
1230 | ||
1231 | static const struct snd_kcontrol_new rt5645_dac1l_mux = | |
1232 | SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum); | |
1233 | ||
1234 | static SOC_ENUM_SINGLE_DECL( | |
1235 | rt5645_dac1r_enum, RT5645_AD_DA_MIXER, | |
1236 | RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src); | |
1237 | ||
1238 | static const struct snd_kcontrol_new rt5645_dac1r_mux = | |
1239 | SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum); | |
1240 | ||
1241 | /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */ | |
1242 | static const char * const rt5645_dac12_src[] = { | |
1243 | "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC" | |
1244 | }; | |
1245 | ||
1246 | static SOC_ENUM_SINGLE_DECL( | |
1247 | rt5645_dac2l_enum, RT5645_DAC_CTRL, | |
1248 | RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src); | |
1249 | ||
1250 | static const struct snd_kcontrol_new rt5645_dac_l2_mux = | |
1251 | SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum); | |
1252 | ||
1253 | static const char * const rt5645_dacr2_src[] = { | |
1254 | "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic" | |
1255 | }; | |
1256 | ||
1257 | static SOC_ENUM_SINGLE_DECL( | |
1258 | rt5645_dac2r_enum, RT5645_DAC_CTRL, | |
1259 | RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src); | |
1260 | ||
1261 | static const struct snd_kcontrol_new rt5645_dac_r2_mux = | |
1262 | SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum); | |
1263 | ||
1264 | ||
1265 | /* INL/R source */ | |
1266 | static const char * const rt5645_inl_src[] = { | |
1267 | "IN2P", "MonoP" | |
1268 | }; | |
1269 | ||
1270 | static SOC_ENUM_SINGLE_DECL( | |
1271 | rt5645_inl_enum, RT5645_INL1_INR1_VOL, | |
1272 | RT5645_INL_SEL_SFT, rt5645_inl_src); | |
1273 | ||
1274 | static const struct snd_kcontrol_new rt5645_inl_mux = | |
1275 | SOC_DAPM_ENUM("INL source", rt5645_inl_enum); | |
1276 | ||
1277 | static const char * const rt5645_inr_src[] = { | |
1278 | "IN2N", "MonoN" | |
1279 | }; | |
1280 | ||
1281 | static SOC_ENUM_SINGLE_DECL( | |
1282 | rt5645_inr_enum, RT5645_INL1_INR1_VOL, | |
1283 | RT5645_INR_SEL_SFT, rt5645_inr_src); | |
1284 | ||
1285 | static const struct snd_kcontrol_new rt5645_inr_mux = | |
1286 | SOC_DAPM_ENUM("INR source", rt5645_inr_enum); | |
1287 | ||
1288 | /* Stereo1 ADC source */ | |
1289 | /* MX-27 [12] */ | |
1290 | static const char * const rt5645_stereo_adc1_src[] = { | |
1291 | "DAC MIX", "ADC" | |
1292 | }; | |
1293 | ||
1294 | static SOC_ENUM_SINGLE_DECL( | |
1295 | rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER, | |
1296 | RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src); | |
1297 | ||
1298 | static const struct snd_kcontrol_new rt5645_sto_adc1_mux = | |
1299 | SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum); | |
1300 | ||
1301 | /* MX-27 [11] */ | |
1302 | static const char * const rt5645_stereo_adc2_src[] = { | |
1303 | "DAC MIX", "DMIC" | |
1304 | }; | |
1305 | ||
1306 | static SOC_ENUM_SINGLE_DECL( | |
1307 | rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER, | |
1308 | RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src); | |
1309 | ||
1310 | static const struct snd_kcontrol_new rt5645_sto_adc2_mux = | |
1311 | SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum); | |
1312 | ||
1313 | /* MX-27 [8] */ | |
1314 | static const char * const rt5645_stereo_dmic_src[] = { | |
1315 | "DMIC1", "DMIC2" | |
1316 | }; | |
1317 | ||
1318 | static SOC_ENUM_SINGLE_DECL( | |
1319 | rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER, | |
1320 | RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src); | |
1321 | ||
1322 | static const struct snd_kcontrol_new rt5645_sto1_dmic_mux = | |
1323 | SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum); | |
1324 | ||
1325 | /* Mono ADC source */ | |
1326 | /* MX-28 [12] */ | |
1327 | static const char * const rt5645_mono_adc_l1_src[] = { | |
1328 | "Mono DAC MIXL", "ADC" | |
1329 | }; | |
1330 | ||
1331 | static SOC_ENUM_SINGLE_DECL( | |
1332 | rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER, | |
1333 | RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src); | |
1334 | ||
1335 | static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux = | |
1336 | SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum); | |
1337 | /* MX-28 [11] */ | |
1338 | static const char * const rt5645_mono_adc_l2_src[] = { | |
1339 | "Mono DAC MIXL", "DMIC" | |
1340 | }; | |
1341 | ||
1342 | static SOC_ENUM_SINGLE_DECL( | |
1343 | rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER, | |
1344 | RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src); | |
1345 | ||
1346 | static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux = | |
1347 | SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum); | |
1348 | ||
1349 | /* MX-28 [8] */ | |
1350 | static const char * const rt5645_mono_dmic_src[] = { | |
1351 | "DMIC1", "DMIC2" | |
1352 | }; | |
1353 | ||
1354 | static SOC_ENUM_SINGLE_DECL( | |
1355 | rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER, | |
1356 | RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src); | |
1357 | ||
1358 | static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux = | |
1359 | SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum); | |
1360 | /* MX-28 [1:0] */ | |
1361 | static SOC_ENUM_SINGLE_DECL( | |
1362 | rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER, | |
1363 | RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src); | |
1364 | ||
1365 | static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux = | |
1366 | SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum); | |
1367 | /* MX-28 [4] */ | |
1368 | static const char * const rt5645_mono_adc_r1_src[] = { | |
1369 | "Mono DAC MIXR", "ADC" | |
1370 | }; | |
1371 | ||
1372 | static SOC_ENUM_SINGLE_DECL( | |
1373 | rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER, | |
1374 | RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src); | |
1375 | ||
1376 | static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux = | |
1377 | SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum); | |
1378 | /* MX-28 [3] */ | |
1379 | static const char * const rt5645_mono_adc_r2_src[] = { | |
1380 | "Mono DAC MIXR", "DMIC" | |
1381 | }; | |
1382 | ||
1383 | static SOC_ENUM_SINGLE_DECL( | |
1384 | rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER, | |
1385 | RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src); | |
1386 | ||
1387 | static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux = | |
1388 | SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum); | |
1389 | ||
1390 | /* MX-77 [9:8] */ | |
1391 | static const char * const rt5645_if1_adc_in_src[] = { | |
21ab3f2b BL |
1392 | "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC", |
1393 | "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1" | |
1319b2f6 OC |
1394 | }; |
1395 | ||
1396 | static SOC_ENUM_SINGLE_DECL( | |
1397 | rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1, | |
1398 | RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src); | |
1399 | ||
1400 | static const struct snd_kcontrol_new rt5645_if1_adc_in_mux = | |
1401 | SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum); | |
1402 | ||
21ab3f2b BL |
1403 | /* MX-78 [4:0] */ |
1404 | static const char * const rt5650_if1_adc_in_src[] = { | |
1405 | "IF_ADC1/IF_ADC2/DAC_REF/Null", | |
1406 | "IF_ADC1/IF_ADC2/Null/DAC_REF", | |
1407 | "IF_ADC1/DAC_REF/IF_ADC2/Null", | |
1408 | "IF_ADC1/DAC_REF/Null/IF_ADC2", | |
1409 | "IF_ADC1/Null/DAC_REF/IF_ADC2", | |
1410 | "IF_ADC1/Null/IF_ADC2/DAC_REF", | |
1411 | ||
1412 | "IF_ADC2/IF_ADC1/DAC_REF/Null", | |
1413 | "IF_ADC2/IF_ADC1/Null/DAC_REF", | |
1414 | "IF_ADC2/DAC_REF/IF_ADC1/Null", | |
1415 | "IF_ADC2/DAC_REF/Null/IF_ADC1", | |
1416 | "IF_ADC2/Null/DAC_REF/IF_ADC1", | |
1417 | "IF_ADC2/Null/IF_ADC1/DAC_REF", | |
1418 | ||
1419 | "DAC_REF/IF_ADC1/IF_ADC2/Null", | |
1420 | "DAC_REF/IF_ADC1/Null/IF_ADC2", | |
1421 | "DAC_REF/IF_ADC2/IF_ADC1/Null", | |
1422 | "DAC_REF/IF_ADC2/Null/IF_ADC1", | |
1423 | "DAC_REF/Null/IF_ADC1/IF_ADC2", | |
1424 | "DAC_REF/Null/IF_ADC2/IF_ADC1", | |
1425 | ||
1426 | "Null/IF_ADC1/IF_ADC2/DAC_REF", | |
1427 | "Null/IF_ADC1/DAC_REF/IF_ADC2", | |
1428 | "Null/IF_ADC2/IF_ADC1/DAC_REF", | |
1429 | "Null/IF_ADC2/DAC_REF/IF_ADC1", | |
1430 | "Null/DAC_REF/IF_ADC1/IF_ADC2", | |
1431 | "Null/DAC_REF/IF_ADC2/IF_ADC1", | |
1432 | }; | |
1433 | ||
1434 | static SOC_ENUM_SINGLE_DECL( | |
1435 | rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2, | |
1436 | 0, rt5650_if1_adc_in_src); | |
1437 | ||
1438 | static const struct snd_kcontrol_new rt5650_if1_adc_in_mux = | |
1439 | SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum); | |
1440 | ||
1441 | /* MX-78 [15:14][13:12][11:10] */ | |
1442 | static const char * const rt5645_tdm_adc_swap_select[] = { | |
1443 | "L/R", "R/L", "L/L", "R/R" | |
1444 | }; | |
1445 | ||
1446 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum, | |
1447 | RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select); | |
1448 | ||
1449 | static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux = | |
1450 | SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum); | |
1451 | ||
1452 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum, | |
1453 | RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select); | |
1454 | ||
1455 | static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux = | |
1456 | SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum); | |
1457 | ||
1458 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum, | |
1459 | RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select); | |
1460 | ||
1461 | static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux = | |
1462 | SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum); | |
1463 | ||
1464 | /* MX-77 [7:6][5:4][3:2] */ | |
1465 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum, | |
1466 | RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select); | |
1467 | ||
1468 | static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux = | |
1469 | SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum); | |
1470 | ||
1471 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum, | |
1472 | RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select); | |
1473 | ||
1474 | static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux = | |
1475 | SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum); | |
1476 | ||
1477 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum, | |
1478 | RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select); | |
1479 | ||
1480 | static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux = | |
1481 | SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum); | |
1482 | ||
1483 | /* MX-79 [14:12][10:8][6:4][2:0] */ | |
1484 | static const char * const rt5645_tdm_dac_swap_select[] = { | |
1485 | "Slot0", "Slot1", "Slot2", "Slot3" | |
1486 | }; | |
1487 | ||
1488 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum, | |
1489 | RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select); | |
1490 | ||
1491 | static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux = | |
1492 | SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum); | |
1493 | ||
1494 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum, | |
1495 | RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select); | |
1496 | ||
1497 | static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux = | |
1498 | SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum); | |
1499 | ||
1500 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum, | |
1501 | RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select); | |
1502 | ||
1503 | static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux = | |
1504 | SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum); | |
1505 | ||
1506 | static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum, | |
1507 | RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select); | |
1508 | ||
1509 | static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux = | |
1510 | SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum); | |
1511 | ||
1512 | /* MX-7a [14:12][10:8][6:4][2:0] */ | |
1513 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum, | |
1514 | RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select); | |
1515 | ||
1516 | static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux = | |
1517 | SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum); | |
1518 | ||
1519 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum, | |
1520 | RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select); | |
1521 | ||
1522 | static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux = | |
1523 | SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum); | |
1524 | ||
1525 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum, | |
1526 | RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select); | |
1527 | ||
1528 | static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux = | |
1529 | SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum); | |
1530 | ||
1531 | static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum, | |
1532 | RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select); | |
1533 | ||
1534 | static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux = | |
1535 | SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum); | |
1536 | ||
5c4ca99d BL |
1537 | /* MX-2d [3] [2] */ |
1538 | static const char * const rt5650_a_dac1_src[] = { | |
1539 | "DAC1", "Stereo DAC Mixer" | |
1540 | }; | |
1541 | ||
1542 | static SOC_ENUM_SINGLE_DECL( | |
1543 | rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR, | |
1544 | RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src); | |
1545 | ||
1546 | static const struct snd_kcontrol_new rt5650_a_dac1_l_mux = | |
1547 | SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum); | |
1548 | ||
1549 | static SOC_ENUM_SINGLE_DECL( | |
1550 | rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR, | |
1551 | RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src); | |
1552 | ||
1553 | static const struct snd_kcontrol_new rt5650_a_dac1_r_mux = | |
1554 | SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum); | |
1555 | ||
1556 | /* MX-2d [1] [0] */ | |
1557 | static const char * const rt5650_a_dac2_src[] = { | |
1558 | "Stereo DAC Mixer", "Mono DAC Mixer" | |
1559 | }; | |
1560 | ||
1561 | static SOC_ENUM_SINGLE_DECL( | |
1562 | rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR, | |
1563 | RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src); | |
1564 | ||
1565 | static const struct snd_kcontrol_new rt5650_a_dac2_l_mux = | |
1566 | SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum); | |
1567 | ||
1568 | static SOC_ENUM_SINGLE_DECL( | |
1569 | rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR, | |
1570 | RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src); | |
1571 | ||
1572 | static const struct snd_kcontrol_new rt5650_a_dac2_r_mux = | |
1573 | SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum); | |
1574 | ||
1319b2f6 OC |
1575 | /* MX-2F [13:12] */ |
1576 | static const char * const rt5645_if2_adc_in_src[] = { | |
1577 | "IF_ADC1", "IF_ADC2", "VAD_ADC" | |
1578 | }; | |
1579 | ||
1580 | static SOC_ENUM_SINGLE_DECL( | |
1581 | rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA, | |
1582 | RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src); | |
1583 | ||
1584 | static const struct snd_kcontrol_new rt5645_if2_adc_in_mux = | |
1585 | SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum); | |
1586 | ||
1587 | /* MX-2F [1:0] */ | |
1588 | static const char * const rt5645_if3_adc_in_src[] = { | |
1589 | "IF_ADC1", "IF_ADC2", "VAD_ADC" | |
1590 | }; | |
1591 | ||
1592 | static SOC_ENUM_SINGLE_DECL( | |
1593 | rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA, | |
1594 | RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src); | |
1595 | ||
1596 | static const struct snd_kcontrol_new rt5645_if3_adc_in_mux = | |
1597 | SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum); | |
1598 | ||
1599 | /* MX-31 [15] [13] [11] [9] */ | |
1600 | static const char * const rt5645_pdm_src[] = { | |
1601 | "Mono DAC", "Stereo DAC" | |
1602 | }; | |
1603 | ||
1604 | static SOC_ENUM_SINGLE_DECL( | |
1605 | rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL, | |
1606 | RT5645_PDM1_L_SFT, rt5645_pdm_src); | |
1607 | ||
1608 | static const struct snd_kcontrol_new rt5645_pdm1_l_mux = | |
1609 | SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum); | |
1610 | ||
1611 | static SOC_ENUM_SINGLE_DECL( | |
1612 | rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL, | |
1613 | RT5645_PDM1_R_SFT, rt5645_pdm_src); | |
1614 | ||
1615 | static const struct snd_kcontrol_new rt5645_pdm1_r_mux = | |
1616 | SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum); | |
1617 | ||
1618 | /* MX-9D [9:8] */ | |
1619 | static const char * const rt5645_vad_adc_src[] = { | |
1620 | "Sto1 ADC L", "Mono ADC L", "Mono ADC R" | |
1621 | }; | |
1622 | ||
1623 | static SOC_ENUM_SINGLE_DECL( | |
1624 | rt5645_vad_adc_enum, RT5645_VAD_CTRL4, | |
1625 | RT5645_VAD_SEL_SFT, rt5645_vad_adc_src); | |
1626 | ||
1627 | static const struct snd_kcontrol_new rt5645_vad_adc_mux = | |
1628 | SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum); | |
1629 | ||
1630 | static const struct snd_kcontrol_new spk_l_vol_control = | |
1631 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, | |
1632 | RT5645_L_MUTE_SFT, 1, 1); | |
1633 | ||
1634 | static const struct snd_kcontrol_new spk_r_vol_control = | |
1635 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL, | |
1636 | RT5645_R_MUTE_SFT, 1, 1); | |
1637 | ||
1638 | static const struct snd_kcontrol_new hp_l_vol_control = | |
1639 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, | |
1640 | RT5645_L_MUTE_SFT, 1, 1); | |
1641 | ||
1642 | static const struct snd_kcontrol_new hp_r_vol_control = | |
1643 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL, | |
1644 | RT5645_R_MUTE_SFT, 1, 1); | |
1645 | ||
1646 | static const struct snd_kcontrol_new pdm1_l_vol_control = | |
1647 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, | |
1648 | RT5645_M_PDM1_L, 1, 1); | |
1649 | ||
1650 | static const struct snd_kcontrol_new pdm1_r_vol_control = | |
1651 | SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL, | |
1652 | RT5645_M_PDM1_R, 1, 1); | |
1653 | ||
1654 | static void hp_amp_power(struct snd_soc_codec *codec, int on) | |
1655 | { | |
1656 | static int hp_amp_power_count; | |
1657 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
1658 | ||
1659 | if (on) { | |
1660 | if (hp_amp_power_count <= 0) { | |
d12d6c4e | 1661 | if (rt5645->codec_type == CODEC_TYPE_RT5650) { |
588cd850 | 1662 | snd_soc_write(codec, RT5645_DEPOP_M2, 0x3100); |
d12d6c4e JL |
1663 | snd_soc_write(codec, RT5645_CHARGE_PUMP, |
1664 | 0x0e06); | |
588cd850 OC |
1665 | snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d); |
1666 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1667 | RT5645_HP_DCC_INT1, 0x9f01); | |
1668 | msleep(20); | |
1669 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1670 | RT5645_HP_CO_MASK, RT5645_HP_CO_EN); | |
d12d6c4e JL |
1671 | regmap_write(rt5645->regmap, RT5645_PR_BASE + |
1672 | 0x3e, 0x7400); | |
1673 | snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737); | |
1674 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1675 | RT5645_MAMP_INT_REG2, 0xfc00); | |
1676 | snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140); | |
91ed37e4 | 1677 | msleep(70); |
588cd850 | 1678 | rt5645->hp_on = true; |
d12d6c4e JL |
1679 | } else { |
1680 | /* depop parameters */ | |
1681 | snd_soc_update_bits(codec, RT5645_DEPOP_M2, | |
1682 | RT5645_DEPOP_MASK, RT5645_DEPOP_MAN); | |
1683 | snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d); | |
1684 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1685 | RT5645_HP_DCC_INT1, 0x9f01); | |
1686 | mdelay(150); | |
1687 | /* headphone amp power on */ | |
1688 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
1689 | RT5645_PWR_FV1 | RT5645_PWR_FV2, 0); | |
1690 | snd_soc_update_bits(codec, RT5645_PWR_VOL, | |
1691 | RT5645_PWR_HV_L | RT5645_PWR_HV_R, | |
1692 | RT5645_PWR_HV_L | RT5645_PWR_HV_R); | |
1693 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
1694 | RT5645_PWR_HP_L | RT5645_PWR_HP_R | | |
1695 | RT5645_PWR_HA, | |
1696 | RT5645_PWR_HP_L | RT5645_PWR_HP_R | | |
1697 | RT5645_PWR_HA); | |
1698 | mdelay(5); | |
1699 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
1700 | RT5645_PWR_FV1 | RT5645_PWR_FV2, | |
1701 | RT5645_PWR_FV1 | RT5645_PWR_FV2); | |
1702 | ||
1703 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1704 | RT5645_HP_CO_MASK | RT5645_HP_SG_MASK, | |
1705 | RT5645_HP_CO_EN | RT5645_HP_SG_EN); | |
1706 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1707 | 0x14, 0x1aaa); | |
1708 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1709 | 0x24, 0x0430); | |
1710 | } | |
1319b2f6 OC |
1711 | } |
1712 | hp_amp_power_count++; | |
1713 | } else { | |
1714 | hp_amp_power_count--; | |
1715 | if (hp_amp_power_count <= 0) { | |
d12d6c4e JL |
1716 | if (rt5645->codec_type == CODEC_TYPE_RT5650) { |
1717 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1718 | 0x3e, 0x7400); | |
1719 | snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737); | |
1720 | regmap_write(rt5645->regmap, RT5645_PR_BASE + | |
1721 | RT5645_MAMP_INT_REG2, 0xfc00); | |
1722 | snd_soc_write(codec, RT5645_DEPOP_M2, 0x1140); | |
1723 | msleep(100); | |
1724 | snd_soc_write(codec, RT5645_DEPOP_M1, 0x0001); | |
1725 | ||
1726 | } else { | |
1727 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1728 | RT5645_HP_SG_MASK | | |
1729 | RT5645_HP_L_SMT_MASK | | |
1730 | RT5645_HP_R_SMT_MASK, | |
1731 | RT5645_HP_SG_DIS | | |
1732 | RT5645_HP_L_SMT_DIS | | |
1733 | RT5645_HP_R_SMT_DIS); | |
1734 | /* headphone amp power down */ | |
1735 | snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000); | |
1736 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
1737 | RT5645_PWR_HP_L | RT5645_PWR_HP_R | | |
1738 | RT5645_PWR_HA, 0); | |
1739 | snd_soc_update_bits(codec, RT5645_DEPOP_M2, | |
1740 | RT5645_DEPOP_MASK, 0); | |
1741 | } | |
1319b2f6 OC |
1742 | } |
1743 | } | |
1744 | } | |
1745 | ||
1746 | static int rt5645_hp_event(struct snd_soc_dapm_widget *w, | |
1747 | struct snd_kcontrol *kcontrol, int event) | |
1748 | { | |
c5f596cb | 1749 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
1319b2f6 OC |
1750 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); |
1751 | ||
1752 | switch (event) { | |
1753 | case SND_SOC_DAPM_POST_PMU: | |
1754 | hp_amp_power(codec, 1); | |
1755 | /* headphone unmute sequence */ | |
d12d6c4e | 1756 | if (rt5645->codec_type == CODEC_TYPE_RT5645) { |
5c4ca99d BL |
1757 | snd_soc_update_bits(codec, RT5645_DEPOP_M3, |
1758 | RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | | |
1759 | RT5645_CP_FQ3_MASK, | |
1760 | (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) | | |
1761 | (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | | |
1762 | (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT)); | |
d12d6c4e JL |
1763 | regmap_write(rt5645->regmap, RT5645_PR_BASE + |
1764 | RT5645_MAMP_INT_REG2, 0xfc00); | |
1765 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1766 | RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN); | |
1767 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1768 | RT5645_RSTN_MASK, RT5645_RSTN_EN); | |
1769 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1770 | RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK | | |
1771 | RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS | | |
1772 | RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); | |
1773 | msleep(40); | |
1774 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1775 | RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK | | |
1776 | RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS | | |
1777 | RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS); | |
5c4ca99d | 1778 | } |
1319b2f6 OC |
1779 | break; |
1780 | ||
1781 | case SND_SOC_DAPM_PRE_PMD: | |
1782 | /* headphone mute sequence */ | |
d12d6c4e | 1783 | if (rt5645->codec_type == CODEC_TYPE_RT5645) { |
5c4ca99d BL |
1784 | snd_soc_update_bits(codec, RT5645_DEPOP_M3, |
1785 | RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK | | |
1786 | RT5645_CP_FQ3_MASK, | |
1787 | (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) | | |
1788 | (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) | | |
1789 | (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT)); | |
d12d6c4e JL |
1790 | regmap_write(rt5645->regmap, RT5645_PR_BASE + |
1791 | RT5645_MAMP_INT_REG2, 0xfc00); | |
1792 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1793 | RT5645_HP_SG_MASK, RT5645_HP_SG_EN); | |
1794 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1795 | RT5645_RSTP_MASK, RT5645_RSTP_EN); | |
1796 | snd_soc_update_bits(codec, RT5645_DEPOP_M1, | |
1797 | RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK | | |
1798 | RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS | | |
1799 | RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN); | |
1800 | msleep(30); | |
5c4ca99d | 1801 | } |
1319b2f6 OC |
1802 | hp_amp_power(codec, 0); |
1803 | break; | |
1804 | ||
1805 | default: | |
1806 | return 0; | |
1807 | } | |
1808 | ||
1809 | return 0; | |
1810 | } | |
1811 | ||
1812 | static int rt5645_spk_event(struct snd_soc_dapm_widget *w, | |
1813 | struct snd_kcontrol *kcontrol, int event) | |
1814 | { | |
c5f596cb | 1815 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
1319b2f6 OC |
1816 | |
1817 | switch (event) { | |
1818 | case SND_SOC_DAPM_POST_PMU: | |
be77b38a | 1819 | rt5645_enable_hweq(codec); |
1319b2f6 OC |
1820 | snd_soc_update_bits(codec, RT5645_PWR_DIG1, |
1821 | RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | | |
1822 | RT5645_PWR_CLS_D_L, | |
1823 | RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | | |
1824 | RT5645_PWR_CLS_D_L); | |
ca8457bb BL |
1825 | snd_soc_update_bits(codec, RT5645_GEN_CTRL3, |
1826 | RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1); | |
1319b2f6 OC |
1827 | break; |
1828 | ||
1829 | case SND_SOC_DAPM_PRE_PMD: | |
ca8457bb BL |
1830 | snd_soc_update_bits(codec, RT5645_GEN_CTRL3, |
1831 | RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS); | |
be77b38a | 1832 | snd_soc_write(codec, RT5645_EQ_CTRL2, 0); |
1319b2f6 OC |
1833 | snd_soc_update_bits(codec, RT5645_PWR_DIG1, |
1834 | RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R | | |
1835 | RT5645_PWR_CLS_D_L, 0); | |
1836 | break; | |
1837 | ||
1838 | default: | |
1839 | return 0; | |
1840 | } | |
1841 | ||
1842 | return 0; | |
1843 | } | |
1844 | ||
1845 | static int rt5645_lout_event(struct snd_soc_dapm_widget *w, | |
1846 | struct snd_kcontrol *kcontrol, int event) | |
1847 | { | |
c5f596cb | 1848 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
1319b2f6 OC |
1849 | |
1850 | switch (event) { | |
1851 | case SND_SOC_DAPM_POST_PMU: | |
1852 | hp_amp_power(codec, 1); | |
1853 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
1854 | RT5645_PWR_LM, RT5645_PWR_LM); | |
1855 | snd_soc_update_bits(codec, RT5645_LOUT1, | |
1856 | RT5645_L_MUTE | RT5645_R_MUTE, 0); | |
1857 | break; | |
1858 | ||
1859 | case SND_SOC_DAPM_PRE_PMD: | |
1860 | snd_soc_update_bits(codec, RT5645_LOUT1, | |
1861 | RT5645_L_MUTE | RT5645_R_MUTE, | |
1862 | RT5645_L_MUTE | RT5645_R_MUTE); | |
1863 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
1864 | RT5645_PWR_LM, 0); | |
1865 | hp_amp_power(codec, 0); | |
1866 | break; | |
1867 | ||
1868 | default: | |
1869 | return 0; | |
1870 | } | |
1871 | ||
1872 | return 0; | |
1873 | } | |
1874 | ||
1875 | static int rt5645_bst2_event(struct snd_soc_dapm_widget *w, | |
1876 | struct snd_kcontrol *kcontrol, int event) | |
1877 | { | |
c5f596cb | 1878 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
1319b2f6 OC |
1879 | |
1880 | switch (event) { | |
1881 | case SND_SOC_DAPM_POST_PMU: | |
1882 | snd_soc_update_bits(codec, RT5645_PWR_ANLG2, | |
1883 | RT5645_PWR_BST2_P, RT5645_PWR_BST2_P); | |
1884 | break; | |
1885 | ||
1886 | case SND_SOC_DAPM_PRE_PMD: | |
1887 | snd_soc_update_bits(codec, RT5645_PWR_ANLG2, | |
1888 | RT5645_PWR_BST2_P, 0); | |
1889 | break; | |
1890 | ||
1891 | default: | |
1892 | return 0; | |
1893 | } | |
1894 | ||
1895 | return 0; | |
1896 | } | |
1897 | ||
588cd850 OC |
1898 | static int rt5650_hp_event(struct snd_soc_dapm_widget *w, |
1899 | struct snd_kcontrol *k, int event) | |
1900 | { | |
1901 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); | |
1902 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
1903 | ||
1904 | switch (event) { | |
1905 | case SND_SOC_DAPM_POST_PMU: | |
1906 | if (rt5645->hp_on) { | |
1907 | msleep(100); | |
1908 | rt5645->hp_on = false; | |
1909 | } | |
1910 | break; | |
1911 | ||
1912 | default: | |
1913 | return 0; | |
1914 | } | |
1915 | ||
1916 | return 0; | |
1917 | } | |
1918 | ||
1319b2f6 OC |
1919 | static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = { |
1920 | SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER, | |
1921 | RT5645_PWR_LDO2_BIT, 0, NULL, 0), | |
1922 | SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2, | |
1923 | RT5645_PWR_PLL_BIT, 0, NULL, 0), | |
1924 | ||
1925 | SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2, | |
1926 | RT5645_PWR_JD1_BIT, 0, NULL, 0), | |
1927 | SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL, | |
1928 | RT5645_PWR_MIC_DET_BIT, 0, NULL, 0), | |
1929 | ||
9e268353 BL |
1930 | /* ASRC */ |
1931 | SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1, | |
1932 | 11, 0, NULL, 0), | |
1933 | SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1, | |
1934 | 12, 0, NULL, 0), | |
1935 | SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1, | |
1936 | 10, 0, NULL, 0), | |
1937 | SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1, | |
1938 | 9, 0, NULL, 0), | |
1939 | SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1, | |
1940 | 8, 0, NULL, 0), | |
1941 | SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1, | |
1942 | 7, 0, NULL, 0), | |
1943 | SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1, | |
1944 | 5, 0, NULL, 0), | |
1945 | SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1, | |
1946 | 4, 0, NULL, 0), | |
1947 | SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1, | |
1948 | 3, 0, NULL, 0), | |
1949 | SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1, | |
1950 | 1, 0, NULL, 0), | |
1951 | SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1, | |
1952 | 0, 0, NULL, 0), | |
1953 | ||
1319b2f6 OC |
1954 | /* Input Side */ |
1955 | /* micbias */ | |
1956 | SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2, | |
1957 | RT5645_PWR_MB1_BIT, 0), | |
1958 | SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2, | |
1959 | RT5645_PWR_MB2_BIT, 0), | |
1960 | /* Input Lines */ | |
1961 | SND_SOC_DAPM_INPUT("DMIC L1"), | |
1962 | SND_SOC_DAPM_INPUT("DMIC R1"), | |
1963 | SND_SOC_DAPM_INPUT("DMIC L2"), | |
1964 | SND_SOC_DAPM_INPUT("DMIC R2"), | |
1965 | ||
1966 | SND_SOC_DAPM_INPUT("IN1P"), | |
1967 | SND_SOC_DAPM_INPUT("IN1N"), | |
1968 | SND_SOC_DAPM_INPUT("IN2P"), | |
1969 | SND_SOC_DAPM_INPUT("IN2N"), | |
1970 | ||
1971 | SND_SOC_DAPM_INPUT("Haptic Generator"), | |
1972 | ||
1973 | SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1974 | SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1975 | SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0, | |
1976 | set_dmic_clk, SND_SOC_DAPM_PRE_PMU), | |
1977 | SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1, | |
1978 | RT5645_DMIC_1_EN_SFT, 0, NULL, 0), | |
1979 | SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1, | |
1980 | RT5645_DMIC_2_EN_SFT, 0, NULL, 0), | |
1981 | /* Boost */ | |
1982 | SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2, | |
1983 | RT5645_PWR_BST1_BIT, 0, NULL, 0), | |
1984 | SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2, | |
1985 | RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event, | |
1986 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
1987 | /* Input Volume */ | |
1988 | SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL, | |
1989 | RT5645_PWR_IN_L_BIT, 0, NULL, 0), | |
1990 | SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL, | |
1991 | RT5645_PWR_IN_R_BIT, 0, NULL, 0), | |
1992 | /* REC Mixer */ | |
1993 | SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT, | |
1994 | 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)), | |
1995 | SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT, | |
1996 | 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)), | |
1997 | /* ADCs */ | |
1998 | SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), | |
1999 | SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), | |
2000 | ||
2001 | SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1, | |
2002 | RT5645_PWR_ADC_L_BIT, 0, NULL, 0), | |
2003 | SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1, | |
2004 | RT5645_PWR_ADC_R_BIT, 0, NULL, 0), | |
2005 | ||
2006 | /* ADC Mux */ | |
2007 | SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0, | |
2008 | &rt5645_sto1_dmic_mux), | |
2009 | SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0, | |
2010 | &rt5645_sto_adc2_mux), | |
2011 | SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0, | |
2012 | &rt5645_sto_adc2_mux), | |
2013 | SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0, | |
2014 | &rt5645_sto_adc1_mux), | |
2015 | SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0, | |
2016 | &rt5645_sto_adc1_mux), | |
2017 | SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0, | |
2018 | &rt5645_mono_dmic_l_mux), | |
2019 | SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0, | |
2020 | &rt5645_mono_dmic_r_mux), | |
2021 | SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0, | |
2022 | &rt5645_mono_adc_l2_mux), | |
2023 | SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0, | |
2024 | &rt5645_mono_adc_l1_mux), | |
2025 | SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0, | |
2026 | &rt5645_mono_adc_r1_mux), | |
2027 | SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0, | |
2028 | &rt5645_mono_adc_r2_mux), | |
2029 | /* ADC Mixer */ | |
2030 | ||
2031 | SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2, | |
2032 | RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0), | |
1319b2f6 OC |
2033 | SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0, |
2034 | rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix), | |
2035 | NULL, 0), | |
2036 | SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0, | |
2037 | rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix), | |
2038 | NULL, 0), | |
2039 | SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2, | |
2040 | RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0), | |
2041 | SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0, | |
2042 | rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix), | |
2043 | NULL, 0), | |
2044 | SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2, | |
2045 | RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0), | |
2046 | SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0, | |
2047 | rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix), | |
2048 | NULL, 0), | |
2049 | ||
2050 | /* ADC PGA */ | |
2051 | SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2052 | SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2053 | SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2054 | SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2055 | SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2056 | SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2057 | SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2058 | SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2059 | SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2060 | SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2061 | ||
2062 | /* IF1 2 Mux */ | |
1319b2f6 OC |
2063 | SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM, |
2064 | 0, 0, &rt5645_if2_adc_in_mux), | |
2065 | ||
2066 | /* Digital Interface */ | |
2067 | SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1, | |
2068 | RT5645_PWR_I2S1_BIT, 0, NULL, 0), | |
786aa09b | 2069 | SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0), |
1319b2f6 OC |
2070 | SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
2071 | SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
786aa09b | 2072 | SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
1319b2f6 OC |
2073 | SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), |
2074 | SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2075 | SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2076 | SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1, | |
2077 | RT5645_PWR_I2S2_BIT, 0, NULL, 0), | |
2078 | SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2079 | SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2080 | SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2081 | SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2082 | ||
2083 | /* Digital Interface Select */ | |
2084 | SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, | |
2085 | 0, 0, &rt5645_vad_adc_mux), | |
2086 | ||
2087 | /* Audio Interface */ | |
2088 | SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), | |
2089 | SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), | |
2090 | SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0), | |
2091 | SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), | |
2092 | ||
2093 | /* Output Side */ | |
2094 | /* DAC mixer before sound effect */ | |
2095 | SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0, | |
2096 | rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)), | |
2097 | SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0, | |
2098 | rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)), | |
2099 | ||
2100 | /* DAC2 channel Mux */ | |
2101 | SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux), | |
2102 | SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux), | |
2103 | SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1, | |
2104 | RT5645_PWR_DAC_L2_BIT, 0, NULL, 0), | |
2105 | SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1, | |
2106 | RT5645_PWR_DAC_R2_BIT, 0, NULL, 0), | |
2107 | ||
2108 | SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux), | |
2109 | SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux), | |
2110 | ||
2111 | /* DAC Mixer */ | |
2112 | SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2, | |
2113 | RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0), | |
2114 | SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2, | |
2115 | RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0), | |
2116 | SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2, | |
2117 | RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0), | |
2118 | SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0, | |
2119 | rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)), | |
2120 | SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0, | |
2121 | rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)), | |
2122 | SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0, | |
2123 | rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)), | |
2124 | SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0, | |
2125 | rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)), | |
2126 | SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0, | |
2127 | rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)), | |
2128 | SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0, | |
2129 | rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)), | |
2130 | ||
2131 | /* DACs */ | |
2132 | SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT, | |
2133 | 0), | |
2134 | SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT, | |
2135 | 0), | |
2136 | SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT, | |
2137 | 0), | |
2138 | SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT, | |
2139 | 0), | |
2140 | /* OUT Mixer */ | |
2141 | SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT, | |
2142 | 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)), | |
2143 | SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT, | |
2144 | 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)), | |
2145 | SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT, | |
2146 | 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)), | |
2147 | SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT, | |
2148 | 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)), | |
2149 | /* Ouput Volume */ | |
2150 | SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0, | |
2151 | &spk_l_vol_control), | |
2152 | SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0, | |
2153 | &spk_r_vol_control), | |
2154 | SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT, | |
2155 | 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)), | |
2156 | SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT, | |
2157 | 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)), | |
2158 | SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER, | |
2159 | RT5645_PWR_HM_L_BIT, 0, NULL, 0), | |
2160 | SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER, | |
2161 | RT5645_PWR_HM_R_BIT, 0, NULL, 0), | |
2162 | SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2163 | SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2164 | SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0), | |
2165 | SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control), | |
2166 | SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control), | |
2167 | ||
2168 | /* HPO/LOUT/Mono Mixer */ | |
2169 | SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix, | |
2170 | ARRAY_SIZE(rt5645_spo_l_mix)), | |
2171 | SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix, | |
2172 | ARRAY_SIZE(rt5645_spo_r_mix)), | |
2173 | SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix, | |
2174 | ARRAY_SIZE(rt5645_hpo_mix)), | |
2175 | SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix, | |
2176 | ARRAY_SIZE(rt5645_lout_mix)), | |
2177 | ||
2178 | SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event, | |
2179 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
2180 | SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event, | |
2181 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
2182 | SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event, | |
2183 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU), | |
2184 | ||
2185 | /* PDM */ | |
2186 | SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT, | |
2187 | 0, NULL, 0), | |
2188 | SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux), | |
2189 | SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux), | |
2190 | ||
2191 | SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control), | |
2192 | SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control), | |
2193 | ||
2194 | /* Output Lines */ | |
2195 | SND_SOC_DAPM_OUTPUT("HPOL"), | |
2196 | SND_SOC_DAPM_OUTPUT("HPOR"), | |
2197 | SND_SOC_DAPM_OUTPUT("LOUTL"), | |
2198 | SND_SOC_DAPM_OUTPUT("LOUTR"), | |
2199 | SND_SOC_DAPM_OUTPUT("PDM1L"), | |
2200 | SND_SOC_DAPM_OUTPUT("PDM1R"), | |
2201 | SND_SOC_DAPM_OUTPUT("SPOL"), | |
2202 | SND_SOC_DAPM_OUTPUT("SPOR"), | |
588cd850 | 2203 | SND_SOC_DAPM_POST("DAPM_POST", rt5650_hp_event), |
1319b2f6 OC |
2204 | }; |
2205 | ||
83c09290 BL |
2206 | static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = { |
2207 | SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, | |
2208 | &rt5645_if1_dac0_tdm_sel_mux), | |
2209 | SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, | |
2210 | &rt5645_if1_dac1_tdm_sel_mux), | |
2211 | SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, | |
2212 | &rt5645_if1_dac2_tdm_sel_mux), | |
2213 | SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, | |
2214 | &rt5645_if1_dac3_tdm_sel_mux), | |
2215 | SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM, | |
2216 | 0, 0, &rt5645_if1_adc_in_mux), | |
2217 | SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM, | |
2218 | 0, 0, &rt5645_if1_adc1_in_mux), | |
2219 | SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM, | |
2220 | 0, 0, &rt5645_if1_adc2_in_mux), | |
2221 | SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM, | |
2222 | 0, 0, &rt5645_if1_adc3_in_mux), | |
1319b2f6 OC |
2223 | }; |
2224 | ||
5c4ca99d BL |
2225 | static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = { |
2226 | SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM, | |
2227 | 0, 0, &rt5650_a_dac1_l_mux), | |
2228 | SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM, | |
2229 | 0, 0, &rt5650_a_dac1_r_mux), | |
2230 | SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM, | |
2231 | 0, 0, &rt5650_a_dac2_l_mux), | |
2232 | SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM, | |
2233 | 0, 0, &rt5650_a_dac2_r_mux), | |
851b81e8 MC |
2234 | |
2235 | SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM, | |
2236 | 0, 0, &rt5650_if1_adc1_in_mux), | |
2237 | SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM, | |
2238 | 0, 0, &rt5650_if1_adc2_in_mux), | |
2239 | SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM, | |
2240 | 0, 0, &rt5650_if1_adc3_in_mux), | |
2241 | SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM, | |
2242 | 0, 0, &rt5650_if1_adc_in_mux), | |
2243 | ||
2244 | SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0, | |
2245 | &rt5650_if1_dac0_tdm_sel_mux), | |
2246 | SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0, | |
2247 | &rt5650_if1_dac1_tdm_sel_mux), | |
2248 | SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0, | |
2249 | &rt5650_if1_dac2_tdm_sel_mux), | |
2250 | SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0, | |
2251 | &rt5650_if1_dac3_tdm_sel_mux), | |
5c4ca99d BL |
2252 | }; |
2253 | ||
1319b2f6 | 2254 | static const struct snd_soc_dapm_route rt5645_dapm_routes[] = { |
9e268353 | 2255 | { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc }, |
9e268353 BL |
2256 | { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc }, |
2257 | { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc }, | |
2258 | { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc }, | |
2259 | { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc }, | |
2260 | { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc }, | |
2261 | ||
2262 | { "I2S1", NULL, "I2S1 ASRC" }, | |
2263 | { "I2S2", NULL, "I2S2 ASRC" }, | |
2264 | ||
1319b2f6 OC |
2265 | { "IN1P", NULL, "LDO2" }, |
2266 | { "IN2P", NULL, "LDO2" }, | |
2267 | ||
2268 | { "DMIC1", NULL, "DMIC L1" }, | |
2269 | { "DMIC1", NULL, "DMIC R1" }, | |
2270 | { "DMIC2", NULL, "DMIC L2" }, | |
2271 | { "DMIC2", NULL, "DMIC R2" }, | |
2272 | ||
2273 | { "BST1", NULL, "IN1P" }, | |
2274 | { "BST1", NULL, "IN1N" }, | |
2275 | { "BST1", NULL, "JD Power" }, | |
2276 | { "BST1", NULL, "Mic Det Power" }, | |
2277 | { "BST2", NULL, "IN2P" }, | |
2278 | { "BST2", NULL, "IN2N" }, | |
2279 | ||
2280 | { "INL VOL", NULL, "IN2P" }, | |
2281 | { "INR VOL", NULL, "IN2N" }, | |
2282 | ||
2283 | { "RECMIXL", "HPOL Switch", "HPOL" }, | |
2284 | { "RECMIXL", "INL Switch", "INL VOL" }, | |
2285 | { "RECMIXL", "BST2 Switch", "BST2" }, | |
2286 | { "RECMIXL", "BST1 Switch", "BST1" }, | |
2287 | { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" }, | |
2288 | ||
2289 | { "RECMIXR", "HPOR Switch", "HPOR" }, | |
2290 | { "RECMIXR", "INR Switch", "INR VOL" }, | |
2291 | { "RECMIXR", "BST2 Switch", "BST2" }, | |
2292 | { "RECMIXR", "BST1 Switch", "BST1" }, | |
2293 | { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" }, | |
2294 | ||
2295 | { "ADC L", NULL, "RECMIXL" }, | |
2296 | { "ADC L", NULL, "ADC L power" }, | |
2297 | { "ADC R", NULL, "RECMIXR" }, | |
2298 | { "ADC R", NULL, "ADC R power" }, | |
2299 | ||
2300 | {"DMIC L1", NULL, "DMIC CLK"}, | |
2301 | {"DMIC L1", NULL, "DMIC1 Power"}, | |
2302 | {"DMIC R1", NULL, "DMIC CLK"}, | |
2303 | {"DMIC R1", NULL, "DMIC1 Power"}, | |
2304 | {"DMIC L2", NULL, "DMIC CLK"}, | |
2305 | {"DMIC L2", NULL, "DMIC2 Power"}, | |
2306 | {"DMIC R2", NULL, "DMIC CLK"}, | |
2307 | {"DMIC R2", NULL, "DMIC2 Power"}, | |
2308 | ||
2309 | { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" }, | |
2310 | { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" }, | |
9e268353 | 2311 | { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" }, |
1319b2f6 OC |
2312 | |
2313 | { "Mono DMIC L Mux", "DMIC1", "DMIC L1" }, | |
2314 | { "Mono DMIC L Mux", "DMIC2", "DMIC L2" }, | |
9e268353 | 2315 | { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" }, |
1319b2f6 OC |
2316 | |
2317 | { "Mono DMIC R Mux", "DMIC1", "DMIC R1" }, | |
2318 | { "Mono DMIC R Mux", "DMIC2", "DMIC R2" }, | |
9e268353 | 2319 | { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" }, |
1319b2f6 OC |
2320 | |
2321 | { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" }, | |
2322 | { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" }, | |
2323 | { "Stereo1 ADC L1 Mux", "ADC", "ADC L" }, | |
2324 | { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" }, | |
2325 | ||
2326 | { "Stereo1 ADC R1 Mux", "ADC", "ADC R" }, | |
2327 | { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" }, | |
2328 | { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" }, | |
2329 | { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" }, | |
2330 | ||
2331 | { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" }, | |
2332 | { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, | |
2333 | { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" }, | |
2334 | { "Mono ADC L1 Mux", "ADC", "ADC L" }, | |
2335 | ||
2336 | { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, | |
2337 | { "Mono ADC R1 Mux", "ADC", "ADC R" }, | |
2338 | { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" }, | |
2339 | { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" }, | |
2340 | ||
2341 | { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" }, | |
2342 | { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" }, | |
2343 | { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" }, | |
2344 | { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" }, | |
2345 | ||
2346 | { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" }, | |
2347 | { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" }, | |
2348 | { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2349 | ||
2350 | { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" }, | |
2351 | { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" }, | |
2352 | { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2353 | ||
2354 | { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" }, | |
2355 | { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" }, | |
2356 | { "Mono ADC MIXL", NULL, "adc mono left filter" }, | |
2357 | { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2358 | ||
2359 | { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" }, | |
2360 | { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" }, | |
2361 | { "Mono ADC MIXR", NULL, "adc mono right filter" }, | |
2362 | { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll }, | |
2363 | ||
2364 | { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" }, | |
2365 | { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" }, | |
2366 | { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" }, | |
2367 | ||
2368 | { "IF_ADC1", NULL, "Stereo1 ADC MIXL" }, | |
2369 | { "IF_ADC1", NULL, "Stereo1 ADC MIXR" }, | |
2370 | { "IF_ADC2", NULL, "Mono ADC MIXL" }, | |
2371 | { "IF_ADC2", NULL, "Mono ADC MIXR" }, | |
2372 | { "VAD_ADC", NULL, "VAD ADC Mux" }, | |
2373 | ||
1319b2f6 OC |
2374 | { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" }, |
2375 | { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" }, | |
2376 | { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" }, | |
2377 | ||
2378 | { "IF1 ADC", NULL, "I2S1" }, | |
1319b2f6 OC |
2379 | { "IF2 ADC", NULL, "I2S2" }, |
2380 | { "IF2 ADC", NULL, "IF2 ADC Mux" }, | |
2381 | ||
1319b2f6 OC |
2382 | { "AIF2TX", NULL, "IF2 ADC" }, |
2383 | ||
21ab3f2b | 2384 | { "IF1 DAC0", NULL, "AIF1RX" }, |
1319b2f6 OC |
2385 | { "IF1 DAC1", NULL, "AIF1RX" }, |
2386 | { "IF1 DAC2", NULL, "AIF1RX" }, | |
21ab3f2b | 2387 | { "IF1 DAC3", NULL, "AIF1RX" }, |
1319b2f6 OC |
2388 | { "IF2 DAC", NULL, "AIF2RX" }, |
2389 | ||
21ab3f2b | 2390 | { "IF1 DAC0", NULL, "I2S1" }, |
1319b2f6 OC |
2391 | { "IF1 DAC1", NULL, "I2S1" }, |
2392 | { "IF1 DAC2", NULL, "I2S1" }, | |
21ab3f2b | 2393 | { "IF1 DAC3", NULL, "I2S1" }, |
1319b2f6 OC |
2394 | { "IF2 DAC", NULL, "I2S2" }, |
2395 | ||
1319b2f6 OC |
2396 | { "IF2 DAC L", NULL, "IF2 DAC" }, |
2397 | { "IF2 DAC R", NULL, "IF2 DAC" }, | |
2398 | ||
1319b2f6 | 2399 | { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" }, |
1319b2f6 OC |
2400 | { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" }, |
2401 | ||
2402 | { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" }, | |
2403 | { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" }, | |
2404 | { "DAC1 MIXL", NULL, "dac stereo1 filter" }, | |
2405 | { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" }, | |
2406 | { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" }, | |
2407 | { "DAC1 MIXR", NULL, "dac stereo1 filter" }, | |
2408 | ||
1319b2f6 OC |
2409 | { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" }, |
2410 | { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" }, | |
2411 | { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" }, | |
2412 | { "DAC L2 Volume", NULL, "DAC L2 Mux" }, | |
2413 | { "DAC L2 Volume", NULL, "dac mono left filter" }, | |
2414 | ||
1319b2f6 OC |
2415 | { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" }, |
2416 | { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" }, | |
2417 | { "DAC R2 Mux", "Haptic", "Haptic Generator" }, | |
2418 | { "DAC R2 Volume", NULL, "DAC R2 Mux" }, | |
2419 | { "DAC R2 Volume", NULL, "dac mono right filter" }, | |
2420 | ||
2421 | { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, | |
2422 | { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" }, | |
2423 | { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, | |
2424 | { "Stereo DAC MIXL", NULL, "dac stereo1 filter" }, | |
2425 | { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, | |
2426 | { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" }, | |
2427 | { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, | |
2428 | { "Stereo DAC MIXR", NULL, "dac stereo1 filter" }, | |
2429 | ||
2430 | { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" }, | |
2431 | { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, | |
2432 | { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, | |
2433 | { "Mono DAC MIXL", NULL, "dac mono left filter" }, | |
2434 | { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" }, | |
2435 | { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, | |
2436 | { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, | |
2437 | { "Mono DAC MIXR", NULL, "dac mono right filter" }, | |
2438 | ||
2439 | { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" }, | |
2440 | { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" }, | |
2441 | { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" }, | |
2442 | { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" }, | |
2443 | { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" }, | |
2444 | { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" }, | |
2445 | ||
1319b2f6 | 2446 | { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll }, |
1319b2f6 | 2447 | { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll }, |
1319b2f6 | 2448 | { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll }, |
1319b2f6 OC |
2449 | { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll }, |
2450 | ||
2451 | { "SPK MIXL", "BST1 Switch", "BST1" }, | |
2452 | { "SPK MIXL", "INL Switch", "INL VOL" }, | |
2453 | { "SPK MIXL", "DAC L1 Switch", "DAC L1" }, | |
2454 | { "SPK MIXL", "DAC L2 Switch", "DAC L2" }, | |
2455 | { "SPK MIXR", "BST2 Switch", "BST2" }, | |
2456 | { "SPK MIXR", "INR Switch", "INR VOL" }, | |
2457 | { "SPK MIXR", "DAC R1 Switch", "DAC R1" }, | |
2458 | { "SPK MIXR", "DAC R2 Switch", "DAC R2" }, | |
2459 | ||
2460 | { "OUT MIXL", "BST1 Switch", "BST1" }, | |
2461 | { "OUT MIXL", "INL Switch", "INL VOL" }, | |
2462 | { "OUT MIXL", "DAC L2 Switch", "DAC L2" }, | |
2463 | { "OUT MIXL", "DAC L1 Switch", "DAC L1" }, | |
2464 | ||
2465 | { "OUT MIXR", "BST2 Switch", "BST2" }, | |
2466 | { "OUT MIXR", "INR Switch", "INR VOL" }, | |
2467 | { "OUT MIXR", "DAC R2 Switch", "DAC R2" }, | |
2468 | { "OUT MIXR", "DAC R1 Switch", "DAC R1" }, | |
2469 | ||
2470 | { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" }, | |
2471 | { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" }, | |
2472 | { "HPOVOL MIXL", "INL Switch", "INL VOL" }, | |
2473 | { "HPOVOL MIXL", "BST1 Switch", "BST1" }, | |
2474 | { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" }, | |
2475 | { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" }, | |
2476 | { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" }, | |
2477 | { "HPOVOL MIXR", "INR Switch", "INR VOL" }, | |
2478 | { "HPOVOL MIXR", "BST2 Switch", "BST2" }, | |
2479 | { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" }, | |
2480 | ||
2481 | { "DAC 2", NULL, "DAC L2" }, | |
2482 | { "DAC 2", NULL, "DAC R2" }, | |
2483 | { "DAC 1", NULL, "DAC L1" }, | |
2484 | { "DAC 1", NULL, "DAC R1" }, | |
2485 | { "HPOVOL L", "Switch", "HPOVOL MIXL" }, | |
2486 | { "HPOVOL R", "Switch", "HPOVOL MIXR" }, | |
2487 | { "HPOVOL", NULL, "HPOVOL L" }, | |
2488 | { "HPOVOL", NULL, "HPOVOL R" }, | |
2489 | { "HPO MIX", "DAC1 Switch", "DAC 1" }, | |
2490 | { "HPO MIX", "HPVOL Switch", "HPOVOL" }, | |
2491 | ||
2492 | { "SPKVOL L", "Switch", "SPK MIXL" }, | |
2493 | { "SPKVOL R", "Switch", "SPK MIXR" }, | |
2494 | ||
2495 | { "SPOL MIX", "DAC R1 Switch", "DAC R1" }, | |
2496 | { "SPOL MIX", "DAC L1 Switch", "DAC L1" }, | |
2497 | { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" }, | |
2498 | { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" }, | |
2499 | { "SPOR MIX", "DAC R1 Switch", "DAC R1" }, | |
2500 | { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" }, | |
2501 | ||
2502 | { "LOUT MIX", "DAC L1 Switch", "DAC L1" }, | |
2503 | { "LOUT MIX", "DAC R1 Switch", "DAC R1" }, | |
2504 | { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" }, | |
2505 | { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" }, | |
2506 | ||
2507 | { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" }, | |
2508 | { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" }, | |
2509 | { "PDM1 L Mux", NULL, "PDM1 Power" }, | |
2510 | { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" }, | |
2511 | { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" }, | |
2512 | { "PDM1 R Mux", NULL, "PDM1 Power" }, | |
2513 | ||
2514 | { "HP amp", NULL, "HPO MIX" }, | |
2515 | { "HP amp", NULL, "JD Power" }, | |
2516 | { "HP amp", NULL, "Mic Det Power" }, | |
2517 | { "HP amp", NULL, "LDO2" }, | |
2518 | { "HPOL", NULL, "HP amp" }, | |
2519 | { "HPOR", NULL, "HP amp" }, | |
2520 | ||
2521 | { "LOUT amp", NULL, "LOUT MIX" }, | |
2522 | { "LOUTL", NULL, "LOUT amp" }, | |
2523 | { "LOUTR", NULL, "LOUT amp" }, | |
2524 | ||
2525 | { "PDM1 L", "Switch", "PDM1 L Mux" }, | |
2526 | { "PDM1 R", "Switch", "PDM1 R Mux" }, | |
2527 | ||
2528 | { "PDM1L", NULL, "PDM1 L" }, | |
2529 | { "PDM1R", NULL, "PDM1 R" }, | |
2530 | ||
2531 | { "SPK amp", NULL, "SPOL MIX" }, | |
2532 | { "SPK amp", NULL, "SPOR MIX" }, | |
2533 | { "SPOL", NULL, "SPK amp" }, | |
2534 | { "SPOR", NULL, "SPK amp" }, | |
2535 | }; | |
2536 | ||
5c4ca99d BL |
2537 | static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = { |
2538 | { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"}, | |
2539 | { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, | |
2540 | { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"}, | |
2541 | { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, | |
2542 | ||
2543 | { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"}, | |
2544 | { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"}, | |
2545 | { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"}, | |
2546 | { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"}, | |
2547 | ||
2548 | { "DAC L1", NULL, "A DAC1 L Mux" }, | |
2549 | { "DAC R1", NULL, "A DAC1 R Mux" }, | |
2550 | { "DAC L2", NULL, "A DAC2 L Mux" }, | |
2551 | { "DAC R2", NULL, "A DAC2 R Mux" }, | |
21ab3f2b BL |
2552 | |
2553 | { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, | |
2554 | { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, | |
2555 | { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, | |
2556 | { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, | |
2557 | ||
2558 | { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, | |
2559 | { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, | |
2560 | { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, | |
2561 | { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, | |
2562 | ||
2563 | { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, | |
2564 | { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, | |
2565 | { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, | |
2566 | { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, | |
2567 | ||
2568 | { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" }, | |
2569 | { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" }, | |
2570 | { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" }, | |
2571 | ||
2572 | { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" }, | |
2573 | { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" }, | |
2574 | { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" }, | |
2575 | { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" }, | |
2576 | { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" }, | |
2577 | { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" }, | |
2578 | ||
2579 | { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" }, | |
2580 | { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" }, | |
2581 | { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" }, | |
2582 | { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" }, | |
2583 | { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" }, | |
2584 | { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" }, | |
2585 | ||
2586 | { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" }, | |
2587 | { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" }, | |
2588 | { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" }, | |
2589 | { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" }, | |
2590 | { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" }, | |
2591 | { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" }, | |
2592 | ||
2593 | { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" }, | |
2594 | { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" }, | |
2595 | { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" }, | |
2596 | { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" }, | |
2597 | { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" }, | |
2598 | { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" }, | |
2599 | { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" }, | |
2600 | ||
2601 | { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, | |
2602 | { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, | |
2603 | { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, | |
2604 | { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, | |
2605 | ||
2606 | { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, | |
2607 | { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, | |
2608 | { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, | |
2609 | { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, | |
2610 | ||
2611 | { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, | |
2612 | { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, | |
2613 | { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, | |
2614 | { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, | |
2615 | ||
2616 | { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, | |
2617 | { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, | |
2618 | { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, | |
2619 | { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, | |
2620 | ||
2621 | { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" }, | |
2622 | { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" }, | |
2623 | ||
2624 | { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" }, | |
2625 | { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" }, | |
5c4ca99d BL |
2626 | }; |
2627 | ||
2628 | static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = { | |
2629 | { "DAC L1", NULL, "Stereo DAC MIXL" }, | |
2630 | { "DAC R1", NULL, "Stereo DAC MIXR" }, | |
2631 | { "DAC L2", NULL, "Mono DAC MIXL" }, | |
2632 | { "DAC R2", NULL, "Mono DAC MIXR" }, | |
21ab3f2b BL |
2633 | |
2634 | { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" }, | |
2635 | { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" }, | |
2636 | { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" }, | |
2637 | { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" }, | |
2638 | ||
2639 | { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" }, | |
2640 | { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" }, | |
2641 | { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" }, | |
2642 | { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" }, | |
2643 | ||
2644 | { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" }, | |
2645 | { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" }, | |
2646 | { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" }, | |
2647 | { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" }, | |
2648 | ||
2649 | { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" }, | |
2650 | { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" }, | |
2651 | { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" }, | |
2652 | ||
2653 | { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" }, | |
2654 | { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" }, | |
2655 | { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" }, | |
2656 | { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" }, | |
2657 | { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" }, | |
2658 | ||
2659 | { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" }, | |
2660 | { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" }, | |
2661 | { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" }, | |
2662 | { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" }, | |
2663 | ||
2664 | { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" }, | |
2665 | { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" }, | |
2666 | { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" }, | |
2667 | { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" }, | |
2668 | ||
2669 | { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" }, | |
2670 | { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" }, | |
2671 | { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" }, | |
2672 | { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" }, | |
2673 | ||
2674 | { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" }, | |
2675 | { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" }, | |
2676 | { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" }, | |
2677 | { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" }, | |
2678 | ||
2679 | { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" }, | |
2680 | { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" }, | |
2681 | ||
2682 | { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" }, | |
2683 | { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" }, | |
5c4ca99d BL |
2684 | }; |
2685 | ||
1319b2f6 OC |
2686 | static int rt5645_hw_params(struct snd_pcm_substream *substream, |
2687 | struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) | |
2688 | { | |
2689 | struct snd_soc_codec *codec = dai->codec; | |
2690 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
57bf2736 | 2691 | unsigned int val_len = 0, val_clk, mask_clk, dl_sft; |
1319b2f6 OC |
2692 | int pre_div, bclk_ms, frame_size; |
2693 | ||
2694 | rt5645->lrck[dai->id] = params_rate(params); | |
d92950e7 | 2695 | pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]); |
1319b2f6 OC |
2696 | if (pre_div < 0) { |
2697 | dev_err(codec->dev, "Unsupported clock setting\n"); | |
2698 | return -EINVAL; | |
2699 | } | |
2700 | frame_size = snd_soc_params_to_frame_size(params); | |
2701 | if (frame_size < 0) { | |
2702 | dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size); | |
2703 | return -EINVAL; | |
2704 | } | |
57bf2736 BL |
2705 | |
2706 | switch (rt5645->codec_type) { | |
2707 | case CODEC_TYPE_RT5650: | |
2708 | dl_sft = 4; | |
2709 | break; | |
2710 | default: | |
2711 | dl_sft = 2; | |
2712 | break; | |
2713 | } | |
2714 | ||
1319b2f6 OC |
2715 | bclk_ms = frame_size > 32; |
2716 | rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms); | |
2717 | ||
2718 | dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n", | |
2719 | rt5645->bclk[dai->id], rt5645->lrck[dai->id]); | |
2720 | dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n", | |
2721 | bclk_ms, pre_div, dai->id); | |
2722 | ||
2723 | switch (params_width(params)) { | |
2724 | case 16: | |
2725 | break; | |
2726 | case 20: | |
57bf2736 | 2727 | val_len = 0x1; |
1319b2f6 OC |
2728 | break; |
2729 | case 24: | |
57bf2736 | 2730 | val_len = 0x2; |
1319b2f6 OC |
2731 | break; |
2732 | case 8: | |
57bf2736 | 2733 | val_len = 0x3; |
1319b2f6 OC |
2734 | break; |
2735 | default: | |
2736 | return -EINVAL; | |
2737 | } | |
2738 | ||
2739 | switch (dai->id) { | |
2740 | case RT5645_AIF1: | |
33de3d54 BL |
2741 | mask_clk = RT5645_I2S_PD1_MASK; |
2742 | val_clk = pre_div << RT5645_I2S_PD1_SFT; | |
1319b2f6 | 2743 | snd_soc_update_bits(codec, RT5645_I2S1_SDP, |
57bf2736 | 2744 | (0x3 << dl_sft), (val_len << dl_sft)); |
1319b2f6 OC |
2745 | snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk); |
2746 | break; | |
2747 | case RT5645_AIF2: | |
2748 | mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK; | |
2749 | val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT | | |
2750 | pre_div << RT5645_I2S_PD2_SFT; | |
2751 | snd_soc_update_bits(codec, RT5645_I2S2_SDP, | |
57bf2736 | 2752 | (0x3 << dl_sft), (val_len << dl_sft)); |
1319b2f6 OC |
2753 | snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk); |
2754 | break; | |
2755 | default: | |
2756 | dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); | |
2757 | return -EINVAL; | |
2758 | } | |
2759 | ||
2760 | return 0; | |
2761 | } | |
2762 | ||
2763 | static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
2764 | { | |
2765 | struct snd_soc_codec *codec = dai->codec; | |
2766 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
57bf2736 BL |
2767 | unsigned int reg_val = 0, pol_sft; |
2768 | ||
2769 | switch (rt5645->codec_type) { | |
2770 | case CODEC_TYPE_RT5650: | |
2771 | pol_sft = 8; | |
2772 | break; | |
2773 | default: | |
2774 | pol_sft = 7; | |
2775 | break; | |
2776 | } | |
1319b2f6 OC |
2777 | |
2778 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
2779 | case SND_SOC_DAIFMT_CBM_CFM: | |
2780 | rt5645->master[dai->id] = 1; | |
2781 | break; | |
2782 | case SND_SOC_DAIFMT_CBS_CFS: | |
2783 | reg_val |= RT5645_I2S_MS_S; | |
2784 | rt5645->master[dai->id] = 0; | |
2785 | break; | |
2786 | default: | |
2787 | return -EINVAL; | |
2788 | } | |
2789 | ||
2790 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2791 | case SND_SOC_DAIFMT_NB_NF: | |
2792 | break; | |
2793 | case SND_SOC_DAIFMT_IB_NF: | |
57bf2736 | 2794 | reg_val |= (1 << pol_sft); |
1319b2f6 OC |
2795 | break; |
2796 | default: | |
2797 | return -EINVAL; | |
2798 | } | |
2799 | ||
2800 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
2801 | case SND_SOC_DAIFMT_I2S: | |
2802 | break; | |
2803 | case SND_SOC_DAIFMT_LEFT_J: | |
2804 | reg_val |= RT5645_I2S_DF_LEFT; | |
2805 | break; | |
2806 | case SND_SOC_DAIFMT_DSP_A: | |
2807 | reg_val |= RT5645_I2S_DF_PCM_A; | |
2808 | break; | |
2809 | case SND_SOC_DAIFMT_DSP_B: | |
2810 | reg_val |= RT5645_I2S_DF_PCM_B; | |
2811 | break; | |
2812 | default: | |
2813 | return -EINVAL; | |
2814 | } | |
2815 | switch (dai->id) { | |
2816 | case RT5645_AIF1: | |
2817 | snd_soc_update_bits(codec, RT5645_I2S1_SDP, | |
57bf2736 | 2818 | RT5645_I2S_MS_MASK | (1 << pol_sft) | |
1319b2f6 OC |
2819 | RT5645_I2S_DF_MASK, reg_val); |
2820 | break; | |
8c325704 AL |
2821 | case RT5645_AIF2: |
2822 | snd_soc_update_bits(codec, RT5645_I2S2_SDP, | |
57bf2736 | 2823 | RT5645_I2S_MS_MASK | (1 << pol_sft) | |
1319b2f6 OC |
2824 | RT5645_I2S_DF_MASK, reg_val); |
2825 | break; | |
2826 | default: | |
2827 | dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); | |
2828 | return -EINVAL; | |
2829 | } | |
2830 | return 0; | |
2831 | } | |
2832 | ||
2833 | static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai, | |
2834 | int clk_id, unsigned int freq, int dir) | |
2835 | { | |
2836 | struct snd_soc_codec *codec = dai->codec; | |
2837 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
2838 | unsigned int reg_val = 0; | |
2839 | ||
2840 | if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src) | |
2841 | return 0; | |
2842 | ||
2843 | switch (clk_id) { | |
2844 | case RT5645_SCLK_S_MCLK: | |
2845 | reg_val |= RT5645_SCLK_SRC_MCLK; | |
2846 | break; | |
2847 | case RT5645_SCLK_S_PLL1: | |
2848 | reg_val |= RT5645_SCLK_SRC_PLL1; | |
2849 | break; | |
2850 | case RT5645_SCLK_S_RCCLK: | |
2851 | reg_val |= RT5645_SCLK_SRC_RCCLK; | |
2852 | break; | |
2853 | default: | |
2854 | dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); | |
2855 | return -EINVAL; | |
2856 | } | |
2857 | snd_soc_update_bits(codec, RT5645_GLB_CLK, | |
2858 | RT5645_SCLK_SRC_MASK, reg_val); | |
2859 | rt5645->sysclk = freq; | |
2860 | rt5645->sysclk_src = clk_id; | |
2861 | ||
2862 | dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id); | |
2863 | ||
2864 | return 0; | |
2865 | } | |
2866 | ||
1319b2f6 OC |
2867 | static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, |
2868 | unsigned int freq_in, unsigned int freq_out) | |
2869 | { | |
2870 | struct snd_soc_codec *codec = dai->codec; | |
2871 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
71c7a2d6 | 2872 | struct rl6231_pll_code pll_code; |
1319b2f6 OC |
2873 | int ret; |
2874 | ||
2875 | if (source == rt5645->pll_src && freq_in == rt5645->pll_in && | |
2876 | freq_out == rt5645->pll_out) | |
2877 | return 0; | |
2878 | ||
2879 | if (!freq_in || !freq_out) { | |
2880 | dev_dbg(codec->dev, "PLL disabled\n"); | |
2881 | ||
2882 | rt5645->pll_in = 0; | |
2883 | rt5645->pll_out = 0; | |
2884 | snd_soc_update_bits(codec, RT5645_GLB_CLK, | |
2885 | RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK); | |
2886 | return 0; | |
2887 | } | |
2888 | ||
2889 | switch (source) { | |
2890 | case RT5645_PLL1_S_MCLK: | |
2891 | snd_soc_update_bits(codec, RT5645_GLB_CLK, | |
2892 | RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK); | |
2893 | break; | |
2894 | case RT5645_PLL1_S_BCLK1: | |
2895 | case RT5645_PLL1_S_BCLK2: | |
2896 | switch (dai->id) { | |
2897 | case RT5645_AIF1: | |
2898 | snd_soc_update_bits(codec, RT5645_GLB_CLK, | |
2899 | RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1); | |
2900 | break; | |
2901 | case RT5645_AIF2: | |
2902 | snd_soc_update_bits(codec, RT5645_GLB_CLK, | |
2903 | RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2); | |
2904 | break; | |
2905 | default: | |
2906 | dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id); | |
2907 | return -EINVAL; | |
2908 | } | |
2909 | break; | |
2910 | default: | |
2911 | dev_err(codec->dev, "Unknown PLL source %d\n", source); | |
2912 | return -EINVAL; | |
2913 | } | |
2914 | ||
71c7a2d6 | 2915 | ret = rl6231_pll_calc(freq_in, freq_out, &pll_code); |
1319b2f6 OC |
2916 | if (ret < 0) { |
2917 | dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); | |
2918 | return ret; | |
2919 | } | |
2920 | ||
2921 | dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n", | |
2922 | pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code), | |
2923 | pll_code.n_code, pll_code.k_code); | |
2924 | ||
2925 | snd_soc_write(codec, RT5645_PLL_CTRL1, | |
2926 | pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code); | |
2927 | snd_soc_write(codec, RT5645_PLL_CTRL2, | |
2928 | (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT | | |
2929 | pll_code.m_bp << RT5645_PLL_M_BP_SFT); | |
2930 | ||
2931 | rt5645->pll_in = freq_in; | |
2932 | rt5645->pll_out = freq_out; | |
2933 | rt5645->pll_src = source; | |
2934 | ||
2935 | return 0; | |
2936 | } | |
2937 | ||
2938 | static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, | |
2939 | unsigned int rx_mask, int slots, int slot_width) | |
2940 | { | |
2941 | struct snd_soc_codec *codec = dai->codec; | |
42ce5b8a BL |
2942 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); |
2943 | unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft; | |
2944 | unsigned int mask, val = 0; | |
2945 | ||
2946 | switch (rt5645->codec_type) { | |
2947 | case CODEC_TYPE_RT5650: | |
2948 | en_sft = 15; | |
2949 | i_slot_sft = 10; | |
2950 | o_slot_sft = 8; | |
2951 | i_width_sht = 6; | |
2952 | o_width_sht = 4; | |
2953 | mask = 0x8ff0; | |
2954 | break; | |
2955 | default: | |
2956 | en_sft = 14; | |
2957 | i_slot_sft = o_slot_sft = 12; | |
2958 | i_width_sht = o_width_sht = 10; | |
2959 | mask = 0x7c00; | |
2960 | break; | |
2961 | } | |
850577db | 2962 | if (rx_mask || tx_mask) { |
42ce5b8a BL |
2963 | val |= (1 << en_sft); |
2964 | if (rt5645->codec_type == CODEC_TYPE_RT5645) | |
2965 | snd_soc_update_bits(codec, RT5645_BASS_BACK, | |
2966 | RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB); | |
850577db | 2967 | } |
1319b2f6 OC |
2968 | |
2969 | switch (slots) { | |
2970 | case 4: | |
42ce5b8a | 2971 | val |= (1 << i_slot_sft) | (1 << o_slot_sft); |
1319b2f6 OC |
2972 | break; |
2973 | case 6: | |
42ce5b8a | 2974 | val |= (2 << i_slot_sft) | (2 << o_slot_sft); |
1319b2f6 OC |
2975 | break; |
2976 | case 8: | |
42ce5b8a | 2977 | val |= (3 << i_slot_sft) | (3 << o_slot_sft); |
1319b2f6 OC |
2978 | break; |
2979 | case 2: | |
2980 | default: | |
2981 | break; | |
2982 | } | |
2983 | ||
2984 | switch (slot_width) { | |
2985 | case 20: | |
42ce5b8a | 2986 | val |= (1 << i_width_sht) | (1 << o_width_sht); |
1319b2f6 OC |
2987 | break; |
2988 | case 24: | |
42ce5b8a | 2989 | val |= (2 << i_width_sht) | (2 << o_width_sht); |
1319b2f6 OC |
2990 | break; |
2991 | case 32: | |
42ce5b8a | 2992 | val |= (3 << i_width_sht) | (3 << o_width_sht); |
1319b2f6 OC |
2993 | break; |
2994 | case 16: | |
2995 | default: | |
2996 | break; | |
2997 | } | |
2998 | ||
42ce5b8a | 2999 | snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, mask, val); |
1319b2f6 OC |
3000 | |
3001 | return 0; | |
3002 | } | |
3003 | ||
3004 | static int rt5645_set_bias_level(struct snd_soc_codec *codec, | |
3005 | enum snd_soc_bias_level level) | |
3006 | { | |
6e747d53 BL |
3007 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); |
3008 | ||
1319b2f6 | 3009 | switch (level) { |
0b2e4959 | 3010 | case SND_SOC_BIAS_PREPARE: |
e2ada818 | 3011 | if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) { |
1319b2f6 OC |
3012 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, |
3013 | RT5645_PWR_VREF1 | RT5645_PWR_MB | | |
3014 | RT5645_PWR_BG | RT5645_PWR_VREF2, | |
3015 | RT5645_PWR_VREF1 | RT5645_PWR_MB | | |
3016 | RT5645_PWR_BG | RT5645_PWR_VREF2); | |
3017 | mdelay(10); | |
3018 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
3019 | RT5645_PWR_FV1 | RT5645_PWR_FV2, | |
3020 | RT5645_PWR_FV1 | RT5645_PWR_FV2); | |
3021 | snd_soc_update_bits(codec, RT5645_GEN_CTRL1, | |
3022 | RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); | |
3023 | } | |
3024 | break; | |
3025 | ||
0b2e4959 BL |
3026 | case SND_SOC_BIAS_STANDBY: |
3027 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
3028 | RT5645_PWR_VREF1 | RT5645_PWR_MB | | |
3029 | RT5645_PWR_BG | RT5645_PWR_VREF2, | |
3030 | RT5645_PWR_VREF1 | RT5645_PWR_MB | | |
3031 | RT5645_PWR_BG | RT5645_PWR_VREF2); | |
3032 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, | |
3033 | RT5645_PWR_FV1 | RT5645_PWR_FV2, | |
3034 | RT5645_PWR_FV1 | RT5645_PWR_FV2); | |
c962d03b OC |
3035 | if (rt5645->en_button_func && |
3036 | snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) | |
3037 | queue_delayed_work(system_power_efficient_wq, | |
3038 | &rt5645->jack_detect_work, msecs_to_jiffies(0)); | |
0b2e4959 BL |
3039 | break; |
3040 | ||
1319b2f6 OC |
3041 | case SND_SOC_BIAS_OFF: |
3042 | snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100); | |
6e747d53 BL |
3043 | if (!rt5645->en_button_func) |
3044 | snd_soc_update_bits(codec, RT5645_GEN_CTRL1, | |
3045 | RT5645_DIG_GATE_CTRL, 0); | |
0b2e4959 BL |
3046 | snd_soc_update_bits(codec, RT5645_PWR_ANLG1, |
3047 | RT5645_PWR_VREF1 | RT5645_PWR_MB | | |
3048 | RT5645_PWR_BG | RT5645_PWR_VREF2 | | |
3049 | RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0); | |
1319b2f6 OC |
3050 | break; |
3051 | ||
3052 | default: | |
3053 | break; | |
3054 | } | |
1319b2f6 OC |
3055 | |
3056 | return 0; | |
3057 | } | |
3058 | ||
6e747d53 BL |
3059 | static void rt5645_enable_push_button_irq(struct snd_soc_codec *codec, |
3060 | bool enable) | |
f3fa1bbd | 3061 | { |
e2ada818 | 3062 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
f3fa1bbd | 3063 | |
6e747d53 | 3064 | if (enable) { |
a4e3c5fa NB |
3065 | snd_soc_dapm_force_enable_pin(dapm, "ADC L power"); |
3066 | snd_soc_dapm_force_enable_pin(dapm, "ADC R power"); | |
3067 | snd_soc_dapm_sync(dapm); | |
22f5d9f8 | 3068 | |
15b0f4d4 | 3069 | snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD1, 0x3, 0x3); |
6e747d53 BL |
3070 | snd_soc_update_bits(codec, |
3071 | RT5645_INT_IRQ_ST, 0x8, 0x8); | |
3072 | snd_soc_update_bits(codec, | |
3073 | RT5650_4BTN_IL_CMD2, 0x8000, 0x8000); | |
3074 | snd_soc_read(codec, RT5650_4BTN_IL_CMD1); | |
3075 | pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1, | |
3076 | snd_soc_read(codec, RT5650_4BTN_IL_CMD1)); | |
3077 | } else { | |
3078 | snd_soc_update_bits(codec, RT5650_4BTN_IL_CMD2, 0x8000, 0x0); | |
3079 | snd_soc_update_bits(codec, RT5645_INT_IRQ_ST, 0x8, 0x0); | |
22f5d9f8 | 3080 | |
a4e3c5fa NB |
3081 | snd_soc_dapm_disable_pin(dapm, "ADC L power"); |
3082 | snd_soc_dapm_disable_pin(dapm, "ADC R power"); | |
3083 | snd_soc_dapm_sync(dapm); | |
75945896 | 3084 | } |
6e747d53 | 3085 | } |
f3fa1bbd | 3086 | |
6e747d53 BL |
3087 | static int rt5645_jack_detect(struct snd_soc_codec *codec, int jack_insert) |
3088 | { | |
e2ada818 | 3089 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
6e747d53 BL |
3090 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); |
3091 | unsigned int val; | |
f3fa1bbd | 3092 | |
6e747d53 | 3093 | if (jack_insert) { |
05a9b46a JL |
3094 | regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0006); |
3095 | ||
b14c9174 NB |
3096 | /* for jack type detect */ |
3097 | snd_soc_dapm_force_enable_pin(dapm, "LDO2"); | |
3098 | snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power"); | |
3099 | snd_soc_dapm_sync(dapm); | |
3100 | if (!dapm->card->instantiated) { | |
6e747d53 BL |
3101 | /* Power up necessary bits for JD if dapm is |
3102 | not ready yet */ | |
05a9b46a JL |
3103 | regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1, |
3104 | RT5645_PWR_MB | RT5645_PWR_VREF2, | |
3105 | RT5645_PWR_MB | RT5645_PWR_VREF2); | |
3106 | regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER, | |
6e747d53 | 3107 | RT5645_PWR_LDO2, RT5645_PWR_LDO2); |
05a9b46a | 3108 | regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL, |
6e747d53 BL |
3109 | RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET); |
3110 | } | |
f3fa1bbd | 3111 | |
05a9b46a | 3112 | regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0); |
f2988afe OC |
3113 | regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, |
3114 | RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); | |
3115 | regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, | |
3116 | RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN); | |
05a9b46a | 3117 | msleep(100); |
f2988afe OC |
3118 | regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, |
3119 | RT5645_CBJ_MN_JD, 0); | |
05a9b46a | 3120 | |
8db7f56d | 3121 | msleep(600); |
05a9b46a JL |
3122 | regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val); |
3123 | val &= 0x7; | |
f3fa1bbd OC |
3124 | dev_dbg(codec->dev, "val = %d\n", val); |
3125 | ||
6e747d53 BL |
3126 | if (val == 1 || val == 2) { |
3127 | rt5645->jack_type = SND_JACK_HEADSET; | |
3128 | if (rt5645->en_button_func) { | |
6e747d53 BL |
3129 | rt5645_enable_push_button_irq(codec, true); |
3130 | } | |
3131 | } else { | |
b14c9174 NB |
3132 | snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); |
3133 | snd_soc_dapm_sync(dapm); | |
6e747d53 BL |
3134 | rt5645->jack_type = SND_JACK_HEADPHONE; |
3135 | } | |
917536ae JL |
3136 | if (rt5645->pdata.jd_invert) |
3137 | regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, | |
7ff6319e | 3138 | RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR); |
6e747d53 BL |
3139 | } else { /* jack out */ |
3140 | rt5645->jack_type = 0; | |
a4e3c5fa | 3141 | |
fce97b4d OC |
3142 | regmap_update_bits(rt5645->regmap, RT5645_HP_VOL, |
3143 | RT5645_L_MUTE | RT5645_R_MUTE, | |
3144 | RT5645_L_MUTE | RT5645_R_MUTE); | |
f2988afe OC |
3145 | regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, |
3146 | RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD); | |
3147 | regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, | |
3148 | RT5645_CBJ_BST1_EN, 0); | |
8db7f56d | 3149 | |
6e747d53 BL |
3150 | if (rt5645->en_button_func) |
3151 | rt5645_enable_push_button_irq(codec, false); | |
a4e3c5fa NB |
3152 | |
3153 | if (rt5645->pdata.jd_mode == 0) | |
3154 | snd_soc_dapm_disable_pin(dapm, "LDO2"); | |
3155 | snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); | |
3156 | snd_soc_dapm_sync(dapm); | |
917536ae JL |
3157 | if (rt5645->pdata.jd_invert) |
3158 | regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, | |
7ff6319e | 3159 | RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); |
f3fa1bbd OC |
3160 | } |
3161 | ||
6e747d53 | 3162 | return rt5645->jack_type; |
f3fa1bbd OC |
3163 | } |
3164 | ||
f312bc59 NB |
3165 | static int rt5645_button_detect(struct snd_soc_codec *codec) |
3166 | { | |
3167 | int btn_type, val; | |
3168 | ||
3169 | val = snd_soc_read(codec, RT5650_4BTN_IL_CMD1); | |
3170 | pr_debug("val=0x%x\n", val); | |
3171 | btn_type = val & 0xfff0; | |
3172 | snd_soc_write(codec, RT5650_4BTN_IL_CMD1, val); | |
3173 | ||
3174 | return btn_type; | |
3175 | } | |
3176 | ||
345b0f50 | 3177 | static irqreturn_t rt5645_irq(int irq, void *data); |
d5660422 | 3178 | |
f3fa1bbd | 3179 | int rt5645_set_jack_detect(struct snd_soc_codec *codec, |
6e747d53 BL |
3180 | struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack, |
3181 | struct snd_soc_jack *btn_jack) | |
f3fa1bbd OC |
3182 | { |
3183 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
3184 | ||
471f208a BL |
3185 | rt5645->hp_jack = hp_jack; |
3186 | rt5645->mic_jack = mic_jack; | |
6e747d53 BL |
3187 | rt5645->btn_jack = btn_jack; |
3188 | if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) { | |
3189 | rt5645->en_button_func = true; | |
3190 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3191 | RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); | |
6e747d53 BL |
3192 | regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1, |
3193 | RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); | |
3194 | } | |
345b0f50 | 3195 | rt5645_irq(0, rt5645); |
f3fa1bbd OC |
3196 | |
3197 | return 0; | |
3198 | } | |
3199 | EXPORT_SYMBOL_GPL(rt5645_set_jack_detect); | |
3200 | ||
cd6e82b8 OC |
3201 | static void rt5645_jack_detect_work(struct work_struct *work) |
3202 | { | |
3203 | struct rt5645_priv *rt5645 = | |
3204 | container_of(work, struct rt5645_priv, jack_detect_work.work); | |
6e747d53 BL |
3205 | int val, btn_type, gpio_state = 0, report = 0; |
3206 | ||
f2a5ded3 | 3207 | if (!rt5645->codec) |
f136dce4 | 3208 | return; |
f2a5ded3 | 3209 | |
6e747d53 BL |
3210 | switch (rt5645->pdata.jd_mode) { |
3211 | case 0: /* Not using rt5645 JD */ | |
0b0cefc8 OC |
3212 | if (rt5645->gpiod_hp_det) { |
3213 | gpio_state = gpiod_get_value(rt5645->gpiod_hp_det); | |
3214 | dev_dbg(rt5645->codec->dev, "gpio_state = %d\n", | |
3215 | gpio_state); | |
3216 | report = rt5645_jack_detect(rt5645->codec, gpio_state); | |
6e747d53 BL |
3217 | } |
3218 | snd_soc_jack_report(rt5645->hp_jack, | |
3219 | report, SND_JACK_HEADPHONE); | |
3220 | snd_soc_jack_report(rt5645->mic_jack, | |
3221 | report, SND_JACK_MICROPHONE); | |
f312bc59 | 3222 | return; |
6e747d53 BL |
3223 | case 1: /* 2 port */ |
3224 | val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0070; | |
3225 | break; | |
3226 | default: /* 1 port */ | |
3227 | val = snd_soc_read(rt5645->codec, RT5645_A_JD_CTRL1) & 0x0020; | |
3228 | break; | |
3229 | ||
3230 | } | |
3231 | ||
3232 | switch (val) { | |
3233 | /* jack in */ | |
3234 | case 0x30: /* 2 port */ | |
3235 | case 0x0: /* 1 port or 2 port */ | |
3236 | if (rt5645->jack_type == 0) { | |
3237 | report = rt5645_jack_detect(rt5645->codec, 1); | |
3238 | /* for push button and jack out */ | |
3239 | break; | |
3240 | } | |
3241 | btn_type = 0; | |
3242 | if (snd_soc_read(rt5645->codec, RT5645_INT_IRQ_ST) & 0x4) { | |
3243 | /* button pressed */ | |
3244 | report = SND_JACK_HEADSET; | |
3245 | btn_type = rt5645_button_detect(rt5645->codec); | |
3246 | /* rt5650 can report three kinds of button behavior, | |
3247 | one click, double click and hold. However, | |
3248 | currently we will report button pressed/released | |
3249 | event. So all the three button behaviors are | |
3250 | treated as button pressed. */ | |
3251 | switch (btn_type) { | |
3252 | case 0x8000: | |
3253 | case 0x4000: | |
3254 | case 0x2000: | |
3255 | report |= SND_JACK_BTN_0; | |
3256 | break; | |
3257 | case 0x1000: | |
3258 | case 0x0800: | |
3259 | case 0x0400: | |
3260 | report |= SND_JACK_BTN_1; | |
3261 | break; | |
3262 | case 0x0200: | |
3263 | case 0x0100: | |
3264 | case 0x0080: | |
3265 | report |= SND_JACK_BTN_2; | |
3266 | break; | |
3267 | case 0x0040: | |
3268 | case 0x0020: | |
3269 | case 0x0010: | |
3270 | report |= SND_JACK_BTN_3; | |
3271 | break; | |
3272 | case 0x0000: /* unpressed */ | |
3273 | break; | |
3274 | default: | |
3275 | dev_err(rt5645->codec->dev, | |
3276 | "Unexpected button code 0x%04x\n", | |
3277 | btn_type); | |
3278 | break; | |
3279 | } | |
3280 | } | |
3281 | if (btn_type == 0)/* button release */ | |
3282 | report = rt5645->jack_type; | |
7ff6319e BL |
3283 | else { |
3284 | if (rt5645->pdata.jd_invert) { | |
3285 | mod_timer(&rt5645->btn_check_timer, | |
3286 | msecs_to_jiffies(100)); | |
3287 | } | |
3288 | } | |
6e747d53 BL |
3289 | |
3290 | break; | |
3291 | /* jack out */ | |
3292 | case 0x70: /* 2 port */ | |
3293 | case 0x10: /* 2 port */ | |
3294 | case 0x20: /* 1 port */ | |
3295 | report = 0; | |
3296 | snd_soc_update_bits(rt5645->codec, | |
3297 | RT5645_INT_IRQ_ST, 0x1, 0x0); | |
3298 | rt5645_jack_detect(rt5645->codec, 0); | |
3299 | break; | |
3300 | default: | |
3301 | break; | |
3302 | } | |
3303 | ||
3304 | snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE); | |
3305 | snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE); | |
3306 | if (rt5645->en_button_func) | |
3307 | snd_soc_jack_report(rt5645->btn_jack, | |
e0b5d906 BL |
3308 | report, SND_JACK_BTN_0 | SND_JACK_BTN_1 | |
3309 | SND_JACK_BTN_2 | SND_JACK_BTN_3); | |
f312bc59 | 3310 | } |
6e747d53 | 3311 | |
7099ee85 OC |
3312 | static void rt5645_rcclock_work(struct work_struct *work) |
3313 | { | |
3314 | struct rt5645_priv *rt5645 = | |
3315 | container_of(work, struct rt5645_priv, rcclock_work.work); | |
3316 | ||
3317 | regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, | |
3318 | RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD); | |
3319 | } | |
3320 | ||
f312bc59 NB |
3321 | static irqreturn_t rt5645_irq(int irq, void *data) |
3322 | { | |
3323 | struct rt5645_priv *rt5645 = data; | |
3324 | ||
3325 | queue_delayed_work(system_power_efficient_wq, | |
3326 | &rt5645->jack_detect_work, msecs_to_jiffies(250)); | |
6e747d53 | 3327 | |
f312bc59 | 3328 | return IRQ_HANDLED; |
6e747d53 BL |
3329 | } |
3330 | ||
7ff6319e BL |
3331 | static void rt5645_btn_check_callback(unsigned long data) |
3332 | { | |
3333 | struct rt5645_priv *rt5645 = (struct rt5645_priv *)data; | |
3334 | ||
3335 | queue_delayed_work(system_power_efficient_wq, | |
3336 | &rt5645->jack_detect_work, msecs_to_jiffies(5)); | |
3337 | } | |
3338 | ||
1319b2f6 OC |
3339 | static int rt5645_probe(struct snd_soc_codec *codec) |
3340 | { | |
e2ada818 | 3341 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
1319b2f6 OC |
3342 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); |
3343 | ||
3344 | rt5645->codec = codec; | |
3345 | ||
5c4ca99d BL |
3346 | switch (rt5645->codec_type) { |
3347 | case CODEC_TYPE_RT5645: | |
f2a76385 | 3348 | snd_soc_dapm_new_controls(dapm, |
83c09290 BL |
3349 | rt5645_specific_dapm_widgets, |
3350 | ARRAY_SIZE(rt5645_specific_dapm_widgets)); | |
e2ada818 | 3351 | snd_soc_dapm_add_routes(dapm, |
5c4ca99d BL |
3352 | rt5645_specific_dapm_routes, |
3353 | ARRAY_SIZE(rt5645_specific_dapm_routes)); | |
3354 | break; | |
3355 | case CODEC_TYPE_RT5650: | |
e2ada818 | 3356 | snd_soc_dapm_new_controls(dapm, |
5c4ca99d BL |
3357 | rt5650_specific_dapm_widgets, |
3358 | ARRAY_SIZE(rt5650_specific_dapm_widgets)); | |
e2ada818 | 3359 | snd_soc_dapm_add_routes(dapm, |
5c4ca99d BL |
3360 | rt5650_specific_dapm_routes, |
3361 | ARRAY_SIZE(rt5650_specific_dapm_routes)); | |
3362 | break; | |
3363 | } | |
3364 | ||
bd1204cb | 3365 | snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); |
1319b2f6 | 3366 | |
bb656add | 3367 | /* for JD function */ |
ac4fc3ee | 3368 | if (rt5645->pdata.jd_mode) { |
e2ada818 LPC |
3369 | snd_soc_dapm_force_enable_pin(dapm, "JD Power"); |
3370 | snd_soc_dapm_force_enable_pin(dapm, "LDO2"); | |
3371 | snd_soc_dapm_sync(dapm); | |
bb656add BL |
3372 | } |
3373 | ||
be77b38a OC |
3374 | rt5645->eq_param = devm_kzalloc(codec->dev, |
3375 | RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s), GFP_KERNEL); | |
3376 | ||
1319b2f6 OC |
3377 | return 0; |
3378 | } | |
3379 | ||
3380 | static int rt5645_remove(struct snd_soc_codec *codec) | |
3381 | { | |
3382 | rt5645_reset(codec); | |
3383 | return 0; | |
3384 | } | |
3385 | ||
3386 | #ifdef CONFIG_PM | |
3387 | static int rt5645_suspend(struct snd_soc_codec *codec) | |
3388 | { | |
3389 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
3390 | ||
3391 | regcache_cache_only(rt5645->regmap, true); | |
3392 | regcache_mark_dirty(rt5645->regmap); | |
3393 | ||
3394 | return 0; | |
3395 | } | |
3396 | ||
3397 | static int rt5645_resume(struct snd_soc_codec *codec) | |
3398 | { | |
3399 | struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); | |
3400 | ||
3401 | regcache_cache_only(rt5645->regmap, false); | |
0f776efd | 3402 | regcache_sync(rt5645->regmap); |
1319b2f6 OC |
3403 | |
3404 | return 0; | |
3405 | } | |
3406 | #else | |
3407 | #define rt5645_suspend NULL | |
3408 | #define rt5645_resume NULL | |
3409 | #endif | |
3410 | ||
3411 | #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000 | |
3412 | #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
3413 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) | |
3414 | ||
64793047 | 3415 | static const struct snd_soc_dai_ops rt5645_aif_dai_ops = { |
1319b2f6 OC |
3416 | .hw_params = rt5645_hw_params, |
3417 | .set_fmt = rt5645_set_dai_fmt, | |
3418 | .set_sysclk = rt5645_set_dai_sysclk, | |
3419 | .set_tdm_slot = rt5645_set_tdm_slot, | |
3420 | .set_pll = rt5645_set_dai_pll, | |
3421 | }; | |
3422 | ||
9e22f782 | 3423 | static struct snd_soc_dai_driver rt5645_dai[] = { |
1319b2f6 OC |
3424 | { |
3425 | .name = "rt5645-aif1", | |
3426 | .id = RT5645_AIF1, | |
3427 | .playback = { | |
3428 | .stream_name = "AIF1 Playback", | |
3429 | .channels_min = 1, | |
3430 | .channels_max = 2, | |
3431 | .rates = RT5645_STEREO_RATES, | |
3432 | .formats = RT5645_FORMATS, | |
3433 | }, | |
3434 | .capture = { | |
3435 | .stream_name = "AIF1 Capture", | |
3436 | .channels_min = 1, | |
fbe039bb | 3437 | .channels_max = 4, |
1319b2f6 OC |
3438 | .rates = RT5645_STEREO_RATES, |
3439 | .formats = RT5645_FORMATS, | |
3440 | }, | |
3441 | .ops = &rt5645_aif_dai_ops, | |
3442 | }, | |
3443 | { | |
3444 | .name = "rt5645-aif2", | |
3445 | .id = RT5645_AIF2, | |
3446 | .playback = { | |
3447 | .stream_name = "AIF2 Playback", | |
3448 | .channels_min = 1, | |
3449 | .channels_max = 2, | |
3450 | .rates = RT5645_STEREO_RATES, | |
3451 | .formats = RT5645_FORMATS, | |
3452 | }, | |
3453 | .capture = { | |
3454 | .stream_name = "AIF2 Capture", | |
3455 | .channels_min = 1, | |
3456 | .channels_max = 2, | |
3457 | .rates = RT5645_STEREO_RATES, | |
3458 | .formats = RT5645_FORMATS, | |
3459 | }, | |
3460 | .ops = &rt5645_aif_dai_ops, | |
3461 | }, | |
3462 | }; | |
3463 | ||
3464 | static struct snd_soc_codec_driver soc_codec_dev_rt5645 = { | |
3465 | .probe = rt5645_probe, | |
3466 | .remove = rt5645_remove, | |
3467 | .suspend = rt5645_suspend, | |
3468 | .resume = rt5645_resume, | |
3469 | .set_bias_level = rt5645_set_bias_level, | |
3470 | .idle_bias_off = true, | |
3471 | .controls = rt5645_snd_controls, | |
3472 | .num_controls = ARRAY_SIZE(rt5645_snd_controls), | |
3473 | .dapm_widgets = rt5645_dapm_widgets, | |
3474 | .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets), | |
3475 | .dapm_routes = rt5645_dapm_routes, | |
3476 | .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes), | |
3477 | }; | |
3478 | ||
3479 | static const struct regmap_config rt5645_regmap = { | |
3480 | .reg_bits = 8, | |
3481 | .val_bits = 16, | |
afefc128 | 3482 | .use_single_rw = true, |
1319b2f6 OC |
3483 | .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * |
3484 | RT5645_PR_SPACING), | |
3485 | .volatile_reg = rt5645_volatile_register, | |
3486 | .readable_reg = rt5645_readable_register, | |
3487 | ||
3488 | .cache_type = REGCACHE_RBTREE, | |
3489 | .reg_defaults = rt5645_reg, | |
3490 | .num_reg_defaults = ARRAY_SIZE(rt5645_reg), | |
3491 | .ranges = rt5645_ranges, | |
3492 | .num_ranges = ARRAY_SIZE(rt5645_ranges), | |
3493 | }; | |
3494 | ||
49abc6cd BL |
3495 | static const struct regmap_config rt5650_regmap = { |
3496 | .reg_bits = 8, | |
3497 | .val_bits = 16, | |
3498 | .use_single_rw = true, | |
3499 | .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) * | |
3500 | RT5645_PR_SPACING), | |
3501 | .volatile_reg = rt5645_volatile_register, | |
3502 | .readable_reg = rt5645_readable_register, | |
3503 | ||
3504 | .cache_type = REGCACHE_RBTREE, | |
3505 | .reg_defaults = rt5650_reg, | |
3506 | .num_reg_defaults = ARRAY_SIZE(rt5650_reg), | |
3507 | .ranges = rt5645_ranges, | |
3508 | .num_ranges = ARRAY_SIZE(rt5645_ranges), | |
3509 | }; | |
3510 | ||
3511 | static const struct regmap_config temp_regmap = { | |
3512 | .name="nocache", | |
3513 | .reg_bits = 8, | |
3514 | .val_bits = 16, | |
3515 | .use_single_rw = true, | |
3516 | .max_register = RT5645_VENDOR_ID2 + 1, | |
3517 | .cache_type = REGCACHE_NONE, | |
3518 | }; | |
3519 | ||
1319b2f6 OC |
3520 | static const struct i2c_device_id rt5645_i2c_id[] = { |
3521 | { "rt5645", 0 }, | |
5c4ca99d | 3522 | { "rt5650", 0 }, |
1319b2f6 OC |
3523 | { } |
3524 | }; | |
3525 | MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id); | |
3526 | ||
3168c201 | 3527 | #ifdef CONFIG_ACPI |
e2973769 | 3528 | static const struct acpi_device_id rt5645_acpi_match[] = { |
3168c201 FY |
3529 | { "10EC5645", 0 }, |
3530 | { "10EC5650", 0 }, | |
3531 | {}, | |
3532 | }; | |
3533 | MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match); | |
3534 | #endif | |
3535 | ||
9761c0f6 | 3536 | static struct rt5645_platform_data general_platform_data = { |
ac4fc3ee | 3537 | .dmic1_data_pin = RT5645_DMIC1_DISABLE, |
78c34fd4 | 3538 | .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, |
78c34fd4 FY |
3539 | .jd_mode = 3, |
3540 | }; | |
3541 | ||
0bc7d10c | 3542 | static const struct dmi_system_id dmi_platform_intel_braswell[] = { |
78c34fd4 FY |
3543 | { |
3544 | .ident = "Intel Strago", | |
78c34fd4 FY |
3545 | .matches = { |
3546 | DMI_MATCH(DMI_PRODUCT_NAME, "Strago"), | |
3547 | }, | |
3548 | }, | |
c1713485 | 3549 | { |
9761c0f6 | 3550 | .ident = "Google Chrome", |
6b3cecd1 | 3551 | .matches = { |
9761c0f6 | 3552 | DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), |
6b3cecd1 BL |
3553 | }, |
3554 | }, | |
78c34fd4 FY |
3555 | { } |
3556 | }; | |
3557 | ||
e9159e75 JL |
3558 | static struct rt5645_platform_data buddy_platform_data = { |
3559 | .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5, | |
3560 | .dmic2_data_pin = RT5645_DMIC_DATA_IN2P, | |
3561 | .jd_mode = 3, | |
917536ae | 3562 | .jd_invert = true, |
e9159e75 JL |
3563 | }; |
3564 | ||
dc542fb4 | 3565 | static struct dmi_system_id dmi_platform_intel_broadwell[] = { |
e9159e75 JL |
3566 | { |
3567 | .ident = "Chrome Buddy", | |
e9159e75 JL |
3568 | .matches = { |
3569 | DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"), | |
3570 | }, | |
3571 | }, | |
3572 | { } | |
3573 | }; | |
3574 | ||
9761c0f6 BL |
3575 | static bool rt5645_check_dp(struct device *dev) |
3576 | { | |
3577 | if (device_property_present(dev, "realtek,in2-differential") || | |
3578 | device_property_present(dev, "realtek,dmic1-data-pin") || | |
3579 | device_property_present(dev, "realtek,dmic2-data-pin") || | |
3580 | device_property_present(dev, "realtek,jd-mode")) | |
3581 | return true; | |
3582 | ||
3583 | return false; | |
3584 | } | |
e9159e75 | 3585 | |
48edaa4b OC |
3586 | static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev) |
3587 | { | |
3588 | rt5645->pdata.in2_diff = device_property_read_bool(dev, | |
3589 | "realtek,in2-differential"); | |
3590 | device_property_read_u32(dev, | |
3591 | "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin); | |
3592 | device_property_read_u32(dev, | |
3593 | "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin); | |
3594 | device_property_read_u32(dev, | |
3595 | "realtek,jd-mode", &rt5645->pdata.jd_mode); | |
3596 | ||
3597 | return 0; | |
3598 | } | |
3599 | ||
1319b2f6 OC |
3600 | static int rt5645_i2c_probe(struct i2c_client *i2c, |
3601 | const struct i2c_device_id *id) | |
3602 | { | |
3603 | struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev); | |
3604 | struct rt5645_priv *rt5645; | |
9fc114c5 | 3605 | int ret, i; |
1319b2f6 | 3606 | unsigned int val; |
49abc6cd | 3607 | struct regmap *regmap; |
1319b2f6 OC |
3608 | |
3609 | rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv), | |
3610 | GFP_KERNEL); | |
3611 | if (rt5645 == NULL) | |
3612 | return -ENOMEM; | |
3613 | ||
f3fa1bbd | 3614 | rt5645->i2c = i2c; |
1319b2f6 OC |
3615 | i2c_set_clientdata(i2c, rt5645); |
3616 | ||
48edaa4b | 3617 | if (pdata) |
1319b2f6 | 3618 | rt5645->pdata = *pdata; |
9761c0f6 BL |
3619 | else if (dmi_check_system(dmi_platform_intel_broadwell)) |
3620 | rt5645->pdata = buddy_platform_data; | |
3621 | else if (rt5645_check_dp(&i2c->dev)) | |
48edaa4b | 3622 | rt5645_parse_dt(rt5645, &i2c->dev); |
9761c0f6 BL |
3623 | else if (dmi_check_system(dmi_platform_intel_braswell)) |
3624 | rt5645->pdata = general_platform_data; | |
1319b2f6 | 3625 | |
25c8888a AL |
3626 | rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect", |
3627 | GPIOD_IN); | |
0b0cefc8 OC |
3628 | |
3629 | if (IS_ERR(rt5645->gpiod_hp_det)) { | |
0b0cefc8 | 3630 | dev_err(&i2c->dev, "failed to initialize gpiod\n"); |
25c8888a | 3631 | return PTR_ERR(rt5645->gpiod_hp_det); |
0b0cefc8 OC |
3632 | } |
3633 | ||
9fc114c5 KC |
3634 | for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++) |
3635 | rt5645->supplies[i].supply = rt5645_supply_names[i]; | |
3636 | ||
3637 | ret = devm_regulator_bulk_get(&i2c->dev, | |
3638 | ARRAY_SIZE(rt5645->supplies), | |
3639 | rt5645->supplies); | |
3640 | if (ret) { | |
3641 | dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); | |
3642 | return ret; | |
3643 | } | |
3644 | ||
3645 | ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies), | |
3646 | rt5645->supplies); | |
3647 | if (ret) { | |
3648 | dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); | |
3649 | return ret; | |
3650 | } | |
3651 | ||
49abc6cd BL |
3652 | regmap = devm_regmap_init_i2c(i2c, &temp_regmap); |
3653 | if (IS_ERR(regmap)) { | |
3654 | ret = PTR_ERR(regmap); | |
3655 | dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n", | |
3656 | ret); | |
3657 | return ret; | |
3658 | } | |
3659 | regmap_read(regmap, RT5645_VENDOR_ID2, &val); | |
5c4ca99d BL |
3660 | |
3661 | switch (val) { | |
3662 | case RT5645_DEVICE_ID: | |
49abc6cd | 3663 | rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap); |
5c4ca99d BL |
3664 | rt5645->codec_type = CODEC_TYPE_RT5645; |
3665 | break; | |
3666 | case RT5650_DEVICE_ID: | |
49abc6cd | 3667 | rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap); |
5c4ca99d BL |
3668 | rt5645->codec_type = CODEC_TYPE_RT5650; |
3669 | break; | |
3670 | default: | |
1319b2f6 | 3671 | dev_err(&i2c->dev, |
8f68e80f | 3672 | "Device with ID register %#x is not rt5645 or rt5650\n", |
5c4ca99d | 3673 | val); |
9fc114c5 KC |
3674 | ret = -ENODEV; |
3675 | goto err_enable; | |
d12d6c4e JL |
3676 | } |
3677 | ||
49abc6cd BL |
3678 | if (IS_ERR(rt5645->regmap)) { |
3679 | ret = PTR_ERR(rt5645->regmap); | |
3680 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
3681 | ret); | |
3682 | return ret; | |
3683 | } | |
3684 | ||
1319b2f6 OC |
3685 | regmap_write(rt5645->regmap, RT5645_RESET, 0); |
3686 | ||
3687 | ret = regmap_register_patch(rt5645->regmap, init_list, | |
3688 | ARRAY_SIZE(init_list)); | |
3689 | if (ret != 0) | |
3690 | dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret); | |
3691 | ||
5c4ca99d BL |
3692 | if (rt5645->codec_type == CODEC_TYPE_RT5650) { |
3693 | ret = regmap_register_patch(rt5645->regmap, rt5650_init_list, | |
3694 | ARRAY_SIZE(rt5650_init_list)); | |
3695 | if (ret != 0) | |
3696 | dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n", | |
3697 | ret); | |
3698 | } | |
3699 | ||
1319b2f6 OC |
3700 | if (rt5645->pdata.in2_diff) |
3701 | regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL, | |
3702 | RT5645_IN_DF2, RT5645_IN_DF2); | |
3703 | ||
ac4fc3ee | 3704 | if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) { |
1319b2f6 OC |
3705 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, |
3706 | RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL); | |
ac4fc3ee BL |
3707 | } |
3708 | switch (rt5645->pdata.dmic1_data_pin) { | |
3709 | case RT5645_DMIC_DATA_IN2N: | |
3710 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3711 | RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N); | |
3712 | break; | |
1319b2f6 | 3713 | |
ac4fc3ee | 3714 | case RT5645_DMIC_DATA_GPIO5: |
a094935e BL |
3715 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, |
3716 | RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO); | |
ac4fc3ee BL |
3717 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, |
3718 | RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5); | |
3719 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3720 | RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA); | |
3721 | break; | |
1319b2f6 | 3722 | |
ac4fc3ee BL |
3723 | case RT5645_DMIC_DATA_GPIO11: |
3724 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3725 | RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11); | |
3726 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3727 | RT5645_GP11_PIN_MASK, | |
3728 | RT5645_GP11_PIN_DMIC1_SDA); | |
3729 | break; | |
1319b2f6 | 3730 | |
ac4fc3ee BL |
3731 | default: |
3732 | break; | |
3733 | } | |
1319b2f6 | 3734 | |
ac4fc3ee BL |
3735 | switch (rt5645->pdata.dmic2_data_pin) { |
3736 | case RT5645_DMIC_DATA_IN2P: | |
3737 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3738 | RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P); | |
3739 | break; | |
1319b2f6 | 3740 | |
ac4fc3ee BL |
3741 | case RT5645_DMIC_DATA_GPIO6: |
3742 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3743 | RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6); | |
3744 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3745 | RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA); | |
3746 | break; | |
1319b2f6 | 3747 | |
ac4fc3ee BL |
3748 | case RT5645_DMIC_DATA_GPIO10: |
3749 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3750 | RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10); | |
3751 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3752 | RT5645_GP10_PIN_MASK, | |
3753 | RT5645_GP10_PIN_DMIC2_SDA); | |
3754 | break; | |
1319b2f6 | 3755 | |
ac4fc3ee BL |
3756 | case RT5645_DMIC_DATA_GPIO12: |
3757 | regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1, | |
3758 | RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12); | |
3759 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3760 | RT5645_GP12_PIN_MASK, | |
3761 | RT5645_GP12_PIN_DMIC2_SDA); | |
3762 | break; | |
1319b2f6 | 3763 | |
ac4fc3ee BL |
3764 | default: |
3765 | break; | |
1319b2f6 OC |
3766 | } |
3767 | ||
ac4fc3ee | 3768 | if (rt5645->pdata.jd_mode) { |
bb656add | 3769 | regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, |
ac4fc3ee BL |
3770 | RT5645_IRQ_CLK_GATE_CTRL, |
3771 | RT5645_IRQ_CLK_GATE_CTRL); | |
bb656add | 3772 | regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, |
ac4fc3ee | 3773 | RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT); |
2d4e2d02 BL |
3774 | regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, |
3775 | RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN); | |
3776 | regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, | |
3777 | RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE); | |
3778 | regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER, | |
3779 | RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE); | |
3780 | regmap_update_bits(rt5645->regmap, RT5645_MICBIAS, | |
3781 | RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN); | |
3782 | regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1, | |
3783 | RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); | |
3784 | switch (rt5645->pdata.jd_mode) { | |
3785 | case 1: | |
3786 | regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, | |
3787 | RT5645_JD1_MODE_MASK, | |
3788 | RT5645_JD1_MODE_0); | |
3789 | break; | |
3790 | case 2: | |
3791 | regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, | |
3792 | RT5645_JD1_MODE_MASK, | |
3793 | RT5645_JD1_MODE_1); | |
3794 | break; | |
3795 | case 3: | |
3796 | regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1, | |
3797 | RT5645_JD1_MODE_MASK, | |
3798 | RT5645_JD1_MODE_2); | |
3799 | break; | |
3800 | default: | |
3801 | break; | |
3802 | } | |
3803 | } | |
3804 | ||
7ff6319e BL |
3805 | if (rt5645->pdata.jd_invert) { |
3806 | regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2, | |
3807 | RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV); | |
3808 | setup_timer(&rt5645->btn_check_timer, | |
3809 | rt5645_btn_check_callback, (unsigned long)rt5645); | |
3810 | } | |
3811 | ||
7ea3470a | 3812 | INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work); |
7099ee85 | 3813 | INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work); |
7ea3470a | 3814 | |
f3fa1bbd OC |
3815 | if (rt5645->i2c->irq) { |
3816 | ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq, | |
3817 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | |
3818 | | IRQF_ONESHOT, "rt5645", rt5645); | |
5168c547 | 3819 | if (ret) { |
f3fa1bbd | 3820 | dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret); |
9fc114c5 | 3821 | goto err_enable; |
5168c547 | 3822 | } |
f3fa1bbd OC |
3823 | } |
3824 | ||
5168c547 KC |
3825 | ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645, |
3826 | rt5645_dai, ARRAY_SIZE(rt5645_dai)); | |
3827 | if (ret) | |
3828 | goto err_irq; | |
3829 | ||
3830 | return 0; | |
3831 | ||
3832 | err_irq: | |
3833 | if (rt5645->i2c->irq) | |
3834 | free_irq(rt5645->i2c->irq, rt5645); | |
9fc114c5 KC |
3835 | err_enable: |
3836 | regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); | |
5168c547 | 3837 | return ret; |
1319b2f6 OC |
3838 | } |
3839 | ||
3840 | static int rt5645_i2c_remove(struct i2c_client *i2c) | |
3841 | { | |
f3fa1bbd OC |
3842 | struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); |
3843 | ||
3844 | if (i2c->irq) | |
3845 | free_irq(i2c->irq, rt5645); | |
3846 | ||
cd6e82b8 | 3847 | cancel_delayed_work_sync(&rt5645->jack_detect_work); |
7099ee85 | 3848 | cancel_delayed_work_sync(&rt5645->rcclock_work); |
cd6e82b8 | 3849 | |
1319b2f6 | 3850 | snd_soc_unregister_codec(&i2c->dev); |
9fc114c5 | 3851 | regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies); |
1319b2f6 OC |
3852 | |
3853 | return 0; | |
3854 | } | |
3855 | ||
f2988afe OC |
3856 | static void rt5645_i2c_shutdown(struct i2c_client *i2c) |
3857 | { | |
3858 | struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c); | |
3859 | ||
3860 | regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3, | |
3861 | RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND); | |
3862 | regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD, | |
3863 | RT5645_CBJ_MN_JD); | |
3864 | regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN, | |
3865 | 0); | |
a2c026cf OC |
3866 | msleep(20); |
3867 | regmap_write(rt5645->regmap, RT5645_RESET, 0); | |
f2988afe OC |
3868 | } |
3869 | ||
9e22f782 | 3870 | static struct i2c_driver rt5645_i2c_driver = { |
1319b2f6 OC |
3871 | .driver = { |
3872 | .name = "rt5645", | |
3168c201 | 3873 | .acpi_match_table = ACPI_PTR(rt5645_acpi_match), |
1319b2f6 OC |
3874 | }, |
3875 | .probe = rt5645_i2c_probe, | |
f2988afe OC |
3876 | .remove = rt5645_i2c_remove, |
3877 | .shutdown = rt5645_i2c_shutdown, | |
1319b2f6 OC |
3878 | .id_table = rt5645_i2c_id, |
3879 | }; | |
3880 | module_i2c_driver(rt5645_i2c_driver); | |
3881 | ||
3882 | MODULE_DESCRIPTION("ASoC RT5645 driver"); | |
3883 | MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>"); | |
3884 | MODULE_LICENSE("GPL v2"); |